A cache data prefetching method, apparatus, device and storage medium

Abstract

The application discloses a cache data prefetching method and device, equipment and storage medium, and relates to the technical field of computers, which comprises the following steps: when the accumulation table receives a data access request initiated by a CPU, if the accumulation table has a target table item that needs to be removed, it is judged whether the number of target effective bits in the candidate bit vector corresponding to the target table item is greater than a preset threshold; if yes, it is judged whether the mode table has a target bit vector corresponding to the candidate bit vector; if not, it is judged whether the mode table has a target idle table item; if not, it is judged whether the program counter corresponding to the candidate bit vector and the training counter both satisfy a first target saturation condition; if not, it is judged whether the program counter corresponding to the candidate bit vector and the access offset corresponding to the access missing counter both satisfy a second target saturation condition; if yes, the candidate bit vector is stored in the mode table, and a cache data prefetching operation is performed based on the mode table. The accuracy and efficiency of data prefetching are improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, device, and storage medium for cached data prefetching. Background Technology

[0002] High CPU memory access latency is one of the main bottlenecks hindering performance improvement. Cache data prefetchers predict the data addresses required by the CPU and load data from memory into the cache in advance, thereby reducing average memory access latency and improving overall CPU performance. Currently, some advanced prefetching methods extract program memory access behavior patterns from the CPU memory access request sequence, organize these patterns into bit vectors, and index them using multiple program features, significantly improving overall CPU performance. These prefetchers include SMS, DSPatch, and Bingo. However, the problem with these prefetchers is that they require a large amount of hardware storage space, resulting in huge hardware overhead and making them difficult to implement in industry. For example, the classic SMS prefetcher, even with a filter table, still needs to store thousands of memory access pattern entries. Its performance is built on this large storage overhead; as storage overhead decreases, prefetching performance drops significantly. There are also methods that reduce overhead by merging bit vectors, but this loses details of the original memory access patterns, leading to decreased prefetching accuracy and the inability to filter interference from low-frequency invalid patterns. Furthermore, the strategy of merging bit vectors is not suitable for TPC-C type tests in database applications. In this scenario, a large number of different program counters (PCs) access data. The merging strategy attempts to split the training PC (Program Counter) table and the offset table, with a maximum number of patterns: PC entries × offset entries. When a large number of different PCs access memory, the PC table frequently jitters due to size limitations, making prefetching difficult. If the number of PC entries is increased, the storage overhead increases dramatically because it uses a saturation counter to represent the memory access status of each bit, and the number of patterns represented degenerates to: PC entries.

[0003] As can be seen from the above, improving the accuracy and efficiency of data prefetching is an urgent problem to be solved. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a method, apparatus, device, and storage medium for cached data prefetching, which can improve the accuracy and efficiency of data prefetching. The specific solution is as follows: Firstly, this application provides a method for prefetching cached data, including: When the cumulative table receives a data memory access request initiated by the CPU, it collects the virtual address and program counter of the data to be accessed based on the data memory access request, records the memory access history in a memory area of ​​a preset size, and if there is a target entry in the cumulative table that needs to be removed, it determines a candidate bit vector based on the target entry and the corresponding memory access history. Determine whether the number of target valid bits in the candidate bit vector is greater than a preset threshold; If the value is greater than the preset threshold, the program counter corresponding to the candidate bit vector and the training counter corresponding to the memory access offset are incremented by 1 respectively, and it is determined whether there is a target bit vector corresponding to the candidate bit vector in the pattern table; the pattern table is a pattern table constructed based on the hybrid index of the program counter and the memory access offset. If the target bit vector does not exist, then determine whether there is a target free entry in the pattern table. If there is no target free entry, then determine whether the program counter and training counter corresponding to the candidate bit vector both satisfy the first target saturation condition. If the first target saturation condition is not met, then determine whether the program counter corresponding to the candidate bit vector and the memory access miss counter corresponding to the memory access offset both meet the second target saturation condition. If all conditions meet the second target saturation condition, the candidate bit vectors are stored in the pattern table, the target bit vector corresponding to the target data memory access request is determined based on the pattern table, the target bit vector is used to generate the corresponding prefetch address, and the corresponding cache data prefetch operation is performed based on the prefetch address.

[0005] Optionally, when the accumulator table receives a data memory access request initiated by the CPU, it collects the virtual address and program counter of the data to be accessed based on the data memory access request, records the memory access history within a preset size memory area, and if the accumulator table contains a target entry that needs to be removed, it determines a candidate bit vector based on the target entry and the corresponding memory access history, including: When the CPU accesses the L1 data cache, it initiates a corresponding data access request and collects the virtual address and program counter of the data to be accessed based on the data access request. Record the memory access history within a memory region of a preset size. If the cumulative table contains a target entry that needs to be removed, then determine a candidate bit vector based on the target entry and the corresponding memory access history. The target entry is an entry within the memory region.

[0006] Optionally, determining whether the number of target valid bits in the candidate bit vector is greater than a preset threshold includes: The total number of 1s in the candidate bit vector is determined as the target number of valid bits, and it is determined whether the target number of valid bits is greater than a preset threshold.

[0007] Optionally, after determining whether the number of target valid bits in the candidate bit vector is greater than a preset threshold, the method further includes: If the number of target valid bits in the candidate bit vector is not greater than a preset threshold, the candidate bit vector is eliminated.

[0008] Optionally, determining whether both the program counter and the training counter corresponding to the candidate bit vector satisfy the first target saturation condition includes: Determine whether the first count of the training counter corresponding to the program counter of the candidate bit vector and the second count of the training counter corresponding to the memory access offset are both greater than a first preset saturation threshold. Accordingly, after determining whether the program counter and training counter corresponding to the candidate bit vector both satisfy the first target saturation condition, the method further includes: If all values ​​are greater than the first preset saturation threshold, the candidate bit vector is stored in the pattern table, the training counters corresponding to the candidate bit vectors are reset, and the process jumps to the step of determining the target bit vector corresponding to the target data access request based on the pattern table.

[0009] Optionally, determining whether the program counter corresponding to the candidate bit vector and the memory miss counter corresponding to the memory access offset both satisfy the second target saturation condition includes: Determine whether the third count of the memory miss counter corresponding to the program counter of the candidate bit vector and the fourth count of the memory miss counter corresponding to the memory offset are both greater than the second preset saturation threshold. Accordingly, after determining whether the program counter corresponding to the candidate bit vector and the memory miss counter corresponding to the memory access offset both satisfy the second target saturation condition, the method further includes: If none of the candidate bit vectors are greater than the second preset saturation threshold, then the candidate bit vectors are eliminated.

[0010] Optionally, if all conditions meet the second target saturation condition, the candidate bit vectors are stored in the pattern table, the target bit vector corresponding to the target data memory access request is determined based on the pattern table, a corresponding prefetch address is generated using the target bit vector, and a corresponding cached data prefetch operation is performed based on the prefetch address, including: If the second target saturation condition is met, the candidate bit vector is stored in the pattern table, and the memory access miss counter corresponding to the candidate bit vector is reset. Based on the pattern table, the target bit vector corresponding to the target data memory access request is determined. The starting address of the target memory region accessed by the CPU and the memory access offset corresponding to the target bit vector are used to generate the corresponding prefetch address. The corresponding cache data prefetch operation is then performed based on the prefetch address.

[0011] Secondly, this application provides a cached data prefetching apparatus, comprising: The candidate bit vector generation module is used to collect the virtual address and program counter of the data to be accessed based on the data access request when the cumulative table receives a data access request initiated by the CPU, record the memory access history in a memory area of ​​a preset size, and determine the candidate bit vector based on the target table entry and the corresponding memory access history if the cumulative table has a target table entry that needs to be removed. The quantity judgment module is used to determine whether the number of target valid bits in the candidate bit vector is greater than a preset threshold. The target bit vector determination module is used to increment the program counter corresponding to the candidate bit vector and the training counter corresponding to the memory access offset by 1 respectively if the target bit vector is greater than the preset threshold, and to determine whether there is a target bit vector corresponding to the candidate bit vector in the pattern table; the pattern table is a pattern table constructed based on the hybrid index of the program counter and the memory access offset. The pattern table judgment module is used to determine whether there is a target free entry in the pattern table if the target bit vector does not exist, and if there is no target free entry, to determine whether the program counter and training counter corresponding to the candidate bit vector both satisfy the first target saturation condition. The counter judgment module is used to determine whether the program counter corresponding to the candidate bit vector and the memory access miss counter corresponding to the memory access offset both satisfy the second target saturation condition if the first target saturation condition is not met. The address generation module is used to store the candidate bit vectors into the pattern table if all conditions meet the second target saturation condition, determine the target bit vector corresponding to the target data access request based on the pattern table, generate the corresponding prefetch address using the target bit vector, and perform the corresponding cache data prefetch operation based on the prefetch address.

[0012] Thirdly, this application provides an electronic device, comprising: Memory, used to store computer programs; A processor is configured to execute the computer program to implement the aforementioned cached data prefetching method.

[0013] Fourthly, this application provides a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the aforementioned cached data prefetching method.

[0014] When the cumulative table receives a data memory access request initiated by the CPU, this application collects the virtual address and program counter of the data to be accessed based on the data memory access request, records the memory access history within a preset size memory area, and if the cumulative table contains a target entry that needs to be removed, then a candidate bit vector is determined based on the target entry and the corresponding memory access history; it is determined whether the number of target valid bits in the candidate bit vector is greater than a preset threshold; if it is greater than the preset threshold, the program counter corresponding to the candidate bit vector and the training counter corresponding to the memory access offset are incremented by 1 respectively, and it is determined whether there is a target bit vector corresponding to the candidate bit vector in the pattern table; the pattern table is a pattern table constructed based on a hybrid index of the program counter and the memory access offset; if If the target bit vector does not exist, it is determined whether there is a target free entry in the pattern table. If there is no target free entry, it is determined whether the program counter and training counter corresponding to the candidate bit vector both satisfy the first target saturation condition. If they do not both satisfy the first target saturation condition, it is determined whether the program counter corresponding to the candidate bit vector and the memory access offset corresponding to the memory access miss counter both satisfy the second target saturation condition. If they both satisfy the second target saturation condition, the candidate bit vector is stored in the pattern table, the target bit vector corresponding to the target data memory access request is determined based on the pattern table, the corresponding prefetch address is generated using the target bit vector, and the corresponding cached data prefetch operation is performed based on the prefetch address.

[0015] As can be seen from the above, the cumulative table of this application records the target virtual address and program counter in real time based on CPU memory access, and accumulates the memory access history within a preset memory area. Only when an entry is removed is a candidate bit vector generated based on the memory access history, without occupying the clock resources of the CPU core memory access path. When the number of valid bits recorded in the candidate bit vector exceeds the threshold, the subsequent counter update stage is entered to increment the program counter and the training counter corresponding to the memory access offset by 1 respectively. The pattern table is constructed using a hybrid index of program counter and memory access offset. The hybrid index is used to query whether the target bit vector corresponding to the candidate bit vector already exists in the pattern table. If it does not exist, it is determined whether there is a free invalid entry. If there is no free entry, it is first determined whether the program counter and training counter corresponding to the candidate bit vector both meet the first target saturation condition. If not, it is further determined whether the program counter and the memory access missing counter corresponding to the candidate bit vector both meet the second target saturation condition. If they meet the condition, they are stored; otherwise, they are discarded. In this way, by adding a filtering and identification mechanism, bit vectors with relatively high memory access patterns can be selected, thereby reducing storage overhead, ensuring prefetch performance, and greatly improving prefetch coverage without reducing prefetch accuracy. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0017] Figure 1 This is a flowchart of a cached data prefetching method disclosed in this application; Figure 2 This is a flowchart of a specific cached data prefetching method disclosed in this application; Figure 3 This is a schematic diagram of a hardware structure simulation configuration disclosed in this application; Figure 4 This is a schematic diagram of a test set disclosed in this application; Figure 5 This is a schematic diagram of a test case disclosed in this application; Figure 6 This is a schematic diagram illustrating a prefetch accuracy comparison disclosed in this application; Figure 7 This is a schematic diagram illustrating the change in prefetch coverage as a function of the pattern table size, as disclosed in this application. Figure 8 This is a schematic diagram of a CPU speedup disclosed in this application; Figure 9 This is a schematic diagram of a cached data prefetching device disclosed in this application; Figure 10 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Currently, some advanced prefetching methods extract program memory access behavior patterns from CPU memory access request sequences, organize these patterns into bit vectors, and index them using multiple program features, significantly improving overall CPU performance. However, these prefetchers require substantial hardware storage space, resulting in significant hardware overhead and making them difficult to implement in industry. To address this, this application provides a cache data prefetching method that adds a filtering and identification mechanism to select bit vectors of relatively high-frequency memory access patterns, thereby reducing storage overhead, ensuring prefetching performance, and significantly improving prefetch coverage without compromising prefetching accuracy.

[0020] See Figure 1 As shown, an embodiment of the present invention discloses a method for prefetching cached data, including: Step S11: When the cumulative table receives a data memory access request initiated by the CPU, it collects the virtual address and program counter of the data to be accessed based on the data memory access request, records the memory access history in a memory area of ​​a preset size, and if there is a target entry in the cumulative table that needs to be removed, it determines a candidate bit vector based on the target entry and the corresponding memory access history.

[0021] In this embodiment, when the processor core accesses the L1 data cache (i.e., the first-level cache) and the CPU initiates a data memory access request, the virtual address of the data to be accessed corresponding to the data memory access request and the corresponding program counter are collected. Based on a cumulative table and using a memory region of a preset size, the memory access behavior of each region is recorded. Each memory region corresponds to an entry in the cumulative table. The entry records the memory access history in the form of a bit vector. Each bit of the bit vector corresponds to a cache block of a fixed size in the corresponding memory region. A bit value of 1 indicates that the cache block at the corresponding offset has been accessed by the CPU during the recording cycle, and a bit value of 0 indicates that it has not been accessed. The cumulative table entry stores the PC and the offset relative to the region base address when a region is accessed for the first time. Subsequent accesses will not modify the PC and offset. Each entry stores a bit vector representing the access status of each cache block in that region. When there is a target entry in the cumulative table that needs to be removed (i.e. evicted), a candidate bit vector corresponding to the target entry is determined. The eviction operation is triggered when the number of entries exceeds the limit and is replaced or when a buffer block is evicted by the L1 data cache.

[0022] Specifically, when the accumulator table receives a data memory access request initiated by the CPU, it collects the virtual address and program counter of the data to be accessed based on the data memory access request, records the memory access history within a preset size memory area, and if the accumulator table contains a target entry that needs to be removed, it determines a candidate bit vector based on the target entry and the corresponding memory access history. This includes: when the CPU accesses the L1 data cache, it initiates a corresponding data memory access request, collects the virtual address and program counter of the data to be accessed based on the data memory access request, records the memory access history within a preset size memory area, and if the accumulator table contains a target entry that needs to be removed, it determines a candidate bit vector based on the target entry and the corresponding memory access history; the target entry is an entry within the memory area.

[0023] Step S12: Determine whether the number of target valid bits in the candidate bit vector is greater than a preset threshold.

[0024] In this embodiment, the target number of valid bits refers to the total number of binary bits with a value of 1 in the candidate bit vector, representing the number of cache blocks covered by the memory access mode in the corresponding memory region. More valid bits indicate a higher memory access density and greater prefetch value for the memory access mode. The determination of whether the target number of valid bits in the candidate bit vector is greater than a preset threshold is made. The preset threshold can be 3, or it can be adjusted according to actual conditions. Specifically, determining whether the target number of valid bits in the candidate bit vector is greater than the preset threshold includes: determining the total number of bits with a value of 1 in the candidate bit vector as the target number of valid bits, and determining whether the target number of valid bits is greater than the preset threshold.

[0025] It is understandable that if the number of target valid bits in the candidate bit vector is not greater than a preset threshold, the candidate bit vector is discarded, indicating that the pre-fetching value of the candidate bit vector is small. Specifically, after determining whether the number of target valid bits in the candidate bit vector is greater than the preset threshold, the method further includes: if the number of target valid bits in the candidate bit vector is not greater than the preset threshold, then the candidate bit vector is discarded.

[0026] Step S13: If the value is greater than the preset threshold, the program counter corresponding to the candidate bit vector and the training counter corresponding to the memory access offset are incremented by 1 respectively, and it is determined whether there is a target bit vector corresponding to the candidate bit vector in the pattern table; the pattern table is a pattern table constructed based on the hybrid index of the program counter and the memory access offset.

[0027] In this embodiment, if the number of valid target bits in the candidate bit vector is greater than a preset threshold, the training counter of the program counter corresponding to the candidate bit vector and the training counter corresponding to the memory access offset are incremented by 1 respectively. The record table includes an offset record table and a PC record table. Each entry in the record table is two 2-bit saturation counters, including a memory access miss counter and a training counter. The training counter is used to record the number of valid training iterations for the corresponding PC and memory access offset; the memory access miss counter is used to record the number of times the PC and memory access offset miss the pattern table. The pattern table is a set-associative structure, using a hybrid hashing method of PC and memory access offset for indexing. Compared with traditional prefetchers with single PC index and single offset index, the index collision rate is lower and the pattern matching accuracy is higher. An index is generated using the PC and memory access offset corresponding to the current candidate bit vector to query whether there is a valid, matching target bit vector in the pattern table.

[0028] Step S14: If the target bit vector does not exist, determine whether there is a target free entry in the pattern table. If there is no target free entry, determine whether the program counter and training counter corresponding to the candidate bit vector both satisfy the first target saturation condition.

[0029] In this embodiment, if the target bit vector corresponding to the candidate bit vector does not exist in the pattern table, it is determined whether there is an empty invalid entry in the pattern table. If it does, the candidate bit vector is directly inserted into the empty entry. If it does not exist, it is determined that the counts corresponding to the training counter and the memory access offset of the candidate bit vector have reached their respective saturation thresholds, i.e., both counters are saturated, and saturation of only one counter does not meet the triggering condition. The saturation thresholds can be set according to the actual situation. If both meet the first target saturation condition, the candidate bit vector is stored in the pattern table, and the two training counters corresponding to the candidate bit vector are reset, i.e., the training counter corresponding to the PC and the training counter for the memory access offset are reset.

[0030] Specifically, determining whether the program counter and training counter corresponding to the candidate bit vector both satisfy the first target saturation condition includes: determining whether the first count of the training counter corresponding to the program counter of the candidate bit vector and the second count of the training counter corresponding to the memory access offset are both greater than a first preset saturation threshold; correspondingly, after determining whether the program counter and training counter corresponding to the candidate bit vector both satisfy the first target saturation condition, the method further includes: if both are greater than the first preset saturation threshold, then storing the candidate bit vector in the pattern table, resetting each training counter corresponding to the candidate bit vector, and jumping to the step of determining the target bit vector corresponding to the target data memory access request based on the pattern table.

[0031] Step S15: If the first target saturation condition is not met, determine whether the program counter corresponding to the candidate bit vector and the memory access miss counter corresponding to the memory access offset both meet the second target saturation condition.

[0032] In this embodiment, if either the first count of the training counter corresponding to the program counter of the candidate bit vector or the second count of the training counter corresponding to the memory access offset does not meet the corresponding saturation threshold, or neither of them meets the corresponding saturation threshold, it indicates that the first target saturation condition is not met. Then, it is determined whether the third count of the memory access miss counter of the program counter corresponding to the candidate bit vector and the fourth count of the memory access miss counter corresponding to the memory access offset are both greater than their respective saturation thresholds. If they are not both greater than the thresholds, the candidate bit vector is eliminated.

[0033] Specifically, determining whether the program counter corresponding to the candidate bit vector and the memory access miss counter corresponding to the memory access offset both satisfy the second target saturation condition includes: determining whether the third count of the memory access miss counter corresponding to the program counter of the candidate bit vector and the fourth count of the memory access miss counter corresponding to the memory access offset are both greater than the second preset saturation threshold; correspondingly, after determining whether the program counter corresponding to the candidate bit vector and the memory access miss counter corresponding to the memory access offset both satisfy the second target saturation condition, the method further includes: if they are not both greater than the second preset saturation threshold, then the candidate bit vector is eliminated.

[0034] Step S16: If all conditions meet the second target saturation condition, the candidate bit vector is stored in the pattern table, the target bit vector corresponding to the target data access request is determined based on the pattern table, the target bit vector is used to generate the corresponding prefetch address, and the corresponding cache data prefetch operation is performed based on the prefetch address.

[0035] In this embodiment, if the second target saturation condition is met, the candidate bit vector is stored in the pattern table, and the memory access miss counters corresponding to the candidate bit vectors are reset. Then, the target bit vector corresponding to the target data memory access request is obtained from the pattern table, and the corresponding prefetch address is determined. The prefetch address is the address determined based on the starting address of the target memory region accessed by the CPU and the memory access offset corresponding to the target bit vector.

[0036] Specifically, if all conditions meet the second target saturation condition, the candidate bit vectors are stored in the pattern table. Based on the pattern table, a target bit vector corresponding to the target data memory access request is determined. A corresponding prefetch address is generated using the target bit vector, and a corresponding cache data prefetch operation is performed based on the prefetch address. This includes: if all conditions meet the second target saturation condition, the candidate bit vectors are stored in the pattern table, and the memory access miss counter corresponding to the candidate bit vectors is reset; based on the pattern table, a target bit vector corresponding to the target data memory access request is determined; a corresponding prefetch address is generated using the starting address of the target memory region accessed by the CPU and the memory access offset corresponding to the target bit vector; and a corresponding cache data prefetch operation is performed based on the prefetch address.

[0037] As can be seen from the above, the cumulative table of this application records the target virtual address and program counter in real time based on CPU memory access, and accumulates the memory access history within a preset memory area. Only when an entry is removed is a candidate bit vector generated based on the memory access history, without occupying the clock resources of the CPU core memory access path. When the number of valid bits recorded in the candidate bit vector exceeds the threshold, the subsequent counter update stage is entered to increment the program counter and the training counter corresponding to the memory access offset by 1 respectively. The pattern table is constructed using a hybrid index of program counter and memory access offset. The hybrid index is used to query whether the target bit vector corresponding to the candidate bit vector already exists in the pattern table. If it does not exist, it is determined whether there is a free invalid entry. If there is no free entry, it is first determined whether the program counter and training counter corresponding to the candidate bit vector both meet the first target saturation condition. If not, it is further determined whether the program counter and the memory access missing counter corresponding to the candidate bit vector both meet the second target saturation condition. If they meet the condition, they are stored; otherwise, they are discarded. In this way, by adding a filtering and identification mechanism, bit vectors with relatively high memory access patterns can be selected, thereby reducing storage overhead, ensuring prefetch performance, and greatly improving prefetch coverage without reducing prefetch accuracy.

[0038] As can be seen from the above embodiments, this application uses a multi-layer filtering mechanism to select bit vectors with relatively high memory access patterns in order to reduce storage overhead. Therefore, the process of selecting bit vectors with relatively high memory access patterns based on a multi-layer filtering mechanism is described.

[0039] See Figure 2 As shown, this embodiment of the invention discloses a specific method for prefetching cached data, including: In this embodiment, the CPU core initiates a data access request to the L1 data cache, sending the virtual address of the data to be accessed and the access information of the corresponding program counter to the prefetcher's accumulator table. When the accumulator table is full, meaning space needs to be freed up to store new access information, entries that haven't been accessed for a long time are identified as target entries, and candidate bit vectors are generated based on the target entries and their corresponding access history. When the record table receives the candidate bit vectors, it determines whether the number of target valid bits in the candidate bit vectors is greater than a preset threshold. If it is not greater than the preset threshold, the candidate bit vector has no prefetching value and is discarded; if it is greater than the preset threshold, the training counter of the program counter corresponding to the candidate bit vector and the training counter corresponding to the access offset are incremented by 1 respectively.

[0040] Understandably, if it is determined that there is no target bit vector corresponding to the candidate bit vector in the pattern table, then it is determined whether there is a free invalid entry in the pattern table; if there is, the candidate bit vector is directly inserted into the free entry to update the pattern table; if there is no target bit vector, it is determined that the first count of the training counter corresponding to the program counter of the candidate bit vector and the second count of the training counter of the memory access offset have both reached their respective saturation thresholds. If both satisfy the first target saturation condition, then the candidate bit vector is stored in the pattern table, and the training counter corresponding to the program counter of the candidate bit vector and the training counter of the memory access offset are reset.

[0041] Furthermore, if the first target saturation condition is not met, it is determined whether the program counter corresponding to the candidate bit vector and the memory access offset corresponding to the memory access miss counter both meet the second target saturation condition. If either the first count of the training counter corresponding to the program counter of the candidate bit vector or the second count of the training counter corresponding to the memory access offset does not meet the corresponding saturation threshold, or neither of them meets the corresponding saturation threshold, it indicates that the first target saturation condition is not met. Then it is determined whether the third count of the memory access miss counter corresponding to the program counter of the candidate bit vector and the fourth count of the memory access miss counter corresponding to the memory access offset are both greater than their respective corresponding saturation thresholds. If neither is greater than the threshold, the candidate bit vector is eliminated. If both meet the second target saturation condition, the candidate bit vector is stored in the pattern table. At this time, the pattern table stores only verified, high-value memory access patterns that can truly reduce CPU memory access latency, without any redundant or invalid data. It only requires a very small amount of hardware storage space to achieve extremely high prefetch performance.

[0042] In this embodiment, when the CPU core initiates a new target data memory access request, a query is performed based on the pattern table to match the target bit vector corresponding to the target data memory access request. Combined with the starting address of the memory page of this memory access and the cache line offset of the target bit vector index 1, a complete prefetch address is formed. According to the priority from the nearest to the current memory access offset, prefetch requests are sent to the L1 data cache in sequence to preload the corresponding data from the L3 / L2 cache into the L1 cache so that when the CPU core uses these data, the data has already been preloaded into the L1 data cache.

[0043] Understandably, to verify the actual performance of the prefetcher in this solution, the XS-GEM5 simulator was used for hardware structure simulation, with the corresponding configuration as follows: Figure 3 As shown, the matching is completely consistent with the mainstream parameters of current commercial server CPUs; this experiment selects the most core scenario of industrial server CPUs, namely database load, and is divided into two major standard test sets, TPC-C and TPC-H, with the corresponding test sets as follows: Figure 4 As shown, these two scenarios have complex memory access patterns and a high proportion of random memory access, which are the performance bottleneck scenarios for traditional prefetchers. Being able to demonstrate advantages in these two scenarios proves the industrial value of the solution more effectively than the general test set.

[0044] Understandable Figure 5 This is a test case diagram. Online transaction processing (OLTP) testing simulates high-frequency, short-transaction scenarios such as e-commerce orders, retail warehousing, and government processing. These are the core commercial database scenarios in the internet, finance, and retail industries. The TPC-C16 warehouse corresponds to a typical configuration for small to medium-sized commercial systems, such as small to medium-sized e-commerce businesses or city commercial bank branch operations. The data volume is moderate, and the access patterns are highly repetitive, making it a benchmark scenario for verifying the basic performance of the prefetcher. The TPC-C32 warehouse corresponds to a typical configuration for medium to large-scale commercial systems. Decision support system testing simulates complex read-only query scenarios such as enterprise business intelligence reports, big data analysis, operational data statistics, and financial accounting. These are core database scenarios for enterprise digital transformation and big data analysis. TPC-H's Qry1 is a pricing report query, the core of which is a full table scan of the largest order detail table in the database; Qry2 is a nested multi-table join scenario; Qry8 is a multi-table join and multi-level aggregation scenario, with more tables and more complex logical connections compared to Qry2; Qry11 is a hybrid scenario of continuous full table scans and skip-style multi-table joins. The above test cases cover all dimensions of test scenarios.

[0045] Figure 6This diagram illustrates a comparison of prefetch accuracy. The horizontal axis covers four typical queries of TPC-H and two workloads of TPC-C to achieve full scenario coverage. The vertical axis represents prefetch accuracy. The blue bars represent the SMS prefetcher, and the red bars represent the prefetcher of this method. It can be seen that this solution does not reduce prefetch accuracy at all while significantly reducing storage overhead, and is even better in complex scenarios. Figure 7 This diagram illustrates how prefetch coverage varies with pattern table size. The horizontal axis represents pattern table size, and the vertical axis represents prefetch coverage. The blue line represents the coverage of this method in TPC-H and TPC-C scenarios, while the yellow line represents the coverage of the SMS prefetcher in both scenarios. It can be seen that the prefetch coverage of this invention far exceeds that of the SMS prefetcher, and the performance difference is more pronounced when the pattern table is smaller. This demonstrates that the filtering and identification mechanism can effectively screen out high-frequency memory access patterns.

[0046] Furthermore, Figure 8 This diagram illustrates CPU speedup. The horizontal axis represents different test cases, covering both TPC-H and TPC-C scenarios; the vertical axis represents the speedup ratio, i.e., the performance improvement of the CPU compared to the baseline without a prefetcher. It shows that the proposed method achieves an average speedup of 9.05% across all scenarios, with an average speedup of 10.32% in the TPC-H big data analysis scenario, and the highest speedup in the Qry2 multi-table join scenario. The TPC-C online transaction scenario achieves an average speedup of 6.48%. This represents a breakthrough improvement in CPU chip design within the industry.

[0047] As can be seen from the above, when an entry is removed, this application generates a candidate bit vector based on the memory access history. When the number of valid bits recorded in the candidate bit vector exceeds a threshold, the corresponding program counter and the training counter corresponding to the memory access offset are incremented by 1. The application then checks whether a target bit vector corresponding to the candidate bit vector already exists in the pattern table. If it does not exist, it checks whether there are any idle invalid entries. If there are no idle entries, it first checks whether the program counter and training counter corresponding to the candidate bit vector both meet the first target saturation condition. If not, it continues to check whether the program counter corresponding to the candidate bit vector and the memory access missing counter corresponding to the memory access offset both meet the second target saturation condition. If they meet the condition, the bit vector is stored; otherwise, it is discarded. In this way, through multi-layer filtering, bit vectors of high-frequency memory access patterns are obtained, greatly improving the prefetch coverage without reducing prefetch accuracy.

[0048] Accordingly, see Figure 9 As shown, this application also provides a cached data prefetching apparatus, comprising: The candidate bit vector generation module 11 is used to collect the virtual address and program counter of the data to be accessed based on the data access request when the cumulative table receives a data access request initiated by the CPU, record the access history in a memory area of ​​a preset size, and determine the candidate bit vector based on the target table entry and the corresponding access history if the cumulative table has a target table entry that needs to be removed. The quantity judgment module 12 is used to determine whether the number of target valid bits in the candidate bit vector is greater than a preset threshold. The target bit vector determination module 13 is used to increment the program counter corresponding to the candidate bit vector and the training counter corresponding to the memory access offset by 1 respectively if the target bit vector is greater than the preset threshold, and to determine whether there is a target bit vector corresponding to the candidate bit vector in the pattern table; the pattern table is a pattern table constructed based on the hybrid index of the program counter and the memory access offset. The pattern table judgment module 14 is used to determine whether there is a target free entry in the pattern table if the target bit vector does not exist, and if there is no target free entry, to determine whether the program counter and training counter corresponding to the candidate bit vector both satisfy the first target saturation condition. The counter judgment module 15 is used to determine whether the program counter corresponding to the candidate bit vector and the memory access miss counter corresponding to the memory access offset both satisfy the second target saturation condition if the first target saturation condition is not met. The address generation module 16 is used to store the candidate bit vector into the pattern table if all conditions meet the second target saturation condition, determine the target bit vector corresponding to the target data memory access request based on the pattern table, generate the corresponding prefetch address using the target bit vector, and perform the corresponding cache data prefetch operation based on the prefetch address.

[0049] In some specific embodiments, the candidate bit vector generation module 11 may specifically include: The address collection unit is used to initiate a corresponding data access request when the CPU accesses the L1 data cache, and collect the virtual address and program counter of the data to be accessed based on the data access request. The candidate bit vector generation unit is used to record the memory access history within a memory region of a preset size. If there is a target entry in the cumulative table that needs to be removed, then a candidate bit vector is determined based on the target entry and the corresponding memory access history. The target entry is an entry within the memory region.

[0050] In some specific embodiments, the quantity determination module 12 may specifically include: The target number determination unit is used to determine the total number of 1s in the candidate bit vector as the target effective number of bits, and to determine whether the target effective number of bits is greater than a preset threshold.

[0051] In some specific embodiments, the cached data prefetching device may further include: The first vector elimination unit is used to eliminate the candidate bit vector if the number of target valid bits in the candidate bit vector is not greater than a preset threshold.

[0052] In some specific embodiments, the pattern table determination module 14 may specifically include: The first counting judgment unit is used to determine whether the first count of the training counter corresponding to the program counter of the candidate bit vector and the second count of the training counter corresponding to the memory access offset are both greater than the first preset saturation threshold. Accordingly, the cached data prefetching device may further include: The bit vector storage unit is used to store the candidate bit vector into the pattern table if all of them are greater than the first preset saturation threshold, reset each training counter corresponding to the candidate bit vector, and jump to the step of determining the target bit vector corresponding to the target data access request based on the pattern table.

[0053] In some specific embodiments, the counter judgment module 15 may specifically include: The second counting judgment unit is used to determine whether the third count of the memory access miss counter corresponding to the program counter of the candidate bit vector and the fourth count of the memory access miss counter corresponding to the memory access offset are both greater than the second preset saturation threshold. Accordingly, the cached data prefetching device may further include: The second bit vector elimination unit is used to eliminate the candidate bit vectors if none of them are greater than the second preset saturation threshold.

[0054] In some specific embodiments, the address generation module 16 may specifically include: The counter reset unit is used to store the candidate bit vector into the pattern table and reset the memory access miss counter corresponding to the candidate bit vector if the second target saturation condition is met. The prefetch address generation unit is used to determine the target bit vector corresponding to the target data memory access request based on the pattern table, generate the corresponding prefetch address using the starting address of the target memory region accessed by the CPU and the memory access offset corresponding to the target bit vector, and perform the corresponding cache data prefetch operation based on the prefetch address.

[0055] Furthermore, embodiments of this application also disclose an electronic device, Figure 10This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the cached data prefetching method disclosed in any of the foregoing embodiments. Furthermore, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0056] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0057] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0058] The operating system 221 is used to manage and control the various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the cached data prefetching method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.

[0059] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned disclosed cached data prefetching method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0060] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0061] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0062] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0063] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0064] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for prefetching cached data, characterized in that, include: When the cumulative table receives a data memory access request initiated by the CPU, it collects the virtual address and program counter of the data to be accessed based on the data memory access request, records the memory access history in a memory area of ​​a preset size, and if there is a target entry in the cumulative table that needs to be removed, it determines a candidate bit vector based on the target entry and the corresponding memory access history. Determine whether the number of target valid bits in the candidate bit vector is greater than a preset threshold; If it is greater than the preset threshold, then the program counter corresponding to the candidate bit vector and the training counter corresponding to the memory access offset are incremented by 1 respectively, and it is determined whether there is a target bit vector corresponding to the candidate bit vector in the pattern table. The schema table is constructed based on a hybrid index of the program counter and memory access offset; If the target bit vector does not exist, then determine whether there is a target free entry in the pattern table. If there is no target free entry, then determine whether the program counter and training counter corresponding to the candidate bit vector both satisfy the first target saturation condition. If the first target saturation condition is not met, then determine whether the program counter corresponding to the candidate bit vector and the memory access miss counter corresponding to the memory access offset both meet the second target saturation condition. If all conditions meet the second target saturation condition, the candidate bit vectors are stored in the pattern table, the target bit vector corresponding to the target data memory access request is determined based on the pattern table, the target bit vector is used to generate the corresponding prefetch address, and the corresponding cache data prefetch operation is performed based on the prefetch address.

2. The cached data prefetching method according to claim 1, characterized in that, When the accumulator table receives a data memory access request initiated by the CPU, it collects the virtual address and program counter of the data to be accessed based on the data memory access request, records the memory access history within a preset size memory area, and if the accumulator table contains a target entry that needs to be removed, it determines a candidate bit vector based on the target entry and the corresponding memory access history, including: When the CPU accesses the L1 data cache, it initiates a corresponding data access request and collects the virtual address and program counter of the data to be accessed based on the data access request. Record the memory access history within a memory region of a preset size. If the cumulative table contains a target entry that needs to be removed, then determine a candidate bit vector based on the target entry and the corresponding memory access history. The target entry is an entry within the memory region.

3. The cached data prefetching method according to claim 1, characterized in that, The step of determining whether the number of target valid bits in the candidate bit vector is greater than a preset threshold includes: The total number of 1s in the candidate bit vector is determined as the target number of valid bits, and it is determined whether the target number of valid bits is greater than a preset threshold.

4. The cached data prefetching method according to claim 1, characterized in that, After determining whether the number of target valid bits in the candidate bit vector is greater than a preset threshold, the method further includes: If the number of target valid bits in the candidate bit vector is not greater than a preset threshold, the candidate bit vector is eliminated.

5. The cached data prefetching method according to claim 1, characterized in that, The step of determining whether the program counter and training counter corresponding to the candidate bit vector both satisfy the first target saturation condition includes: Determine whether the first count of the training counter corresponding to the program counter of the candidate bit vector and the second count of the training counter corresponding to the memory access offset are both greater than a first preset saturation threshold. Accordingly, after determining whether the program counter and training counter corresponding to the candidate bit vector both satisfy the first target saturation condition, the method further includes: If all values ​​are greater than the first preset saturation threshold, the candidate bit vector is stored in the pattern table, the training counters corresponding to the candidate bit vectors are reset, and the process jumps to the step of determining the target bit vector corresponding to the target data access request based on the pattern table.

6. The cached data prefetching method according to claim 5, characterized in that, The step of determining whether the program counter corresponding to the candidate bit vector and the memory miss counter corresponding to the memory access offset both satisfy the second target saturation condition includes: Determine whether the third count of the memory miss counter corresponding to the program counter of the candidate bit vector and the fourth count of the memory miss counter corresponding to the memory offset are both greater than the second preset saturation threshold. Accordingly, after determining whether the program counter corresponding to the candidate bit vector and the memory miss counter corresponding to the memory access offset both satisfy the second target saturation condition, the method further includes: If none of the candidate bit vectors are greater than the second preset saturation threshold, then the candidate bit vectors are eliminated.

7. The cached data prefetching method according to any one of claims 1 to 6, characterized in that, If all conditions meet the second target saturation condition, the candidate bit vectors are stored in the pattern table. Based on the pattern table, the target bit vector corresponding to the target data memory access request is determined. The target bit vector is used to generate a corresponding prefetch address, and the corresponding cached data prefetch operation is performed based on the prefetch address, including: If the second target saturation condition is met, the candidate bit vector is stored in the pattern table, and the memory access miss counter corresponding to the candidate bit vector is reset. Based on the pattern table, the target bit vector corresponding to the target data memory access request is determined. The starting address of the target memory region accessed by the CPU and the memory access offset corresponding to the target bit vector are used to generate the corresponding prefetch address. The corresponding cache data prefetch operation is then performed based on the prefetch address.

8. A cached data prefetching device, characterized in that, include: The candidate bit vector generation module is used to collect the virtual address and program counter of the data to be accessed based on the data access request when the cumulative table receives a data access request initiated by the CPU, record the memory access history in a memory area of ​​a preset size, and determine the candidate bit vector based on the target table entry and the corresponding memory access history if the cumulative table has a target table entry that needs to be removed. The quantity judgment module is used to determine whether the number of target valid bits in the candidate bit vector is greater than a preset threshold. The target bit vector determination module is used to increment the program counter corresponding to the candidate bit vector and the training counter corresponding to the memory access offset by 1 respectively if the target bit vector is greater than the preset threshold, and to determine whether there is a target bit vector corresponding to the candidate bit vector in the mode table. The schema table is constructed based on a hybrid index of the program counter and memory access offset; The pattern table judgment module is used to determine whether there is a target free entry in the pattern table if the target bit vector does not exist, and if there is no target free entry, to determine whether the program counter and training counter corresponding to the candidate bit vector both satisfy the first target saturation condition. The counter judgment module is used to determine whether the program counter corresponding to the candidate bit vector and the memory access miss counter corresponding to the memory access offset both satisfy the second target saturation condition if the first target saturation condition is not met. The address generation module is used to store the candidate bit vectors into the pattern table if all conditions meet the second target saturation condition, determine the target bit vector corresponding to the target data access request based on the pattern table, generate the corresponding prefetch address using the target bit vector, and perform the corresponding cache data prefetch operation based on the prefetch address.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the cached data prefetching method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used to store a computer program, wherein the computer program, when executed by a processor, implements the cached data prefetching method as described in any one of claims 1 to 7.

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