Artificial intelligence chip and operating method thereof

Abstract

The present application relates to an artificial intelligence chip and an operation method thereof. Based on the present application, a multi-channel transmitter of the artificial intelligence chip can only set a loading signal generator for generating a loading signal based on a clock signal in a transmitter common circuit, and a serializer of each transmitter channel circuit can serialize and output parallel input channel data for sending through a corresponding physical channel of a multi-channel bus based on the clock signal and the loading signal received from the transmitter common circuit. Therefore, the serializers of the plurality of transmitter channel circuits do not need to be provided with a loading signal generator, and the serialization and output of the parallel input channel data can be completed using the loading signal. Thus, compared with related technologies in which the serializers of each transmitter channel circuit are all provided with a loading signal generator, the circuit area and the circuit power consumption of the multi-channel transmitter can be reduced by reducing the loading signal generator.

Claims

1. An artificial intelligence chip, characterized in that, The device includes a multi-channel transmitter for transmitting data via a multi-channel bus, the multi-channel transmitter including a transmitter common circuit and multiple transmitter channel circuits corresponding to multiple physical channels of the multi-channel bus; The transmitter common circuit includes a clock source and a load signal generator, the clock source being configured to generate a clock signal, and the load signal generator being configured to generate a load signal based on the clock signal; Each of the transmitter channel circuits includes a serializer, and the serializer of each of the transmitter channel circuits is configured to serialize and output channel data that is input in parallel and is intended to be transmitted through the corresponding physical channel based on the clock signal and the load signal received from the transmitter common circuit.

2. The artificial intelligence chip according to claim 1, characterized in that, Each of the transmitter channel circuits further includes a channel clock path, and the clock signal reaches the serializer via the channel clock path in each of the transmitter channel circuits; The transmitter common circuit further includes a delay compensation path; wherein the delay compensation path is configured to give the load signal a delay compensation that matches the channel transmission delay of the clock signal in each of the transmitter channel circuits caused by the channel clock path.

3. The artificial intelligence chip according to claim 2, characterized in that, The delay compensation path is located between the clock source and the load signal generator, and the delay compensation path is specifically configured to generate the delay compensation for the clock signal transmitted from the clock source to the load signal generator in the transmitter common circuit, so that the load signal generated by the load signal generator has the delay compensation; The clock signal that arrives at the serializer via the channel clock path in each of the transmitter channel circuits is bypassed in the transmitter common circuit via the delay compensation path.

4. The artificial intelligence chip according to claim 2, characterized in that, The serializer includes a shift register, and the shift register includes multiple flip-flops; The loading signal is used to control the cascading state between the multiple flip-flops, so that the channel data input in parallel is loaded into the multiple flip-flops in parallel and then serialized and output by shifting in the cascading direction of the multiple flip-flops; The channel data is loaded into multiple triggers and shifted in the cascading direction of multiple triggers, all by the flipping of the triggers based on the clock signal; the delay compensation is configured to match the timing relationship between the loading signal and the clock signal with the flipping association parameter of the trigger, and the flipping association parameter includes the setup time threshold and the hold time threshold of the trigger.

5. The artificial intelligence chip according to claim 4, characterized in that, The delay compensation is specifically configured to ensure that the timing relationship between the loading signal and the clock signal satisfies: The actual setup time for the channel data by the trigger is greater than the setup time threshold. The actual holding time of the channel data by the trigger is greater than the holding time threshold.

6. The artificial intelligence chip according to claim 5, characterized in that, The actual setup time and the actual hold time are related to the channel transmission delay of the clock signal, the delay compensation of the load signal, and the loading delay generated by the parallel loading process of the channel data to multiple triggers.

7. The artificial intelligence chip according to claim 6, characterized in that, The actual setup time SU_margin = 2UI + Delay_clk - Delay_load - Delay_trans; The actual hold time HD_margin = Delay_load + Delay_trans - Delay_clk; Wherein, 2UI represents one signal period of the clock signal, Delay_clk represents the channel transmission delay of the clock signal, Delay_load represents the delay compensation of the load signal, and Delay_trans represents the loading delay generated by the parallel loading process of the channel data to multiple triggers.

8. The artificial intelligence chip according to any one of claims 1 to 7, characterized in that, The transmitter common circuit also includes a drive buffer; wherein the drive buffer is configured to boost the signal load of the clock signal and the signal load of the loading signal to a multi-channel load level matching the multiple transmitter channel circuits, and then split the signal loads into single-channel load levels and transmit them to the multiple transmitter channel circuits.

9. The artificial intelligence chip according to claim 4, characterized in that, The transmitter common circuit also includes a drive buffer; wherein the drive buffer is configured to boost the signal load of the clock signal and the signal load of the loading signal to a multi-channel load level matching the multiple transmitter channel circuits, and then split the signal loads into single-channel load levels and transmit them to the multiple transmitter channel circuits. The serializer of each of the transmitter channel circuits further includes a clock shaping buffer and a signal shaping buffer, wherein: The clock shaping buffer is configured to allow the clock signal transmitted to the serializer to be bundled and corrected at the single-path load level before reaching the shift register. The signal shaping buffer is configured such that the load signal transmitted to the serializer is subjected to the single-path load level beamforming correction before reaching the shift register.

10. The artificial intelligence chip according to claim 8, characterized in that, The drive buffer includes a clock drive buffer and a signal drive buffer, wherein: The clock drive buffer is configured to make the signal load of the clock signal reach the multiple load level that matches the multiple transmitter channel circuits; The signal drive buffer is configured to make the signal load of the loaded signal reach the multiple load level that matches the multiple transmitter channel circuits.

11. The artificial intelligence chip according to claim 10, characterized in that, The clock signal generated by the clock source has a load signal at the single-channel load level, and the clock drive buffer is configured to increase the load signal of the clock signal generated by the clock source from the single-channel load level to the multi-channel load level matching the multiple transmitter channel circuits. The load signal generated by the load signal generator has a signal load at the single-channel load level, and the signal drive buffer is configured to increase the signal load of the load signal generated by the load signal generator from the single-channel load level to the multi-channel load level matching the multiple transmitter channel circuits.

12. The artificial intelligence chip according to claim 2, characterized in that, The serializer of each of the transmitter channel circuits serializes the parallel-input channel data by serializing the odd-numbered bits and even-numbered bits of the channel data, respectively. The serializer includes a shift register, which includes two sets of flip-flops corresponding to odd-numbered bits and even-numbered bits, respectively. The loading signal is used to control the intra-group cascading state between the two sets of triggers, so that the odd and even bits of the channel data are loaded in parallel to the two sets of triggers respectively, and then serialized and output by shifting in the cascading direction of the corresponding sets of triggers. The odd and even bits of the channel data are shifted in the loading of the corresponding group of the flip-flops and in the cascading direction of the corresponding group of the flip-flops, respectively, by the flip-flops based on the toggling of the clock signal. The delay compensation is configured to match the timing relationship between the loading signal and the clock signal with the toggling association parameter of the flip-flops. The toggling association parameter includes the setup time threshold and the hold time threshold of the flip-flops.

13. A method for operating an artificial intelligence chip, characterized in that, The artificial intelligence chip includes a multi-channel transmitter for transmitting data via a multi-channel bus. The multi-channel transmitter includes a transmitter common circuit and multiple transmitter channel circuits corresponding to multiple physical channels of the multi-channel bus. The operation method includes: A clock signal is generated by the clock source of the transmitter common circuit, and a load signal is generated by the load signal generator of the transmitter common circuit based on the clock signal; The serializer of each of the transmitter channel circuits serializes the parallel-input channel data for transmission through the corresponding physical channel based on the clock signal and the load signal received from the transmitter common circuit.

14. The operating method according to claim 13, characterized in that, Each of the transmitter channel circuits further includes a channel clock path, and the clock signal reaches the serializer via the channel clock path in each of the transmitter channel circuits; The transmitter common circuit also includes a delay compensation path, and the operation method further includes: The delay compensation path is used to make the loading signal have delay compensation that matches the channel transmission delay of the clock signal in each of the transmitter channel circuits caused by the channel clock path.

15. The operating method according to claim 13 or 14, characterized in that, The transmitter common circuit also includes a drive buffer, and the operation method further includes: After the signal load of the clock signal and the signal load of the loading signal are both boosted to the multi-channel load level matching the multiple transmitter channel circuits by the drive buffer, the signal loads are split into single-channel load levels and transmitted to the multiple transmitter channel circuits.

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