A method for solving dynamic voltage drop with packaging based on LU decomposition combined with SMW formula

Abstract

The application provides a method for solving dynamic voltage drop of a chip-package based on LU decomposition combined with an SMW formula. The chip-package power supply network is regarded as a composite system connected by an interconnection node Pad between a package part and a plurality of chip sub-networks. A chip-package partition solving strategy is introduced. According to the chip and package characteristics, a large-scale sparse matrix of the composite system is disassembled into a structural model with a plurality of diagonal sub-blocks, so as to convert the chip-package power supply network equation into a block structure, and avoid the inefficient redundancy of full matrix repeated decomposition by focusing on necessary coupling calculation. Meanwhile, the SMW formula is used for low-rank incremental updating of the package network influence, so as to quickly update the influence introduced by the package and quickly correct the solution vector. The calculation task is split into a plurality of sub-problems for synchronous execution, so that the plurality of sub-blocks are solved synchronously. The application can provide a high-precision and high-efficiency solution for dynamic voltage drop analysis of a large-scale chip package power supply network.

Description

Technical Field

[0001] This invention relates to, and in particular to, a method for solving dynamic voltage drop across a package based on LU decomposition combined with the SMW formula, in the field of power integrity analysis and chip packaging co-simulation technology for very large-scale integrated circuits. Background Technology

[0002] In real-world scenarios involving dynamic voltage drop (IR Drop) analysis of large-scale chip-package power distribution networks, it is necessary to efficiently solve large sparse linear equation systems across multiple time steps. The accuracy and speed of this solution directly affect the effectiveness of design verification and reliability analysis.

[0003] In the dynamic voltage drop analysis of VLSI (Very Large Scale Integration) circuits, existing technologies mainly calculate the time-varying voltage changes of power supply network nodes through transient circuit simulation or iterative linear solutions. Iterative algorithms (such as the conjugate gradient method) have gained some application due to their fast single-step solution speed, but they have significant limitations: the computational accuracy is highly sensitive to the matrix condition number. In the scenario of rigid-flexible coupling (ill-conditioned) matrices formed by complex chip-package power networks, iterative methods often exhibit slow convergence or even divergence, resulting in large deviations between the calculated results and actual values, making it difficult to meet the accuracy requirements of design verification. To improve robustness, engineering attempts have been made to improve iterative solutions by shortening the simulation step size and enhancing preconditions. However, when the node scale reaches millions and the number of time steps reaches tens of thousands, these measures still cannot fundamentally solve the accuracy and convergence problems.

[0004] On the other hand, traditional direct solution methods (such as LU decomposition and Cholesky decomposition) can guarantee computational accuracy and are reliable means of solving linear equation systems. However, when applied to the dynamic simulation of ultra-large-scale power networks with packages, they face two major challenges: First, the overall admittance matrix formed by the coupling of the internal power network and packaged circuitry is large and complex. Accurate decomposition will generate a large number of filler elements, causing storage requirements to grow exponentially and memory usage to exceed hardware processing capabilities. Second, in dynamic simulation, it is necessary to repeatedly solve linear equations with nearly identical structures at multiple time points. If matrix decomposition is performed completely at each time point, a large number of repeated calculations will significantly reduce the solution efficiency. Ideally, when the matrix remains unchanged at each time step, the results can be reused by substituting back and forth multiple times after a single decomposition. However, in actual circuits, there are nonlinear devices or time-varying loads, and the equivalent matrix may change during the simulation. In engineering, a conservative strategy of re-decomposing at each step is often adopted, resulting in more than 90% of the computation being wasted in the repeated decomposition process. To alleviate this problem, some technical solutions attempt to simplify external networks such as packages by representing them as equivalent circuit models or to reduce the overall matrix size using model reduction techniques. However, these often come at the cost of accuracy, making it difficult to predict dynamic voltage drops comprehensively and accurately. Therefore, existing technologies lack efficient and high-precision solutions for large-scale dynamic voltage drop calculations that take into account the impact of packages.

[0005] In the field of dynamic voltage drop simulation of chip power networks, existing technologies have significant limitations. Traditional stepwise direct solutions require matrix decomposition of the entire network at each time point, resulting in extremely high computational complexity and storage overhead. Especially after incorporating packaged networks, the matrix dimension and non-zero elements increase significantly, leading to a substantial increase in the time complexity of a single solution. The number of filler elements during decomposition grows exponentially, not only causing a sharp increase in memory costs but also resulting in a large amount of computing power being wasted on redundant calculations, severely impacting efficiency. While iterative solutions are faster in some scenarios, they are extremely sensitive to the matrix condition number and often fail to converge in complex power networks coupled with chip-package, failing to meet the accuracy and stability requirements of industrial applications. Furthermore, existing methods lack sufficient multi-core parallel expansion, and the sequential dependency of dynamic simulation makes it difficult to fully utilize parallel computing to accelerate the solution, failing to meet the real-time and high-throughput requirements of practical applications.

[0006] For dynamic voltage drop analysis of large-scale chip packaged power networks, existing technologies suffer from several bottlenecks: First, traditional methods often employ direct full matrix decomposition step-by-step, leading to a rapid increase in time complexity with problem size. Facing simulation requirements involving hundreds of millions of nodes and thousands of time steps, the computational load grows exponentially, resulting in excessively long simulation times that fail to meet engineering time requirements. Furthermore, the repeated full matrix decomposition at each step introduces over 90% computational redundancy, resulting in inefficient use and significant waste of computational resources. Second, the integration of packaged circuits into the chip power network significantly increases the matrix size and coupling density, drastically increasing the number of non-zero padding elements generated by conventional LU or Cholesky decomposition. This leads to memory consumption exceeding hardware limitations, severely restricting algorithm scalability and hindering its adaptation to larger-scale power network analysis. Third, dynamic simulation exhibits strong sequential dependence, with subsequent steps relying on the results of previous steps. This data dependency makes it difficult to fully leverage parallel acceleration computation. Existing parallel solutions can only be implemented to a limited extent within a single step, and multi-core computing capabilities cannot be linearly scaled, resulting in an overall speedup far below expectations and failing to fully utilize the performance of multi-core processors.

[0007] The aforementioned shortcomings make it difficult for existing technologies to meet the urgent need in engineering for high-speed and accurate analysis of dynamic voltage drop in packaged power networks.

[0008] To address the aforementioned challenges, this invention proposes an efficient solution: It innovatively employs a partitioned, block-based solution strategy, decomposing a large-scale sparse matrix into a structural model with multiple diagonal sub-blocks based on chip and packaging characteristics. This focuses on necessary coupled solutions, avoiding the inefficiency of repetitive full-matrix calculations and significantly reducing computational complexity. Furthermore, it cleverly utilizes the Sherman-Morson-Woodbury formula to quickly update the effects introduced by packaging, obtaining accurate solutions without needing to re-decompose the matrix at each step, greatly improving solution efficiency. Finally, combined with the parallel computing capabilities of multi-core processors, it enables simultaneous execution of solutions for multiple sub-blocks, further enhancing computational speed. Summary of the Invention

[0009] This invention proposes a method for solving dynamic voltage drop across packaged power networks based on LU decomposition combined with the SMW formula. It innovatively employs a partitioned, block-based solution strategy, decomposing a large-scale sparse matrix into a structural model with multiple diagonal sub-blocks according to the characteristics of the chip and package. This focuses on necessary coupled solutions, avoiding the inefficiency of repetitive full-matrix calculations and significantly reducing computational complexity. The invention cleverly utilizes the Sherman-Morston-Woodbury formula to quickly update the effects introduced by the package, obtaining accurate solutions without re-decomposing the matrix at each step, greatly improving solution efficiency. Combined with the parallel computing capabilities of multi-core processors, it enables simultaneous execution of solutions for multiple sub-blocks, further enhancing computational speed. This provides a high-precision, high-efficiency solution for dynamic voltage drop analysis of power networks in large-scale chip packages.

[0010] The present invention adopts the following technical solution.

[0011] A method for solving dynamic voltage drop across a packaged network based on LU decomposition combined with the SMW formula is presented. This method treats the chip-package power network as a composite system consisting of a package portion and multiple chip sub-networks tightly connected via interconnect nodes (Pads). By introducing a chip-package partitioning solution strategy, the large-scale sparse matrix of the composite system is decomposed into a structural model with multiple diagonal sub-blocks based on the characteristics of the chip and package. This transforms the chip-package power network equation into a block structure, and avoids inefficient redundancy by focusing on necessary coupled calculations. Simultaneously, the SMW formula (Sherman-Morson-Woodbury (SMW) formula) is used to perform low-rank incremental updates on the package network's influence, rapidly updating the effects introduced by the package. Accurate solutions can be obtained without re-decomposing the matrix at each step, significantly improving solution efficiency. The solution vector is quickly corrected while maintaining computational accuracy. Furthermore, the method fully leverages the parallel computing advantages of multi-core processors, splitting the main computational tasks into multiple sub-problems for simultaneous execution. This allows for simultaneous solving of multiple sub-blocks, significantly reducing simulation computational complexity and effectively minimizing memory usage. This provides a high-precision, high-efficiency solution for dynamic voltage drop analysis of large-scale chip-package power networks.

[0012] The method includes the following steps;

[0013] Step 1: Block modeling of the packaged circuit system;

[0014] Step 2: Matrix sorting preprocessing;

[0015] Step 3: Pre-LU decomposition of the block matrix;

[0016] Step 4: Parallel solution of vector groups ;

[0017] Step 5: Inverse of the coefficient matrix Solve this problem;

[0018] Step 6: Structured decomposition of activation vectors;

[0019] Step 7: Parallel solution of vector groups ;

[0020] Step 8: Pad Interconnect Node Voltage Solve this problem;

[0021] Step 9: Parallel solution of sub-network node voltages ;

[0022] Step 10: Global voltage vector reconstruction;

[0023] Step 11: Calculate the activation vector and matrix update amount;

[0024] Step 12: LU decomposition of the low-rank matrix update quantity.

[0025] Step one is as follows: To achieve efficient analysis and simulation of the composite system corresponding to the chip-package power network, a structured block representation method is used to construct the admittance matrix of the composite system. Assume that the packaged power network integrates multiple components such as resistors R, capacitors C, inductors L, and mutual inductance M. These components together form a real symmetric positive semi-definite admittance submatrix, denoted as... This matrix comprehensively characterizes the electrical connections between components within the package, as well as the interaction characteristics between the package and external circuits. Each chip sub-network is also composed of components such as resistors and capacitors, forming its own independent real symmetric positive definite admittance sub-matrix; assuming the system contains m chip sub-networks, the admittance sub-matrices of these sub-networks are expressed as follows: ,in These matrices describe the electrical connections between components within the chip, but do not involve interactions with the package or other chip subnetworks; the electrical connections between the package and chip subnetworks are characterized by a specific set of column vectors and their transposes.

[0026] Specifically, define the interconnection matrix. and its corresponding transpose These matrices are used to describe the electrical characteristics of the Pad interconnect area, i.e. the connection points and connection methods between the package and the chip subnets.

[0027] The system matrix is ​​represented in block form as follows:

[0028]

[0029] in, To encapsulate the voltage vectors of the sub-network nodes, , For the first Voltage vector of each chip sub-network node For the Pad interconnect node voltage vector, These are the activation vectors for the corresponding sub-network nodes.

[0030] In step two, to suppress the growth of matrix filling elements during subsequent LU decomposition and improve the stability and efficiency of numerical computation, the Approximate Minimum Degree Permutation Algorithm (AMD) is used to partition the matrix. Perform sorting optimization; interconnection matrix and its transpose matrix The dimensional adaptation adjustment is completed synchronously following the sorting results of the corresponding block matrix;

[0031] In step three, the block matrices after sorting and optimization in step two are processed. , Perform LU decomposition in advance and store the decomposition results to support subsequent iterative calculations:

[0032]

[0033] in, It is a unit lower triangular matrix. It is an upper triangular matrix. ;

[0034] Step 4: Parallel solution of vector groups ;

[0035] Based on the Sherman-Morson-Woodbury (SMW) formula, and using the LU decomposition results obtained in step three, the following system of linear equations is solved in parallel to obtain the vector set. :

[0036]

[0037] in, and These are the low-rank update values ​​of the matrix. The LU decomposition results; the computation tasks of all sub-blocks are executed in parallel to improve the overall solution efficiency.

[0038] In step five, a coefficient matrix is ​​constructed based on the coupling and interconnection relationships of the block matrix. And solve for its inverse matrix:

[0039]

[0040] Combining the calculation results from step four The above formula can be simplified to:

[0041]

[0042] Finally, the inverse matrix of the coefficient matrix is ​​solved numerically:

[0043] ;

[0044] In step six, based on the block topology of the system matrix, the global excitation vector is... Decomposed into sub-vectors corresponding to each sub-network:

[0045]

[0046] in, for The activation vector corresponding to the (encapsulated sub-network) , For the first The excitation vectors corresponding to each chip sub-network This is the excitation vector corresponding to the Pad interconnect node.

[0047] In step seven, based on the SMW formula, and combining the LU decomposition results from step three with the excitation vectors from step six, the following system of linear equations is solved in parallel to obtain the vector set. :

[0048] .

[0049] In step eight, the result obtained in step five... With the vector group obtained in step seven Substituting into the block matrix coupling equation, solve for the Pad interconnect node voltage:

[0050]

[0051] This formula is derived by rearranging terms of the block linear equation system and is used to accurately characterize the coupling relationship between the voltage of the Pad interconnect node and the voltage of each sub-network node;

[0052] In step nine, the Pad interconnect node voltage obtained in step eight is used as a basis. The nodal voltages of each subnetwork are solved in parallel using the SMW formula:

[0053]

[0054] in, To encapsulate the voltage of sub-network nodes, , This refers to the voltage of the chip's sub-network nodes.

[0055] In step ten, the voltage vectors of each sub-network node obtained in step nine are... Interconnection node voltage with Pad The series merging is performed according to the original node topology order, and the global node voltage vector is reconstructed, which can be expressed by the formula:

[0056]

[0057] This vector represents the solution for the dynamic voltage drop of the chip-package power network at the current time step.

[0058] In step eleven, based on the time-series evolution characteristics of the dynamic voltage drop, the first... Global voltage vector at time step Excitation vector and system matrix (Depend on

[0059] (and Pad interconnection relationship constitutes), and the first is calculated through circuit dynamic equations. activation vector of time step With the low-rank update quantity of the system matrix The formula is:

[0060]

[0061] in, and This is a dynamically updated function defined based on circuit characteristics; superscript and Respectively characterize the first Time step and the The physical quantity of the time step, obtained through calculation Return to step six to participate in the iterative calculation of the next time step.

[0062] In step twelf, the first result obtained in step eleven... Low-rank update quantity of the time-step system matrix Perform LU decomposition to obtain the incremental decomposition results for each sub-block:

[0063]

[0064] in, The decomposition results Storage, for the first Iterative calculation of time steps (return to step four and repeat).

[0065] This invention relates to the field of power integrity analysis and chip-package co-simulation technology for very large-scale integrated circuits (VLSI), and has significant application value in the dynamic voltage drop (IR Drop) analysis of large-scale chip-package power distribution networks. In real-world scenarios, it is necessary to efficiently solve large sparse linear equation systems with multiple time steps, and the accuracy and speed of the solution directly affect the effectiveness of design verification and reliability analysis. This invention proposes a fast solution method for dynamic voltage drop across packages based on LU decomposition combined with the Sherman-Morrison-Woodbury (SMW) formula. This method innovatively introduces a chip-package partitioning solution strategy, transforming the original VLSI power network equations into a block structure, focusing on necessary coupled calculations, and avoiding the inefficient redundancy of repeated full-matrix decomposition. Simultaneously, it utilizes the SMW formula to perform low-rank incremental updates on the impact of the package network, quickly correcting the solution vector while ensuring computational accuracy. Furthermore, it fully leverages the parallel computing advantages of multi-core processors, splitting the main computational tasks into multiple sub-problems for simultaneous execution, significantly reducing simulation computational complexity and effectively reducing memory usage, providing a high-precision and high-efficiency solution for dynamic voltage drop analysis of large-scale chip-package power networks.

[0066] This invention innovatively adopts a partitioned and block-based solution strategy. Based on the characteristics of the chip and packaging, the large-scale sparse matrix is ​​decomposed into a structural model with multiple diagonal sub-blocks. It focuses on necessary coupled solutions, avoids the inefficiency of repeated calculations of the entire matrix, and significantly reduces computational complexity. It cleverly uses the Sherman-Morston-Woodbury formula to quickly update the effects introduced by the packaging, and obtains an accurate solution without re-decomposing the matrix at each step, which greatly improves the solution efficiency. Combined with the parallel computing capabilities of multi-core processors, it enables the simultaneous execution of solutions for multiple sub-blocks, further improving the computational speed. Attached Figure Description

[0067] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0068] Appendix Figure 1 This is a schematic diagram of the original sparse matrix structure in an embodiment of the present invention;

[0069] Appendix Figure 2 This is a schematic diagram of the sparse structure of the sorted matrix in an embodiment of the present invention;

[0070] Appendix Figure 3 This is a schematic diagram of the operation process in an embodiment of the present invention;

[0071] Appendix Figure 4 This is a schematic diagram comparing the time consumption of dynamic voltage drop block parallelization and direct solution in an embodiment of the present invention. Detailed Implementation

[0072] As shown in the figure, a method for solving dynamic voltage drop across a packaged network based on LU decomposition combined with the SMW formula is presented. This method treats the chip-package power network as a composite system consisting of a packaged portion and multiple chip sub-networks tightly connected via interconnect nodes (Pads). By introducing a chip-package partitioning solution strategy, the large-scale sparse matrix of the composite system is decomposed into a structural model with multiple diagonal sub-blocks based on the characteristics of the chip and package. This transforms the chip-package power network equation into a block structure, and avoids inefficient redundancy by focusing on necessary coupled calculations. Simultaneously, the SMW formula (Sherman-Morrison-Woodbury (SMW) formula) is used to perform low-rank incremental updates on the impact of the packaged network, quickly updating the effects introduced by the package. Accurate solutions can be obtained without re-decomposing the matrix at each step, significantly improving solution efficiency. The solution vector is quickly corrected while maintaining computational accuracy. Furthermore, the parallel computing advantages of multi-core processors are fully utilized, splitting the main computational tasks into multiple sub-problems for simultaneous execution. This allows for simultaneous solving of multiple sub-blocks, significantly reducing simulation computational complexity and effectively minimizing memory usage. This provides a high-precision, high-efficiency solution for dynamic voltage drop analysis of large-scale chip-packaged power networks.

[0073] The method includes the following steps;

[0074] Step 1: Block modeling of the packaged circuit system;

[0075] Step 2: Matrix sorting preprocessing;

[0076] Step 3: Pre-LU decomposition of the block matrix;

[0077] Step 4: Parallel solution of vector groups ;

[0078] Step 5: Inverse of the coefficient matrix Solve this problem;

[0079] Step 6: Structured decomposition of activation vectors;

[0080] Step 7: Parallel solution of vector groups ;

[0081] Step 8: Pad Interconnect Node Voltage Solve this problem;

[0082] Step 9: Parallel solution of sub-network node voltages ;

[0083] Step 10: Global voltage vector reconstruction;

[0084] Step 11: Calculate the activation vector and matrix update amount;

[0085] Step 12: LU decomposition of the low-rank matrix update quantity.

[0086] Step one is as follows: To achieve efficient analysis and simulation of the composite system corresponding to the chip-package power network, a structured block representation method is used to construct the admittance matrix of the composite system. Assume that the packaged power network integrates multiple components such as resistors R, capacitors C, inductors L, and mutual inductance M. These components together form a real symmetric positive semi-definite admittance submatrix, denoted as... This matrix comprehensively characterizes the electrical connections between components within the package, as well as the interaction characteristics between the package and external circuits. Each chip sub-network is also composed of components such as resistors and capacitors, forming its own independent real symmetric positive definite admittance sub-matrix; assuming the system contains m chip sub-networks, the admittance sub-matrices of these sub-networks are expressed as follows: ,in These matrices describe the electrical connections between components within the chip, but do not involve interactions with the package or other chip subnetworks; the electrical connections between the package and chip subnetworks are characterized by a specific set of column vectors and their transposes.

[0087] Specifically, define the interconnection matrix. and its corresponding transpose These matrices are used to describe the electrical characteristics of the Pad interconnect area, i.e. the connection points and connection methods between the package and the chip subnets.

[0088] The system matrix is ​​represented in block form as follows:

[0089]

[0090] in, To encapsulate the voltage vectors of the sub-network nodes, , For the first Voltage vector of each chip sub-network node For the Pad interconnect node voltage vector, These are the activation vectors for the corresponding sub-network nodes.

[0091] In step two, to suppress the growth of matrix filling elements during subsequent LU decomposition and improve the stability and efficiency of numerical computation, the Approximate Minimum Degree Permutation Algorithm (AMD) is used to partition the matrix. Perform sorting optimization; interconnection matrix and its transpose matrix The dimensional adaptation adjustment is completed synchronously following the sorting results of the corresponding block matrix;

[0092] In step three, the block matrices after sorting and optimization in step two are processed. , Perform LU decomposition in advance and store the decomposition results to support subsequent iterative calculations:

[0093]

[0094] in, It is a unit lower triangular matrix. It is an upper triangular matrix. ;

[0095] Step 4: Parallel solution of vector groups ;

[0096] Based on the Sherman-Morson-Woodbury (SMW) formula, and using the LU decomposition results obtained in step three, the following system of linear equations is solved in parallel to obtain the vector set. :

[0097]

[0098] in, and These are the low-rank update values ​​of the matrix. The LU decomposition results; the computation tasks of all sub-blocks are executed in parallel to improve the overall solution efficiency.

[0099] In step five, a coefficient matrix is ​​constructed based on the coupling and interconnection relationships of the block matrix. And solve for its inverse matrix:

[0100]

[0101] Combining the calculation results from step four The above formula can be simplified to:

[0102]

[0103] Finally, the inverse matrix of the coefficient matrix is ​​solved numerically:

[0104] ;

[0105] In step six, based on the block topology of the system matrix, the global excitation vector is... Decomposed into sub-vectors corresponding to each sub-network:

[0106]

[0107] in, for The activation vector corresponding to the (encapsulated sub-network) , For the first The excitation vectors corresponding to each chip sub-network This is the excitation vector corresponding to the Pad interconnect node.

[0108] In step seven, based on the SMW formula, and combining the LU decomposition results from step three with the excitation vectors from step six, the following system of linear equations is solved in parallel to obtain the vector set. :

[0109] .

[0110] In step eight, the result obtained in step five... With the vector group obtained in step seven Substituting into the block matrix coupling equation, solve for the Pad interconnect node voltage:

[0111]

[0112] This formula is derived by rearranging terms of the block linear equation system and is used to accurately characterize the coupling relationship between the voltage of the Pad interconnect node and the voltage of each sub-network node;

[0113] In step nine, the Pad interconnect node voltage obtained in step eight is used as a basis. The nodal voltages of each subnetwork are solved in parallel using the SMW formula:

[0114]

[0115] in, To encapsulate the voltage of sub-network nodes, , This refers to the voltage of the chip's sub-network nodes.

[0116] In step ten, the voltage vectors of each sub-network node obtained in step nine are... Interconnection node voltage with Pad The series merging is performed according to the original node topology order, and the global node voltage vector is reconstructed, which can be expressed by the formula:

[0117]

[0118] This vector represents the solution for the dynamic voltage drop of the chip-package power network at the current time step.

[0119] In step eleven, based on the time-series evolution characteristics of the dynamic voltage drop, the first... Global voltage vector at time step Excitation vector and system matrix (Depend on

[0120] (and Pad interconnection relationship constitutes), and the first is calculated through circuit dynamic equations. activation vector of time step With the low-rank update quantity of the system matrix The formula is:

[0121]

[0122] in, and This is a dynamically updated function defined based on circuit characteristics; superscript and Respectively characterize the first Time step and the The physical quantity of the time step, obtained through calculation Return to step six to participate in the iterative calculation of the next time step.

[0123] In step twelf, the first result obtained in step eleven... Low-rank update quantity of the time-step system matrix Perform LU decomposition to obtain the incremental decomposition results for each sub-block:

[0124]

[0125] in, The decomposition results Storage, for the first Iterative calculation of time steps (return to step four and repeat).

Claims

1. A method for solving dynamic voltage drop across a package based on LU decomposition combined with the SMW formula, characterized in that: The method treats the chip-package power network as a composite system consisting of a package portion and multiple chip sub-networks connected by interconnect nodes Pad. By introducing a chip-package partitioning solution strategy, the large-scale sparse matrix of the composite system is decomposed into a structural model with multiple diagonal sub-blocks based on the characteristics of the chip and package. This transforms the chip-package power network equation into a block structure and avoids inefficient redundancy by focusing on necessary coupled calculations. Simultaneously, the SMW formula is used to perform low-rank incremental updates on the effects of the encapsulation network, quickly updating the effects introduced by encapsulation and rapidly correcting the solution vector; the computational task is split into multiple sub-problems and executed synchronously, enabling multiple sub-blocks to be solved simultaneously.

2. The method for solving dynamic voltage drop across a package based on LU decomposition combined with the SMW formula according to claim 1, characterized in that: The method includes the following steps; Step 1: Block modeling of the packaged circuit system; Step 2: Matrix sorting preprocessing; Step 3: Pre-LU decomposition of the block matrix; Step 4: Parallel solution of vector groups ; Step 5: Inverse of the coefficient matrix Solve this problem; Step 6: Structured decomposition of activation vectors; Step 7: Parallel solution of vector groups ; Step 8: Pad Interconnect Node Voltage Solve this problem; Step 9: Parallel solution of sub-network node voltages ; Step 10: Global voltage vector reconstruction; Step 11: Calculate the activation vector and matrix update amount; Step 12: LU decomposition of the low-rank matrix update quantity.

3. The method for solving the dynamic voltage drop of a packaged circuit based on LU decomposition combined with the SMW formula according to claim 2, characterized in that: Step one specifically involves: constructing the admittance matrix of the composite system using a structured block representation method; assuming that the packaged power network integrates resistors R, capacitors C, inductors L, and mutual inductors M, forming a real symmetric positive semi-definite admittance submatrix, denoted as... This matrix comprehensively characterizes the electrical connections between components within the package and the interaction characteristics between the package and external circuits. Each chip sub-network is also composed of components such as resistors and capacitors, forming its own independent real symmetric positive definite admittance sub-matrix. Assuming the system contains m chip sub-networks, the admittance sub-matrices of these sub-networks are expressed as follows: ,in These matrices describe the electrical connections between components within the chip, but do not involve interactions with the package or other chip subnetworks; the electrical connections between the package and chip subnetworks are characterized by a specific set of column vectors and their transposes. Specifically, define the interconnection matrix. and its corresponding transpose These matrices are used to describe the electrical characteristics of the Pad interconnect area, i.e. the connection points and connection methods between the package and the chip subnets. The system matrix is ​​represented in block form as follows: in, This encapsulates the voltage vectors of the sub-network nodes. , For the first Voltage vector of each chip sub-network node For the Pad interconnect node voltage vector, These are the activation vectors for the corresponding sub-network nodes.

4. The method for solving the dynamic voltage drop of a packaged circuit based on LU decomposition combined with the SMW formula according to claim 3, characterized in that: In step two, an approximate minimum degree permutation algorithm is used to process the block matrix. Perform sorting optimization; interconnection matrix and its transpose matrix The dimensional adaptation adjustment is completed synchronously following the sorting results of the corresponding block matrix; In step three, the block matrices after sorting and optimization in step two are processed. , Perform LU decomposition in advance and store the decomposition results to support subsequent iterative calculations: in, It is a unit lower triangular matrix. It is an upper triangular matrix. ; Step 4: Parallel solution of vector groups ; Based on the SMW formula, and using the LU decomposition results obtained in step three, the following system of linear equations is solved in parallel to obtain a vector group. : in, and These are the low-rank update values ​​of the matrix. The LU decomposition results; the computation tasks of all sub-blocks are executed in parallel paradigm.

5. The method for solving the dynamic voltage drop of a packaged circuit based on LU decomposition combined with the SMW formula according to claim 4, characterized in that: In step five, a coefficient matrix is ​​constructed based on the coupling and interconnection relationships of the block matrix. And solve for its inverse matrix: Combining the calculation results from step four The above formula can be simplified to: Finally, the inverse matrix of the coefficient matrix is ​​solved numerically: ； In step six, based on the block topology of the system matrix, the global excitation vector is... Decomposed into sub-vectors corresponding to each sub-network: in, for The corresponding excitation vector, , For the first The excitation vectors corresponding to each chip sub-network This is the excitation vector corresponding to the Pad interconnect node.

6. The method for solving the dynamic voltage drop of a packaged circuit based on LU decomposition combined with the SMW formula according to claim 5, characterized in that: In step seven, based on the SMW formula, and combining the LU decomposition results from step three with the excitation vectors from step six, the following system of linear equations is solved in parallel to obtain the vector set. : 。 7. The method for solving the dynamic voltage drop of a packaged circuit based on LU decomposition combined with the SMW formula according to claim 6, characterized in that: In step eight, the result obtained in step five... With the vector group obtained in step seven Substituting into the block matrix coupling equation, solve for the Pad interconnect node voltage: This formula is derived by rearranging terms of the block linear equation system and is used to accurately characterize the coupling relationship between the voltage of the Pad interconnect node and the voltage of each sub-network node; In step nine, the Pad interconnect node voltage obtained in step eight is used as a basis. The nodal voltages of each subnetwork are solved in parallel using the SMW formula: in, To encapsulate the voltage of sub-network nodes, , This refers to the voltage of the chip's sub-network nodes.

8. The method for solving the dynamic voltage drop of a packaged circuit based on LU decomposition combined with the SMW formula according to claim 7, characterized in that: In step ten, the voltage vectors of each sub-network node obtained in step nine are... Interconnection node voltage with Pad The series merging is performed according to the original node topology order, and the global node voltage vector is reconstructed, which can be expressed by the formula: This vector represents the solution for the dynamic voltage drop of the chip-package power network at the current time step.

9. The method for solving the dynamic voltage drop of a packaged circuit based on LU decomposition combined with the SMW formula according to claim 8, characterized in that: In step eleven, based on the time-series evolution characteristics of the dynamic voltage drop, the first... Global voltage vector at time step Excitation vector and system matrix The first circuit is calculated using the circuit dynamic equation. activation vector of time step With the low-rank update quantity of the system matrix The formula is: in, and This is a dynamically updated function defined based on circuit characteristics; superscript and Respectively characterize the first Time step and the The physical quantity of the time step, obtained through calculation Return to step six to participate in the iterative calculation of the next time step.

10. The method for solving the dynamic voltage drop of a packaged circuit based on LU decomposition combined with the SMW formula according to claim 9, characterized in that: In step twelf, the first result obtained in step eleven... Low-rank update quantity of the time-step system matrix Perform LU decomposition to obtain the incremental decomposition results for each sub-block: in, The decomposition results Storage, for the first Iterative calculation of time steps.

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