A design method of a multi-modal flexible sensor adaptive signal conditioning system

Abstract

The application discloses a kind of multi-modal flexible sensor adaptive signal conditioning system design method, belong to flexible sensor signal conditioning technical field.The present application overcomes the defects of poor universality, performance compromise, high cost of mass production of existing conditioning circuit, adopts layered decoupling and dynamic reconstruction system-level architecture: through multi-modal feature analysis and demand mapping modeling, the feature vector composition of scene recognition is determined;Design configurable analog front end, integrate instrument amplifier, transimpedance amplifier, charge amplifier, bridge amplifier four parallel processing sub-modules, wherein charge and bridge amplifier adopt self-designed architecture with dynamic adaptive gain adjustment capability;Build heterogeneous digital processing platform with NPU, CPU, DSP as core, through cross-modal data fusion, scene recognition engine, dynamic hardware configuration combined with feedforward and feedback, loadable algorithm library and closed-loop optimization control law, realize the real-time scene reconstruction of hardware parameters and digital algorithm;Combined with domestic single-chip selection, rigid-flex PCB and automatic calibration, meet the demand of low-cost mass production.The present application realizes the native adaptation and performance optimization of single hardware platform to voltage, current, charge, impedance and other types of sensor signals, and can be widely applied in robot dexterous hand, medical monitoring, intelligent bandage, consumer motion monitoring and industrial monitoring fields.

Description

Technical Field

[0001] This invention belongs to the field of flexible sensor signal conditioning technology, specifically relating to an adaptive signal conditioning system design method suitable for multimodal flexible sensors. In particular, it addresses the technical problems of performance trade-offs, poor versatility, and high mass production costs caused by the huge differences in signal characteristics in traditional fixed-parameter conditioning circuits in various application scenarios such as robot dexterity hands, medical monitoring, smart bandages, consumer motion monitoring, and industrial monitoring, through hardware architecture innovation and software-hardware co-design. Background Technology

[0002] Flexible sensors are being widely used in healthcare, human-computer interaction, and the Industrial Internet of Things (IIoT). However, a key challenge they face is the significant differences in the operating modes and output signal characteristics (such as amplitude, frequency, impedance, and signal type) of sensors across various application scenarios. For example, medical ECG signals are low-frequency, weak voltage signals in the μV range, industrial piezoelectric vibration sensors output high-frequency charge signals in the mV range, while photoelectric or electrochemical sensors generate slowly varying current signals in the nA range. Traditional signal conditioning systems are typically optimized for a single scenario, employing amplification and filtering circuits with fixed parameters, which cannot maintain optimal performance in variable environments.

[0003] Existing adaptive solutions, such as dynamically adjusting the RC parameters of a single conditioning path using digital potentiometers or switched capacitor networks, are essentially still fine-tuning the parameters of a fixed topology circuit. This approach has fundamental limitations: 1. Architectural limitations: The adjustment range of a single signal path is limited, making it difficult to simultaneously meet the full spectrum of requirements, from weak DC voltages to high-frequency charge signals. 2. Performance trade-offs: Parameter adjustment is essentially a compromise of overall performance. 3. Poor versatility: The circuit topology is designed for specific sensing principles, making it difficult to adapt to different electrical characteristics such as voltage, current, charge, and impedance. 4. Cost and integration: The use of numerous discrete adjustable components is detrimental to the miniaturization and mass production of flexible circuit boards.

[0004] Therefore, the industry urgently needs a signal conditioning system design method that innovates at the system architecture level and can fundamentally solve multimodal compatibility, performance optimization, and mass production feasibility. Summary of the Invention

[0005] The technical problem to be solved by this invention is to overcome the shortcomings of existing flexible sensor conditioning circuits, such as poor versatility, inability to balance performance, and difficulty in low-cost mass production, and to provide a system-level solution based on the collaborative design of "configurable analog front-end + heterogeneous digital processing + scene adaptive algorithm".

[0006] To address the aforementioned technical problems, this invention proposes a hierarchical decoupling and dynamic reconfiguration design method. This method divides the complete signal chain into relatively independent hardware functional layers and software algorithm layers, and achieves dynamic matching between the two through intelligent decision-making. The method includes the following steps: Step S1: Multimodal Feature Analysis and Demand Mapping Modeling This study analyzes the signal characteristics of various sensors in a target application scenario set (including at least five types: robotic dexterity hand, medical health monitoring, smart bandage, consumer health and exercise monitoring, and industrial equipment monitoring) and establishes a three-dimensional mapping database of "scenario-signal characteristics-conditioning requirements". The signal characteristics include signal type, amplitude range, characteristic frequency bandwidth, dynamic range, and common-mode rejection requirements; the conditioning requirements include gain range, filter type and cutoff frequency, excitation source requirements, sampling rate, and power consumption budget.

[0007] 1.1 Multimodal signal feature extraction method Upon power-up or periodically, the system enters "learning mode," acquiring raw data from each sensor at a high sampling rate and wide dynamic range via a configurable analog front-end (AFE), and performs the following feature extraction process to define the feature vector composition used for scene recognition: a) Temporal feature extraction: Amplitude statistical characteristics: mean, variance, peak-to-peak value, root mean square (RMS) Waveform characteristics: zero-crossing rate, signal amplitude area (SMA), specific waveform template matching degree (e.g., QRS wave). Correlation and stability: inter-channel correlation coefficient, signal baseline drift b) Frequency domain feature extraction: Perform a Fast Fourier Transform (FFT) on the signal or calculate the power spectral density (PSD). Spectral characteristics: dominant frequency, spectral centroid, spectral entropy, and energy proportion of specific frequency bands (δ wave 0.5-4Hz, θ wave 4-8Hz, α wave 8-13Hz, β wave 13-30Hz). c) Time-frequency domain feature extraction (applicable to non-stationary signals): Short-time Fourier transform (STFT) or wavelet transform (WT) are used to extract the characteristics of the joint time and frequency distribution of signal energy. d) Modal-specific characteristics: Electrocardiogram (ECG): R wave peak value, standard deviation of RR interval (SDNN), root mean square of the difference between adjacent RR intervals (RMSSD) Electromyography / Strain: Muscle activation envelope, fatigue index (median frequency shift) Accelerometer: Static gravity component direction (attitude estimation), dynamic acceleration spectrum characteristics Chemical / Biological Sensors: Response Curve Slope, Steady-State Time, Peak Integral Value The extracted features are combined into a multidimensional feature vector, which serves as the input to the scene recognition model.

[0008] Step S2: Modular architecture design of configurable analog front-end (AFE) The innovation of designing a highly integrated and software-configurable analog front-end hardware platform lies in: 2.1 Hardware Configuration and Implementation of the Parallel Conditioning Submodule This invention integrates multiple basic conditioning sub-modules optimized for different signal types, including four core amplifier topologies, the composition, selection, and electrical connection design of which are as follows: (1) High-impedance instrumentation amplifier submodule (for voltage-type signals) Composition: Instrumentation amplifier with three operational amplifiers or current feedback structure, input impedance >10GΩ, common mode rejection ratio >100dB.

[0009] Hardware configuration: The domestically produced Chipsea CSA37F71 chip is selected. This chip has a built-in high-performance instrumentation amplifier PGA, supports 10 channels of fully differential or 20 channels of single-ended input, and has a programmable gain range of 1-256 times. It also has an embedded 16-bit SAR ADC, which is suitable for the acquisition of weak voltage signals such as ECG, EEG, and EMG.

[0010] Electrical connections: The sensor differential output is connected to the AINPx / AINNx pins; the on-chip PGA output is connected to the reconfigurable filter network via the internal MUX; and the CPU gain configuration command is received via the I2C interface.

[0011] (2) Transimpedance Amplifier (TIA) Submodule (for current-mode signals) Composition: It adopts a feedback transimpedance topology composed of low bias current and low noise operational amplifiers. The feedback resistor RF adopts a programmable resistor array, and the feedback capacitor CF is used for phase compensation.

[0012] Hardware configuration: Integrated into the domestic AWE AW8687x series AFE chip. This series of chips supports 2-4 channels of analog differential input, has a built-in two-stage PGA and 14-bit SAR ADC, supports up to 256x amplification, and has a built-in 12-bit DAC for output offset calibration. It is suitable for nA-level current detection of photodiodes and electrochemical sensors.

[0013] Electrical connections: The anode of the photodiode is connected to the virtual ground of the TIA input, and the cathode is connected to the bias voltage; the TIA output is connected to the reconfigurable filter network; the feedback resistor value is configured via the I2C interface to adjust the transimpedance gain.

[0014] (3) Charge amplifier submodule (for charge-type signals) - custom-designed architecture Since there are currently no mature commercially available dedicated AFE chips for charge amplifiers in China, this invention adopts a discrete, high-reliability self-designed scheme and achieves dynamic adaptive gain adjustment.

[0015] Composition: It consists of a low-noise JFET input stage operational amplifier (such as the domestic 3CPA103BM, with an input bias current of <5pA), a programmable integrating capacitor array, an automatic reset switch, and a bias resistor network.

[0016] Dynamic adaptive gain design: The integrating capacitor uses a 4-bit digitally controlled capacitor array with a capacitance range of 5pF to 80pF, in 5pF increments, corresponding to a charge sensitivity of 1mV / pC to 16mV / pC.

[0017] Gain control logic: Based on the scene recognition results (such as piezoelectric vibration, ultrasonic detection), the CPU writes control words to the digital switch of the capacitor array (such as the domestic Rongpai Semiconductor digital isolation analog switch) via the SPI bus to switch the feedback capacitor value in real time.

[0018] Gain adaptive closed loop: The DSP monitors the peak-to-peak value of the output signal. If DRU < 20% and there is no saturation, the CPU gradually reduces the integrating capacitor to increase the gain. If the output is saturated, the reset switch is immediately opened to discharge the charge and the integrating capacitor is increased.

[0019] Electrical connections: The piezoelectric sensor output is connected to the inverting input of the charge amplifier, and the non-inverting input is connected to signal ground.

[0020] Feedback loop: A programmable capacitor array is connected in parallel with a high-value resistor (>100MΩ, providing a DC bias path).

[0021] The output is connected to a reconfigurable filter network.

[0022] Control interface: 3-wire SPI (CS / SCLK / MOSI) connected to the GPIO of the heterogeneous processor CPU.

[0023] (4) Bridge amplifier submodule (for impedance / strain sensors) - custom-designed architecture Since there is currently no dedicated AFE chip for a full-function bridge circuit that integrates programmable excitation and digital correction in China, this invention adopts a self-designed hybrid architecture that combines a highly integrated domestic AFE with peripheral programmable excitation.

[0024] Composition: Based on the PGA+ADC of the domestically produced CSA37F71 chip, combined with a self-designed programmable bridge excitation source and digital domain baseline tracking correction algorithm.

[0025] Dynamic adaptive gain and excitation design: Programmable excitation source: A 12-bit DAC (integrated in CSA37F71 or external domestic SGM5347) with low-noise op-amp buffer is used to generate a programmable bridge excitation voltage of 0.5V~3.3V; or a 250µA~2mA programmable constant current source is used.

[0026] Gain Adaptive: Utilizing the internal PGA of CSA37F71, the gain range is 1~256 times, and the CPU dynamically adjusts the PGA gain according to the bridge output sensitivity.

[0027] Automatic baseline tracking: Drawing inspiration from the built-in baseline tracking algorithm in the AW8687x from Awinic Technology, software baseline tracking is implemented in the DSP—real-time calculation of the signal sliding window mean, dynamic adjustment of the DAC output offset compensation code, and elimination of temperature drift and common-mode offset.

[0028] Electrical connections: The excitation terminal of the Wheatstone bridge is connected to the output of a programmable DAC.

[0029] The differential output of the bridge is connected to the differential input channels (AINP / AINN) of the CSA37F71.

[0030] The PGA output is connected to the ADC via an internal MUX or directly output to a reconfigurable filter network.

[0031] The DAC control unit communicates with the CPU via I2C.

[0032] 2.2 Unified Interface and Multimodal Adaptation The design incorporates a unified sensor physical interface, which uses a built-in automatic identification circuit (impedance measurement, bias detection) to initially determine the sensor type and route the signal to the corresponding signal conditioning submodule.

[0033] 2.3 Reconfigurable Filtering Networks A wide range of software configurations for filter types (low-pass, high-pass, band-pass, notch) and cutoff frequencies are achieved using a switched capacitor array or a configurable operational amplifier feedback network. The parameter calculation and switching control algorithm are described in step S3.

[0034] 2.4 High Dynamic Range ADC Path High-resolution Σ-Δ ADCs (such as the domestically produced Yunxin Microelectronics 24-bit Σ-Δ ADC) are used, and their sampling rate and pre-amplifier anti-aliasing filter parameters can be dynamically configured according to the scenario.

[0035] Step S3: Design of Intelligent Digital Processing Architecture Based on Heterogeneous Processors The design utilizes a heterogeneous processor as its core decision-making and processing unit, with innovations in task division and dynamic scheduling. The heterogeneous processor comprises a neural network processing unit (NPU), a central processing unit (CPU), and a digital signal processor (DSP).

[0036] 3.1 Cross-modal data alignment and fusion strategy To achieve accurate scene recognition and decision-making based on multi-sensor information collaboration, the system adopts the following strategies: a) Timestamp synchronization: At the hardware level, a unified clock source is provided for ADC sampling of all AFE channels, and a high-precision hardware timestamp from the heterogeneous processor is generated for each data sample.

[0037] At the software level, a global time base is maintained to ensure that data streams from different sensors are precisely aligned on the timeline.

[0038] b) Data alignment algorithm: For asynchronously sampled data streams, linear interpolation or spline interpolation is used to resample to a unified time grid.

[0039] For phase differences caused by sensor response delays (such as chemical sensors), compensation and alignment are performed on the time axis using pre-calibrated delay parameters.

[0040] c) Feature-level and decision-level fusion: Feature-level fusion: After extraction, feature vectors from different sensors are directly concatenated to form a higher-dimensional joint feature vector, which is then input into a unified neural network model for scene classification.

[0041] Decision-level fusion: Each sensor modality is first predicted for the initial scene probability by an independent lightweight classifier, and then the prediction results of each modality are weighted and synthesized by a meta-decision maker (Bayesian averaging, DS evidence theory or shallow neural network).

[0042] Adaptive fusion weights: dynamically adjusted based on the instantaneous signal-to-noise ratio (SNR) or confidence level of each modal signal, with the weights of low-quality modal signals automatically reduced.

[0043] 3.2 Scene Recognition Engine (NPU) Algorithm Implementation a) Model training and deployment: In the offline phase, labeled multimodal sensor data covering the target scenario (stationary, walking, running, sleeping, device vibration, etc.) are used to train lightweight neural networks (such as one-dimensional convolutional neural networks 1D-CNN, temporal convolutional networks TCN, or Transformer encoders).

[0044] The model learns the mapping relationship from the fused feature vectors to scene labels. The trained model is then quantized and deployed on the NPU of a heterogeneous processor.

[0045] b) Online reasoning and decision output: When running online, the NPU periodically performs forward propagation inference on the fused features extracted in the latest time window.

[0046] The model output probability distribution vector P = [p1, p2, ..., p n ].

[0047] Decision-making rules: Threshold decision: If pᵢ > θ_high (e.g., 0.85), immediately determine it as scenario i.

[0048] Hysteresis comparison decision: Introduce a state machine, and trigger scene switching only when the probability of the new scene p_new is consistently higher than the probability of the current scene p_current by more than the threshold θ_hysteresis (e.g., 0.1) and remains so for a period of time (e.g., 3 inference cycles).

[0049] The decision output is a clear scene ID and confidence level.

[0050] 3.3 Implementation of Dynamic Hardware Configuration Management (CPU) Algorithm a) Feedforward initial configuration: After receiving the scene ID, the CPU reads the optimal AFE parameter set (gain, filter type and cutoff frequency, excitation source settings, ADC sampling rate) preset for that scene from the non-volatile memory.

[0051] Write to each hardware unit of the AFE via the SPI / I2C bus in a predetermined order (turn off the excitation source first → set the gain → configure the filter → set the ADC → turn on the excitation source).

[0052] b) Feedback-based closed-loop optimization (model-driven adaptive control): Performance metrics monitoring: The DSP continuously calculates the signal-to-noise ratio (SNR) and dynamic range utilization (DRU) of the output signal.

[0053] SNR = 20 * log10(Asignal / Anoise) DRU = (Vpp_observed / Vfs_adc) * 100% Control law (taking PGA gain adaptive control as an example): If DRU < 20%, the judgment gain is too low and there is a risk of quantization noise. Gain_new = Gain_current * (30% / DRU) (with an upper limit).

[0054] If DRU > 80%, the signal is considered to be at risk of saturation, and Gain_new = Gain_current * (70% / DRU) (adjusted downwards).

[0055] Fine-tuning of filter parameters: If the FFT detects a 50 / 60Hz power frequency interference spike, the digital notch filter is automatically enabled or strengthened.

[0056] If the high-frequency component SNR of the signal drops sharply, the cutoff frequency of the analog low-pass filter should be appropriately reduced to suppress broadband noise.

[0057] Optimized execution: The CPU generates a new AFE configuration command based on the control law calculation results, writes it into the register through the digital bus, and completes the online adaptation of hardware parameters.

[0058] 3.4 Loadable Digital Signal Processing Library (DSP) Algorithm Implementation The DSP dynamically loads the corresponding digital signal processing algorithm library from external memory based on the current scene ID, and establishes a real-time processing pipeline: digital filtering → feature extraction → result output.

[0059] Step S4: Cost and Integration Optimization Design for Mass Production To meet the low-cost mass production requirements of consumer applications, the following collaborative design is implemented: Selection of core chip localization and integration: The domestic single-chip AFE solution integrating multiple PGAs, filters, ADCs and MCUs was selected.

[0060] Rigid-Flex PCB Design: The core processing chip is placed in the rigid area, while the sensor interface and traces are placed in the flexible area.

[0061] Standardized interfaces and modularity: Define a unified sensor interface socket and communication protocol.

[0062] Automated calibration and testing: Design a software-based digital calibration process, with calibration completed in one go at the end of the production line via ATE.

[0063] Step S5: System Integration and Verification The hardware modules designed above were integrated with embedded software to build a prototype system, and the accuracy, response speed and performance indicators of the system’s automatic switching between multiple scenarios were verified.

[0064] Beneficial effects of the present invention Disruptive versatility: Through parallel and reconfigurable design of multiple sub-modules at the hardware level, a single system can natively support multiple sensing principles such as voltage, current, charge, and impedance.

[0065] Optimal performance in specific scenarios: The "scene recognition + dynamic hardware configuration" model is adopted to achieve the optimal hardware and algorithm parameters for the current scenario.

[0066] Independent and controllable key modules: For key modules such as charge amplifiers and bridge amplifiers that lack domestically produced commercial chips, a self-designed architecture with dynamic adaptive gain adjustment capability is proposed to fill the gap in domestic production.

[0067] Significant technological innovation: a leap from "fine-tuning single-path parameters" to system-level innovation of "dynamic reconstruction of hardware and algorithms based on scene recognition".

[0068] Excellent mass production economy: Through highly integrated domestic chips, rigid-flex PCBs and software-defined functions, it meets the miniaturization and flexibility requirements of wearable devices.

[0069] Strong scalability: The software-defined architecture supports the expansion to new sensor types by updating the configuration database and algorithm library. Attached Figure Description

[0070] Figure 1 This is an overview flowchart of the design method of the present invention.

[0071] Figure 2 This is a block diagram of the core hardware architecture of the system of the present invention.

[0072] Figure 3 This is a schematic diagram of the internal functional modules and signal routing of the configurable analog front-end (AFE) (update needed: refine the parallel structure of the four amplifiers).

[0073] Figure 4 A flowchart of task division and data processing for heterogeneous processors (to be updated: to reflect cross-modal alignment, feature fusion, and closed-loop control laws).

[0074] Figure 5 This is a schematic diagram of a state machine that adapts to five scenarios.

[0075] Figure 6 A schematic diagram of cost optimization design for mass production (rigid-flex PCB and modular design). Detailed Implementation

[0076] I. System Architecture Overview like Figure 1As shown, the design method of this invention follows the process of "analysis-design-implementation-verification". First, a multi-scenario requirement model is established (S1), which guides the collaborative design of configurable hardware (S2) and intelligent software (S3), and incorporates the concept of cost optimization (S4). Finally, integration and verification are performed (S5).

[0077] like Figure 2 , Figure 3 As shown, the core hardware of the adaptive signal conditioning system of this invention consists of the following components: a sensor array, a configurable analog front-end (AFE), a heterogeneous processor (integrating NPU, CPU, and DSP), a memory, and a power management module. The AFE integrates four parallel conditioning sub-modules—a high-impedance instrumentation amplifier, a transimpedance amplifier, a charge amplifier, and a bridge amplifier—to adapt to voltage, current, charge, and impedance / strain sensors, respectively. The outputs of each sub-module are digitized via a reconfigurable filter network and a high dynamic range ADC path, and then interconnected with the heterogeneous processor through a high-speed digital bus (SPI / I2C) to form a closed-loop link for sensing, decision-making, and execution.

[0078] Example 1: Consumer Health and Fitness Monitoring Wristband This embodiment demonstrates how to design a low-cost, high-performance smart wristband core module using the method of the present invention, focusing on the collaborative operation of the instrumentation amplifier and the transimpedance amplifier.

[0079] Demand Mapping (S1): Wristband integrating a single-lead ECG electrode (voltage signal, 0.5-40Hz, 0.1-5mV), a triaxial accelerometer (voltage signal, 0-50Hz), and a photoelectric pulse wave (PPG) sensor (current signal, 0.1-10Hz, nA level). The core requirements are motion artifact suppression and low power consumption.

[0080] AFE and Hardware Design (S2, S4): Chip selection: The domestic CSA37F71 (integrated instrumentation amplifier PGA, multi-channel ADC) from Chipsea Technologies and the AW8687x (integrated transimpedance amplifier TIA) from Awinic Technology were selected.

[0081] Hardware connection: The ECG electrode is connected to the differential PGA channel of the CSA37F71 and configured in instrumentation amplifier mode with a gain of 1 to 256 times programmable.

[0082] The PPG photodiode is connected to the TIA input of the AW8687x, and the feedback resistor is adjustable via I2C (10kΩ~10MΩ).

[0083] The accelerometer is directly connected to the auxiliary ADC input of the CSA37F71.

[0084] PCB design: A rigid-flex board is used, with the core chip placed in the rigid area and the sensor pads and flexible traces extending to the wristband contact area.

[0085] Software and Algorithm Implementation (S3): Feature extraction and alignment: The system uses a 200Hz synchronous sampling accelerometer and ECG to extract the RMS acceleration, 0.5-3Hz frequency band energy, and ECG RR interval standard deviation and waveform entropy every 2 seconds. After hardware timestamp alignment, a 4-dimensional feature vector is formed.

[0086] Intelligent recognition: A lightweight 1D-CNN model is deployed in the NPU to output scene probabilities (stationary / walking / running), and scene IDs are switched using hysteresis comparison decision (θ_hysteresis=0.1, for 3 consecutive windows).

[0087] Dynamic configuration: After switching to "walking mode", the CPU performs feedforward configuration: the ECG gain is reduced from 1000 to 600, the TIA feedback resistor of PPG is adjusted from 1MΩ to 500kΩ, and the accelerometer filter cutoff frequency is reduced from 50Hz to 20Hz.

[0088] Closed-loop optimization: The DSP continuously monitors the dynamic range utilization (DRU) of the ECG channel. When the DRU drops to 15%, the CPU calculates the gain according to the control law Gain_new = Gain_current × (30% / DRU). To prevent motion artifact saturation, the gain is limited to 800 and then written to the PGA register via SPI to complete the adaptive gain adjustment.

[0089] Verification results: The tested system completes recognition and reconfiguration within 2-3 seconds after the user's status changes. The accuracy of heart rate detection under strenuous exercise is more than 20% higher than that of the traditional fixed parameter solution, and the battery life meets the 24-hour requirement.

[0090] Example 2: Industrial Equipment Monitoring and Robotic Dexterity Hand This embodiment demonstrates how to apply the method of the present invention to design a multimodal signal conditioning module suitable for industrial piezoelectric vibration monitoring and robot dexterity hand tactile perception, highlighting the self-designed architecture of the charge amplifier and bridge amplifier and their dynamic adaptive gain adjustment capability.

[0091] Demand Mapping (S1): Industrial scenarios require monitoring of piezoelectric accelerometers (charge signal, 0.1Hz~10kHz, 0.1pC~1000pC) and strain gauge force sensors at the dexterous fingertips of robots (impedance / bridge signal, DC~1kHz, full-scale output 0.5mV / V~10mV / V). The core requirements are wide bandwidth adaptation, wide dynamic range, and resistance to harsh environments.

[0092] AFE Hardware Design – Charge Amplifier Submodule (Self-designed): Composition: It adopts a domestic 3CPA103BM JFET input operational amplifier (input bias current <5pA, GBW=10MHz), and the feedback loop is connected to a 4-bit programmable integrating capacitor array (controlled by domestic Rongpai Semiconductor digital switches, with capacitor values ​​of 5pF / 10pF / 20pF / 40pF, which can be combined to achieve 5pF~80pF, in 5pF steps). A high-value resistor (100MΩ) is connected in parallel to provide a DC bias path, and a MOSFET reset switch is set for fast discharge.

[0093] Electrical connections: The coaxial output of the piezoelectric sensor is connected to the inverting input of the charge amplifier, and the non-inverting input is connected to analog ground.

[0094] The digital control terminal of the feedback capacitor array is connected to the GPIO of the heterogeneous processor via a 3-wire SPI (CS / SCLK / MOSI).

[0095] The amplifier output is connected to a reconfigurable filter network (configured as a bandpass filter with an adjustable lower limit of 0.1Hz and an upper limit of 10kHz).

[0096] Dynamic adaptive gain mechanism: Feedforward configuration: The CPU reads the preset integral capacitor value from the configuration library based on the scene ID (such as "high frequency vibration analysis" or "low frequency impact detection") identified by the NPU.

[0097] Feedback optimization: The DSP calculates the peak-to-peak value (Vpp) and effective value (RMS) of the ADC sampled signal in real time to evaluate the dynamic range utilization (DRU). If DRU < 20% and there is no saturation, the CPU reduces the integrating capacitor (increasing gain) by setting C_new = C_current × (DRU / 30%). If the output is saturated, the reset switch is immediately closed, and the integrating capacitor is increased by setting C_new = C_current × 1.5 to prevent subsequent saturation. All adjustments are completed by rewriting the capacitor array control word via SPI.

[0098] AFE Hardware Design – Bridge Amplifier Submodule (Self-designed Hybrid Architecture): Composition: Based on the PGA+ADC of the domestic CSA37F71 chip, combined with an external programmable excitation DAC (domestic SGM5347, 12-bit, output 0~3.3V) and a software baseline tracking algorithm running in the DSP.

[0099] Electrical connections: The excitation terminal of the Wheatstone bridge is connected to the DAC output buffer.

[0100] The differential output of the bridge is connected to the differential PGA input (AINP / AINN) of the CSA37F71.

[0101] The PGA output is connected to a reconfigurable filter network (configured as a low-pass filter with an adjustable cutoff frequency of 100Hz to 1kHz) via an internal MUX.

[0102] The DAC control unit communicates with the CPU via I2C, and the PGA gain is configured via SPI.

[0103] Dynamic adaptive gain and excitation adjustment: Adaptive excitation voltage: The CPU presets the initial excitation voltage based on the scene ID (e.g., 2.5V is commonly used for metal strain gauges). The DSP monitors the DC baseline of the bridge output. If the baseline exceeds the common-mode range of the PGA input, the excitation voltage is adjusted in steps (10mV step) to reduce offset by adjusting the DAC output code value.

[0104] PGA gain adaptive: The DSP calculates the DRU signal. When DRU < 20%, the CPU increases the PGA gain level (e.g., from 16x to 32x); when DRU > 80%, the gain level decreases.

[0105] Baseline drift digital correction: The DSP performs sliding window mean filtering on the ADC data (window length 1 second), extracts the DC drift in real time, and dynamically adds it to the compensation term of the DAC output code to achieve closed-loop baseline locking, which is equivalent to the automatic zeroing function in a traditional bridge amplifier.

[0106] Intelligent digital processing and closed-loop verification (S3, S5): Scene recognition: The NPU extracts features (time-domain zero-crossing rate, frequency-domain dominant frequency, and impact pulse width) from the raw signals initially acquired by the AFE and identifies them as either "piezoelectric vibration monitoring" or "strain sensing" modes.

[0107] Dynamic reconfiguration: Taking "piezoelectric vibration monitoring" as an example, the CPU executes: Configure the charge amplifier integrating capacitor to 20pF (corresponding to a sensitivity of approximately 50mV / pC).

[0108] Configure the reconfigurable filter network to a bandpass filter of 0.1Hz to 10kHz.

[0109] The ADC sampling rate is configured to be 25.6kHz.

[0110] Instruct the DSP to load the vibration analysis algorithm library (including FFT and envelope demodulation).

[0111] Adaptive operation: The system continuously monitors the signal amplitude. When the impact signal causes the charge amplifier output to approach saturation, the closed-loop optimization immediately switches the integrating capacitor to 40pF, reducing the gain by half. At the same time, the DSP compensates for the amplification factor through digital gain to ensure the accuracy of the amplitude in subsequent spectrum analysis.

[0112] Integration Testing: The module was integrated into an industrial piezoelectric accelerometer and a strain-sensitive tactile array for a robot's dexterous hand. Field tests showed that the system can complete scene recognition and hardware reconfiguration within 5ms, achieves a charge measurement dynamic range of 100dB, and exhibits 15 times better temperature drift suppression for bridge measurements compared to traditional uncorrected circuits, meeting the requirements of industrial environments and precision force control.

[0113] As can be seen from the two embodiments above, the design method proposed in this invention, through deep collaboration between hardware reconfigurability (parallel operation of four amplifiers, programmable capacitor array, and programmable excitation DAC) and software intelligent decision-making (scene recognition, model-driven control law, and closed-loop optimization), successfully achieves high-performance adaptive conditioning of four types of sensor signals—voltage, current, charge, and impedance—on a single hardware platform. In particular, for key modules such as charge amplifiers and bridge amplifiers, for which there are currently no domestically produced commercial chips, the self-designed architecture proposed in this invention fills a domestic gap. Its dynamic adaptive gain adjustment capability has been fully verified in industrial monitoring and robotic tactile perception scenarios, demonstrating both technological advancement and mass production feasibility.

[0114] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, various modifications, substitutions, and variations can be made to the embodiments without departing from the principles and spirit of the present invention, and all such modifications and variations should be covered within the protection scope of the present invention.

Claims

1. A design method for an adaptive signal conditioning system for a multimodal flexible sensor, characterized in that, Includes the following steps: Step S1: Multimodal feature analysis and demand mapping modeling, establish a three-dimensional mapping database of "scene-signal features-conditioning requirements", and clarify the composition of multi-dimensional feature vectors used for scene recognition; Step S2: Modular architecture design of configurable analog front end (AFE), integrating parallel conditioning sub-modules including instrumentation amplifier, transimpedance amplifier, charge amplifier, and bridge amplifier, and designing reconfigurable filter network and configurable ADC path; Step S3: Design of intelligent digital processing architecture based on heterogeneous processors, through scene recognition engine, dynamic hardware configuration management, loadable digital signal processing library and adaptive closed-loop optimization, to realize dynamic reconfiguration of hardware and algorithms; Step S4: Focusing on cost and integration optimization design for mass production, adopting domestically produced single-chip, rigid-flex PCB and automated calibration; Step S5: System integration and verification.

2. The design method according to claim 1, characterized in that, The multidimensional feature vector composition in step S1 includes: time-domain amplitude statistical features, waveform features, channel correlation features; frequency-domain spectral centroid and frequency band energy proportion features; time-frequency domain wavelet / STFT energy distribution features; and modal-specific features of ECG, electromyography, accelerometer, and chemical sensor; the features are aligned and fused across modalities to form a joint feature vector.

3. The design method according to claim 1, characterized in that, The parallel conditioning submodule mentioned in step S2 includes: The instrumentation amplifier submodule uses the domestically produced CSA37F71 chip from Chipsea Technologies, and is used for weak voltage signals such as ECG and EEG. The transimpedance amplifier submodule uses the domestically produced AW8687x series chip from Awinic Electronics, and is used for current signals from photodiodes and electrochemical sensors. The charge amplifier submodule adopts a self-designed architecture, consisting of a low-noise JFET operational amplifier, a 4-bit programmable integrating capacitor array, an automatic reset switch, and a bias resistor network, and has dynamic adaptive gain adjustment capability based on the SPI interface. The bridge amplifier submodule adopts a self-designed hybrid architecture, with the domestic CSA37F71 PGA+ADC as the core, combined with a programmable DAC excitation source and DSP software baseline tracking algorithm to achieve programmable excitation voltage / current, adaptive gain and automatic temperature drift compensation.

4. The design method according to claim 3, characterized in that, The programmable integrating capacitor array of the charge amplifier submodule is a 4-bit digitally controlled capacitor array with a capacitance value range of 5pF to 80pF, in 5pF increments. The CPU dynamically adjusts the charge gain by switching the capacitance value in real time via the SPI bus based on the scene recognition results and the DRU index fed back by the DSP.

5. The design method according to claim 3, characterized in that, The programmable excitation source of the bridge amplifier submodule is a 12-bit DAC with an excitation voltage programming range of 0.5V to 3.3V or an excitation current programming range of 250µA to 2mA. The software baseline tracking algorithm running in the DSP dynamically adjusts the DAC output offset compensation code by calculating the mean of the sliding window of the ADC signal, thereby eliminating temperature drift and common-mode offset.

6. The design method according to claim 1, characterized in that, The implementation of the scene recognition engine in step S3 includes: offline training of a lightweight neural network and quantization deployment on the NPU; online inference output of scene probability distribution; and the adoption of a switching decision rule that combines threshold decision and hysteresis comparison.

7. The design method according to claim 1, characterized in that, The adaptive closed-loop optimization in step S3 includes: the DSP periodically calculates the signal-to-noise ratio (SNR) and dynamic range utilization (DRU) of the output signal; the CPU performs online fine-tuning of the PGA gain and filter cutoff frequency according to a preset control law; the control law includes the gain adaptive adjustment formula based on DRU: Gain_new = Gain_current × (Target_DRU / DRU).

8. The design method according to claim 1, characterized in that, The domestically produced single-chip AFE solution mentioned in step S4 is selected from Chipsea Technologies CSA37F71, Awinic Technology AW8687x, or Yunxin Microelectronics high-precision Σ-Δ ADC series; The rigid-flex PCB design places the core processing chip in the rigid area and the sensor interface and traces in the flexible area.

9. A multimodal flexible sensor adaptive signal conditioning system, constructed using the design method described in any one of claims 1 to 8, characterized in that, include: The configurable analog front end (AFE) integrates four parallel conditioning sub-modules: instrumentation, transimpedance, charge, and bridge, as well as a reconfigurable filter network and a configurable ADC. The heterogeneous processor includes an NPU, CPU, and DSP, which respectively perform scene recognition, hardware configuration management, and digital signal processing. The memory stores the preset AFE parameter set and the loadable DSP algorithm library; Power management module.

10. The system according to claim 9, characterized in that, The charge amplifier submodule and bridge amplifier submodule are designed independently based on the architecture described in claim 4 or 5, and are not compatible with any domestically produced commercial chips. They have dynamic adaptive gain adjustment and parameter software configurability capabilities.

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