Display device

Abstract

The application relates to a display device. The pixel circuit in the display device comprises an amplitude modulation module and a pulse width modulation module. The amplitude modulation module comprises a first capacitor, a first coupling control unit, a second coupling control unit and a driving unit. In a data writing stage, the first coupling control unit receives and outputs a preset voltage signal to a first end of the first capacitor; the driving unit receives a PAM data signal and stores the PAM data signal to the first capacitor. In a comparison light emitting stage, the second coupling control unit receives and outputs a first power voltage signal to the first end of the first capacitor, and a voltage difference at the first end of the first capacitor is coupled to the driving unit. Under the action of a first light emitting control signal, the driving unit outputs a driving current signal to a light emitting device based on the voltage difference, the PAM data signal and the first power voltage signal; wherein the second coupling control signal is valid earlier than the first light emitting control signal. The display consistency of the display device is high.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display device. Background Technology

[0002] LED (light-emitting diode) devices have gradually become commonly used light-emitting devices in display devices due to their advantages such as small size, fast response speed, high luminous efficiency, strong stability and long service life.

[0003] The pixel circuits in a display device can drive LED devices to emit light using pulse width modulation (PWM) and pulse amplitude modulation (PAM). Specifically, the amplitude modulation module in the pixel circuit outputs a drive current based on the power supply voltage and the PAM signal to drive the LED device. However, an IR drop occurs in the power supply path, causing differences in the power supply voltage delivered to multiple pixel circuits. This difference affects the magnitude of the drive current output by each pixel circuit, which in turn affects the light intensity of each LED device, ultimately impacting the display uniformity of the display device. Summary of the Invention

[0004] Therefore, it is necessary to provide a display device with high display uniformity.

[0005] This application provides a display device, including: a light-emitting device for constituting a display pixel and a pixel circuit connected to the light-emitting device; the pixel circuit includes:

[0006] A pulse width modulation module is connected to the PWM data output terminal; it is used to receive the PWM data signal output by the PWM data output terminal and output a light emission duration control signal according to the PWM data signal.

[0007] An amplitude modulation module, the amplitude modulation module comprising:

[0008] First capacitor;

[0009] The first coupling control unit is connected to the target voltage output terminal, the first coupling control signal output terminal, and the first terminal of the first capacitor;

[0010] The second coupling control unit is connected to the first power output terminal, the second coupling control signal output terminal and the first terminal of the first capacitor;

[0011] The driving unit is connected to the second terminal of the first capacitor, the first power output terminal, the PAM data output terminal, the first light emission control signal output terminal, the pulse width modulation module, and the light emission device.

[0012] During the data writing phase, the first coupling control unit, under the action of the first coupling control signal output from the first coupling control signal output terminal, receives and outputs the preset voltage signal output from the target voltage output terminal to the first terminal of the first capacitor; the driving unit receives the PAM data signal output from the PAM data output terminal and stores it in the first capacitor.

[0013] During the comparison light emission stage, under the action of the second coupling control signal output from the second coupling control signal output terminal, the second coupling control unit receives and outputs the first power supply voltage signal output from the first power supply output terminal to the first terminal of the first capacitor, and the voltage difference at the first terminal of the first capacitor is coupled to the driving unit; under the action of the first light emission control signal output from the first light emission control signal output terminal, the driving unit outputs a driving current signal to the light emission device based on the voltage difference, the PAM data signal, and the first power supply voltage signal; the duration of the driving unit outputting the driving current signal is determined according to the light emission duration control signal; wherein, the second coupling control signal is effective earlier than the first light emission control signal.

[0014] In the aforementioned display device, during the data writing phase, the first coupling control unit, under the action of the first coupling control signal, receives and outputs a preset voltage signal to the first terminal of the first capacitor. The driving unit receives the PAM data signal output from the PAM data output terminal and stores it in the first capacitor. During the comparison and light emission phase, under the action of the second coupling control signal, the second coupling control unit outputs a first power supply voltage signal to the first terminal of the first capacitor. The voltage difference at the first terminal of the first capacitor is coupled to the driving unit. Under the action of the first light emission control signal output from the first light emission control signal output terminal, the driving unit outputs a driving current signal to the light-emitting device based on the voltage difference, the PAM data signal, and the first power supply voltage signal. Thus, the driving current signal output by the driving unit is related to the preset voltage signal but not to the first power supply voltage signal. Since the transmission path of the preset voltage signal does not require current flow, the voltage drop of this path is significantly lower than that of the power supply path of the first power supply voltage signal. The potential of each pixel circuit in the display device that receives the preset voltage signal is more stable, resulting in higher consistency of the driving current signals output by the driving units of each pixel circuit, and consequently, more uniform brightness of each light-emitting device, leading to higher display consistency of the display device. Furthermore, since the second coupling control signal is effective earlier than the first light emission control signal, the first power supply voltage signal can be transmitted to the driving unit before the driving unit outputs the driving current signal. When the driving unit generates the driving current, the voltage difference of the first capacitor coupling is more stable, and the driving current signal generated based on this voltage difference is more stable, thereby further improving the display consistency of the display device and resulting in a better display effect.

[0015] In one embodiment, the amplitude of the preset voltage signal is less than the amplitude of the first power supply voltage signal.

[0016] In the above embodiments, by making the amplitude of the preset voltage signal lower than the amplitude of the first power supply voltage signal, the voltage of the PAM data signal can be reduced, so that the PAM data signal can meet the driving requirements of the driving unit without using a higher voltage. This reduces the driving voltage requirements of the driving circuit and decreases its workload. Simultaneously, with the driving voltage of the driving circuit reduced, its own power consumption also decreases, thereby optimizing the overall power consumption of the display device.

[0017] In one embodiment, the amplitude modulation module further includes a first reset unit; a first end of the first reset unit is connected to the driving unit and the second end of the first capacitor, and a second end of the first reset unit is connected to a first reset signal output terminal;

[0018] During the reset phase, the first coupling control unit outputs a preset voltage signal under the action of the first coupling control signal, and the first reset unit resets the drive unit according to the first reset signal output by the first reset signal output terminal received by the first reset signal; the reset phase is earlier than the data writing phase.

[0019] In the above embodiments, during the reset phase, the first coupling control unit outputs a preset voltage signal, which ensures that the first terminal of the first capacitor has a stable voltage input and will not cause malfunctions due to being in a floating state, thereby improving the reliability of the circuit.

[0020] In one embodiment, the first coupling control unit includes a first switching transistor; the first terminal of the first switching transistor is connected to the target voltage output terminal, the second terminal of the first switching transistor is connected to the first terminal of the first capacitor, and the control terminal of the first switching transistor is connected to the first coupling control signal output terminal.

[0021] In the above embodiments, the first coupling control unit is implemented through a first switching transistor, which has a simple circuit structure and low cost.

[0022] In one embodiment, the second coupling control unit includes a second switching transistor; the first terminal of the second switching transistor is connected to the first power output terminal, the second terminal of the second switching transistor is connected to the first terminal of the first capacitor, and the control terminal of the second switching transistor is connected to the second coupling control signal output terminal.

[0023] In the above embodiments, the second coupling control unit is implemented through a second switching transistor, which has a simple circuit structure and low cost.

[0024] In one embodiment, the pulse width modulation module is connected to the second light emission control signal output terminal; during the comparison light emission stage, under the action of the second light emission control signal output from the second light emission control signal output terminal, the pulse width modulation module outputs a light emission duration control signal according to the PWM data signal; the second coupling control signal and the second light emission control signal are effective simultaneously.

[0025] In the above embodiments, the second coupling control signal and the second light emission control signal are effective simultaneously. The pulse width modulation module starts working synchronously with the second coupling control unit transmitting the first power supply voltage signal to the first terminal of the first capacitor. This allows the voltage difference coupling of the first capacitor to be synchronized with the pulse width modulation module starting to compare the PWM data signal and the ramp signal. This can reduce problems such as light emission duration control deviation caused by the timing deviation of the two, and improve the working reliability of the pixel circuit.

[0026] In one embodiment, the second coupling control signal and the second light emission control signal are the same signal.

[0027] In the above embodiments, the second coupling control signal can reuse the second light emission control signal, reducing one signal output terminal of the driving circuit. This also reduces the number of signal lines transmitted from the non-display area where the driving circuit is located to the display area where the pixel circuit is located, thereby simplifying the layout design of the driving circuit, reducing the area occupied by the non-display area, and facilitating a narrow bezel design for the display device. Furthermore, reducing the number of signal lines also reduces interference during signal transmission, reduces signal delay and loss, and further improves the driving reliability of the pixel circuit.

[0028] In one embodiment, the pulse width modulation module includes: a second capacitor, a pulse width control unit, a first light-emitting control unit, and a second light-emitting control unit; a first terminal of the first light-emitting control unit is connected to a second power output terminal, a second terminal of the first light-emitting control unit is connected to a first input terminal of the pulse width control unit, a second input terminal of the pulse width control unit is connected to the PWM data output terminal, a drive control terminal of the pulse width control unit is connected to a first terminal of the second capacitor, and a second terminal of the second capacitor is connected to a ramp voltage output terminal; the output terminal of the pulse width control unit is connected to the drive unit via the second light-emitting control unit; both the first light-emitting control unit and the second light-emitting control unit are connected to the second light-emitting control signal output terminal.

[0029] During the data writing phase, the pulse width control unit receives the PWM data signal and stores the voltage corresponding to the PWM data signal into the second capacitor;

[0030] During the comparison light emission stage, under the action of the second light emission control signal, both the first light emission control unit and the second light emission control unit are turned on. The pulse width control unit outputs a light emission duration control signal according to the PWM data signal, the ramp signal output by the ramp voltage output terminal, and the second power supply voltage signal output by the second power supply output terminal.

[0031] In the above embodiments, the control terminals of the first light-emitting control unit and the second light-emitting control unit are both connected to the output terminal of the second light-emitting control signal, sharing the same second light-emitting control signal, which can ensure the synchronization of control.

[0032] In one embodiment, the driving unit includes a PAM driving module and a third light-emitting control unit; a first terminal of the third light-emitting control unit is connected to the first power output terminal, a second terminal of the third light-emitting control unit is connected to the first input terminal of the PAM driving module, and a control terminal of the third light-emitting control unit is connected to the first light-emitting control signal output terminal; a second input terminal of the PAM driving module is connected to the PAM data output terminal, an output terminal of the PAM driving module is connected to the light-emitting device, and a driving control terminal of the PAM driving module is connected to the second terminal of the first capacitor and the pulse width modulation module;

[0033] During the data writing phase, the PAM driver module receives the PAM data signal and stores the voltage corresponding to the PAM data signal into the first capacitor;

[0034] During the comparison light emission stage, the third light emission control unit is turned on, and the PAM driving module outputs a driving current signal to the light emission device based on the voltage difference, the PAM data signal, and the first power supply voltage signal; the duration of the PAM driving module outputting the driving current signal is determined according to the light emission duration control signal.

[0035] In the above embodiments, during the comparison light emission stage, the first light emission control signal is valid, and the third light emission control unit is turned on under the action of the first light emission control signal. The first power supply voltage signal output by the first power supply output terminal can be transmitted to the first input terminal of the PAM driving module through the third light emission control unit. When the PAM driving module outputs a driving current signal based on the voltage corresponding to the PAM data signal stored in the first capacitor, the voltage difference coupled by the first capacitor, and the first power supply voltage signal connected to the first input terminal, the first power supply voltage signal connected to the first input terminal cancels out the first power supply voltage signal component in the voltage difference. The driving current signal is unrelated to the first power supply voltage signal and is therefore unaffected by the voltage drop of the first power supply voltage signal, resulting in higher stability of the driving current signal.

[0036] In one embodiment, the pulse width modulation module is further configured to output a shutdown signal during the reset phase; the driving unit includes a third capacitor, a PAM driving module, a third light-emitting control unit, and a fourth light-emitting control unit; the first terminal of the third light-emitting control unit is connected to the first power output terminal, and the second terminal of the third light-emitting control unit is connected to the first input terminal of the PAM driving module; the second input terminal of the PAM driving module is connected to the PAM data output terminal, and the output terminal of the PAM driving module is connected to the light-emitting device via the fourth light-emitting control unit; the driving control terminal of the PAM driving module is connected to the second terminal of the first capacitor; the first terminal of the third capacitor is connected to the first terminal of the third light-emitting control unit, and the second terminal of the third capacitor is connected to the control terminal of the third light-emitting control unit and the pulse width modulation module; the control terminal of the fourth light-emitting control unit is connected to the first light-emitting control signal output terminal;

[0037] During the reset phase, the third light-emitting control unit is turned off according to the turn-off signal;

[0038] During the data writing phase, the PAM driver module receives the PAM data signal and stores the voltage corresponding to the PAM data signal into the first capacitor;

[0039] During the comparison light emission stage, the third light emission control unit is turned on according to the light emission duration control signal, and the PAM driving module outputs a driving current signal to the light emission device based on the voltage difference, the PAM data signal, and the first power supply voltage signal.

[0040] In the above embodiments, the driving current signal is related to the preset voltage signal but not to the first power supply voltage signal, thereby resulting in stronger consistency of the driving current in the display device, more uniform brightness of each light-emitting device, and higher light emission consistency of the display device. Moreover, the light emission duration control signal does not affect the voltage of the PAM driving module, making the driving current signal generated by the PAM driving module more stable, which in turn makes the light emission state of the light-emitting devices more stable and the display effect of the display device better. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of a pixel circuit according to an embodiment of this application;

[0043] Figure 2 This is a schematic diagram of a pixel circuit according to another embodiment of this application;

[0044] Figure 3 This is a schematic diagram of a pixel circuit according to another embodiment of this application;

[0045] Figure 4 This is a schematic diagram of a pixel circuit according to another embodiment of this application;

[0046] Figure 5 This is a schematic diagram of a pixel circuit according to another embodiment of this application;

[0047] Figure 6 This is a circuit structure diagram of a pixel circuit according to an embodiment of this application;

[0048] Figure 7 This is a schematic diagram of the control timing of a pixel circuit according to an embodiment of this application;

[0049] Figure 8 This is a circuit structure diagram of a pixel circuit according to another embodiment of this application. Detailed Implementation

[0050] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0052] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0053] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0054] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0055] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0056] The pixel circuits in a display device drive LEDs to emit light using pulse width modulation (PWM) and pulse amplitude modulation (PAM). Specifically, the PAM module in the pixel circuit determines the driving current value based on the PAM data signal, thus determining the light intensity of the LED during emission. The PWM module controls the timing of the driving current generation by the PAM module, controlling the LED's emission time within each frame display cycle, thereby collaboratively controlling the brightness of the LED within each frame display cycle. However, due to the driving current flowing through the power path, a significant voltage drop (IR-drop) occurs, resulting in differences in the power supply voltage delivered to the PWM modules of each pixel circuit. This difference affects the magnitude of the driving current generated by the PWM modules of each pixel circuit, which in turn affects the light intensity of each LED, ultimately impacting the display uniformity of the display device.

[0057] To address the aforementioned technical issues, this application provides a display device including a light-emitting device for constituting display pixels and a pixel circuit connected to the light-emitting device. The pixel circuit drives the light-emitting device to emit light. The light-emitting device can be MicroLED (micro-light-emitting diode), MiniLED (sub-millimeter light-emitting diode), or other LEDs. It is understood that in actual implementation, multiple light-emitting devices and corresponding pixel circuits are used to achieve image display and refresh.

[0058] In some embodiments, such as Figure 1 As shown, the pixel circuit includes a pulse width modulation module 100 and an amplitude modulation module 200.

[0059] The pulse width modulation module 100 is connected to the PWM data output terminal, which is used to output the PWM data signal Data_PWM. The pulse width modulation module 100 is used to receive the PWM data signal Data_PWM output from the PWM data output terminal, and outputs a light emission duration control signal to the amplitude modulation module 200 according to the PWM data signal Data_PWM, so as to coordinate with the amplitude modulation module 200 to control the light emission of the LED device.

[0060] The pulse width modulation module 100 outputs a light emission duration control signal, which can be understood as converting the light emission duration control signal from an invalid level to an effective level; or it can be understood as the pulse width modulation module 100 having an invalid level before outputting the light emission duration control signal, and switching from an invalid level to an effective level when outputting the light emission duration control signal.

[0061] The amplitude modulation module 200 includes a driving unit 210, a first capacitor C1, a first coupling control unit 220, and a second coupling control unit 230. The first capacitor C1 serves to store electrical energy and perform coupling; its type and capacitance value can be selected according to actual circuit requirements, and this embodiment does not limit this.

[0062] The first coupling control unit 220 is connected to a target voltage output terminal, a first coupling control signal output terminal (not shown), and the first terminal of a first capacitor C1. The target voltage output terminal is used to output a preset voltage signal VGH, and the first coupling control signal output terminal is used to output a first coupling control signal. The first coupling control signal is used to control the operating state of the first coupling control unit 220. When the first coupling control signal is valid (at an active level), the first coupling control unit 220 outputs the received preset voltage signal VGH to the first terminal of the first capacitor C1. When the first coupling control signal is invalid (at an invalid level), the first coupling control unit 220 stops transmitting the preset voltage signal VGH.

[0063] The second coupling control unit 230 is connected to a first power output terminal, a second coupling control signal output terminal (not shown), and the first terminal of a first capacitor C1. The first power output terminal outputs a first power supply voltage signal VDD1, and the second coupling control signal output terminal outputs a second coupling control signal, which controls the operating state of the second coupling control unit 230. When the second coupling control signal is valid, the second coupling control unit 230 outputs the received first power supply voltage signal VDD1 to the first terminal of the first capacitor C1. When the second coupling control signal is invalid, the second coupling control unit 230 stops transmitting the first power supply voltage signal VDD1. The second coupling control signal and the first coupling control signal will not be valid simultaneously, thus preventing a short circuit caused by simultaneous operation of the first coupling control unit 220 and the second coupling control unit 230.

[0064] The driving unit 210 is connected to the second terminal of the first capacitor C1, the first power output terminal, the PAM data output terminal, the first light-emitting control signal output terminal, the pulse width modulation module 100, and the light-emitting device LED. The PAM data output terminal is used to output the PAM data signal Data_PAM. The first light-emitting control signal output terminal is used to output the first light-emitting control signal EM1, which is used to control the working state of the driving unit 210. In some embodiments, during the data writing stage, the first coupling control unit 220, under the action of the first coupling control signal output from the first coupling control signal output terminal, receives and outputs the preset voltage signal VGH output from the target voltage output terminal to the first terminal of the first capacitor C1. The driving unit 210 receives the PAM data signal Data_PAM output from the PAM data output terminal and stores it in the first capacitor C1. At this time, the first terminal of the first capacitor C1 is the preset voltage signal VGH, and the PAM data signal Data_PAM received by the driving unit 210 is transmitted to the second terminal of the first capacitor C1, whereby the first capacitor C1 stores the voltage corresponding to the PAM data signal Data_PAM.

[0065] During the comparison light emission stage, under the action of the second coupling control signal output from the second coupling control signal output terminal, the second coupling control unit 230 receives and outputs the first power supply voltage signal VDD1 from the first power supply output terminal to the first terminal of the first capacitor C1. The voltage difference at the first terminal of the first capacitor C1 is coupled to the driving unit 210. In the initial stage of this comparison light emission stage, the first power supply voltage signal VDD1 is transmitted to the first terminal of the first capacitor C1, and the voltage at the first terminal of the first capacitor C1 switches from the preset voltage signal VGH to the first power supply voltage signal VDD1. The resulting voltage difference is coupled to the driving unit 210 through the first capacitor C1.

[0066] Under the action of the first light-emitting control signal EM1 output from the first light-emitting control signal output terminal, the driving unit 210 outputs a driving current signal to the light-emitting device LED based on the voltage difference, the PAM data signal Data_PAM, and the first power supply voltage signal VDD1. At this time, the first power supply voltage signal VDD1 component included in the voltage difference cancels out the first power supply voltage signal VDD1 directly output from the first power supply output terminal. Therefore, the driving current signal output by the driving unit 210 is unrelated to the first power supply voltage signal but is related to the preset voltage signal VGH and the PAM data signal Data_PAM. By adjusting the voltage value of the PAM data signal Data_PAM, the magnitude of the driving current can be adjusted, thereby regulating the brightness of the light-emitting device LED and achieving control over the light emission brightness.

[0067] The second coupling control signal is effective before the first light-emitting control signal EM1. This allows for the voltage switching and capacitive coupling of the first terminal of the first capacitor C1 to be completed before the driving unit 210 is turned on. This reduces the risk of the driving unit 210 outputting unstable driving current due to voltage instability, ensuring stable LED light emission and improving display performance. The timing of the second coupling control signal preceding the first light-emitting control signal is not limited and can be set according to actual conditions.

[0068] During the comparison light-emitting phase, the duration of the drive current signal output by the drive unit 210 is determined according to the light-emitting duration control signal. In some embodiments, at the initial stage of the comparison light-emitting phase, the light-emitting duration control signal of the pulse width modulation module 100 is at an invalid level. At this time, the amplitude modulation module 200 can normally output the drive current signal to drive the light-emitting device LED to emit light. When the light-emitting duration control signal becomes valid, the drive unit 210 stops outputting the drive current to the light-emitting device LED, and the light-emitting device LED stops emitting light until the next display cycle arrives. The pixel circuit repeats the above working process to complete the display of each frame and realize the normal display function of the display device. In some embodiments, the driving unit 210 may not output driving current to the LED before the pulse width modulation module 100 outputs the light emission duration control signal to an effective level. After the pulse width modulation module 100 outputs the light emission duration control signal to an effective level, the driving unit 210 outputs driving current to the LED, and the LED emits light until the reset phase of the next display cycle arrives. At this point, the light emission duration control signal output by the pulse width modulation module 100 becomes invalid, the driving unit 210 stops outputting driving current to the LED, and the LED stops emitting light.

[0069] In the aforementioned display device, during the data writing phase, the first coupling control unit 220, under the action of the first coupling control signal, receives and outputs a preset voltage signal VGH to the first terminal of the first capacitor C1, and the driving unit 210 receives the PAM data signal Data_PAM and stores it in the first capacitor C1. During the light emission phase, under the action of the second coupling control signal, the second coupling control unit 230 outputs a first power supply voltage signal VDD1 to the first terminal of the first capacitor C1, and the voltage difference at the first terminal of the first capacitor C1 is coupled to the driving unit 210. Under the action of the first light emission control signal EM1, the driving unit 210 outputs a driving current signal to the light-emitting device LED based on the voltage difference, the PAM data signal Data_PAM, and the first power supply voltage signal VDD1. Therefore, the driving current signal output by the driving unit 210 is related to the preset voltage signal VGH, but not to the first power supply voltage signal VDD1. Since the transmission path of the preset voltage signal VGH flows through the driving current, the voltage drop along this path is significantly lower than that along the power supply path of the first power supply voltage signal VDD1. The potential of each pixel circuit in the display device receives the preset voltage signal VGH more stably, resulting in higher consistency of the drive current signal output by the drive unit 210 of each pixel circuit. Consequently, the brightness of each LED light-emitting device is more uniform, and the display device exhibits higher display consistency. Furthermore, the second coupling control signal becomes effective earlier than the first light-emitting control signal EM1, allowing the first power supply voltage signal VDD1 to be transmitted to the drive unit 210 before the drive unit 210 outputs the drive current signal. This makes the voltage difference coupled by the first capacitor C1 more stable when the drive unit 210 generates the drive current, leading to a more stable drive current signal generated based on this voltage difference. This further improves the display consistency of the display device, resulting in a better display effect.

[0070] In some embodiments, the first coupling control signal and the second coupling control signal are out of phase during the same display cycle. That is, when the first coupling control signal is valid, the second coupling control signal is invalid; when the first coupling control signal is invalid, the second coupling control signal is valid.

[0071] Therefore, when the first coupling control signal is valid, the second coupling control signal is invalid. At this time, the first coupling control unit 220 is turned on and transmits a preset voltage signal VGH to the first terminal of the first capacitor C1, while the second coupling control unit 230 stops outputting. When the first coupling control signal is invalid, the second coupling control signal is valid. At this time, the second coupling control unit 230 is turned on and transmits a first power supply voltage signal VDD1 to the first terminal of the first capacitor C1, while the first coupling control unit 220 stops outputting. This ensures that the first terminal of the first capacitor C1 always has a stable voltage input and will not be in a floating state, guaranteeing the stability of the voltage coupling of the first capacitor C1. Furthermore, it prevents the simultaneous transmission of two voltage signals, effectively reducing the risk of short circuits caused by signal conflict at the first terminal of the first capacitor C1 and improving circuit safety.

[0072] In some embodiments, the pulse width modulation module 100 is connected to a second light emission control signal output terminal, which outputs a second light emission control signal to control the operation of the pulse width modulation module 100. For example, during the light emission comparison phase, under the influence of the second light emission control signal, the pulse width modulation module 100 outputs a light emission duration control signal based on the PWM data signal Data_PWM.

[0073] The second coupling control signal and the second light emission control signal are effective simultaneously. That is, the pulse width modulation module 100 starts working and the second coupling control unit 230 transmits the first power supply voltage signal VDD1 to the first terminal of the first capacitor C1 in a synchronized manner. This allows the voltage difference coupling of the first capacitor C1 to be synchronized with the pulse width modulation module 100 starting to generate the light emission runaway control signal, thereby reducing problems such as light emission duration control deviation caused by the start-up timing deviation of the two and improving the working reliability of the pixel circuit.

[0074] In some embodiments, the second coupling control signal and the second light emission control signal are the same signal. As an example, the second coupling control signal multiplexes the second light emission control signal; that is, the second coupling control signal input terminal of the second coupling control unit 230 is connected to the second light emission control signal input terminal of the pulse width modulation module 100, and both are connected to the second light emission control signal output terminal (the second light emission control signal output terminal is also the second coupling control signal output terminal). The same second light emission control signal simultaneously provides control signals to both units. When the second light emission control signal is valid, it simultaneously controls the pulse width modulation module 100 to start working, and the second coupling control unit 230 to conduct and transmit the first power supply voltage signal VDD1 to the first terminal of the first capacitor C1. When the second light emission control signal is invalid, it simultaneously controls the pulse width modulation module 100 to stop working, and the second coupling control unit 230 to turn off and stop transmitting the first power supply voltage signal VDD1.

[0075] It is understood that the display device also includes a driving circuit (not shown). The driving circuit provides various signals required for the operation of the pixel circuit, including but not limited to PWM data signal Data_PWM, PAM data signal Data_PAM, first light emission control signal EM1, second light emission control signal, and various scanning signals, to ensure that each unit of the pixel circuit works in coordination. By multiplexing the second light emission control signal into a control signal for the second coupling control unit 230, the driving circuit can reduce one signal output terminal, and also reduce the number of signal lines transmitted from the non-display area where the driving circuit is located to the display area where the pixel circuit is located. This simplifies the layout design of the driving circuit, reduces the area occupied by the non-display area, and is beneficial for the display device to achieve a narrow bezel design. At the same time, reducing the number of signal lines can also reduce interference during signal transmission, reduce signal delay and loss, and further improve the driving reliability of the pixel circuit.

[0076] In some embodiments, the amplitude of the preset voltage signal VGH is less than the amplitude of the first power supply voltage signal VDD1.

[0077] The magnitude of the drive current signal is related to the voltage magnitudes of the preset voltage signal VGH and the PAM data signal Data_PAM. The first power supply voltage signal VDD1 is the operating power supply voltage of the amplitude modulation module 200. By making the amplitude of the preset voltage signal VGH lower than the amplitude of the first power supply voltage signal VDD1, the voltage of the PAM data signal Data_PAM can be reduced, allowing the PAM data signal Data_PAM to meet the drive requirements of the drive unit 210 without requiring a higher voltage. This reduces the drive voltage requirements of the drive circuit and decreases its workload. Simultaneously, the reduced drive voltage of the drive circuit also reduces its power consumption, thus optimizing the overall power consumption of the display device.

[0078] In some embodiments, such as Figure 2 As shown, the amplitude modulation module 200 also includes a first reset unit 240. The first terminal of the first reset unit 240 is connected to the second terminal of the driving unit 210 and the first capacitor C1, and the second terminal of the first reset unit 240 is connected to a first reset signal output terminal. The first reset signal output terminal outputs a first reset signal Vref1. The magnitude of the first reset signal Vref1 is not limited and can be set according to specific needs.

[0079] The display cycle of the pixel circuit also includes a reset phase, which precedes the data writing phase. During the reset phase, the first coupling control unit 220 outputs a preset voltage signal VGH under the action of the first coupling control signal, and the first reset unit 240 resets the drive unit 210 according to the received first reset signal Vref1.

[0080] The first reset unit 240 is connected to the drive unit 210 and the first reset signal output terminal. Before the data writing phase of each display cycle begins (i.e., after the comparison and illumination phase of the previous display cycle ends), it resets the drive unit 210 and the first capacitor C1, clearing the stored PAM data signal Data_PAM from the previous cycle. This reduces the impact of residual data from the previous cycle on the accuracy of the current cycle's drive control, improving issues such as brightness deviation and display ghosting. Simultaneously, during this reset phase, the first coupling control unit 220 outputs a preset voltage signal VGH, ensuring a stable voltage input to the first terminal of the first capacitor C1. This prevents malfunctions caused by the capacitor being in a floating state, improving circuit reliability.

[0081] In other embodiments, the second coupling control unit 230 may also transmit the first power supply voltage signal VDD1 to the first capacitor C1 during the reset phase. However, it should be noted that the second light emission control signal is only valid during the light emission comparison phase and is invalid during the reset phase. If the second coupling control unit 230 provides voltage to the second terminal of the first capacitor C1 during the reset phase, a separate control signal needs to be provided for the second coupling control unit 230 to enable it to conduct during the reset phase. This would prevent the second coupling control signal from being reused as the second light emission control signal. Therefore, having the first coupling control unit 220 output a preset voltage signal VGH during the reset phase allows the second light emission control signal to be reused as the control signal for the second coupling control unit 230, thereby simplifying the circuit layout and reducing hardware costs.

[0082] The pulse width modulation module 100 outputs a light-emitting duration control signal based on the PWM data signal Data_PWM in various ways. In some embodiments, the driving circuit outputs a modulated PWM data signal Data_PWM according to the light-emitting requirements of the LED. For example, the driving circuit modulates the voltage amplitude and the output duration of the PWM data signal Data_PWM during the light-emitting phase according to the brightness requirements of the LED, making the output PWM data signal Data_PWM a square wave signal with a preset duty cycle. This preset duty cycle corresponds to the duration required for the driving unit 210 to output the driving current signal. Therefore, when the pulse width modulation module 100 outputs the corresponding light-emitting duration control signal based on the PWM data signal, it can correspondingly control the duration of the driving unit 210's output driving current signal, causing the LED to display the corresponding brightness.

[0083] In some embodiments, it may also be as follows Figure 2As shown, the pulse width modulation module 100 is connected to the PWM data output terminal and the ramp voltage output terminal, which outputs the ramp signal SWEEP. During the data writing phase, the pulse width modulation module 100 receives and stores the PWM data signal Data_PWM output from the PWM data output terminal; during the light emission comparison phase, it outputs a light emission duration control signal to the amplitude modulation module 200 based on the PWM data signal Data_PWM and the ramp signal SWEEP output from the ramp voltage output terminal, coordinating with the amplitude modulation module 200 to control the LED light emission.

[0084] The ramp signal SWEEP is a voltage signal whose amplitude changes linearly with time at a constant rate. In the initial stage of the light emission phase, the light emission duration control signal is at an invalid level. As the voltage of the ramp signal SWEEP gradually changes (e.g., gradually decreases), the pulse width modulation module 100 adjusts the light emission duration control signal to an active level based on the PWM data signal Data_PWM and the voltage of the ramp signal SWEEP. The duration for which the light emission duration control signal is active is determined based on the voltages of the PWM data signal Data_PWM and the ramp signal SWEEP. The magnitudes of the PWM data signal Data_PWM and the ramp signal SWEEP can be set according to actual conditions.

[0085] In some embodiments, during the light emission comparison stage, under the action of the second light emission control signal, the pulse width modulation module 100 outputs a light emission duration control signal based on the PWM data signal Data_PWM and the ramp signal SWEEP. The second coupling control signal and the second light emission control signal are simultaneously effective, enabling the voltage difference coupling of the first capacitor C1 to be synchronized with the start of the comparison between the PWM data signal and the ramp signal SWEEP by the pulse width modulation module 100. This reduces problems such as light emission duration control deviations caused by timing discrepancies between the two signals, improving the operational reliability of the pixel circuit.

[0086] In some embodiments, such as Figure 3 As shown, the pulse width modulation module 100 includes a second capacitor C2, a pulse width control unit 110, a first light-emitting control unit 120, and a second light-emitting control unit 130. The first terminal of the first light-emitting control unit 120 is connected to the second power output terminal, and the second terminal of the first light-emitting control unit 120 is connected to the first input terminal of the pulse width control unit 110. The second input terminal of the pulse width control unit 110 is connected to the PWM data output terminal. The drive control terminal of the pulse width control unit 110 is connected to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 is connected to the ramp voltage output terminal. The output terminal of the pulse width control unit 110 is connected to the drive unit 210 via the second light-emitting control unit 130. Both the first light-emitting control unit 120 and the second light-emitting control unit 130 are connected to the second light-emitting control signal output terminal.

[0087] During the data writing phase, the pulse width control unit 110 receives the PWM data signal Data_PWM and stores the voltage (charge) corresponding to the PWM data signal Data_PWM into the second capacitor C2.

[0088] During the comparison phase, under the action of the second light emission control signal EM2, both the first light emission control unit 120 and the second light emission control unit 130 are turned on. The pulse width control unit 110 outputs the light emission duration control signal according to the PWM data signal Data_PWM, the ramp signal SWEEP, and the second power supply voltage signal VDD2 output from the second power supply output terminal.

[0089] In this embodiment, the control terminals of the first light-emitting control unit 120 and the second light-emitting control unit 130 are both connected to the second light-emitting control signal output terminal and share the same second light-emitting control signal EM2, which can ensure the synchronization of control.

[0090] Furthermore, the second light-emitting control signal EM2 simultaneously controls the second coupling control unit 230, the first light-emitting control unit 120, and the second light-emitting control unit 130. This eliminates the need for separate control signal output terminals and transmission signal lines for these three units, further reducing the number of signal output terminals in the drive circuit and the number of signal lines between the display area and the non-display area, simplifying the drive circuit layout, and reducing the area occupied by the non-display area. Moreover, the synchronous control of the three units improves the performance of the pixel circuit. For example, it effectively addresses issues such as the pulse width control unit 110 outputting the light-emitting duration control signal before the second coupling control unit 230 completes voltage transmission, thereby ensuring the orderly execution of each stage in the comparison and light-emitting phase and improving the driving stability of the pixel circuit.

[0091] The structure of the driving unit 210 is not unique. In some embodiments, such as... Figure 4 As shown, the driving unit 210 includes a PAM driving module 211 and a third light-emitting control unit 212. The first end of the third light-emitting control unit 212 is connected to the first power output terminal, the second end of the third light-emitting control unit 212 is connected to the first input terminal of the PAM driving module 211, and the control terminal of the third light-emitting control unit 212 is connected to the first light-emitting control signal output terminal.

[0092] The second input terminal of the PAM driver module 211 is connected to the PAM data output terminal, the output terminal of the PAM driver module 211 is connected to the light-emitting device LED, and the drive control terminal of the PAM driver module 211 is connected to the second terminal of the first capacitor C1 and the pulse width modulation module 100.

[0093] During the data writing phase, the PAM driver module 211 receives the PAM data signal Data_PAM and stores the voltage corresponding to the PAM data signal Data_PAM into the first capacitor C1.

[0094] During the comparison phase, the third light-emitting control unit 212 is turned on, and the PAM driving module 211 outputs a driving current signal to the light-emitting device based on the voltage difference, the PAM data signal Data_PAM, and the first power supply voltage signal VDD1.

[0095] It is understandable that during the light emission phase, the first light emission control signal EM1 is effective, and the third light emission control unit 212 is turned on under the action of the first light emission control signal EM1. The first power supply voltage signal VDD1 output from the first power supply output terminal can be transmitted to the first input terminal of the PAM drive module 211 via the third light emission control unit 212. When the PAM drive module 211 outputs a drive current signal based on the voltage corresponding to the PAM data signal Data_PAM stored in the first capacitor C1, the voltage difference coupled by the first capacitor C1, and the first power supply voltage signal VDD1 connected to the first input terminal, the first power supply voltage signal VDD1 connected to the first input terminal cancels out the first power supply voltage signal VDD1 component in the voltage difference. This drive current signal is unrelated to the first power supply voltage signal VDD1, and is therefore not affected by the voltage drop of the first power supply voltage signal VDD1, resulting in higher stability of the drive current signal.

[0096] Since the second light-emitting control signal EM2 is effective earlier than the first light-emitting control signal EM1, the stable state of the voltage difference coupled by the first capacitor C1 can be achieved earlier than the start-up time of the PAM drive module 211, and the drive current signal generated by the PAM drive module 211 based on the stable voltage difference is more stable.

[0097] In this embodiment, the duration of the drive current signal output by the PAM drive module 211 is determined according to the light emission duration control signal. For example, in the initial stage of the light emission phase, the light emission duration control signal is at an invalid level. At this time, the PAM drive module 211 can normally output the drive current signal to drive the LED to emit light. When the light emission duration control signal becomes valid, the PAM drive module 211 stops outputting the drive current to the LED according to the light emission duration control signal, and the LED stops emitting light until the next display cycle arrives. The pixel circuit repeats the above process to complete the display of each frame.

[0098] In some embodiments, such as Figure 5 As shown, the driving unit 210 also includes a fourth light-emitting control unit 213. The first end of the fourth light-emitting control unit 213 is connected to the output end of the PAM driving module 211, the second end of the fourth light-emitting control unit 213 is connected to the light-emitting device LED, and the control end of the fourth light-emitting control unit 213 is connected to the first light-emitting control signal output end.

[0099] The control terminal of the fourth light-emitting control unit 213 is connected to the output terminal of the first light-emitting control signal and shares the same first light-emitting control signal EM1 with the third light-emitting control unit 212. There is no need to set a separate control signal output terminal, which simplifies the circuit structure and ensures the control synchronization of the two light-emitting control units controlled by the first light-emitting control signal EM1.

[0100] In some embodiments, the amplitude modulation module 200 further includes a second reset unit 250. The first end of the second reset unit 250 is connected to the output end of the driving unit 210 and the anode of the light-emitting device LED, and the second end of the second reset unit 250 is connected to a second reset signal output end. The second reset signal output end outputs a second reset signal Vref2. The magnitude of the second reset signal Vref2 is not limited and can be set according to specific needs.

[0101] The second reset unit 250 resets the output of the PAM drive module 211 and the LED light-emitting device according to the received second reset signal Vref2. This ensures that the anode potential of the LED is in its initial state, unaffected by residual potential from the previous display cycle, resulting in more accurate display. Furthermore, the reset action of the second reset unit 250 is synchronized with that of the first reset unit 240, ensuring that the amplitude modulation module 200 is in its initial state during the reset phase of each display cycle, thus further improving the accuracy of light emission control.

[0102] In some embodiments, such as Figure 6 As shown, the PAM driving module 211 includes a first transistor T1, a second transistor T2, and a third transistor T3. The first terminal of the first transistor T1 is connected to the first terminal of the third light-emitting control unit 212 and the third transistor T3. The second terminal of the third transistor T3 is connected to the PAM data output terminal to receive the PAM data signal Data_PAM. The control terminal of the third transistor T3 is used to receive the second scan signal S2. The second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2 and the fourth light-emitting control unit 213. The second terminal of the second transistor T2 is connected to the control terminal of the first transistor T1 and the second terminal of the first capacitor C1. The control terminal of the first transistor T1 is also connected to the pulse width modulation module 100, and the control terminal of the second transistor T2 is used to receive the second scan signal S2.

[0103] In some embodiments, the third light-emitting control unit 212 includes a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to the first power supply output terminal, the second terminal of the fourth transistor T4 is connected to the first terminal of the first transistor T1, and the control terminal of the fourth transistor T4 is connected to the first light-emitting control signal output terminal.

[0104] In some embodiments, the fourth light-emitting control unit 213 includes a fifth transistor T5. The first terminal of the fifth transistor T5 is connected to the second terminal of the first transistor T1, the control terminal of the fifth transistor T5 is connected to the first light-emitting control signal output terminal, the second terminal of the fifth transistor T5 is connected to the anode of the light-emitting device LED, and the cathode of the light-emitting device LED is connected to the ground signal VSS.

[0105] In some embodiments, the first reset unit 240 includes a first reset transistor T6. The first terminal of the first reset transistor T6 is connected to the control terminal of the first transistor T1, and the second terminal of the first reset transistor T6 is connected to the first reset signal output terminal. The control terminal of the first reset transistor T6 is used to receive the first scan signal S1.

[0106] In some embodiments, the second reset unit 250 includes a second reset transistor T7. The first terminal of the second reset transistor T7 is connected to the anode of the light-emitting device LED, the second terminal of the second reset transistor T7 is connected to the second reset signal output terminal, and the control terminal of the second reset transistor T7 is used to receive the first scan signal S1.

[0107] In some embodiments, the pulse width control unit 110 includes an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. The first terminal of the eighth transistor T8 is connected to the first terminal of the first light-emitting control unit 120 and the first terminal of the ninth transistor T9. The second terminal of the ninth transistor T9 is connected to the PWM data output terminal for receiving the PWM data signal Data_PWM. The control terminal of the ninth transistor T9 is used to receive the second scan signal S2. The second terminal of the eighth transistor T8 is connected to the first terminal of the tenth transistor T10 and the second light-emitting control unit 130. The second terminal of the tenth transistor T10 is connected to the control terminal of the eighth transistor T8 and the second capacitor C2. The control terminal of the tenth transistor T10 is used to receive the second scan signal S2.

[0108] In some embodiments, the first light-emitting control unit 120 includes an eleventh transistor T11, the first terminal of the eleventh transistor T11 is connected to the second power output terminal, the second terminal of the eleventh transistor T11 is connected to the first terminal of the eighth transistor T8, and the control terminal of the eleventh transistor T11 is used to receive the second light-emitting control signal EM2.

[0109] In some embodiments, the second light-emitting control unit 130 includes a twelfth transistor T12, the first terminal of the twelfth transistor T12 is connected to the first terminal of the tenth transistor T10, the second terminal of the twelfth transistor T12 is connected to the driving unit 210, and the control terminal of the twelfth transistor T12 is used to receive the second light-emitting control signal EM2.

[0110] In some embodiments, the pulse width modulation module 100 further includes a third reset transistor T13. The first terminal of the third reset transistor T13 is connected to the control terminal of the eighth transistor T8, the second terminal of the third reset transistor T13 is connected to the third reset signal output terminal, and receives the third reset signal Vref3. The control terminal of the third reset transistor T13 is used to receive the first scan signal S1.

[0111] In some embodiments, the first coupling control unit 220 includes a first switching transistor T14. The first terminal of the first switching transistor T14 is connected to the target voltage output terminal, the second terminal of the first switching transistor T14 is connected to the first terminal of the first capacitor C1, and the control terminal of the first switching transistor T14 is connected to the first coupling control signal output terminal to receive the first coupling control signal S3. In this embodiment, the first coupling control unit 220 is implemented using a single first switching transistor T14, resulting in a simple circuit structure and low cost.

[0112] In some embodiments, the second coupling control unit 230 includes a second switching transistor T15. The first terminal of the second switching transistor T15 is connected to the first power supply output terminal, the second terminal of the second switching transistor T15 is connected to the first terminal of the first capacitor C1, and the control terminal of the second switching transistor T15 is connected to the second coupling control signal output terminal. In this embodiment, the second coupling control unit 230 is implemented using a single second switching transistor T15, resulting in a simple circuit structure and low cost.

[0113] It should be noted that, for the sake of uniformity in manufacturing process and to simplify the subsequent method of driving the pixel circuit, the aforementioned transistors can all be P-type transistors or N-type transistors; no specific limitation is made here. Furthermore, those skilled in the art will understand that, since the signal levels in the pixel circuit differ in different implementation scenarios, for the same transistor, in one implementation scenario the control electrode may be the gate, the first electrode the source, and the second electrode the drain, while in another implementation scenario the control electrode may be the gate, the first electrode the drain, and the second electrode the source. In the embodiments of this application, the first and second electrodes are only used to distinguish the two pins of the transistor other than the gate, and are not otherwise limited. The other embodiments of this application and the accompanying drawings of other embodiments are similar and will not be described again.

[0114] The driving timing of the pixel circuit in the display device provided in the above embodiments will be described in detail below. Taking a P-type TFT as an example, refer to... Figure 7 The timing diagrams of the signal lines shown are for example... Figure 6 The working principle of the pixel circuit shown is explained in detail. Figure 7 As shown, a display cycle may include a reset phase t1, a data writing phase t2, and a comparison and illumination phase t3 arranged from earliest to latest in time.

[0115] Reset Phase t1: The first coupling control signal S3 is low, the first switching transistor T14 is turned on, and the voltage at the first terminal of the first capacitor C1 is the voltage of the preset voltage signal VGH. At this time, the first scan signal S1 is also low, and the first reset transistor T6, the second reset transistor T7, and the third reset transistor T13 are all turned on. The first reset signal Vref1 is input to node B through the first reset transistor T6. Since the first reset signal Vref1 is low, the first transistor T1 is in the on state. The second reset signal Vref2 is input to the anode of the light-emitting device LED through the second reset transistor T7. Since the second reset signal Vref2 is low, it can ensure that the light-emitting device LED is turned off, and the anode level is not affected by the previous cycle. The third reset signal Vref3 is input to node C through the third reset transistor T13. Since the third reset signal Vref3 is low, the eighth transistor T8 is in the on state, and the third reset signal Vref3 charges the second capacitor C2.

[0116] Data writing phase t2: The second scan signal S2 is low, the second transistor T2 and the third transistor T3 are turned on, and the PAM data signal Data_PAM is written to node B through the third transistor T3, the first transistor T1, and the second transistor T2, and charges the first capacitor C1 until the potential V of node B is reached. B achieve ,in, This represents the voltage value of the PAM data signal Data_PAM. This represents the threshold voltage of the first transistor T1. At this time, the ninth transistor T9 and the tenth transistor T10 are turned on, and the PWM data signal Data_PWM is written to node C through the ninth transistor T9, the eighth transistor T8, and the tenth transistor T10, and charges the second capacitor C2 until the potential V of node C is reached. c achieve ,in, This represents the voltage value of the PWM data signal Data_PWM. This indicates the threshold voltage of the eighth transistor, T8. This stage completes the data signal writing and threshold voltage compensation.

[0117] During the light-emitting stage t3, the first coupling control signal S3 is a high-level signal, while the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are both low-level signals. The eleventh transistor T11, the twelfth transistor T12, the fourth transistor T4, the fifth transistor T5, and the second switching transistor T15 are turned on. The voltage at the first terminal of the first capacitor C1 changes from the preset voltage signal VGH to the first power supply voltage signal VDD1. Due to the coupling effect of the first capacitor C1, the potential at point B changes from... Become The drive current output by the first transistor T1 Where W represents the width of the channel of the first transistor T1, and L represents the length of the channel. Indicates electron mobility. This represents the gate oxide capacitance per unit area. It can be seen that this drive current... It is related to the preset voltage signal VGH, but not to the first power supply voltage signal VDD1. Since the transmission path of the first power supply voltage signal VDD1 carries current, its voltage drop is significant. The transmission path of the preset voltage signal VGH does not carry current, therefore its voltage drop is very small, resulting in better uniformity of the driving current signal received by each LED.

[0118] As the voltage of the ramp signal SWEEP gradually decreases and due to the coupling effect of the second capacitor C2, the potential of node C gradually decreases until the eighth transistor T8 turns on. The second power supply voltage signal VDD2 is output through the eleventh transistor T11, the eighth transistor T8, and the twelfth transistor T12. The level at the output of the twelfth transistor T12 becomes the second power supply voltage signal VDD2, which converts the light emission duration control signal to an effective level. At this time, the second power supply voltage signal VDD2 charges the first capacitor C1, and the potential of node B becomes the second power supply voltage signal VDD2. The difference between the gate-source voltage Vgs and the threshold voltage Vth1 of the first transistor T1 is... - When the first transistor T1 is turned off, the LED light-emitting device is cut off.

[0119] In the aforementioned pixel circuit, the driving current signal output by the first transistor T1 is related to the preset voltage signal VGH, but not to the first power supply voltage signal VDD1. This results in stronger consistency of the driving current in the display device, more uniform brightness of each light-emitting device, and higher light emission consistency of the display device.

[0120] In some embodiments, the pulse width modulation module 100 is further configured to output a shutdown signal during the reset phase. For example... Figure 8As shown, the driving unit 210 includes a third capacitor C3, a PAM driving module 211, a third light-emitting control unit 212, and a fourth light-emitting control unit 213. The first terminal of the third light-emitting control unit 212 is connected to the first power output terminal, and the second terminal of the third light-emitting control unit 212 is connected to the first input terminal of the PAM driving module 211. The second input terminal of the PAM driving module 211 is connected to the PAM data output terminal, and the output terminal of the PAM driving module 211 is connected to the light-emitting device LED via the fourth light-emitting control unit 213. The driving control terminal of the PAM driving module 211 is connected to the second terminal of the first capacitor C1, the first terminal of the third capacitor C3 is connected to the first terminal of the third light-emitting control unit 212, the second terminal of the third capacitor C3 is connected to the control terminal of the third light-emitting control unit 212 and the pulse width modulation module 100, and the control terminal of the fourth light-emitting control unit 213 is connected to the first light-emitting control signal output terminal.

[0121] During the reset phase, the third light-emitting control unit 212 is turned off according to the turn-off signal.

[0122] During the data writing phase, the PAM driver module 211 receives the PAM data signal Data_PAM and stores the voltage corresponding to the PAM data signal Data_PAM into the first capacitor C1.

[0123] During the comparison phase, the third light-emitting control unit 212 is turned on according to the light-emitting duration control signal, and the PAM drive module 211 outputs a drive current signal to the light-emitting device LED based on the voltage difference, the PAM data signal Data_PAM and the first power supply voltage signal VDD1.

[0124] In this embodiment, during the reset phase, the third light-emitting control unit 212 is turned off, cutting off the transmission path between the first power supply voltage signal VDD1 and the PAM driving module 211, and the PAM driving module 211 will not start working. At this time, the third capacitor C3 stores the turn-off signal. During the data writing phase, under the action of the third capacitor C3, the third light-emitting control unit 212 remains off, so the first power supply voltage signal VDD1 will not interfere with the writing of the PAM data signal Data_PAM, and will not affect the accuracy of the writing of the PAM data signal Data_PAM. In the early stage of the comparison light-emitting phase, the third light-emitting control unit 212 is turned off until the light-emitting duration control signal becomes an effective level state. Then, the third light-emitting control unit 212 is turned on, and the first power supply voltage signal VDD1 is transmitted to the PAM driving module 211 through the third light-emitting control unit 212. The PAM driving module 211 outputs a driving current signal to the light-emitting device LED based on the voltage difference, the PAM data signal Data_PAM, and the first power supply voltage signal VDD1, and the light-emitting device LED emits light. Thus, the output duration of the driving current signal is adjusted according to the duration of the light-emitting duration control signal being an effective level state.

[0125] It is understandable that the pulse width modulation module 100 converts the light emission duration control signal into an effective level based on the PWM data signal Data_PWM and the gradually changing ramp signal SWEEP. During this process, the change in the light emission duration control signal may fluctuate or be unstable. If the light emission duration control signal is directly provided to the gate of the driving transistor (first transistor T1), it may affect the stability of the driving current generated by the driving transistor. In this embodiment, the light emission duration control signal is provided to the third light emission control unit 212, which controls the transmission of the first power supply voltage signal VDD1 to control whether the PAM driving module 211 starts working. Therefore, when the PAM driving module 211 is working, the driving current it generates will not be affected, the current value is more stable, and thus the light emission state of the LED is more stable.

[0126] In some embodiments, the pulse width modulation module 100 is different from the above embodiments ( Figure 3 In this embodiment, the following two adjustments are made. First, the pulse width modulation module 100 further includes a reset control unit 140. The first terminal of the reset control unit 140 is connected to the second light-emitting control unit 130 and the third light-emitting control unit 212, and the second terminal of the reset control unit 140 is connected to the fourth reset signal output terminal to receive the fourth reset signal Vref4 that enables the third light-emitting control unit 212 to conduct. Second, the first terminal of the first light-emitting control unit 120 is connected to the third power output terminal to receive the third power supply voltage signal VGL that enables the third light-emitting control unit 212 to disconnect. The voltage values ​​of the fourth reset signal Vref4 and the third power supply voltage signal VGL can be set according to the actual circuit structure; this embodiment does not limit this.

[0127] The circuit structure of the pulse width control unit 110, the first light emission control unit 120, and the second light emission control unit 130 in the pulse width modulation module 100, and the PAM driving module 211, the third light emission control unit 212, the fourth light emission control unit 213, the first coupling control unit 220, the second coupling control unit 230, the first reset unit 240, and the second reset unit 250 in the amplitude modulation module 200 can be set with reference to the above embodiments. The similarities will not be repeated in this embodiment.

[0128] In some embodiments, the reset control unit 140 includes a fourth reset transistor T16. The first terminal of the fourth reset transistor T16 is connected to the twelfth transistor T12 and the fourth transistor T4, and the second terminal of the fourth reset transistor T16 is connected to the fourth reset signal output terminal to receive the fourth reset signal Vref4. The control terminal of the fourth transistor T4 is used to receive the first scan signal S1. Thus, during the reset phase, under the action of the first scan signal S1, the fourth reset transistor T16 is turned on, writing the fourth reset signal Vref4 to node A, causing the fourth transistor T4 to turn off. Simultaneously, the third capacitor C3 is charged to store the charge corresponding to the fourth reset signal Vref4. During the data writing phase, under the action of the third capacitor C3, the fourth transistor T4 remains off until the third power supply voltage signal VGL is written to node A, turning the fourth transistor T4 on. The first transistor T1 then begins to generate and output a drive current signal, thereby driving the LED to emit light.

[0129] The following example assumes that all the transistors mentioned above are P-type TFTs, the fourth reset signal Vref4 is a high-level signal, and the third power supply voltage signal VGL is a low-level signal. Figure 7 The timing diagrams of the signal lines shown are for example... Figure 8 The working principle of the pixel circuit shown will be explained in detail.

[0130] Reset Phase t1: The first coupling control signal S3 is low, the first switching transistor T14 is turned on, and the voltage at the first terminal of the first capacitor C1 is the voltage of the preset voltage signal VGH. At this time, the first scan signal S1 is also low, and the first reset transistor T6, the second reset transistor T7, the third reset transistor T13, and the fourth reset transistor T16 are all turned on. The first reset signal Vref1 is input to node B through the first reset transistor T6. Since the first reset signal Vref1 is low, the first transistor T1 is in the on state. The second reset signal Vref2 is input to the anode of the LED through the second reset transistor T7. Since the second reset signal Vref2 is low, it ensures that the LED is off, and the anode level is not affected by the previous cycle. The third reset signal Vref3 is input to node C through the third reset transistor T13. Since the third reset signal Vref3 is low, the eighth transistor T8 is in the on state, and the third reset signal Vref3 charges the second capacitor C2. The fourth reset signal Vref4 is input to node A via the fourth reset transistor T16. Since the fourth reset signal Vref4 is a high-level signal, the fourth transistor T4 is in the off state, and the fourth reset signal Vref4 charges the third capacitor C3. With the fourth transistor T4 off, the transmission path of the first power supply voltage signal VDD1 is disconnected, the first transistor T1 will not generate drive current, and the light-emitting device LED will not emit light.

[0131] Data writing phase t2: Under the action of the third capacitor C3, the fourth transistor T4 remains off. The second scan signal S2 is a low-level signal, the second transistor T2 and the third transistor T3 are turned on, and the PAM data signal Data_PAM is written to node B through the third transistor T3, the first transistor T1, and the second transistor T2, and charges the first capacitor C1 until the potential VB of node B reaches the specified value. ,in, This represents the voltage value of the PAM data signal Data_PAM. This represents the threshold voltage of the first transistor T1. At this time, the ninth transistor T9 and the tenth transistor T10 are turned on, and the PWM data signal Data_PWM is written to node C through the ninth transistor T9, the eighth transistor T8, and the tenth transistor T10, and charges the second capacitor C2 until the potential Vc of node C reaches [value missing]. ,in, This represents the voltage value of the PWM data signal Data_PWM. This indicates the threshold voltage of the eighth transistor, T8. This stage completes the data signal writing and threshold voltage compensation.

[0132] During the light-emitting stage t3, under the influence of the third capacitor C3, the fourth transistor T4 remains off. The first coupling control signal S3 is high, while the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are both low. The eleventh transistor T11, the twelfth transistor T12, the fifth transistor T5, and the second switching transistor T15 are turned on. The voltage at the first terminal of the first capacitor C1 changes from the preset voltage signal VGH to the first power supply voltage signal VDD1. Due to the coupling effect of the first capacitor C1, the potential at point B changes from... Become .

[0133] As the voltage of the ramp signal SWEEP gradually decreases and the coupling effect of the second capacitor C2 occurs, the potential of node C gradually decreases until the eighth transistor T8 turns on. The third power supply voltage signal VGL is output through the eleventh transistor T11, the eighth transistor T8, and the twelfth transistor T12. The output level of the twelfth transistor T12 becomes the third power supply voltage signal VGL, which causes the light emission duration control signal to become effective. Since the third power supply voltage signal VGL is a low-level signal, the fourth transistor T4 turns on, and the first power supply voltage signal VDD1 is transmitted to the first transistor T1, which generates a drive current.

[0134] The drive current output by the first transistor T1 Where W represents the width of the channel of the first transistor T1, and L represents the length of the channel. Indicates electron mobility. This represents the gate oxide capacitance per unit area. It can be seen that this drive current... It is related to the preset voltage signal VGH, but not to the first power supply voltage signal VDD1. Since the transmission path of the first power supply voltage signal VDD1 carries current, its voltage drop is significant. The transmission path of the preset voltage signal VGH does not carry current, resulting in a very small voltage drop, thus improving the uniformity of the driving current signal received by each LED.

[0135] In the aforementioned pixel circuit, the driving current signal output by the first transistor T1 is related to the preset voltage signal VGH, but not to the first power supply voltage signal VDD1. This results in stronger consistency of the driving current in the display device, more uniform brightness of each light-emitting device, and higher light emission consistency. Furthermore, the light emission duration control signal does not affect the gate voltage of the first transistor T1, making the driving current signal generated by the first transistor T1 more stable. This, in turn, makes the light emission state of the LEDs more stable, leading to better display performance.

[0136] In some embodiments, for the two pulse width modulation module 100 structures described above ( Figure 6 Examples and Figure 8 (In the embodiment of the structure), a fourth capacitor, a third coupling control unit, and a fourth coupling control unit can be added to node C. The first end of the fourth capacitor is connected to the gate of the eighth driving transistor T8, and the second end of the fourth capacitor is connected to the third coupling control unit and the fourth coupling control unit, respectively. The third coupling control unit can be set with reference to the first coupling control unit 220, and the fourth coupling control unit can be set with reference to the second coupling control unit 230, thereby improving the control reliability of the pulse width modulation module 100.

[0137] It should be noted that, in the embodiments of this application, "display device" refers to any device with screen display and data processing capabilities. For example, display devices include, but are not limited to, smart TVs, mobile terminals, computers, monitors, advertising screens, wearable devices, virtual reality devices, and augmented reality devices.

[0138] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0139] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0140] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A display device, characterized in that, It includes a light-emitting device for constituting a display pixel and a pixel circuit connected to the light-emitting device; the pixel circuit includes: A pulse width modulation module is connected to the PWM data output terminal; it is used to receive the PWM data signal output by the PWM data output terminal and output a light emission duration control signal according to the PWM data signal. An amplitude modulation module, the amplitude modulation module comprising: First capacitor; The first coupling control unit is connected to the target voltage output terminal, the first coupling control signal output terminal, and the first terminal of the first capacitor; The second coupling control unit is connected to the first power output terminal, the second coupling control signal output terminal and the first terminal of the first capacitor; The driving unit is connected to the second terminal of the first capacitor, the first power output terminal, the PAM data output terminal, the first light emission control signal output terminal, the pulse width modulation module, and the light emission device. During the data writing phase, the first coupling control unit receives and outputs a preset voltage signal from the target voltage output terminal to the first terminal of the first capacitor under the action of the first coupling control signal output from the first coupling control signal output terminal; the driving unit receives the PAM data signal output from the PAM data output terminal and stores it in the first capacitor. During the comparison light emission stage, under the action of the second coupling control signal output from the second coupling control signal output terminal, the second coupling control unit receives and outputs the first power supply voltage signal output from the first power supply output terminal to the first terminal of the first capacitor, and the voltage difference at the first terminal of the first capacitor is coupled to the driving unit; under the action of the first light emission control signal output from the first light emission control signal output terminal, the driving unit outputs a driving current signal to the light emission device based on the voltage difference, the PAM data signal, and the first power supply voltage signal; the duration of the driving unit outputting the driving current signal is determined according to the light emission duration control signal; wherein, the second coupling control signal is effective earlier than the first light emission control signal.

2. The display device according to claim 1, characterized in that, The amplitude of the preset voltage signal is less than the amplitude of the first power supply voltage signal.

3. The display device according to claim 1, characterized in that, The amplitude modulation module further includes a first reset unit; the first end of the first reset unit is connected to the driving unit and the second end of the first capacitor, and the second end of the first reset unit is connected to the first reset signal output terminal. During the reset phase, the first coupling control unit outputs a preset voltage signal under the action of the first coupling control signal, and the first reset unit resets the drive unit according to the first reset signal output by the first reset signal output terminal received by the first reset signal; the reset phase is earlier than the data writing phase.

4. The display device according to claim 1, characterized in that, The first coupling control unit includes a first switching transistor; the first terminal of the first switching transistor is connected to the target voltage output terminal, the second terminal of the first switching transistor is connected to the first terminal of the first capacitor, and the control terminal of the first switching transistor is connected to the first coupling control signal output terminal.

5. The display device according to claim 1, characterized in that, The second coupling control unit includes a second switching transistor; the first terminal of the second switching transistor is connected to the first power output terminal, the second terminal of the second switching transistor is connected to the first terminal of the first capacitor, and the control terminal of the second switching transistor is connected to the second coupling control signal output terminal.

6. The display device according to claim 1, characterized in that, The pulse width modulation module is connected to the second light emission control signal output terminal; during the comparison light emission stage, under the action of the second light emission control signal output from the second light emission control signal output terminal, the pulse width modulation module outputs a light emission duration control signal according to the PWM data signal; the second coupling control signal and the second light emission control signal are effective simultaneously.

7. The display device according to claim 6, characterized in that, The second coupling control signal and the second light emission control signal are the same signal.

8. The display device according to claim 6, characterized in that, The pulse width modulation module includes: a second capacitor, a pulse width control unit, a first light-emitting control unit, and a second light-emitting control unit; the first terminal of the first light-emitting control unit is connected to the second power output terminal, the second terminal of the first light-emitting control unit is connected to the first input terminal of the pulse width control unit, the second input terminal of the pulse width control unit is connected to the PWM data output terminal, the drive control terminal of the pulse width control unit is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the ramp voltage output terminal; the output terminal of the pulse width control unit is connected to the drive unit via the second light-emitting control unit; both the first light-emitting control unit and the second light-emitting control unit are connected to the second light-emitting control signal output terminal. During the data writing phase, the pulse width control unit receives the PWM data signal and stores the voltage corresponding to the PWM data signal into the second capacitor; During the comparison phase, under the action of the second light emission control signal, both the first light emission control unit and the second light emission control unit are turned on. The pulse width control unit outputs a light emission duration control signal based on the PWM data signal, the ramp signal output by the ramp voltage output terminal, and the second power supply voltage signal output by the second power supply output terminal.

9. The display device according to claim 1, characterized in that, The driving unit includes a PAM driving module and a third light-emitting control unit; the first end of the third light-emitting control unit is connected to the first power output terminal, the second end of the third light-emitting control unit is connected to the first input terminal of the PAM driving module, and the control terminal of the third light-emitting control unit is connected to the first light-emitting control signal output terminal; the second input terminal of the PAM driving module is connected to the PAM data output terminal, the output terminal of the PAM driving module is connected to the light-emitting device, and the driving control terminal of the PAM driving module is connected to the second terminal of the first capacitor and the pulse width modulation module; During the data writing phase, the PAM driver module receives the PAM data signal and stores the voltage corresponding to the PAM data signal into the first capacitor; During the comparison light emission stage, the third light emission control unit is turned on, and the PAM driving module outputs a driving current signal to the light emission device based on the voltage difference, the PAM data signal, and the first power supply voltage signal; the duration of the PAM driving module outputting the driving current signal is determined according to the light emission duration control signal.

10. The display device according to claim 1, characterized in that, The pulse width modulation module is also used to output a shutdown signal during the reset phase; the driving unit includes a third capacitor, a PAM driving module, a third light-emitting control unit, and a fourth light-emitting control unit; the first end of the third light-emitting control unit is connected to the first power output terminal, and the second end of the third light-emitting control unit is connected to the first input terminal of the PAM driving module; the second input terminal of the PAM driving module is connected to the PAM data output terminal, and the output terminal of the PAM driving module is connected to the light-emitting device via the fourth light-emitting control unit; the driving control terminal of the PAM driving module is connected to the second end of the first capacitor; the first end of the third capacitor is connected to the first end of the third light-emitting control unit, and the second end of the third capacitor is connected to the control terminal of the third light-emitting control unit and the pulse width modulation module; the control terminal of the fourth light-emitting control unit is connected to the first light-emitting control signal output terminal; During the reset phase, the third light-emitting control unit is turned off according to the turn-off signal; During the data writing phase, the PAM driver module receives the PAM data signal and stores the voltage corresponding to the PAM data signal into the first capacitor; During the comparison light emission stage, the third light emission control unit is turned on according to the light emission duration control signal, and the PAM driving module outputs a driving current signal to the light emission device based on the voltage difference, the PAM data signal, and the first power supply voltage signal.

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