Noise reduction circuit, gate drive circuit and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a noise reduction circuit, a gate driving circuit and a display panel. The noise reduction circuit comprises a noise reduction control unit, a coupling unit, a compensation voltage establishing unit and a noise reduction execution unit. The coupling unit is used for coupling a voltage variation of a first noise reduction control node to a second noise reduction control node. The compensation voltage establishing unit is used for establishing a compensation voltage on the coupling unit according to a low level of the first noise reduction control node and a real-time threshold voltage of a reference transistor in a compensation stage. The noise reduction execution unit is used for performing noise reduction processing on a noise reduction node. In the compensation stage, the real-time threshold voltage of the reference transistor is superimposed into a noise reduction control signal, so that a driving signal applied to the noise reduction execution unit in a noise reduction stage always contains a compensation amount equal to a current threshold voltage of a noise reduction transistor, thereby improving the problem of unstable noise reduction caused by threshold voltage drift of the noise reduction transistor.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a noise reduction circuit, a gate driving circuit, and a display panel. Background Technology

[0002] TFT-LCD (Thin-Film Transistor Liquid Crystal Display) displays images by controlling the light transmittance of pixels in the display area. Specifically, when an external voltage is applied, the liquid crystal molecules inside a single pixel deflect, thereby changing the light transmittance and displaying color. The display area is composed of pixels arranged in an array, and dynamic display is achieved by switching the pixel state frame by frame.

[0003] The GOA (Gate Driver on Array) is a key circuit for TFT-LCD to achieve progressive scanning. However, the noise reduction circuit, which performs noise reduction processing on each key node, is the core module for the reliable operation of the GOA. However, the noise reduction transistor in the noise reduction circuit is in a biased state of forward gate-source voltage (Vgs) for a long time during operation, which can easily cause the threshold voltage (Vth) of the noise reduction transistor to drift. This makes the noise reduction unstable, causing abnormal output signal of GOA and affecting the display effect of the display panel.

[0004] Therefore, how to improve the noise reduction instability caused by threshold voltage drift of the noise reduction transistor is a problem that current baseband technology needs to solve. Summary of the Invention

[0005] This application provides a noise reduction circuit, a gate driving circuit, and a display panel. By superimposing the real-time threshold voltage of the reference transistor onto the noise reduction control signal during the compensation stage, the driving signal applied to the noise reduction execution unit during the noise reduction stage always contains a compensation amount equal to the current threshold voltage of the noise reduction transistor. This improves the problem of noise reduction instability caused by threshold voltage drift of the noise reduction transistor and enhances the noise reduction stability of the noise reduction circuit.

[0006] In a first aspect, embodiments of this application provide a noise reduction circuit, the noise reduction circuit comprising: a noise reduction control unit, connected to a first noise reduction control node, configured to: output a noise reduction control signal to the first noise reduction control node during a noise reduction phase; and output a low level to the first noise reduction control node during a compensation phase; wherein the compensation phase includes a blanking period of the current frame and a scan start period of the next frame; and the noise reduction phase includes a non-scanning period of the current stage gate drive module; and a coupling unit, coupled between the first noise reduction control node and a second noise reduction control node, configured to: couple the voltage change of the first noise reduction control node to the first noise reduction control node. A second noise reduction control node; a compensation voltage establishment unit, connected to the second noise reduction control node, configured to: establish a compensation voltage on the coupling unit based on the low level of the first noise reduction control node and the real-time threshold voltage of the reference transistor during the compensation phase; a noise reduction execution unit, connected to the second noise reduction control node and the noise-reduced node, configured to: perform noise reduction processing on the noise-reduced node in response to a noise reduction control signal superimposed with the compensation voltage on the second noise reduction control node during the noise reduction phase; wherein the reference transistor and the noise reduction transistor in the noise reduction execution unit have the same electrical characteristics.

[0007] Secondly, embodiments of this application provide a gate driving circuit, including N cascaded gate driving modules. The nth-stage gate driving module includes: a pull-up unit, which is connected to the drive output terminal and the stage transmission output terminal of the nith-stage gate driving module, respectively; a pull-down unit, which is connected to the stage transmission output terminal of the (n+j)th-stage gate driving module, and the pull-down unit is also connected to the pull-up unit through a drive control node; an output unit, which is connected to a clock signal terminal and the drive control node, respectively; and a noise reduction circuit, which is connected to the drive control node, drive output terminal, and stage transmission output terminal of the current-stage gate driving module, respectively.

[0008] Thirdly, embodiments of this application provide a display panel including a display area and a non-display area. The display area includes multiple scan lines; the non-display area includes a gate driving circuit, and the drive output terminal of the circuit unit in the gate driving circuit is electrically connected to at least one scan line.

[0009] The technical solutions provided in this application have at least the following beneficial effects:

[0010] This application establishes a compensation voltage based on the real-time threshold voltage of the reference transistor during the compensation stage using a compensation voltage establishment unit. This compensation voltage is then locked and superimposed on the noise reduction control signal via a coupling unit. This ensures that the drive signal applied to the noise reduction execution unit during the noise reduction stage always contains a compensation amount equal to the current threshold voltage of the noise reduction transistor. Therefore, even if the threshold voltage of the noise reduction transistor drifts significantly due to long-term operation, the compensated drive signal received by the noise reduction execution unit can still enable it to conduct fully, maintaining the noise reduction capability and keeping the noise reduction circuit in normal working condition. This improves the problem of noise reduction instability caused by threshold voltage drift of the noise reduction transistor, significantly enhancing the noise reduction stability and reliability of the noise reduction circuit. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0012] Figure 1 The diagram shown is a structural schematic of a gate driving module provided in an embodiment of this application.

[0013] Figure 2 The diagram shown is a schematic of a noise reduction circuit in related technologies.

[0014] Figure 3 As shown Figure 2 Timing diagram of the noise reduction circuit.

[0015] Figure 4 The diagram shown is a structural schematic of the first noise reduction circuit provided in the embodiment of this application.

[0016] Figure 5 The diagram shown is a structural schematic of the second noise reduction circuit provided in the embodiment of this application.

[0017] Figure 6 The diagram shown is a schematic diagram of the first noise reduction circuit provided in the embodiment of this application.

[0018] Figure 7 The diagram shown is a driving timing diagram provided in an embodiment of this application.

[0019] Figure 8 The diagram shown is a schematic diagram of the second noise reduction circuit provided in the embodiment of this application.

[0020] Figure 9 The diagram shown is a schematic diagram of the third noise reduction circuit provided in the embodiment of this application.

[0021] Explanation of reference numerals in the attached figures:

[0022] 100. Noise reduction circuit; 110. Noise reduction control unit; 120. Coupling unit; 130. Compensation voltage establishment unit; 131. Pre-charge sub-unit; 132. Voltage lockout sub-unit; 140. Noise reduction execution unit;

[0023] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; M1, first control transistor; M2, second control transistor; M3, third control transistor; M4, fourth control transistor; M5, fifth control transistor; J1, first noise reduction transistor; J2, second noise reduction transistor; J3, third noise reduction transistor; C1, first capacitor; C2, second capacitor; C3, third capacitor;

[0024] Qn, drive control node; Pn, first noise reduction control node; P1n, second noise reduction control node; Fn, stage transmission output terminal; Gn, drive output terminal; An, intermediate control node; Bn, pre-charge node; Reset, reset signal line; STV, frame start signal line; LC, noise reduction control terminal; VSS, low level terminal. Detailed Implementation

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0026] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0027] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0028] The inventors of this application have discovered that the gate drive circuit includes N cascaded gate drive modules, such as... Figure 1 As shown, the nth-level gate driver module mainly includes pull-up units, pull-down units, output units, reset units, and noise reduction circuits. The pull-up and pull-down units generate a Q-point voltage. The pull-up and pull-down units need to obtain multiple stage transmission signals from the upper and lower gate driver modules. The Q-point voltage is the turn-on voltage of the output unit, enabling the output unit to output the gate drive signal and provide the turn-on voltage for the display area. The reset unit is used to avoid the influence between frames. The noise reduction circuit performs noise reduction processing on the signals at each key node. Among them, Qn represents the drive control node of the nth-level gate driver module, Gn represents the drive output terminal of the nth-level gate driver module, Fn represents the stage transmission output terminal of the nth-level gate driver module, CKn represents the clock signal terminal of the nth-level gate driver module, Reset represents the reset signal terminal, LC represents the noise reduction control terminal, Gn-3 represents the drive output terminal of the (n-3)th-level gate driver module, Fn-3 represents the stage transmission output terminal of the (n-3)th-level gate driver module, and Fn+4 represents the stage transmission output terminal of the (n+4)th-level gate driver module.

[0029] A normal output from the gate drive module is essential for ensuring proper image display; therefore, the noise reduction circuit plays a crucial role in suppressing signal noise. Figure 2 The diagram shown is a schematic of a noise reduction circuit in a related technology. Figure 3 for Figure 2 Timing diagram of the noise reduction circuit; Figure 2 The first control transistor M1, the second control transistor M2, the third control transistor M3, and the fourth control transistor M4 are all control transistors. Figure 2 The first noise reduction transistor J1, the second noise reduction transistor J2, and the third noise reduction transistor J3 are all noise reduction transistors; for example Figure 2 and Figure 3 As shown, the unit composed of the first control transistor M1, the second control transistor M2, the third control transistor M3, and the fourth control transistor M4 mainly inverts the potential of the drive control node Qn to obtain the noise reduction control node ( Figure 2 The voltage at point Pn in the noise reduction control node activates the first noise reduction transistor J1, the second noise reduction transistor J2, and the third noise reduction transistor J3 to perform noise reduction processing on the drive output terminal Gn, the drive control node Qn, and the stage transmission output terminal Fn, respectively. The specific working process is as follows:

[0030] When the drive control node Qn (i.e., Q point) in the nth stage gate drive module is low, the noise reduction control terminal LC continuously outputs a high level. At this time, the first control transistor M1 and the second control transistor M2 are turned on, while the third control transistor M3 and the fourth control transistor M4 are turned off, making the potential on the noise reduction control node high. This turns on the first noise reduction transistor J1, the second noise reduction transistor J2, and the third noise reduction transistor J3, thereby continuously pulling the signals on the drive output terminal Gn, the drive control node Qn, and the stage transmission output terminal Fn low, achieving noise reduction processing for each important node in the gate drive module. Since the drive output terminal, drive control node, and stage transmission output terminal in each stage gate drive module are not denoised during the current stage's scan time, and are denoised during other times, the first noise reduction transistor J1, the second noise reduction transistor J2, and the third noise reduction transistor J3 in the noise reduction circuit need to be in a positive gate-source voltage bias state for a long time. This can easily lead to a drift problem in the threshold voltage (Vth) of the noise reduction transistor, which in turn causes abnormal output signals in the GOA circuit and affects the display effect of the display panel.

[0031] To improve the threshold voltage drift problem of noise reduction transistors, this application provides a noise reduction circuit, specifically including the following embodiments:

[0032] Figure 4 The diagram shown is a structural schematic of the first noise reduction circuit 100 provided in this embodiment. The noise reduction circuit 100 in this embodiment is applied to a gate driving circuit, which includes N cascaded gate driving modules. Each gate driving module includes at least a drive control node Qn, a drive output terminal Gn, a stage transmission output terminal Fn, and a noise reduction circuit 100.

[0033] like Figure 4 As shown, the noise reduction circuit 100 of this embodiment includes a noise reduction control unit 110, which is connected to the first noise reduction control node Pn and configured to: output a noise reduction control signal to the first noise reduction control node Pn during the noise reduction phase; and output a low level to the first noise reduction control node Pn during the compensation phase. That is, the noise reduction control unit 110 of this embodiment outputs different voltages to the first noise reduction control node Pn at different phases: actively outputting a low level during the compensation phase to create initial conditions for the establishment of the subsequent compensation voltage; and operating normally during the noise reduction phase, outputting a high-level noise reduction control signal. Here, this embodiment separates the compensation operation and the noise reduction operation in time through timing division to avoid mutual interference; the low-level output during the compensation phase ensures that the noise reduction execution unit 140 does not work during this period, facilitating the charging of the pre-charge node Bn and the establishment of the compensation voltage.

[0034] Furthermore, the compensation stage in this embodiment includes the blanking period of the current frame and the scan start period of the next frame; the noise reduction stage includes the non-scanning period of the current stage gate drive module. That is to say, the compensation stage in this embodiment spans the boundary between two frames, the blanking period of the current frame and the scan start period of the next frame (i.e., the effective period of the frame start signal), and the noise reduction stage covers all non-scanning time of this stage.

[0035] This embodiment arranges the compensation operation during the blanking period of frame switching and at the beginning of the next frame. This ensures that the normal progressive scan process is not affected, and that the compensation voltage is updated before the start of each frame, enabling real-time tracking of the threshold voltage of the noise reduction transistor. In particular, the frame start signal is used to complete the final locking of the compensation voltage. At this time, the frame start signal is only used to trigger the first-stage scan, and there is no noise reduction requirement in the preceding stage, so it will not have an adverse effect on the normal scan.

[0036] like Figure 4 As shown, the noise reduction circuit 100 in this embodiment further includes a coupling unit 120, which is coupled between the first noise reduction control node Pn and the second noise reduction control node P1n, and is configured to couple the voltage change of the first noise reduction control node Pn to the second noise reduction control node P1n.

[0037] It should be noted that, in this embodiment, the coupling unit 120 serves as a bridge connecting the noise reduction control unit 110 and the noise reduction execution unit 140. It can transmit the voltage changes of the first noise reduction control node Pn and the second noise reduction control node P1n, while maintaining a substantially constant voltage difference between the two ends. In other words, the coupling unit 120 enables the potential of the second noise reduction control node P1n to change in accordance with the changes in the first noise reduction control node Pn, thus realizing the transmission of the noise reduction control signal. Furthermore, the coupling unit 120 can lock the compensation voltage across the two ends, ensuring that the compensation voltage is continuously superimposed on the noise reduction control signal. In this embodiment, the coupling unit 120 can be a capacitor.

[0038] like Figure 4 As shown, the noise reduction circuit 100 in this embodiment also includes a compensation voltage establishment unit 130, which is connected to the second noise reduction control node P1n and is configured to: establish a compensation voltage on the coupling unit 120 based on the low level of the first noise reduction control node Pn and the real-time threshold voltage of the reference transistor during the compensation phase.

[0039] It should be noted that the compensation voltage establishment unit 130 in this embodiment uses the low level of the first noise reduction control node Pn in the compensation stage as a reference, and establishes a compensation voltage on the coupling unit 120 with a magnitude equal to the real-time threshold voltage of the reference transistor through the internal reference transistor (which has the same characteristics as the noise reduction transistor). Since the reference transistor has the same characteristics and bias as the noise reduction transistor, its threshold voltage drift can accurately reflect the threshold voltage drift of the noise reduction transistor. Therefore, in this embodiment, the reference transistor is locked at both ends of the coupling capacitor as the compensation voltage, which is equivalent to presetting a compensation amount equal to the drift amount in the path of the noise reduction control signal.

[0040] like Figure 4 As shown, the noise reduction circuit 100 in this embodiment also includes a noise reduction execution unit 140, which is connected to the second noise reduction control node P1n and the noise-reduced node, and is configured to: in the noise reduction stage, after responding to the noise reduction control signal with the compensation voltage superimposed on the second noise reduction control node P1n, perform noise reduction processing on the noise-reduced node.

[0041] Specifically, the noise-reduced node in this embodiment includes, but is not limited to, the drive control node Qn, the drive output terminal Gn, and the stage transmission output terminal Fn. The noise reduction execution unit 140 in this embodiment is driven by the compensated signal; that is, the received signal is the superposition of the original noise reduction control signal and the compensation voltage. This ensures that the gate signal of the noise reduction transistor in the noise reduction execution unit 140 is always higher than the original noise reduction control signal by a threshold voltage of a reference transistor. Since the threshold voltage of the reference transistor drifts synchronously with the threshold voltage of the noise reduction transistor itself, the noise reduction transistor can obtain sufficient drive voltage regardless of how its threshold voltage changes, ensuring that it is always in a good conducting state and that its noise reduction capability is stable.

[0042] In addition, the reference transistor and the noise reduction transistor in the noise reduction execution unit 140 have the same electrical characteristics. That is to say, the reference transistor and the noise reduction transistor are completely identical in terms of channel type, aspect ratio, and process technology, and they are subjected to the same gate-source voltage bias during operation. This ensures that the threshold voltage drift characteristics of the reference transistor are completely synchronized with those of the noise reduction transistor, so that the compensation voltage can accurately represent the real-time threshold voltage of the noise reduction transistor itself, and achieve precise compensation.

[0043] Therefore, the specific working principle of the noise reduction circuit 100 provided in this embodiment is as follows:

[0044] (1) Division of working stages: In this embodiment, the working timing of the noise reduction circuit 100 is divided into two functional stages:

[0045] ① Compensation phase: This includes the blanking period of the current frame and the start of the next frame scan. The main task of this phase is to extract the current threshold voltage drift and establish a compensation voltage.

[0046] ② Noise Reduction Stage: This includes the non-scanning period of the current stage gate drive module. The main task of this stage is to reduce noise at the node using the compensated signal.

[0047] (2) Compensation stage: Extract the drift amount and establish the compensation voltage.

[0048] During the compensation phase, the noise reduction control unit 110 actively outputs a low level to the first noise reduction control node Pn, causing the noise reduction execution unit 140 to temporarily stop working. At this time, the compensation voltage establishment unit 130 starts working, using a reference transistor to sense the current threshold voltage drift in real time. This reference transistor has the exact same channel type, aspect ratio, and process technology as the noise reduction transistor in the noise reduction execution unit 140, so the threshold voltage drift of the reference transistor can accurately represent the threshold voltage drift of the noise reduction transistor.

[0049] Furthermore, the compensation voltage establishment unit 130 establishes and locks a compensation voltage on the coupling unit 120 based on the low level of the first noise reduction control node Pn and the real-time threshold voltage of the reference transistor. However, the magnitude of this compensation voltage is exactly equal to the current threshold voltage value of the reference transistor.

[0050] (3) Noise reduction stage: superimposed compensation voltage to drive noise reduction.

[0051] After entering the noise reduction stage, the noise reduction control unit 110 outputs a normal noise reduction control signal to the first noise reduction control node Pn.

[0052] The coupling unit 120 (e.g., a capacitor) is connected between the first noise reduction control node Pn and the second noise reduction control node P1n, which can transmit the noise reduction control signal on the first noise reduction control node Pn to the second noise reduction control node P1n. At the same time, since a compensation voltage has been established across the coupling unit 120 during the compensation stage, and the voltage across the capacitor cannot change abruptly, when there is a voltage change on the first noise reduction control node Pn, the voltage on the second noise reduction control node P1n will also change accordingly. At the same time, there is always a voltage difference between the second and first noise reduction control nodes Pn that is equal to the compensation voltage. Finally, the voltage reaching the second noise reduction control node P1n is: noise reduction control signal + compensation voltage (refer to the real-time threshold voltage of the transistor).

[0053] (4) Noise Reduction Execution Stage: The noise reduction execution unit 140 responds to the compensated signal on the second noise reduction control node P1n and performs noise reduction processing on the noise-reduced node. Since the compensationd noise reduction control signal has been superimposed with a compensation amount equal to the threshold voltage of the noise reduction transistor, that is, when the threshold voltage of the noise reduction transistor drifts, the compensationd noise reduction control signal also increases by the same amount, so that the actual overdrive voltage of the noise reduction transistor remains constant; so that the noise reduction transistor is always in a fully conducting state and the noise reduction capability does not decrease with the drift of the threshold voltage.

[0054] This application establishes a compensation voltage based on the real-time threshold voltage of the reference transistor during the compensation phase using a compensation voltage establishment unit 130. This compensation voltage is then locked and superimposed on the noise reduction control signal via a coupling unit 120. This ensures that the drive signal applied to the noise reduction execution unit 140 during the noise reduction phase always contains a compensation amount equal to the current threshold voltage of the noise reduction transistor. Therefore, even if the threshold voltage of the noise reduction transistor drifts significantly due to long-term operation, the compensated drive signal received by the noise reduction execution unit 140 can still enable it to conduct fully, maintaining the noise reduction capability and keeping the noise reduction circuit 100 in normal working condition. This improves the problem of unstable noise reduction caused by the threshold voltage drift of the noise reduction transistor, significantly enhancing the noise reduction stability and reliability of the noise reduction circuit 100.

[0055] Figure 5 The diagram shown is a structural schematic of the second noise reduction circuit 100 provided in an embodiment of this application; as shown Figure 5 As shown, the compensation voltage establishment unit 130 of this embodiment further includes a pre-charge subunit 131 and a voltage locking subunit 132. Specifically, the pre-charge subunit 131 is connected to the reset signal line Reset and the pre-charge node Bn, and is configured to charge the pre-charge node Bn in response to the reset signal output by the reset signal line Reset during the pre-charge period of the compensation phase, so as to establish a preset voltage on the pre-charge node Bn.

[0056] Specifically, the voltage-locked subunit 132 is connected to the frame start signal line STV, the precharge node Bn, and the second noise reduction control node P1n, respectively, and is configured to: during the triggering period of the compensation phase, in response to the frame start signal output by the frame start signal line STV, establish a compensation voltage on the coupling unit 120 based on the preset voltage already established on the precharge node Bn and the internal reference transistor. The compensation voltage is equal to the real-time threshold voltage of the reference transistor.

[0057] The specific working process of the compensation voltage establishment unit 130 in this embodiment is as follows:

[0058] (1) Work during the pre-charging period.

[0059] During the pre-charge phase of the compensation stage, the Reset signal line outputs a valid reset signal; in response to this reset signal, the pre-charge subunit 131 begins charging the pre-charge node Bn; through this charging process, a preset voltage is established and stored on the pre-charge node Bn. This preset voltage is maintained after the pre-charge phase ends, preparing for the subsequent voltage locking step.

[0060] (2) Triggering the work during the period.

[0061] During the triggering period of the compensation phase, the frame start signal line STV outputs a valid frame start signal. In response to this frame start signal, the voltage lockout subunit 132 establishes a compensation voltage on the coupling unit 120 using the preset voltage already established on the precharge node Bn and the internal reference transistor. Specifically, during the triggering period, the voltage lockout subunit 132 introduces the preset voltage of the precharge node Bn into its internal circuit and forms a specific path through the reference transistor, ultimately establishing a stable voltage difference across the coupling unit 120. The magnitude of this voltage difference is precisely equal to the real-time threshold voltage of the reference transistor.

[0062] (3) Locking of compensation voltage.

[0063] Since the coupling unit 120 has the ability to maintain the voltage difference between its two ends, the compensation voltage (i.e., the voltage difference equal to the real-time threshold voltage of the reference transistor) established on the coupling unit 120 is locked after the triggering period ends and can continue to act on the subsequent noise reduction stage.

[0064] In summary, through the aforementioned operations of the pre-charge subunit 131 and the voltage locking subunit 132, this embodiment achieves dynamic compensation for the threshold voltage drift of the noise reduction transistor. The compensation voltage establishment unit 130 extracts and locks the threshold voltage during the compensation phase (blank period + STV period), pre-storing a compensation amount equal to the real-time threshold voltage of the reference transistor at both ends of the coupling unit 120. Upon entering the noise reduction phase (non-scanning period), this compensation amount is naturally superimposed on the noise reduction control signal output by the noise reduction control unit 110, generating a compensated drive signal to control the noise reduction execution unit 140. Therefore, regardless of how the threshold voltage of the noise reduction transistor drifts, the noise reduction execution unit 140 always obtains sufficient driving capability, maintaining a stable noise reduction effect, thus solving the problem of unstable noise reduction caused by threshold voltage drift.

[0065] Figure 6 The diagram shown is a circuit diagram of the first noise reduction circuit provided in an embodiment of this application. Figure 6As shown, the pre-charge sub-unit 131 in this embodiment includes a first transistor T1 and a first capacitor C1; the control terminal and the first terminal of the first transistor T1 are connected to the reset signal line Reset, and the second terminal of the first transistor T1 is connected to the pre-charge node Bn; the first terminal of the first capacitor C1 is connected to the pre-charge node Bn, and the second terminal of the first capacitor C1 is connected to the low-level terminal VSS.

[0066] In this embodiment, as Figure 6 As shown, the voltage-locked subunit 132 includes a second transistor T2 and a third transistor T3; the control terminal of the second transistor T2 is connected to the frame start signal line STV, the first terminal of the second transistor T2 is connected to the second noise reduction control node P1n, and the second terminal of the second transistor T2 is connected to the pre-charge node Bn; the control terminal of the third transistor T3 is connected to the second noise reduction control node P1n, the first terminal of the third transistor T3 is connected to the pre-charge node Bn, and the second terminal of the third transistor T3 is connected to the low-level terminal VSS; wherein, the third transistor T3 serves as a reference transistor.

[0067] In this embodiment, as Figure 6 As shown, the noise reduction control unit 110 includes a first control transistor M1, a second control transistor M2, a third control transistor M3, a fourth control transistor M4, and a second capacitor C2. Specifically, the control terminal and the first terminal of the first control transistor M1 are connected to the noise reduction control terminal LC, and the second terminal of the first control transistor M1 is connected to the intermediate control node An. The control terminal of the second control transistor M2 is connected to the intermediate control node An, the first terminal of the second control transistor M2 is connected to the first terminal of the first control transistor M1, and the second terminal of the second control transistor M2 is connected to the first noise reduction control node Pn. The control terminal of the third control transistor M3 is connected to the drive control node Qn, the first terminal of the third control transistor M3 is connected to the intermediate control node An, and the second terminal of the third control transistor M3 is connected to the low-level terminal VSS. The control terminal of the fourth control transistor M4 is connected to the control terminal of the third control transistor M3, the first terminal of the fourth control transistor M4 is connected to the second terminal of the second control transistor M2, and the second terminal of the fourth control transistor M4 is connected to the low-level terminal VSS. The first terminal of the second capacitor C2 is connected to the intermediate control node An, and the second terminal of the second capacitor C2 is connected to the low-level terminal VSS.

[0068] In this embodiment, as Figure 6As shown, the noise reduction execution unit 140 includes a first noise reduction transistor J1, a second noise reduction transistor J2, and a third noise reduction transistor J3. Specifically, the control terminal of the first noise reduction transistor J1 is connected to the second noise reduction control node P1n, the first terminal of the first noise reduction transistor J1 is connected to the stage transmission output terminal Fn, and the second terminal of the first noise reduction transistor J1 is connected to the low-level terminal VSS. The control terminal of the second noise reduction transistor J2 is connected to the second noise reduction control node P1n, the first terminal of the second noise reduction transistor J2 is connected to the drive output terminal Gn, and the second terminal of the second noise reduction transistor J2 is connected to the low-level terminal VSS. The control terminal of the third noise reduction transistor J3 is connected to the second noise reduction control node P1n, and the second terminal of the third noise reduction transistor J3 is connected to the low-level terminal VSS.

[0069] In this embodiment, the coupling unit 120 includes a third capacitor C3.

[0070] Here, combined with Figure 7 The working principle of the noise reduction circuit 100 in this embodiment is explained as follows:

[0071] (1) Stage definition.

[0072] Compensation phase: This includes the blanking period of the current frame and the scan start period of the next frame. Figure 7 In this context, the compensation phase corresponds to the time period between time t1 and t5.

[0073] Pre-charge period: A sub-period within the compensation phase, corresponding to the period during which the reset signal is valid. Figure 7 In this context, the pre-charging period corresponds to times t2 to t3.

[0074] Triggering period: Another sub-period in the compensation phase, corresponding to the period during which the frame start signal is valid. Figure 7 In this context, the triggering period corresponds to times t4 to t5.

[0075] Noise reduction stage: This includes the non-scanning period of the current stage gate drive module, i.e., all time except for the scan time of this stage. Figure 7 In this context, the noise reduction phase corresponds to the period after time t5.

[0076] (2) t1: The compensation phase begins and the noise reduction execution unit 140 is turned off.

[0077] At time t1, the noise reduction control signal transitions from high to low, officially initiating the compensation phase. The noise reduction control unit 110 responds to this low level by outputting a low level to the first noise reduction control node Pn. This low level is coupled to the second noise reduction control node P1n via the coupling unit 120, causing the potential of the second noise reduction control node P1n to be pulled low as well. The low level of the second noise reduction control node P1n causes all noise reduction transistors in the noise reduction execution unit 140 to be turned off, ceasing the noise reduction operation on the noise-reduced nodes (drive output terminal Gn, stage transmission output terminal Fn, and drive control node Qn). At this point, the noise reduction execution unit 140 is shut down, creating conditions for the subsequent establishment of the compensation voltage.

[0078] (3) t2-t3 period: pre-charging period, the pre-charging node Bn establishes the preset voltage.

[0079] At time t2, the reset signal outputs a high-level pulse. In response to the reset signal, the precharge subunit 131 begins to charge the precharge node Bn and simultaneously charges the internal storage capacitor.

[0080] When the reset signal ends at time t3, a preset voltage is established and stored on the precharge node Bn. Since the precharge sub-unit 131 has unidirectional conductivity, the voltage on the precharge node Bn is maintained stably after the reset signal ends, preparing for the subsequent voltage locking step.

[0081] (4) t3-t4 period: waiting phase.

[0082] The period from t3 to t4 is the waiting period between the end of the precharge period and the start of the trigger period. During this period, the reset signal has ended, but the frame start signal has not yet arrived. The preset voltage stored on the precharge node Bn remains unchanged; the second noise reduction control node P1n remains at a low level; and the noise reduction execution unit 140 remains off.

[0083] (5) t4-t5 period: Triggering period, compensation voltage is established and locked.

[0084] At time t4, the frame start signal for the next frame outputs a high-level pulse. In response to this frame start signal, the voltage lockout subunit 132 transfers the preset voltage stored on the pre-charge node Bn to the second noise reduction control node P1n, causing the potential of the second noise reduction control node P1n to be pulled high.

[0085] After the second noise reduction control node P1n obtains a high potential, it acts on the reference transistor inside the voltage-locked subunit 132. This reference transistor has the same electrical characteristics as the noise reduction transistor in the noise reduction execution unit 140. Due to the specific connection method of the reference transistor, it begins to conduct and forms a discharge circuit, causing the potential of the second noise reduction control node P1n to gradually decrease.

[0086] When the potential of the second noise reduction control node P1n drops to a low level plus the real-time threshold voltage of the reference transistor, the discharge process naturally stops. At this time, a stable voltage difference is established across the coupling unit 120, which is exactly equal to the real-time threshold voltage of the reference transistor and is locked by the coupling unit 120 as the compensation voltage to be superimposed in the subsequent noise reduction stage.

[0087] At time t5, the frame start signal ends, and the path between the pre-charge node Bn and the second noise reduction control node P1n is cut off. However, since the voltage difference locked by the coupling unit 120 remains unchanged, the compensation voltage is continuously maintained.

[0088] (6) t5: The noise reduction phase begins and the noise reduction control signal is restored.

[0089] At time t5, the noise reduction control signal changes from low to high, and the noise reduction phase officially begins.

[0090] In response to the high level, the noise reduction control unit 110 outputs a high-level noise reduction control signal to the first noise reduction control node Pn when the drive control node Qn is low.

[0091] (7) After time t5: the compensation voltage is superimposed and the noise reduction execution unit 140 starts working.

[0092] Since the voltage difference across coupling unit 120 is locked to the real-time threshold voltage of the reference transistor, when the potential of the first noise reduction control node Pn jumps from low to high, the potential of the second noise reduction control node P1n also jumps through the coupling effect of coupling unit 120. During this transition, the voltage difference across coupling unit 120 remains constant. Therefore, the final potential of the second noise reduction control node P1n is equal to the original noise reduction control signal output by noise reduction control unit 110, superimposed with the real-time threshold voltage of the reference transistor. This signal is the compensated noise reduction control signal.

[0093] The compensated noise reduction control signal acts on the gate of each noise reduction transistor in the noise reduction execution unit 140, causing these transistors to conduct simultaneously, pulling the noise reduction nodes (drive output terminal Gn, stage transmission output terminal Fn, drive control node Qn) low to a low level, thereby achieving noise reduction processing.

[0094] (8) Continuous work during the noise reduction stage.

[0095] Throughout the subsequent noise reduction phase (i.e., the non-scanning period of this stage), as long as the first noise reduction control node Pn remains high, the second noise reduction control node P1n maintains a potential of "high level + reference transistor threshold voltage," and the noise reduction execution unit 140 continuously performs effective noise reduction processing on the noise-reduced node. Since the reference transistor and the noise reduction transistor have the same electrical characteristics and bias state, their threshold voltage drifts are completely synchronized. Therefore, even if the threshold voltage of the noise reduction transistor drifts during use, the compensated drive signal always contains an equal compensation amount, ensuring that the noise reduction transistor obtains sufficient conduction capability. The actual overdrive voltage of the noise reduction transistor remains constant, and the noise reduction capability does not change with threshold voltage drift.

[0096] Therefore, this embodiment achieves the following technical effects through the above working sequence and module collaboration: (1) Real-time threshold voltage extraction: Using the reference transistor, its threshold voltage is extracted in real time during the compensation stage of each frame. This value accurately reflects the current threshold voltage of the noise reduction transistor. (2) Compensation voltage locking: A preset voltage is established through the pre-charging subunit 131, and then the real-time threshold voltage of the reference transistor is locked to the coupling unit 120 in the form of voltage difference during the triggering period through the voltage locking subunit 132. (3) Dynamic compensation superposition: During the noise reduction stage, when the noise reduction control signal is transmitted through the coupling unit 120, it is automatically superimposed with the locked compensation voltage to generate a compensated driving signal. (4) Noise reduction capability maintenance: Since the driving signal always contains a compensation amount equal to the current threshold voltage of the noise reduction transistor, the overdrive voltage of the noise reduction transistor remains constant, and the noise reduction capability does not decay with the threshold voltage drift. (5) Signal multiplexing: Only the existing global signals (noise reduction control signal, reset signal, frame start signal) and nodes in the GOA circuit are used, without the need to add additional control signal lines, which is low cost and highly universal.

[0097] Figure 8 The diagram shown is a circuit diagram of the second noise reduction circuit provided in an embodiment of this application; Figure 8 The noise reduction circuit shown is Figure 6 The difference shown is that a fourth transistor T4 is added to the pre-charge sub-unit 131, while one less noise reduction transistor is found in the noise reduction execution unit 140; specifically as follows: Figure 8 As shown, the pre-charge subunit 131 in this embodiment includes, in addition to, Figure 6 In addition to the first transistor T1 and the first capacitor C1, the system also includes a fourth transistor T4, the control terminal and the first terminal of the fourth transistor T4 are connected to the noise-reduced node, and the second terminal of the fourth transistor T4 is connected to the pre-charged node Bn.

[0098] It should be noted that the fourth transistor T4 is connected in a gate-drain diode configuration between the noise-reduced node and the pre-charged node Bn. Its functions include:

[0099] (1) Transistor reuse: During the noise reduction stage, the reference transistor in the voltage lock subunit 132 is reused as a noise reduction transistor, so that the reference transistor simultaneously undertakes the threshold voltage reference function and the noise reduction function, thereby reducing the number of noise reduction transistors in the noise reduction execution unit 140.

[0100] (2) Isolate interference: prevent the signal jump of the noise-reduced node (such as the stage transmission output Fn) from interfering with the potential of the pre-charged node Bn through the parasitic path, and ensure the accuracy of the compensation voltage establishment.

[0101] (3) Unidirectional charging: When the noise-reduced node is at a high level, the fourth transistor T4 is turned on to provide charging current to the pre-charged node Bn; when the potential of the noise-reduced node is lower than that of the pre-charged node Bn, the fourth transistor T4 is turned off to prevent reverse discharge of charge.

[0102] This embodiment simplifies the circuit and reduces the layout area by adding a fourth transistor T4 to the pre-charge sub-unit 131 and removing a noise reduction transistor, while maintaining the compensation effect. At the same time, the unidirectional conduction characteristic of the fourth transistor T4 is used to isolate interference and ensure compensation accuracy.

[0103] The inventors of this application have discovered through their research that Figure 6 The illustrated embodiments have the following potential problems:

[0104] (1) The second capacitor C2 affects the response speed: In Figure 6 In the illustrated embodiment, the second capacitor C2 is used to maintain the potential of the intermediate control node An when the noise reduction control signal is low, keeping the second control transistor M2 on and thus pulling the first noise reduction control node Pn low. However, the introduction of the second capacitor C2 slows down the potential response of the intermediate control node An, making it only suitable for low refresh rate products; in high refresh rate products, the response delay may affect the output performance of the GOA circuit.

[0105] (2) The pull-down capability of the first noise reduction control node Pn is limited: Figure 6 In the illustrated embodiment, the pull-down of the first noise reduction control node Pn mainly relies on the second control transistor M2. Since the second control transistor M2 is typically small in size, its pull-down capability is limited, which may result in the first noise reduction control node Pn not being sufficiently pulled down.

[0106] (3) The accuracy of the compensation voltage is affected by differences in wiring: Figure 6In the illustrated embodiment, the first noise reduction control node Pn is pulled down to the low level provided by the noise reduction control signal, while the second noise reduction control node P1n is discharged to the low level provided by the low-level terminal VSS plus the threshold voltage of the reference transistor. The actual low-level voltage may deviate due to factors such as differences in trace width, load, or signal coupling, resulting in the voltage difference across the coupling unit 120 not being precisely equal to the threshold voltage of the reference transistor, thus affecting the compensation accuracy.

[0107] To address the aforementioned problems, this application provides an improved noise reduction circuit, specifically including the following embodiments:

[0108] Figure 9 The diagram shown is a circuit diagram of the third noise reduction circuit provided in an embodiment of this application; Figure 9 The noise reduction circuit shown is Figure 6 The difference shown is that the connection method of the second terminal of the third transistor T3 is changed, and the second capacitor C2 is replaced with the fifth control transistor M5; specifically as follows: Figure 9 As shown, the voltage lockout subunit 132 in this embodiment includes: a second transistor T2 and a third transistor T3; the control terminal of the second transistor T2 is connected to the frame start signal line STV, the first terminal of the second transistor T2 is connected to the second noise reduction control node P1n, and the second terminal of the second transistor T2 is connected to the precharge node Bn; the control terminal of the third transistor T3 is connected to the second noise reduction control node P1n, the first terminal of the third transistor T3 is connected to the precharge node Bn, and the second terminal of the third transistor T3 is connected to the first noise reduction control node Pn.

[0109] The noise reduction control unit 110 in this embodiment includes a first control transistor M1, a second control transistor M2, a third control transistor M3, a fourth control transistor M4, and a fifth control transistor M5. The control terminal and first terminal of the first control transistor M1 are connected to the noise reduction control terminal LC, and the second terminal of the first control transistor M1 is connected to the intermediate control node An. The control terminal of the second control transistor M2 is connected to the intermediate control node An, and the first terminal of the second control transistor M2 is connected to the first terminal of the first control transistor M1. The second terminal of the second control transistor M2 is connected to the first noise reduction control node Pn. The control terminal of the third control transistor M3... The control terminal of the third control transistor M3 is connected to the drive control node Qn. The first terminal of the third control transistor M3 is connected to the intermediate control node An, and the second terminal of the third control transistor M3 is connected to the low-level terminal VSS. The control terminal of the fourth control transistor M4 is connected to the control terminal of the third control transistor M3. The first terminal of the fourth control transistor M4 is connected to the second terminal of the second control transistor M2, and the second terminal of the fourth control transistor M4 is connected to the low-level terminal VSS. The control terminal of the fifth control transistor M5 is connected to the frame start signal line STV. The first terminal of the fifth control transistor M5 is connected to the first noise reduction control node Pn, and the second terminal of the fifth control transistor M5 is connected to the low-level terminal VSS.

[0110] It should be noted that, in combination Figure 6 and Figure 9 The specific improvements in this embodiment of the circuit structure shown are as follows:

[0111] (1) Remove the second capacitor C2 and add the fifth control transistor M5.

[0112] This embodiment cancels Figure 6 The second capacitor C2 is used to avoid its impact on the response speed of the intermediate control node An. Meanwhile, the advantages of adding a fifth control transistor M5 to the noise reduction control unit 110 are: ① The pull-down of the first noise reduction control node Pn no longer depends on the second control transistor M2, resulting in faster pull-down speed and more reliable performance; ② The intermediate control node An is no longer affected by the delay of the second capacitor C2, improving the response speed and making it suitable for high refresh rate products.

[0113] (2) Change the source connection of the reference transistor.

[0114] In this embodiment, the source connection method of the third transistor T3 (reference transistor) in the voltage-locked subunit 132 is changed by... Figure 6The connection to the low-level terminal VSS in the previous section was changed to connect to the first noise reduction control node Pn. This improvement makes the discharge circuit of the third transistor T3 during the triggering period: second noise reduction control node P1n → third transistor T3 → first noise reduction control node Pn. Since the first noise reduction control node Pn has been pulled down to a low level by the fifth control transistor M5, the final potential of the second noise reduction control node P1n after discharging through the third transistor T3 is: the potential of the first noise reduction control node Pn (V_Pn) plus the real-time threshold voltage of the reference transistor (Vth_ref).

[0115] Meanwhile, the voltage difference established across the coupling unit 120 is: the potential of the second noise reduction control node P1n minus the potential of the first noise reduction control node Pn, i.e. (V_Pn + Vth_ref) - V_Pn = Vth_ref.

[0116] Therefore, the voltage difference across the coupling unit 120 is precisely equal to the real-time threshold voltage of the reference transistor, and is independent of the actual low-level value of the first noise reduction control node Pn. Regardless of how much the low-level value of the first noise reduction control node Pn deviates from the ideal value due to factors such as wiring differences, load differences, or signal coupling, this deviation will be canceled out during the subtraction process, thereby ensuring the accuracy of the compensation voltage.

[0117] The working sequence of this embodiment and Figure 6 The embodiments shown are basically the same, except that the pull-down method of the first noise reduction control node Pn in the compensation stage is adjusted:

[0118] (1) Compensation phase:

[0119] ①During the t1-t4 period: the noise reduction control signal is at a low level, the first control transistor M1 in the noise reduction control unit 110 is turned off, but the second control transistor M2 remains on, and the first noise reduction control node Pn is initially pulled low.

[0120] ② Triggering period (t4-t5): The frame start signal outputs a high-level pulse. At this time, the fifth control transistor M5 is turned on, strongly pulling down the first noise reduction control node Pn to a low level; at the same time, the second transistor T2 in the voltage lockout subunit 132 is turned on, transferring the preset voltage of the pre-charge node Bn to the second noise reduction control node P1n; the reference transistor (whose source is connected to the first noise reduction control node Pn) forms a discharge circuit, causing the potential of the second noise reduction control node P1n to drop to "the potential of the first noise reduction control node Pn + the threshold voltage of the reference transistor"; a compensation voltage that is exactly equal to the real-time threshold voltage of the reference transistor is established and locked at both ends of the coupling unit 120.

[0121] (2) Noise reduction stage:

[0122] After time t5, the noise reduction control signal becomes high level, and the noise reduction control unit 110 outputs a high-level noise reduction control signal to the first noise reduction control node Pn. This signal is superimposed with the locked compensation voltage through the coupling unit 120 to generate a compensated drive signal, which controls the noise reduction execution unit 140 to perform noise reduction processing on the noise-reduced node.

[0123] Therefore, this embodiment has the following technical effects:

[0124] (1) Improved response speed: The second capacitor C2 is removed to avoid its delay effect on the intermediate control node An; the fifth control transistor M5 is added to realize the fast pull-down of the first noise reduction control node Pn, which is suitable for high refresh rate products.

[0125] (2) Enhanced pull-down effect: The fifth control transistor M5 is used to replace the original small-sized second control transistor M2 for pull-down, which has a stronger pull-down capability and a more stable low level of the first noise reduction control node Pn.

[0126] (3) Improved compensation accuracy: The source of the reference transistor is connected to the first noise reduction control node Pn, so that the voltage difference across the coupling unit 120 is decoupled from the actual low level value of the first noise reduction control node Pn, eliminating the voltage deviation caused by wiring differences, load differences or signal coupling, and ensuring that the compensation voltage is exactly equal to the real-time threshold voltage of the reference transistor.

[0127] (4) Greater applicability: The improved solution in this embodiment takes into account the needs of both low refresh rate and high refresh rate products, and is applicable to a wider range of application scenarios.

[0128] In one embodiment, this application provides a gate driving circuit including N cascaded gate driving modules. The nth-stage gate driving module includes a pull-up unit, a pull-down unit, an output unit, and a noise reduction circuit. The pull-up unit is connected to the drive output terminal and the stage transmission output terminal of the ni-th-stage gate driving module, respectively. The pull-down unit is connected to the stage transmission output terminal of the (n+j)th-stage gate driving module and is also connected to the pull-up unit through a drive control node. The output unit is connected to a clock signal terminal and a drive control node, respectively. The noise reduction circuit is connected to the drive control node, drive output terminal, and stage transmission output terminal of the current-stage gate driving module, respectively.

[0129] It should be noted that the specific structure of the gate driving module provided in this embodiment is as follows: Figure 1 As shown above, the working principle of the gate drive module was explained using i=3 and j=4 as an example, and will not be repeated here.

[0130] In one embodiment, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes a gate driving circuit. The drive output terminal of the circuit unit in the gate driving circuit is electrically connected to at least one scan line.

[0131] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0132] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0133] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A noise reduction circuit, characterized in that, The noise reduction circuit includes: A noise reduction control unit, connected to a first noise reduction control node, is configured to: output a noise reduction control signal to the first noise reduction control node during the noise reduction phase; and output a low level to the first noise reduction control node during the compensation phase; wherein the compensation phase includes the blanking period of the current frame and the scan start period of the next frame; and the noise reduction phase includes the non-scanning period of the current stage gate drive module. The coupling unit, coupled between the first noise reduction control node and the second noise reduction control node, is configured to couple the voltage change of the first noise reduction control node to the second noise reduction control node. A compensation voltage establishment unit, connected to the second noise reduction control node, is configured to: establish a compensation voltage on the coupling unit based on the low level of the first noise reduction control node and the real-time threshold voltage of the reference transistor during the compensation phase; A noise reduction execution unit, connected to the second noise reduction control node and the noise-reduced node, is configured to: in the noise reduction stage, in response to a noise reduction control signal on the second noise reduction control node superimposed with the compensation voltage, perform noise reduction processing on the noise-reduced node; wherein the reference transistor has the same electrical characteristics as the noise reduction transistor in the noise reduction execution unit; The compensation voltage establishment unit includes: A pre-charge subunit, connected to a reset signal line and a pre-charge node, is configured to: during the pre-charge period of the compensation phase, charge the pre-charge node in response to a reset signal output by the reset signal line to establish a preset voltage on the pre-charge node; The voltage-locked subunit, connected to the frame start signal line, the pre-charge node, and the second noise reduction control node, is configured to: during the triggering period of the compensation phase, in response to the frame start signal output by the frame start signal line, establish the compensation voltage on the coupling unit based on the preset voltage and the internal reference transistor; wherein the compensation voltage is equal to the real-time threshold voltage of the reference transistor.

2. The noise reduction circuit according to claim 1, characterized in that, The precharge sub-unit includes: The first transistor has its control terminal and first terminal connected to the reset signal line, and its second terminal connected to the precharge node. A first capacitor, the first end of which is connected to the pre-charge node, and the second end of which is connected to a low-level terminal.

3. The noise reduction circuit according to claim 2, characterized in that, The voltage lockout subunit includes: The second transistor has its control terminal connected to the frame start signal line, its first terminal connected to the second noise reduction control node, and its second terminal connected to the precharge node. The third transistor has its control terminal connected to the second noise reduction control node, its first terminal connected to the pre-charge node, and its second terminal connected to the low-level terminal. The third transistor serves as the reference transistor.

4. The noise reduction circuit according to claim 2, characterized in that, The voltage lockout subunit includes: The second transistor has its control terminal connected to the frame start signal line, its first terminal connected to the second noise reduction control node, and its second terminal connected to the precharge node. The third transistor has a control terminal connected to the second noise reduction control node, a first terminal connected to the pre-charge node, and a second terminal connected to the first noise reduction control node. The third transistor serves as the reference transistor.

5. The noise reduction circuit according to claim 3, characterized in that, The noise reduction control unit includes: The first control transistor has a control terminal and a first terminal connected to a noise reduction control terminal, and a second terminal connected to an intermediate control node. The second control transistor has its control terminal connected to the intermediate control node, its first terminal connected to the first terminal of the first control transistor, and its second terminal connected to the first noise reduction control node. The third control transistor has its control terminal connected to the drive control node, its first terminal connected to the intermediate control node, and its second terminal connected to the low-level terminal. A fourth control transistor, wherein the control terminal of the fourth control transistor is connected to the control terminal of the third control transistor, the first terminal of the fourth control transistor is connected to the second terminal of the second control transistor, and the second terminal of the fourth control transistor is connected to the low-level terminal; The second capacitor has its first terminal connected to the intermediate control node and its second terminal connected to the low-level terminal.

6. The noise reduction circuit according to claim 4, characterized in that, The noise reduction control unit includes: The first control transistor has a control terminal and a first terminal connected to a noise reduction control terminal, and a second terminal connected to an intermediate control node. The second control transistor has its control terminal connected to the intermediate control node, its first terminal connected to the first terminal of the first control transistor, and its second terminal connected to the first noise reduction control node. The third control transistor has its control terminal connected to the drive control node, its first terminal connected to the intermediate control node, and its second terminal connected to the low-level terminal. A fourth control transistor, wherein the control terminal of the fourth control transistor is connected to the control terminal of the third control transistor, the first terminal of the fourth control transistor is connected to the second terminal of the second control transistor, and the second terminal of the fourth control transistor is connected to the low-level terminal; The fifth control transistor has its control terminal connected to the frame start signal line, its first terminal connected to the first noise reduction control node, and its second terminal connected to the low-level terminal.

7. The noise reduction circuit according to any one of claims 2-6, characterized in that, The precharge subunit also includes: The fourth transistor has its control terminal and first terminal connected to the noise-reduced node, and its second terminal connected to the pre-charged node.

8. A gate driving circuit, comprising N cascaded gate driving modules, characterized in that, The nth-stage gate drive module includes: Pull-up unit, the pull-up unit is connected to the drive output terminal of the ni-th gate drive module and the stage transmission output terminal of the ni-th gate drive module respectively; A pull-down unit is connected to the stage transmission output terminal of the (n+j)th stage gate drive module, and the pull-down unit is also connected to the pull-up unit through a drive control node; An output unit, wherein the output unit is connected to both the clock signal terminal and the drive control node; The noise reduction circuit according to any one of claims 1-7 is connected to the drive control node, drive output terminal and stage transmission output terminal of the current stage gate drive module, respectively.

9. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines; characterized in that, The non-display area includes the gate driving circuit of claim 8, wherein the driving output terminal of the circuit unit in the gate driving circuit is electrically connected to at least one scan line.

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