Electro-optical device and electronic apparatus

Abstract

The present application provides an electro-optical device and an electronic device, which can realize a high-precision electro-optical device. The electro-optical device (1) comprises: a supply circuit (40a) corresponding to one light emitting element and a supply circuit (40b) corresponding to another light emitting element and arranged opposite to the supply circuit (40a) in a first direction in a plan view. The supply circuits (40a, 40b) each comprise a transistor (121) for driving the corresponding light emitting element. In addition, the electro-optical device (1) comprises a conductive layer (60) electrically connected to the two transistors (121), supplied with a fixed voltage potential Vel, and arranged along a second direction intersecting the first direction.

Description

[0001] This application is a divisional application of the invention patent application entitled "Electro-optical device and electronic device", filed on June 30, 2022, with application number 202210756143.X. Technical Field

[0002] This invention relates to electro-optical devices and electronic devices. Background Technology

[0003] Conventionally, as shown in Patent Document 1, in a display device in which pixels having a light-emitting part and a driving circuit for driving the light-emitting part are arranged in a matrix, there exists a display device in which the m-th pixel and the (m+1)-th pixel in the column direction are arranged in a line symmetrical manner with respect to a boundary line extending in the row direction between the m-th pixel and the (m+1)-th pixel, and a shielding wall is formed on the boundary line.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2014-102319

[0005] However, in the display device described in Patent Document 1, the wiring such as control lines and power wiring that are electrically connected to the drive circuit is arranged in columns or rows, which presents the problem that it is impossible to provide a display device with higher precision. Summary of the Invention

[0006] The electro-optical device includes: a first light-emitting element and a second light-emitting element; a first driving transistor corresponding to the first light-emitting element; a second driving transistor corresponding to the second light-emitting element and disposed opposite to the first driving transistor in a first direction when viewed from above; and a first conductive layer electrically connected to the first driving transistor and the second driving transistor, supplied with a fixed voltage, and disposed along a second direction intersecting the first direction. Attached Figure Description

[0007] Figure 1 This is a block diagram showing the structure of the electro-optical device according to Embodiment 1.

[0008] Figure 2 This is an equivalent circuit diagram showing the electrical structure of the pixel circuit in an electro-optical device.

[0009] Figure 3 This is a top view showing the layout of the gate electrode and impurity region in the supply circuit.

[0010] Figure 4 This is a top view showing the layout of the first wiring layer in the supply circuit.

[0011] Figure 5 It is along Figure 4 The sectional view obtained by cutting along line AA.

[0012] Figure 6 It is along Figure 4 The sectional view obtained by cutting along the BB line.

[0013] Figure 7 It is along Figure 4 The sectional view obtained by cutting along the CC line.

[0014] Figure 8 It is along Figure 4 The sectional view obtained by cutting along the DD line.

[0015] Figure 9 This is a top view showing the layout of the gate electrode and impurity region in the supply circuit of Embodiment 2.

[0016] Figure 10 This is a top view showing the layout of the first wiring layer in the supply circuit of Embodiment 2.

[0017] Figure 11 It is along Figure 10 The sectional view obtained by cutting along line AA.

[0018] Figure 12 This is a top view showing the layout of the gate electrode and impurity region in the supply circuit of Embodiment 3.

[0019] Figure 13 This is a top view showing the layout of the first wiring layer in the supply circuit of Embodiment 3.

[0020] Figure 14 It is along Figure 13 The sectional view obtained by cutting along line AA.

[0021] Figure 15 This is a top view schematically showing part of a virtual image display device as an example of an electronic device.

[0022] Figure 16 This is a three-dimensional view showing a personal computer as an example of an electronic device.

[0023] Label Explanation

[0024] 1: Electro-optic device; 3: Light-emitting element; 10: Display panel; 11: Driving circuit; 12: Scan line; 13: Display unit; 14: Data line; 16: Power supply wiring; 20: Control circuit; 31: Pixel electrode; 32: Light-emitting functional layer; 33: Opposing electrode; 40, 40a, 40b, 40c, 40d, 40e, 40f: Supply circuit; 60, 61, 62: Conductive layer; 64: Relay wiring; 71: Collimator; 72: Light guide; 73: First reflective volume hologram; 74: Second reflective volume hologram; 79: Control unit; 100: Pixel circuit; 111: Scan line driving circuit; 112: Data line driving circuit; 116, 118: Power supply wiring; 121, 122, 123, 124: Transistors; 132: Capacitors; 143, 144: Control lines; 170: N-well; 180: Impurity region; 400: Personal computer; 401: Power switch; 402: Keyboard; 403: Main body; 409: Control unit; 700: Virtual image display device; 721, 722: Surfaces; G1, G2, G3, G4: Gate electrodes; Ha1, Ha2, Ha3, Ha4, Ha5, Ha7, Ha8, Ha10: Contact holes; H1, H2: Spacing; L0: Gate insulating film; L1: Interlayer insulating layer; LL: Image beam; M1: First wiring layer; P: Imaginary line; SD1: Region; Vct; Vel: Potential. Detailed Implementation

[0025] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples illustrating the present invention. The present invention is not limited to the following embodiments.

[0026] Furthermore, in the following figures, the scale of each layer or component differs from the actual size in order to make each layer or component identifiable. In the following description, for example, for a substrate, the phrase "on the substrate" indicates any one of the following: a configuration that is in contact with the substrate, a configuration that is separated from the substrate by other structures, or a configuration that is partially in contact with the substrate and partially separated from other structures.

[0027] 1A. Implementation Method 1

[0028] As an example of the electro-optical device in Embodiment 1, an organic EL (electroluminescent) device is shown. This organic EL device is suitable, for example, for use in head-mounted displays (HMDs), which are electronic devices described later. (See also...) Figure 1 and Figure 2 An overview of the electro-optical device 1 of this embodiment will be described.

[0029] like Figure 1As shown, the electro-optical device 1 of this embodiment includes: a display panel 10 having a plurality of pixel circuits 100 described later; and a control circuit 20 that controls the operation of the display panel 10.

[0030] A host device (not shown) supplies digital image data (Video) to the control circuit 20 in sync with a synchronization signal. Here, the image data (Video) is digital data specifying the grayscale levels that each pixel circuit 100 of the display panel 10 should display. The synchronization signal includes signals such as a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal.

[0031] The control circuit 20 generates a control signal Ctr based on a synchronization signal to control the operation of the display panel 10, and supplies the generated control signal Ctr to the display panel 10. Furthermore, the control circuit 20 generates an analog image signal Vid based on image data Video, and supplies the generated image signal Vid to the display panel 10. Here, the image signal Vid is a signal that defines the brightness of the light-emitting element of each pixel circuit 100 in a manner specified by the grayscale of the image data Video displayed by each pixel circuit 100.

[0032] The display panel 10 includes a display section 13 and a driving circuit 11 for driving the display section 13. The display section 13 has M scan lines 12 extending along the X-axis, 3N data lines 14 extending along the Y-axis intersecting the X-axis, and M×3N pixel circuits 100 arranged corresponding to the intersections of the M scan lines 12 and the 3N data lines 14. Here, M and N are each independent natural numbers greater than 1.

[0033] In the following description, in order to distinguish between the multiple pixel circuits 100, the multiple scan lines 12 and the multiple data lines 14, they are referred to as row 1, row 2, ..., row M in the -Y direction, and as column 1, column 2, ..., column 3N in the +X direction.

[0034] Among the multiple pixel circuits 100 provided in the display unit 13, there are pixel circuits 100 capable of displaying red (R), pixel circuits 100 capable of displaying green (G), and pixel circuits 100 capable of displaying blue (B). Furthermore, consider the following scenario: in the electro-optical device 1, n is set to a natural number satisfying 1 ≤ n ≤ N. A pixel circuit 100 capable of displaying R is arranged in the (3n-2)th column from the 1st to the 3Nth column, a pixel circuit 100 capable of displaying G is arranged in the (3n-1)th column, and a pixel circuit 100 capable of displaying B is arranged in the 3nth column. The driving circuit 11 includes a scan line driving circuit 111 and a data line driving circuit 112.

[0035] The scan line driving circuit 111 sequentially selects scan lines 12 from row 1 to row M. Specifically, during one frame, the scan line driving circuit 111 sequentially sets the scan signals / Gwr(1) to / Gwr(M) output to scan lines 12 from row 1 to row M to a predetermined selection potential for each horizontal scan period, thereby selecting scan lines 12 sequentially on a row-by-row basis for each horizontal scan period. In other words, during the m-th horizontal scan period of one frame, the scan line driving circuit 111 sets the scan signal / Gwr(m) output to scan line 12 in row m to a predetermined selection potential, thereby selecting scan line 12 in row m. Furthermore, one frame refers to the period during which the electro-optical device 1 displays one image.

[0036] The data line driving circuit 112 outputs analog data signals Vd(1) to Vd(3N) specifying the grayscale that each pixel circuit 100 should display during each horizontal scan period, based on the image signal Vid supplied from the control circuit 20 and the control signal Ctr. In other words, the data line driving circuit 112 outputs a data signal Vd(k) to the k-th column of data lines 14 during each horizontal scan period.

[0037] In addition, in this embodiment, the image signal Vid output by the control circuit 20 is an analog signal, but the image signal Vid output by the control circuit 20 can also be a digital signal. In this case, the data line drive circuit 112 performs D / A conversion on the image signal Vid to generate analog data signals Vd(1) to Vd(3N).

[0038] like Figure 2 As shown, the pixel circuit 100 includes a light-emitting element 3 and a supply circuit 40 for supplying current to the light-emitting element 3. The light-emitting element 3 includes a pixel electrode 31, a light-emitting functional layer 32, and a counter electrode 33. The pixel electrode 31 functions as an anode that supplies holes to the light-emitting functional layer 32. The counter electrode 33 is electrically connected to a power supply wiring 118 set to a low-potential side of the pixel circuit 100, namely a potential Vct, and functions as a cathode that supplies electrons to the light-emitting functional layer 32. Furthermore, holes supplied from the pixel electrode 31 and electrons supplied from the counter electrode 33 recombine in the light-emitting functional layer 32, thereby causing the light-emitting functional layer 32 to emit light.

[0039] Furthermore, although detailed descriptions are omitted, a red color filter is superimposed on the light-emitting element 3 of the pixel circuit 100 capable of emitting R light. A green color filter is superimposed on the light-emitting element 3 of the pixel circuit 100 capable of emitting G light. A blue color filter is superimposed on the light-emitting element 3 of the pixel circuit 100 capable of emitting B light.

[0040] The supply circuit 40 includes P-channel transistors 121-124 and capacitor element 132. In addition to the scan signal / Gwr(i), the scan line drive circuit 111 supplies control signals / Gcmp(i) and / Gel(i) to the supply circuit 40 of the i-th row. The display panel 10 is provided with control lines 143 and 144 of M rows. The scan line drive circuit 111 supplies control signals / Gcmp(1), / Gcmp(2), / Gcmp(3), ..., / Gcmp(M) to the control lines 143 of the 1st, 2nd, 3rd, ..., Mth rows, respectively, and supplies control signals / Gel(1), / Gel(2), / Gel(3), ..., / Gel(M) to the control lines 144 of the 1st, 2nd, 3rd, ..., Mth rows, respectively.

[0041] The gate electrode G1 of transistor 121 is electrically connected to one of the source and drain regions of transistor 122. Additionally, one of the source and drain regions of transistor 121 is electrically connected to a power supply wiring 116, which serves as a second conductive layer and is supplied with a fixed voltage, i.e., potential Vel. The other of the source and drain regions of transistor 121 is electrically connected to one of the source and drain regions of transistor 123 and one of the source and drain regions of transistor 124. Furthermore, one end of capacitor element 132 is electrically connected to the gate electrode G1 of transistor 121, and the other end of capacitor element 132 is electrically connected to the power supply wiring 116, which carries a fixed voltage, such as potential Vel. Therefore, capacitor element 132 maintains the voltage between the gate electrode G1 and one of the source and drain regions in transistor 121. This transistor 121 is an example of a driving transistor through which current corresponding to the voltage between the gate electrode G1 and one of the source and drain regions of transistor 121 flows.

[0042] Alternatively, as the capacitor element 132, a capacitor parasitic in the gate electrode G1 of the transistor 121 can be used, or a capacitor formed by sandwiching an insulating layer on a silicon substrate using different conductive layers can be used.

[0043] In the transistor 122 of the supply circuit 40 in the i-th row and any column, the gate electrode G2 is electrically connected to the scan line 12 of the i-th row, one of the source region and the drain region is electrically connected to the gate electrode G1 of the transistor 121, and the other of the source region and the drain region is connected to the data line 14 of that column.

[0044] In the transistor 123 of the supply circuit 40 in the i-th row and any column, the gate electrode G3 is electrically connected to the control line 143 supplied with the control signal / Gcmp(i), one of the source region and the drain region is electrically connected to the other of the source region and the drain region of transistor 121 and one of the source region and the drain region of transistor 124, and the other of the source region and the drain region is electrically connected to the data line 14 of that column.

[0045] In the transistor 124 of the supply circuit 40 located in the i-th row and any column, the gate electrode G4 is electrically connected to the control line 144 supplied with the control signal / Gel(i), one of the source region and the drain region is electrically connected to the other of the source region and the drain region of transistor 121 and one of the source region and the drain region of transistor 123, and the other of the source region and the drain region is electrically connected to the pixel electrode 31, which serves as the anode of the light-emitting element 3.

[0046] Furthermore, the counter electrode 33, which functions as the cathode of the light-emitting element 3, is electrically connected to the power supply wiring 118 at potential Vct. Additionally, since the display panel 10 is formed on a silicon substrate, the substrate potential of transistors 121-124 is, for example, set to a potential equivalent to potential Vel.

[0047] Furthermore, the source and drain regions of transistors 121-124 can be replaced according to the channel type and potential relationship of transistors 121-124. Additionally, transistors 121-124 can be thin-film transistors or field-effect transistors.

[0048] Next, refer to Figures 3-8 The structure of the supply circuit 40 in particular within the pixel circuit 100 will be described. Furthermore, in this embodiment, a P-type semiconductor substrate, which serves as a silicon substrate, is used as the substrate. An N-well 170 is formed on approximately the entire surface of the substrate.

[0049] A potential Vel is supplied to the N-well 170 via an N-type diffusion region. Furthermore, multiple P-type diffusion regions are formed by doping the surface of the N-well 170 with impurities. The P-type diffusion regions can function as either the source or drain regions of transistors 121-124. In this embodiment, both the P-type and N-type diffusion regions are collectively referred to as impurity regions 180.

[0050] Figure 3This is a top view showing the layout of gate electrodes G1 to G4 and impurity regions 180 in three adjacent supply circuits 40a to 40f arranged in the X-axis direction and two adjacent supply circuits arranged in the Y-axis direction. Gate electrodes G1 to G4 are formed on a portion of a silicon semiconductor substrate with a gate insulating film L0 in between, and impurity regions 180, which serve as source and drain regions, are formed in the semiconductor substrate on both sides thereon, thereby forming transistors 121 to 124.

[0051] Figure 4 It is shown Figure 3 The first wiring layer M1 in the supply circuits 40a-40f shown (refer to) Figure 5 The diagram shows a top view of the layout of the first wiring layer M1, with the gate electrodes G1-G4 and the impurity region 180 arranged in a specific configuration. The first wiring layer M1 is formed on a semiconductor substrate on which transistors 121-124 are formed, separated by an interlayer insulating layer L1. For example, the interlayer insulating layer L1 is formed of silicon dioxide, and the first wiring layer M1 is formed of aluminum. Additionally, the markings marked with × within □ in the diagram indicate contact holes provided in the interlayer insulating layer L1 for connecting the wiring of each layer to the upper layer.

[0052] Figure 5 It is along Figure 4 The sectional view obtained by cutting along line AA. Figure 6 It is along Figure 4 The sectional view obtained by cutting along the BB line. Figure 7 It is along Figure 4 The sectional view obtained by cutting along the CC line. Figure 8 It is along Figure 4 The sectional view obtained by cutting along the DD line. Figures 5-8 The first wiring layer M1 is shown, and the upper layer structure is omitted. Furthermore, the structures of the six supply circuits 40a to 40f are largely the same in each row, so the reference numerals for the structural elements are appropriately omitted. In addition, the following description mainly focuses on supply circuits 40a and 40b of supply circuits 40a to 40f, but supply circuits 40c and 40d, as well as supply circuits 40e and 40f, also have the same structure.

[0053] like Figures 3 to 8As shown, supply circuits 40a to 40f each include transistors 121 to 124. Furthermore, in top view, a conductive layer 60, serving as a first conductive layer, is provided between supply circuits 40a and 40b arranged adjacent to each other in the Y-axis direction, and is arranged along the X-axis direction. That is, the conductive layer 60 is arranged across both supply circuits 40a and 40b. The conductive layer 60 is a conductive layer supplied with a potential Vel as a fixed voltage, and is electrically connected to transistors 121 included in supply circuit 40a and supply circuit 40b. The conductive layer 60 is provided in the same layer as the gate electrodes G1 to G4 of transistors 121 to 124. Hereinafter, the Y-axis direction will also be referred to as the "first direction," and the X-axis direction, which intersects the Y-axis direction, will also be referred to as the "second direction."

[0054] Specifically, the conductive layer 60 is electrically connected to the power supply wiring 116 disposed on the first wiring layer M1 via contact hole Ha1. That is, the conductive layer 60 and the power supply wiring 116 are supplied with the same potential. Furthermore, the power supply wiring 116 is electrically connected via contact hole Ha2 to region SD1 in the impurity region 180, which becomes one of the source and drain regions of the transistor 121. That is, the conductive layer 60 is electrically connected via the power supply wiring 116 to region SD1, which becomes one of the source and drain regions of the transistor 121.

[0055] Furthermore, when viewed from above, the conductive layer 60 is disposed between the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40b.

[0056] Furthermore, when viewed from above, the distance H1 between the conductive layer 60 and the gate electrode G1 of the transistor 121 included in the supply circuit 40a is equal to the distance H2 between the conductive layer 60 and the gate electrode G1 of the transistor 121 included in the supply circuit 40b.

[0057] Furthermore, when viewed from above, in the two supply circuits 40a and 40b arranged adjacent to each other in the first direction, transistors 121 to 124 are arranged in a line-symmetrical configuration with respect to an imaginary line P that overlaps with the conductive layer 60 and extends in the second direction. In this invention, the imaginary line P refers to an imaginary straight line that passes through the center of the conductive layer 60 and extends along the second direction when viewed from above. However, the imaginary line P can also be a straight line passing through a position offset from the center of the conductive layer 60.

[0058] Furthermore, it is preferable that the transistors 121 in the four transistors 121 to 124 included in each of the supply circuits 40a and 40b are arranged in a linearly symmetrical manner with respect to the imaginary line P, while the transistors 122 to 124 may not be linearly symmetrical.

[0059] Furthermore, when viewed from above, a portion of the impurity region 180 extends along the second direction in a manner that overlaps with the conductive layer 60.

[0060] like Figure 3 as well as Figure 5 As shown, the impurity region 180 includes a region SD1 that forms one of the source and drain regions of the transistor 121 included in the supply circuits 40a-40f, and is electrically connected to the power supply wiring 116 via a contact hole Ha2. That is, the impurity region 180 is electrically connected to the conductive layer 60 via the power supply wiring 116, and a potential Vel is supplied to the impurity region 180. Furthermore, although not shown in the figure, the impurity region 180 is provided throughout the second direction of the display section 13.

[0061] like Figures 4-8 As shown, scan lines 12, control lines 143, 144, relay wiring 64, and power wiring 16 are formed together with power wiring 116 on the first wiring layer M1. Scan lines 12 are arranged in rows along the second direction and are electrically connected to the gate electrode G2 of the transistors 122 included in each of the supply circuits 40a to 40f via contact holes Ha3.

[0062] The control lines 143 are arranged in rows along the second direction and are electrically connected via contact holes Ha4 to the gate electrodes G3 of the transistors 123 included in the supply circuits 40a to 40f respectively.

[0063] The control lines 144 are arranged in rows along the second direction and are electrically connected via contact holes Ha5 to the gate electrodes G4 of the transistors 124 included in the supply circuits 40a to 40f respectively.

[0064] Relay wiring 64 is provided in each supply circuit 40. Relay wiring 64 is electrically connected to the gate electrode G1 of transistor 121 via contact hole Ha7, and electrically connected to one of the source region and drain region of transistor 122 via contact hole Ha8.

[0065] Power supply wiring 16 is a conductive layer supplied with a fixed voltage, such as potential Vel. Power supply wiring 16 is arranged in rows along a second direction, and a portion of it extends in a first direction. When viewed from above, this portion is positioned between relay wirings 64 of adjacent supply circuits 40 in the second direction. Specifically, when viewed from above, power supply wiring 16 is positioned between relay wirings 64 of supply circuits 40a and 40c, and between relay wirings 64 of supply circuits 40a and 40e, and between relay wirings 64 of supply circuits 40b and 40d, and between relay wirings 64 of supply circuits 40b and 40f.

[0066] The power supply wiring 116 is arranged along a second direction, spanning both the row containing supply circuit 40a and the row containing supply circuit 40b. In plan view, the power supply wiring 116 is electrically connected via contact hole Ha2 to region SD1, which is one of the source or drain regions of the transistors 121 included in each of the supply circuits 40a-40f. Furthermore, in plan view, the power supply wiring 116 overlaps with the conductive layer 60. Also in plan view, the power supply wiring 116 overlaps with the impurity region 180.

[0067] Furthermore, when viewed from above, at least a portion of the power supply wiring 116 is disposed between the gate electrode G1 of the transistor 121 included in each of the supply circuits 40a, 40c, and 40e arranged along the second direction and the gate electrode G1 of the transistor 121 included in each of the supply circuits 40b, 40d, and 40f arranged along the second direction. That is, when viewed from above, at least a portion of the power supply wiring 116 is disposed between the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40b.

[0068] exist Figure 3 and Figure 4 The diagram shows two supply circuits 40 arranged adjacent to each other in the first direction, but the layout of the other supply circuits 40 is also the same as that of the two supply circuits 40 arranged adjacent to each other in the first direction. Regarding the two supply circuits 40 arranged adjacent to each other in the second direction, the same pattern can be repeated, or they can be arranged symmetrically about an imaginary line. Furthermore, the first and second directions in the layout of the supply circuits 40 are not limited to... Figure 1 The X-axis and Y-axis directions are shown.

[0069] like Figure 5 As shown, a power supply wiring 116 is provided in the first wiring layer M1, and a conductive layer 60 is provided between the power supply wiring 116 and the impurity region 180. In other words, the power supply wiring 116 is provided on the side of the conductive layer 60 opposite to the impurity region 180. Furthermore, as described above, the impurity region 180 and the power supply wiring 116 are electrically connected via contact holes Ha2. That is, the impurity region 180 and the power supply wiring 116 are electrically connected via a plurality of contact holes Ha2 arranged at fixed intervals in the second direction. As a result, contact holes Ha2 are arranged between the conductive layers 60 of two adjacent supply circuits 40 in the second direction.

[0070] like Figure 6 As shown, the relay wiring 64 is electrically connected to the gate electrode G1 of the transistor 121 included in each supply circuit 40 via contact hole Ha7. Furthermore, a power supply wiring 16 is arranged between the relay wirings 64 of two adjacent supply circuits 40 in the second direction. Additionally, as... Figure 4 As shown, Figure 6 The three power supply wires 16 shown are the same wire.

[0071] like Figure 7 and Figure 8 As shown, the conductive layer 60 is disposed on the same layer as the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40b, and is disposed between the two gate electrodes G1 when viewed from above. However, the conductive layer 60 may also be disposed on a different layer than the gate electrode G1. In this case, a portion of the conductive layer 60 may overlap with the gate electrode G1 when viewed from above. That is, when viewed from above, it is sufficient that at least a portion of the conductive layer 60 is disposed between the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40b.

[0072] Furthermore, although the illustration is omitted, layers such as the following are provided above the first wiring layer M1: a second wiring layer for configuring various signal lines such as data lines 14 and control lines, a layer for configuring pixel electrodes 31 of light-emitting elements 3, a layer for configuring light-emitting functional layers 32 of light-emitting elements 3, and a layer for configuring counter electrodes 33 of light-emitting elements. However, the structure is not limited to the above, and wiring layers may be added or deleted as appropriate.

[0073] As described above, the electro-optic device 1 includes a conductive layer 60, which is electrically connected to the transistors 121 included in the supply circuit 40a and the supply circuit 40b, and is supplied with a potential Vel as a fixed voltage. That is, the two supply circuits 40 arranged along the first direction are electrically connected to the same conductive layer, thereby reducing the number of wires provided in the electro-optic device 1, enabling the miniaturization of the supply circuits 40 as a whole, and thus enabling the realization of a high-precision electro-optic device 1.

[0074] Furthermore, as previously described, when viewed from above, at least a portion of the conductive layer 60 is disposed between the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40b. Therefore, the interference generated between the two gate electrodes G1 disposed along the first direction can be suppressed, thereby improving the display quality of the electro-optical device 1.

[0075] Furthermore, as mentioned above, when viewed from above, the distance H1 between the conductive layer 60 and the gate electrode G1 of the transistor 121 included in the supply circuit 40a is equal to the distance H2 between the conductive layer 60 and the gate electrode G1 of the transistor 121 included in the supply circuit 40b. Therefore, the deviation of the conductive layer 60 in suppressing parasitic capacitance generated in each supply circuit 40 can be reduced.

[0076] Furthermore, as mentioned above, when viewed from above, the transistors 121 included in supply circuit 40a and supply circuit 40b are configured to be linearly symmetrical about the imaginary line P that overlaps with the conductive layer 60 and extends in the second direction. Therefore, an efficient layout can be achieved.

[0077] Furthermore, as previously described, the conductive layer 60 is disposed on the same layer as the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40b. Therefore, the interference generated between the two gate electrodes G1 disposed along the first direction can be suppressed, thereby improving the display quality of the electro-optical device 1.

[0078] Furthermore, as previously described, the electro-optic device 1 includes an impurity region 180 supplied with the same potential as the conductive layer 60, which overlaps with the conductive layer 60 when viewed from above. Therefore, the conductive layer 60 and the impurity region 180 suppress the effects of interference generated between the two gate electrodes G1 disposed along the first direction, thereby improving the display quality of the electro-optic device 1.

[0079] Furthermore, as previously described, the electro-optical device 1 includes a power supply wiring 116, which is supplied with the same potential as the conductive layer 60 and is disposed on the side of the conductive layer 60 opposite to the impurity region 180. When viewed from above, the power supply wiring 116 overlaps with the conductive layer 60. Therefore, the conductive layer 60, the impurity region 180, and the power supply wiring 116 suppress the effects of interference generated between the two gate electrodes G1 disposed along the first direction, thereby improving the display quality of the electro-optical device 1.

[0080] Furthermore, as previously described, the power supply wiring 116 is electrically connected to the conductive layer 60 via contact hole Ha1 and to the impurity region 180 via contact hole Ha2. Thus, contact holes Ha1 and Ha2 suppress the interference generated between the two gate electrodes G1 disposed along the first direction, thereby improving the display quality of the electro-optical device 1.

[0081] Furthermore, as previously described, the impurity region 180 includes one of the source and drain regions of the transistor 121 included in the supply circuit 40a, and one of the source and drain regions of the transistor 121 included in the supply circuit 40b. Therefore, no additional region is required, thus enabling miniaturization of the entire supply circuit 40 and realizing a highly precise electro-optical device 1.

[0082] Furthermore, in the above embodiment, if the transistor 121 included in the supply circuit 40a is designated as the first driving transistor, then the light-emitting element 3 corresponding to the transistor 121 is equivalent to the first light-emitting element, and the gate electrode G1 of the transistor 121 is equivalent to the first gate electrode. Alternatively, in this case, the transistor 121 included in the supply circuit 40b, which is disposed opposite to the supply circuit 40a in the first direction, is equivalent to the second driving transistor, the light-emitting element 3 corresponding to the transistor 121 is equivalent to the second light-emitting element, and the gate electrode G1 of the transistor 121 is equivalent to the second gate electrode. Additionally, the contact hole Ha1 is equivalent to the first contact hole, and the contact hole Ha2 is equivalent to the second contact hole.

[0083] 1B. Implementation Method 2

[0084] Embodiment 2 will be described. Furthermore, in the following examples, for components that have the same function as those in Embodiment 1, detailed descriptions are appropriately omitted using the reference numerals used in the description of Embodiment 1.

[0085] Figure 9 This is a top view showing the layout of the gate electrodes G1 to G4 and the impurity region 180 in the three supply circuits 40a to 40f arranged adjacently in the X-axis direction and two arranged adjacently in the Y-axis direction in the electro-optic device 1 of Embodiment 2. Furthermore, Figure 10 It is shown Figure 9 The top view of the layout of the first wiring layer M1 in the supply circuits 40a to 40f shown illustrates the layout of the first wiring layer M1 in relation to the gate electrodes G1 to G4 and the impurity region 180. Figure 11 It is along Figure 10 The cross-sectional view obtained by cutting along line AA. In Embodiment 1, the conductive layer 60 is divided according to each column of the supply circuit 40, but in this embodiment, a conductive layer 61 is provided whose width along the second direction corresponds to the three supply circuits 40a, 40c, and 40e when viewed from above.

[0086] like Figures 9 to 11 As shown, in top view, conductive layer 61 is a conductive layer supplied with potential Vel, and is electrically connected to transistor 121 included in supply circuit 40a, transistor 121 included in supply circuit 40b, transistor 121 included in supply circuit 40c, transistor 121 included in supply circuit 40d, transistor 121 included in supply circuit 40e, and transistor 121 included in supply circuit 40f.

[0087] Specifically, the width of the conductive layer 61 along the second direction corresponds to the width of the three supply circuits 40a, 40c, and 40e arranged side-by-side along the second direction. That is, in this embodiment, the conductive layer 61 is divided into every three columns of columns in which the supply circuits 40 are provided.

[0088] In this embodiment, compared with the conductive layer 60 of Embodiment 1, the conductive layer 61 has a wider width along the second direction, thus reducing the number of contact holes Ha2 used to electrically connect the impurity region 180 to the power wiring 116.

[0089] According to this embodiment, since the conductive layer 61 has a wider width along the second direction, it is possible to suppress the interference generated between the two gate electrodes G1 disposed along the first direction when viewed from above, and the interference generated along the third direction when viewed from above. Figure 1 (as shown in the A-axis direction) and the fourth direction ( Figure 1 The conductive layer 61 can suppress the interference generated between the two gate electrodes G1 (in the B-axis direction shown). For example, the conductive layer 61 can suppress the interference generated between the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40d. Additionally, the conductive layer 61 can suppress the interference generated between the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40f.

[0090] 1C. Implementation Method 3

[0091] Embodiment 3 will be described. Furthermore, in the following examples, for components that have the same function as those in Embodiment 1, detailed descriptions are appropriately omitted using the reference numerals used in the description of Embodiment 1.

[0092] Figure 12 This is a top view showing the layout of the plurality of supply circuits 40 arranged in the X-axis direction and the gate electrodes G1 to G4 and the impurity region 180 in two adjacent supply circuits 40 arranged in the Y-axis direction within the display unit 13 of the electro-optic device 1 of Embodiment 3. Furthermore, Figure 13 It is shown Figure 12 The top view of the layout of the first wiring layer M1 in the supply circuit 40 shown illustrates the layout of the first wiring layer M1 in relation to the gate electrodes G1 to G4 and the impurity region 180. Additionally, Figure 14 It is along Figure 13 The cross-sectional view obtained by cutting along line AA. In Embodiment 1, the conductive layer 60 is divided according to each column where the supply circuit 40 is provided, but in this embodiment, a conductive layer 62 is provided whose width along the second direction when viewed from above corresponds to the width of the display section 13.

[0093] like Figures 12-14 As shown, the conductive layer 62 is a conductive layer supplied with a potential Vel. When viewed from above, it is provided throughout the second direction of the display section 13 and is provided between the gate electrodes G1 of the transistors 121 included in each of the two adjacent supply circuits 40 in the first direction.

[0094] Since the conductive layer 62 is provided throughout the second direction of the display unit 13, the impurity region 180 and the power wiring 116 are not electrically connected within the display unit 13. The impurity region 180 and the power wiring 116 are electrically connected on the outside of the display unit 13 via contact holes Ha10, etc.

[0095] According to this embodiment, since the conductive layer 62 has a wider width along the second direction, it is possible to suppress the interference generated between the two gate electrodes G1 disposed along the first direction when viewed from above, as well as the interference generated along the third direction when viewed from above. Figure 1 (as shown in the A-axis direction) and the fourth direction ( Figure 1 The interference generated between the two gate electrodes G1 (shown in the B-axis direction) is also suppressed. Furthermore, the conductive layer 62 can suppress the interference generated on the gate electrodes G1 of the transistors 121 included in the plurality of supply circuits 40 which are disposed opposite to each other on the conductive layer 62.

[0096] In addition, “electro-optical devices” are not limited to organic EL devices; they can also be inorganic EL devices or μLED devices that use inorganic materials.

[0097] 2. Electronic equipment

[0098] The electro-optical device 1 described above can be applied to various electronic devices.

[0099] 2-1. Head-mounted display

[0100] Figure 15 This is a top view schematically showing a portion of a virtual image display device 700, which is an example of an electronic device. Figure 15 The virtual image display device 700 shown is a head-mounted display worn on the head of an observer to display images. The virtual image display device 700 includes the aforementioned electro-optic device 1, collimator 71, light guide 72, first reflective volume hologram 73, second reflective volume hologram 74, and control unit 79. Furthermore, light emitted from the photoelectric device 1 is emitted as image light LL.

[0101] The control unit 79 includes, for example, a processor and a memory, and controls the operation of the electro-optic device 1. A collimator 71 is disposed between the electro-optic device 1 and the light guide 72. The collimator 71 makes the light emitted from the electro-optic device 1 parallel. The collimator 71 is constructed from a collimating lens or the like. The light converted into parallel light by the collimator 71 is incident on the light guide 72.

[0102] The light guide 72 is flat and extends in a direction intersecting the direction of light incident via the collimator 71. The light guide 72 reflects and guides light internally. A light inlet and a light outlet are provided on the surface 721 of the light guide 72 opposite to the collimator 71. A first reflective volume hologram 73 and a second reflective volume hologram 74, serving as diffractive optical elements, are disposed on the surface 722 of the light guide 72 opposite to the surface 721. The second reflective volume hologram 74 is positioned closer to the light outlet than the first reflective volume hologram 73. The first reflective volume hologram 73 and the second reflective volume hologram 74 have interference fringes corresponding to a predetermined wavelength band, causing diffraction and reflection of light within that band.

[0103] In the virtual image display device 700 of this structure, the image light LL that enters the light guide 72 from the light inlet is repeatedly reflected and advanced, and is guided from the light outlet to the observer's pupil EY, so that the observer can observe the image composed of the virtual image formed by the image light LL.

[0104] The virtual image display device 700 includes the aforementioned electro-optical device 1. The aforementioned electro-optical device 1 is small and highly precise. Therefore, by including the electro-optical device 1, a small, lightweight virtual image display device 700 with excellent display quality can be provided.

[0105] 2-2. Personal Computer

[0106] Figure 16 A perspective view of a personal computer 400, which is an example of an electronic device of the present invention. Figure 16 The personal computer 400 shown includes an electro-optical device 1, a main body 403 equipped with a power switch 401 and a keyboard 402, and a control unit 409. The control unit 409 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 1. The personal computer 400 includes the aforementioned electro-optical device 1. The aforementioned electro-optical device 1 is small and highly precise. Therefore, by including the electro-optical device 1, a small, lightweight personal computer 400 with excellent display quality can be provided.

[0107] In addition, as an "electronic device" equipped with electro-optical device 1, besides Figure 15 The illustrated virtual image display device 700 and Figure 16Besides the personal computer 400 exemplified, other devices that are positioned close to the eye include digital oscilloscopes, digital binoculars, digital still cameras, and video cameras. Furthermore, the "electronic device" equipped with the electro-optical device 1 is used in mobile phones, smartphones, PDAs (Personal Digital Assistants), car navigation systems, and in-vehicle displays. Additionally, the "electronic device" equipped with the electro-optical device 1 is used for illumination.

[0108] The present invention has been described above based on the illustrated embodiments, but the present invention is not limited thereto. Furthermore, the structure of each part of the present invention can be replaced with any structure that performs the same function as the embodiments described above, and arbitrary structures can also be added. Additionally, the present invention can combine arbitrary structures of the various embodiments described above with each other.

Claims

1. An electro-optical device comprising: A first light-emitting element and a second light-emitting element arranged along a first direction; A first power supply wiring along the first direction is supplied with a fixed potential; The first data line and the second data line along the second direction intersecting the first direction; A first driving transistor electrically connects the first light-emitting element to the first power supply wiring. The second driving transistor electrically connects the second light-emitting element to the first power supply wiring. A first conductive layer, supplied with a fixed potential, is disposed, when viewed from above, overlapping the first gate electrode of the first driving transistor along the first power supply wiring. The second conductive layer, which is supplied with a fixed potential, is disposed overlapping the second gate electrode of the second driving transistor along the first power supply wiring when viewed from above. A first transistor electrically connects the first data line to the first gate electrode; The second transistor electrically connects the second data line to the second gate electrode; A first relay wiring electrically connects the first gate electrode to the first transistor; as well as The second relay wiring electrically connects the second gate electrode to the second transistor; The first conductive layer and the second conductive layer are disposed on the same layer as the first power supply wiring. When viewed from above, the first conductive layer has: a first portion disposed along the first power supply wiring; The second part extends from the first part along a second direction intersecting the first direction. When viewed from above, the second conductive layer has a third portion disposed along the first power supply wiring; and the fourth part, which extends from the third part along the second direction, Viewed from above, the second relay cabling is positioned between the second section and the fourth section. When viewed from above, the second portion is positioned between the first trunk cabling and the second trunk cabling.

2. The electro-optical device according to claim 1, characterized in that, The electro-optical device has an impurity region disposed along the second direction, and the impurity region is supplied with the same potential as the first power supply wiring. When viewed from above, the impurity region overlaps with the first power supply wiring.

3. The electro-optical device according to claim 2, wherein, The impurity region includes one of the source and drain regions of the first driving transistor, and one of the source and drain regions of the second driving transistor.

4. The electro-optical device according to any one of claims 1-3, wherein, The electro-optical device has a second power supply wiring that is supplied with the same potential as the first power supply wiring. When viewed from above, the second power supply wiring overlaps with the first power supply wiring.

5. The electro-optical device according to claim 4, wherein, The electro-optical device has an insulating layer disposed between the first power wiring and the second power wiring, and the insulating layer has contact holes for electrically connecting the first power wiring and the second power wiring.

6. The electro-optical device according to claim 4, wherein, The second power supply wiring is disposed on the same layer as the first gate electrode and the second gate electrode.

7. An electronic device having the electro-optical device according to any one of claims 1 to 6.

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