A flash memory testing method and system using a solid state disk master control chip

Abstract

The application relates to the technical field of storage device testing, and discloses a flash memory test method and system using a solid state disk master control chip, which comprises the following steps: extracting a feature vector from collected voltage fluctuation data and time sequence response signals to obtain an initial hardware state description; analyzing the mutual influence of voltage parameters and time sequence settings, generating a dynamic voltage correction sequence, injecting the master control module, and obtaining a real-time performance index change trend by monitoring read-write stability; extracting a time sequence setting deviation value to obtain an optimized time sequence configuration scheme; performing multi-dimensional read-write stress testing by applying the optimized time sequence configuration, triggering a hardware feedback cycle to determine a potential fault point position; collecting environmental variable data, and obtaining a comprehensive test case set by using an integrated parameter fusion algorithm; selecting a subset to inject into a test environment, monitoring overall performance limit response, and iteratively adjusting a feedback mechanism to obtain a reliability evaluation report. The application realizes adaptive dynamic optimization and accurate fault positioning of flash memory testing.

Description

Technical Field

[0001] This application relates to the field of storage device testing technology, and in particular to a flash memory testing method and system utilizing a solid-state drive controller chip. Background Technology

[0002] In existing solid-state drive (SSD) testing technologies, traditional flash memory testing methods typically use preset, fixed parameters to verify read and write operations, such as setting constant voltage thresholds and timing configurations, and evaluating the drive's performance and reliability by running standard test cases. These methods rely on offline-defined test specifications and do not dynamically adjust to the actual operating conditions of the drive during testing, thus failing to reflect the complex electrical behavior of SSDs in real-world working environments. Meanwhile, as flash memory storage density continues to increase and manufacturing processes become increasingly refined, physical effects such as voltage fluctuations and timing drift between the drive's controller chip and the flash memory medium have a more significant impact on read and write stability. Traditional testing methods lack the ability to acquire and utilize these underlying dynamic signals in real time, resulting in a severe disconnect between test parameters and the actual physical boundaries of the hardware.

[0003] Furthermore, existing technologies rarely consider the coupling relationship between voltage parameters and timing settings. In actual operation, a sudden drop in voltage can directly cause fluctuations in command response latency, while insufficient timing margin can conversely exacerbate the difficulty of voltage regulation, creating a balancing effect. However, current testing methods often treat voltage adjustment and timing optimization as independent processes, failing to form a collaborative feedback mechanism. This makes it difficult to trace performance bottlenecks, and potential fault points (such as read / write failures of specific flash memory blocks under extreme voltages) are masked within the overall performance degradation metrics. In addition, due to the lack of real-time awareness of the underlying hardware status of the hard drive, test case generation is mostly based on experience or general fault models, failing to perform targeted fusion of environmental variables (such as temperature and ripple) at specific fault locations. This results in blind spots in test coverage and a lack of quantitative basis for reliability assessment.

[0004] Existing flash memory testing technologies generally suffer from drawbacks such as static parameter fixation, fragmented voltage and timing optimization, lack of hardware status awareness, and unquantifiable test coverage, making it difficult to meet the testing requirements of high-reliability solid-state drives (SSDs) under complex operating conditions. Therefore, there is an urgent need for a flash memory testing method that can utilize the hard drive controller chip to collect voltage fluctuations and timing response signals in real time, and then dynamically generate test parameters through feedback control and adaptive optimization to achieve closed-loop iterative testing and precise fault location. Summary of the Invention

[0005] To address the aforementioned technical issues, this application provides a flash memory testing method and system utilizing a solid-state drive (SSD) controller chip, which enables dynamic adaptive testing of SSD flash memory, accurate fault location, and quantitative evaluation of test coverage.

[0006] In a first aspect, this application provides a flash memory testing method using a solid-state drive controller chip, the method comprising: Step S1: Collect voltage fluctuation data and timing response signals during hard disk operation, and extract feature vectors to obtain an initial hardware state description; Step S2: Based on the initial hardware state description, a feedback control algorithm is used to analyze the mutual influence between voltage parameters and timing settings, and to determine the adjustment amplitude threshold. If the voltage fluctuation exceeds the preset amplitude threshold, a dynamic voltage correction sequence is generated and injected into the hard disk controller module. The real-time performance index change trend is obtained by monitoring the stability of read and write operations. Step S3: Extract timing setting deviation values ​​from the real-time performance index change trend, process the timing setting deviation values ​​using an adaptive timing optimization algorithm, and obtain an optimized timing configuration scheme; Step S4: Apply the optimized timing configuration scheme to perform multi-dimensional read and write stress tests on the hard disk media layer. If the performance bottleneck index exceeds the preset index threshold, trigger the hardware feedback loop to determine the location of potential fault points. Step S5: Collect environmental variable data based on the location of the potential fault point, and use an integrated parameter fusion algorithm to merge the corrected values ​​of voltage parameters and timing settings to obtain a comprehensive test case set; Step S6: Select a subset of test cases from the comprehensive test case set that meets diverse needs and inject it into the hard disk test environment. Monitor the overall performance limit response. If the response coverage is lower than the preset coverage threshold, iteratively adjust the feedback mechanism to obtain the final reliability assessment report.

[0007] Secondly, this application provides a flash memory testing system utilizing a solid-state drive controller chip, the system comprising: The feature extraction module is used to collect voltage fluctuation data and timing response signals during hard disk operation, and extract feature vectors to obtain an initial hardware state description; The performance monitoring module is used to analyze the interaction between voltage parameters and timing settings based on the initial hardware state description and a feedback control algorithm to determine the adjustment range threshold. If the voltage fluctuation exceeds the preset range threshold, a dynamic voltage correction sequence is generated and injected into the hard disk controller module. The real-time performance indicator change trend is obtained by monitoring the stability of read and write operations. The timing configuration module is used to extract timing setting deviation values ​​from the changing trends of the real-time performance indicators, process the timing setting deviation values ​​using an adaptive timing optimization algorithm, and obtain an optimized timing configuration scheme. The fault location module is used to perform multi-dimensional read and write stress tests on the hard disk media layer using the optimized timing configuration scheme. If the performance bottleneck index exceeds the preset index threshold, a hardware feedback loop is triggered to determine the location of potential fault points. The test case generation module is used to collect environmental variable data based on the location of the potential fault point, and use an integrated parameter fusion algorithm to merge the correction values ​​of voltage parameters and timing settings to obtain a comprehensive test case set; The performance evaluation module is used to select a subset of test cases from the comprehensive test case set that meet diverse needs and inject them into the hard disk test environment to monitor the overall performance limit response. If the response coverage is lower than the preset coverage threshold, the feedback mechanism is iteratively adjusted to obtain the final reliability evaluation report.

[0008] Compared with the prior art, the beneficial effects of the present invention are at least as follows: 1. This application collects voltage fluctuation data and timing response signals during hard drive operation in real time, and uses feedback control algorithm and adaptive timing optimization algorithm to dynamically adjust voltage parameters and timing settings in a coordinated manner. This significantly improves the matching degree between test parameters and actual hardware state, effectively suppresses read and write operation instability caused by instantaneous voltage drops or timing drift, thereby enhancing the authenticity and reliability of flash memory testing at the source.

[0009] 2. Furthermore, this application, through multi-dimensional read / write stress testing and deep alignment with hardware feedback logs, can penetrate from performance bottleneck indicators to specific physical fault locations, including flash memory chip numbers, block addresses, and page addresses. At the same time, it introduces response coverage as a quantitative indicator and drives the continuous improvement of test case sets through a closed-loop iterative feedback mechanism, eliminating the test blind spots existing in traditional methods and achieving a dual breakthrough in fault location accuracy and test coverage sufficiency.

[0010] 3. Furthermore, this application integrates a parameter fusion algorithm to perform weighted linear fusion of fault location, environmental variables, voltage correction values, and timing correction values, generating a comprehensive test case set covering multi-factor interactions. Combined with simulation mapping, a risk list is extracted, ultimately generating a reliability assessment report containing test coverage descriptions, performance boundaries, and optimization directions. This provides objective and quantifiable technical evidence for the reliability verification of solid-state drives under complex operating conditions, comprehensively improving the automation level of flash memory testing and the accuracy of evaluation results. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart illustrating the steps of a flash memory testing method using a solid-state drive controller chip, as described in an embodiment of this application. Figure 2 This is a schematic diagram illustrating the classification of feature vectors composed of both wave characteristics and response characteristics in an embodiment of this application; Figure 3 This is a schematic diagram illustrating the secondary extraction of signal segments with drastic fluctuations or sudden changes in response delay from the feature vector in an embodiment of this application; Figure 4 This is a structural diagram of a flash memory testing system utilizing a solid-state drive controller chip, as described in an embodiment of this application. Detailed Implementation

[0013] This application provides a flash memory testing method and system utilizing a solid-state drive controller chip. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" or "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0014] Example 1: For ease of understanding, the specific process of the embodiments of this application is described below, such as... Figure 1 The flash memory testing method using a solid-state drive controller chip shown in this embodiment of the application includes: Step S1: Collect voltage fluctuation data and timing response signals during hard disk operation, and extract feature vectors to obtain an initial hardware state description.

[0015] Step S1 further includes: acquiring voltage fluctuation data and timing response signals by collecting data during hard disk operation, constructing a basic dataset, and obtaining preliminary signal records; based on the preliminary signal records, using signal processing methods to denoise the voltage fluctuation data, extracting stable fluctuation patterns, and determining the fluctuation feature set; for the fluctuation feature set, combining the timing response signals, using the support vector machine algorithm to classify the feature vectors and determine the category distribution of hardware states; if the category distribution of hardware states exceeds a preset threshold range, then performing secondary extraction on the feature vectors to obtain more refined signal segments and obtain a refined state description; using the refined state description, analyzing the correlation between voltage fluctuations and timing responses, constructing a detailed model of the initial hardware state, and using it as the initial hardware state description.

[0016] Specifically, to address the technical problem in existing flash memory testing methods that lack the ability to perceive the underlying hardware status of the hard drive in real time, resulting in test parameters being out of sync with the actual physical characteristics and the inability to accurately pinpoint performance bottlenecks, this application constructs an initial hardware status description that can reflect the current operating status of the hard drive.

[0017] In practice, the above steps involve using voltage sensors and timing logic analyzers deployed inside or around the hard drive controller chip to simultaneously collect raw data on voltage fluctuations under typical read / write loads and corresponding command response timing signals. The collected voltage fluctuation data is a sequence of analog voltage values ​​changing over time, and the timing response signal is a sequence of delay times experienced by each read / write command from issuance to completion. The two sets of data are aligned by timestamps to form a basic dataset containing both voltage and delay dimensions, i.e., a preliminary signal record.

[0018] Because the original voltage signal contains noise such as power supply ripple and electromagnetic interference, this application employs signal processing methods such as wavelet denoising or moving average filtering to extract stable fluctuation patterns caused by load abrupt changes from the voltage fluctuation data, such as voltage drop amplitude and recovery time, forming a fluctuation feature set. Simultaneously, the delay data in the time-series response signal is statistically analyzed by percentile to form time-series response features; such as... Figure 2 and Figure 3As shown, the Support Vector Machine (SVM) algorithm is used to classify the feature vector composed of fluctuation features and response features. The classification categories correspond to different hardware states of the hard drive, such as "stable voltage", "undershoot voltage", "normal timing", and "out-of-trace timing". The SVM separates the feature vectors of different states by finding the optimal hyperplane and directly outputs the category label of the current hardware state. If the category label indicates an abnormal state, such as "undershoot voltage" or "out-of-trace timing", it means that the current state deviates from the healthy baseline. Then, the signal segments with violent fluctuations or sudden changes in response delay in the feature vector are extracted a second time. For example, the sub-segment between the voltage drop start point and the recovery point is extracted to obtain more refined local features and form a refined state description.

[0019] Then, by calculating the cross-correlation function between the refined voltage fluctuation waveform and the timing response waveform, the correlation between the two on the time axis is analyzed. Specifically, the voltage sequence is used as a reference signal, and its correlation coefficient with the delay sequence is calculated using a sliding method. When the lag time corresponding to the peak of the correlation coefficient is positive, it indicates that the voltage change occurs first, followed by the timing response change. This constructs an initial detailed hardware state model describing the degree of influence of voltage fluctuations on the timing response. The input to the initial detailed hardware state model consists of two time-aligned sequence data: one is the voltage fluctuation sequence, and the other is the corresponding read / write command delay sequence. The construction process uses the voltage sequence as a reference signal and calculates its correlation coefficient with the delay sequence using a sliding method. The lag time corresponding to the peak correlation coefficient is determined. If the lag time is positive, it is determined that the voltage change comes first and the timing response comes later, thus establishing a quantitative relationship between voltage fluctuation and timing response. Based on this, by fitting the correlation coefficients and lag times of multiple fluctuation segments, a parameterized expression or lookup table describing the mapping relationship between voltage amplitude and delay offset is formed, which is the initial detailed hardware state model. The output of the model includes the parameterized expression or lookup table itself, as well as the key indicators extracted from it, which serve as a quantitative basis for subsequent steps to coordinate voltage and timing adjustments. This model is essentially a set of parameterized expressions or lookup tables characterizing the voltage-timing coupling relationship, serving as the basis for subsequent parameter optimization.

[0020] Furthermore, to accelerate subsequent optimization convergence, this application also extracts key indicators from the detailed model, such as voltage fluctuation amplitude and root mean square value of timing deviation. After dimensionality reduction through principal component analysis, these indicators are mapped to the optimization parameter space to obtain a candidate set of optimization parameters. Only when the parameters in the candidate set meet the preset matching conditions, such as the Euclidean distance from the historical best parameter combination being less than a set threshold, is the candidate set used as the initial input for subsequent parameter optimization processing. This completes all operations in step S1. The final parameter adjustment scheme is generated by step S2 based on the initial input through a feedback control algorithm.

[0021] In this way, this application provides an accurate, reliable, and directly usable hardware state awareness starting point for the entire testing process.

[0022] Step S2: Based on the initial hardware state description, a feedback control algorithm is used to analyze the mutual influence between voltage parameters and timing settings, determine the adjustment amplitude threshold, and if the voltage fluctuation exceeds the preset amplitude threshold, a dynamic voltage correction sequence is generated and injected into the hard disk controller module. The real-time performance indicator change trend is obtained by monitoring the stability of read and write operations.

[0023] The step S2, generating the dynamic voltage correction sequence, includes: using an initial hardware state description and a feedback control algorithm to decompose the interaction between voltage parameters and timing settings to obtain the correlation pattern between them; based on the correlation pattern, calculating the reference boundary of the adjustment amplitude for the voltage parameter variation range to determine the initial threshold range; if the initial threshold range deviates from the preset benchmark threshold range, segmenting and extracting the voltage fluctuation data segments to obtain the local features of the fluctuation signal; using the local features and the response period of the timing settings, marking the abnormal points of the voltage fluctuation and determining the distribution pattern of the abnormal points; generating the initial framework of the dynamic correction sequence based on the distribution pattern of the abnormal points and determining the priority order of each correction unit in the sequence; adjusting the execution logic of the dynamic correction sequence according to the priority order to obtain the final voltage correction scheme.

[0024] Specifically, in order to solve the technical problem in existing flash memory testing methods where voltage parameters and timing settings are coupled and mutually restrictive, causing static preset parameters to be unable to adapt to real-time hardware state changes, thus leading to a decrease in read and write operation stability, this application introduces a feedback control mechanism to dynamically generate a voltage correction sequence based on the initial hardware state description output in step S1 above.

[0025] In specific implementation, the voltage fluctuation feature vector and timing response feature vector in the initial hardware state description are first used as inputs to the feedback control algorithm. This feedback control algorithm adopts a closed-loop error-driven design: the currently collected voltage fluctuation data is compared with the preset expected voltage stability range to calculate the deviation signal; at the same time, the timing response delay is compared with the expected delay threshold to obtain the timing deviation signal. The algorithm performs cross-correlation analysis on the historical sequence data of voltage parameters and timing settings. Specifically, after aligning the voltage value sequence with the corresponding command response delay sequence by time, the ratio of the cross-variance between the voltage sequence and the delay sequence to the autovariance of the voltage sequence is calculated within a sliding window as a correlation pattern reflecting the degree of influence of voltage changes on timing delay. This correlation pattern is represented in the form of a set of transfer functions or difference equations, which clarifies the quantitative relationship between the voltage fluctuation amplitude and the delay change.

[0026] Based on this correlation pattern, the algorithm further calculates the maximum allowable adjustment step size without causing timing violations for the actual variation range of voltage parameters, such as the amplitude range of downward fluctuation from the nominal voltage. This determines the reference boundary of the adjustment amplitude and forms a preliminary threshold range accordingly. The preliminary threshold range is compared with the pre-stored benchmark threshold range, i.e., the safety boundary specified in the hardware specifications. If there is a deviation between the two, it indicates that the current voltage fluctuation has approached or exceeded the safety limit, thus triggering the generation process of the voltage correction sequence. To this end, the time segments with fluctuation amplitudes exceeding the benchmark range are first extracted from the continuous voltage fluctuation data, such as the subsequence between the voltage drop start point and the recovery point. Local extremum detection or wavelet transform modulus maxima method is used to obtain the local features of the fluctuation signal, including drop depth, recovery time, and number of oscillations. Combined with the response period defined in the timing settings, i.e., the minimum response time interval of the main control chip to the voltage adjustment command, abnormal points in the voltage fluctuation data are marked. For example, drop points that cannot be stably recovered within the response period are marked as high-risk abnormal points.

[0027] Next, the distribution patterns of these anomalies on the time axis are statistically analyzed, such as whether they exhibit periodicity or random bursts. Based on the distribution patterns, an initial framework for the dynamic correction sequence is generated, which specifies the timing of action and the expected voltage adjustment for each correction unit. According to the severity of the anomalies, such as the greater the drop depth and the longer the recovery time, the higher the priority, and each correction unit in the sequence is assigned a priority order.

[0028] Finally, the execution logic of the dynamic correction sequence is adjusted in descending order of priority. That is, the correction unit for the most severe anomaly is executed first, and so on, to obtain the final voltage correction scheme. This correction scheme exists in the form of a discrete voltage adjustment instruction sequence. Each instruction contains a timestamp and a target voltage value, which are then injected into the main control module for execution in subsequent steps.

[0029] Through the aforementioned bias-driven feedback decomposition and priority scheduling, this application achieves quantitative analysis and adaptive correction of voltage-timing coupling relationship, laying a dynamic adjustment foundation for improving read and write operation stability.

[0030] The step S2, obtaining the real-time performance indicator change trend, includes: injecting a dynamic voltage correction sequence into the hard disk controller module to complete the initial voltage adjustment process and obtain the module's initial response state; based on the initial response state, acquiring the execution data of read and write operations, monitoring the stability of the operation process, and determining the operation's stability parameters; analyzing the fluctuation of real-time performance through the stability parameters, using a support vector machine algorithm to classify the indicator changes, determining whether the fluctuation exceeds a preset performance fluctuation threshold, and if so, performing layered extraction on the data segments of indicator changes to obtain the local pattern of the change trajectory; based on the local pattern and combined with the time-series data of performance feedback, adjusting the priority order of operation responses and determining the adjusted response strategy; and updating the voltage adjustment logic of the hard disk controller module through the response strategy to obtain the updated voltage configuration and generate the real-time performance indicator change trend.

[0031] Specifically, in order to address the technical problem that after a solid-state drive (SSD) injects a dynamic voltage correction sequence, the lack of real-time quantitative evaluation and adaptive response adjustment of read and write operation stability leads to the inability of voltage configuration to be optimized in tandem with performance fluctuations, thereby affecting the accuracy of test results, this application further specifies a specific method for obtaining the real-time performance indicator change trend in step S2.

[0032] In practice, the dynamic voltage correction sequence generated in the aforementioned steps is first injected into the hard disk controller module in timed order through the debug interface or firmware command channel of the main controller chip. During the injection process, each correction unit contains the target voltage value and duration. After receiving the instruction, the main controller module adjusts the output of the internal voltage regulator to complete one voltage adjustment operation. After each voltage adjustment, the voltage establishment status fed back by the main controller module is automatically recorded, such as whether the voltage is stable within the allowable error range, thereby obtaining the initial response status of the module. This response status reflects the success rate and response delay of the main controller module in executing the voltage adjustment command, which is the benchmark for subsequent stability monitoring.

[0033] Based on this initial response state, real-time acquisition of read and write operation execution data is initiated. Specifically, within a continuous time window after the voltage adjustment takes effect, a set of preset read and write test commands, such as sequential read and random write, are sent to the hard drive, and the completion time, data verification result, and number of retries for each command are recorded. This execution data constitutes the raw input for reading and write operation stability monitoring. From this data, stationarity parameters are extracted, including the moving average of read and write latency, latency variance, error rate, and retry rate. Among them, the stationarity parameters are used to quantify the jitter of read and write operations after voltage adjustment. For example, the smaller the latency variance and the lower the error rate, the more stable the operation.

[0034] Then, the feature vectors formed by these stationarity parameters are classified using the Support Vector Machine (SVM) algorithm. SVM is a supervised learning model, and its training process is conducted offline: a large amount of historical test data is pre-collected, in which each set of stationarity parameter feature vectors is manually labeled as either "normal fluctuation" or "fluctuation exceeding limits," based on whether subsequent performance triggers hardware errors or exceeds design specifications. During training, the SVM divides the feature space into two regions by finding the hyperplane that maximizes the classification margin, thus obtaining the classification model. In actual testing, the stationarity parameter feature vectors extracted in real time are input into the trained SVM model, and the model outputs the corresponding category label. If the output is "fluctuation exceeding limits," it indicates that the current voltage correction sequence has caused significant performance instability, requiring further analysis.

[0035] To address situations where fluctuations exceed limits, the most drastic time segments of fluctuation are extracted from the raw execution data, such as intervals of continuously increasing latency or sudden errors. A hierarchical extraction strategy is employed: first, the start and end points of the fluctuation are identified; then, within this segment, local change patterns are decomposed layer by layer in chronological order, such as a stepped increase pattern in latency or a cluster pattern of sudden errors. These local patterns are represented as feature sub-vectors, describing the evolution trajectory of performance fluctuations at a micro-timescale. Next, the priority of the current operation response is dynamically adjusted by combining the time-series data of performance feedback—that is, the latency change sequence recorded after each round of voltage adjustment and the time of error occurrence. The adjustment rules are as follows: for voltage correction units that cause severe fluctuations, such as a sudden increase in error rate, their subsequent execution priority is reduced; for units that can improve stability, such as a decrease in latency variance, their priority is increased; thus forming the adjusted response strategy; finally, the voltage adjustment logic of the hard disk controller module is updated according to this response strategy, such as modifying the step size of the voltage regulator, adjusting the minimum interval between two adjacent adjustments, etc., to obtain the updated voltage configuration; under the updated voltage configuration, read and write operation performance continues to be monitored, and real-time performance indicator change trends reflecting the co-evolution law of voltage and performance are generated, providing data support for subsequent timing deviation extraction.

[0036] Through the closed-loop process of injection, monitoring, classification, hierarchical extraction and priority adjustment described above, this application achieves adaptive matching between voltage correction and performance response.

[0037] Step S3: Extract timing setting deviation values ​​from the real-time performance index change trend, process the timing setting deviation values ​​using an adaptive timing optimization algorithm, and obtain the optimized timing configuration scheme.

[0038] Step S3 further includes: obtaining time-series features from the real-time performance indicator change trends to determine the preliminary time-series deviation distribution; extracting key time points from the deviation data based on the preliminary time-series deviation distribution, using an adaptive time-series optimization algorithm to iteratively optimize the time-series parameters corresponding to the key time points, and determining the optimized time-series parameters; analyzing the residual offset of the deviation data based on the performance monitoring feedback data for the optimized time-series parameters, and compensating and adjusting the time-series configuration according to the residual offset to obtain the adjusted time-series configuration; updating the current time-series configuration scheme through the adjusted time-series configuration to obtain the optimized time-series configuration scheme; matching and verifying the real-time data of performance monitoring using the optimized time-series configuration scheme, obtaining the matched performance feedback result; if the matched performance feedback result indicates the existence of a new time-series deviation, then using the new time-series deviation as input, continuing to perform iterative optimization of the time-series parameters until the matched performance feedback result meets the preset stability requirements.

[0039] Specifically, in order to address the technical problem that the timing deviations implied in the real-time performance index change trends after voltage correction cannot be automatically identified and compensated, resulting in a mismatch between timing configuration and the current hardware state, and thus limiting further improvement in read and write performance, this application introduces an adaptive timing optimization algorithm to deeply mine and iteratively calibrate the real-time performance index change trends generated in the above steps.

[0040] In practical implementation, this application first extracts time-series features from the changing trends of real-time performance indicators. These trends are a sequence of read / write latency, throughput, and error rate ordered by time. Using a sliding window method, the autocorrelation function and partial autocorrelation function of the latency sequence are calculated within each window to extract the periodic fluctuation component, trend term, and random noise term of the latency. These components are then combined into a time-series feature vector. The trend term refers to the systematic change in read / write latency over time, exhibiting monotonically increasing, decreasing, or slowly drifting behavior, reflecting the degree to which the overall timing configuration deviates from the ideal state. The random noise term refers to the irregular instantaneous fluctuations in the latency sequence caused by uncertainties such as power supply ripple and electromagnetic interference. Caused by various factors, these two factors, together with the periodic fluctuation component, constitute a timing feature vector, which is used to quantify the timing deviation distribution and drive subsequent adaptive optimization. Based on this timing feature vector, by statistically analyzing the distribution of latency values ​​at different percentiles, a preliminary timing deviation distribution is determined, namely, the magnitude of the latency value deviating from the expected baseline and its probability distribution. Among them, timing configuration refers to the combination of timing parameters used when the solid-state drive controller chip and the flash memory medium interact with commands and data, including register settings such as command latch enable time, data setup and hold time, read and write operation cycle, and response window, which are used to control the timing relationship of signals on the physical bus and directly affect the stability and reliability of read and write operations.

[0041] Based on the preliminary timing deviation distribution, key time points in the deviation data are further identified. Key time points refer to the time points where the accumulated timing deviation exceeds a set threshold, such as the starting point when the latency of multiple consecutive read / write commands remains consistently high and exceeds the normal fluctuation range. After extracting these key time points, an adaptive timing optimization algorithm is used to iteratively optimize the timing parameters corresponding to these key time points. In this embodiment, the adaptive timing optimization algorithm employs a Bayesian optimization method. This optimization process is executed offline in engineering debugging mode: each time a new set of timing parameters is tried, such as command latch enable time, data establishment and hold time window, etc., the... After the parameters are written to the configuration register of the main control chip, the improvement in read / write latency at key time points is measured in a secure test environment, and this improvement is used as feedback. Bayesian optimization predicts the performance response under different combinations of timing parameters by constructing a Gaussian process surrogate model, and uses the acquisition function, such as the expected improvement balance exploration and utilization, to find the optimal timing parameters with the fewest iterations. During the iteration process, a new set of timing parameters is tried each time, and the latency improvement measured under these parameters is used as feedback to update the Gaussian process model until the latency improvement of several consecutive iterations is less than the convergence threshold. The timing parameters obtained at this time are the optimized timing parameters.

[0042] For the optimized timing parameters, combined with performance monitoring feedback data—namely, the actual measured latency sequence and error rate after parameter adjustment—the residual offset of the deviation data is analyzed. The residual offset refers to the difference between the actual latency after adopting the optimized timing parameters and the minimum reference latency specified in the datasheet. This difference is obtained by subtracting the reference latency from the average latency of multiple read and write commands. By calculating the rate of change of the residual offset over time, it is determined whether there are still systematic lag or lead deviations. The timing configuration is then compensated and adjusted based on the residual offset. For example, if the residual offset shows a monotonically increasing trend, the data setup time is appropriately increased; if it exhibits random jitter, the jitter attenuation coefficient of the phase-locked loop is adjusted to obtain the adjusted timing configuration. Finally, the current timing configuration scheme is updated using the adjusted timing configuration to obtain the optimized timing configuration scheme.

[0043] To verify the reliability of the scheme, the optimized timing configuration scheme was used to match and verify the real-time data of performance monitoring: a new set of read and write latency data was collected under the same load, and compared with the latency distribution before optimization. The deviation ratio of the two at the high percentile latency was calculated to obtain the performance feedback result after matching. If the feedback result indicates that there are still new timing deviations, such as the high percentile latency still exceeding the design target, these new timing deviations are used as input to continue iterative optimization and compensation adjustment of timing parameters until the performance feedback result after matching meets the preset stability requirements.

[0044] Through the above closed-loop iteration, this application achieves adaptive optimization of the timing configuration scheme from coarse to fine, providing an accurate timing benchmark for subsequent multi-dimensional stress testing.

[0045] Step S4: Apply the optimized timing configuration scheme to perform multi-dimensional read and write stress tests on the hard disk media layer. If the performance bottleneck index exceeds the preset index threshold, a hardware feedback loop is triggered to determine the location of potential fault points.

[0046] Step S4 further includes: applying the optimized timing configuration scheme to perform layered read / write pressure tests on the hard disk media layer, obtaining preliminary data on performance bottlenecks under different load scenarios, and determining the distribution range of bottleneck indicators; based on the distribution range of bottleneck indicators, performing in-depth monitoring of the response latency and throughput of the hard disk media, extracting abnormal fluctuations in read / write pressure from the monitoring data, and obtaining preliminary clues to potential faults; using the preliminary clues to potential faults, combined with the log records of hardware feedback, analyzing the abnormal points in the read / write pressure test, and when the frequency of occurrence of abnormal points exceeds a preset frequency threshold, determining the specific location of the fault point, and using the specific location of the fault point as the potential fault point location.

[0047] Specifically, in order to address the technical problem that while the optimized timing configuration scheme can improve overall read and write performance, it cannot directly expose the physical defects or potential fault points of the hard disk media layer under extreme load, making it difficult to trace the source of performance bottlenecks, this application adopts a method that combines multi-dimensional read and write stress testing with hardware feedback loops to perform layer-by-layer detection and fault location of the hard disk media layer.

[0048] In practice, the optimized timing configuration scheme output from the above steps is first applied to perform tiered read / write pressure tests on the hard disk media layer. Tiered testing means constructing multiple load scenarios based on different combinations of access granularity, access mode, read / write ratio, and queue depth. Each scenario is maintained for a preset time window, and the average read / write latency, throughput, error rate, and number of retries are recorded. Preliminary data on performance bottlenecks are extracted from this data. For example, if the latency in a certain scenario is significantly higher than in other scenarios or the error rate shows a step increase, it is determined that a performance bottleneck exists in that scenario. The load parameters of all bottleneck scenarios are summarized to determine the distribution range of bottleneck indicators. For example, the bottleneck mainly occurs when there is random writing and a high queue depth.

[0049] Based on the distribution range of bottleneck indicators, in-depth monitoring is performed on the response latency and throughput of hard disk media. In-depth monitoring refers to continuously recording the precise completion time, number of bytes transferred, and status codes fed back by the media layer for each read / write operation at a microsecond sampling rate, forming a timestamped monitoring data stream. From this data stream, a sliding window anomaly detection algorithm is used to extract abnormal fluctuations in read / write pressure, such as a sudden increase in the mean latency of more than two standard deviations in multiple consecutive sampling points, or a sharp drop in throughput to less than 50% of the normal value. These abnormal fluctuations and the load scenarios in which they occur together constitute preliminary clues to potential faults, such as "periodic latency spikes during high queue depth random writes".

[0050] Using the initial clues of potential faults mentioned above, combined with the hardware feedback logs recorded by the hard drive controller chip, further analysis was conducted on anomalies during read / write stress testing. The hardware feedback logs included the number of error correction codes at the media layer, the number of read retry triggers, the number of programming failures, and erase block damage markers. The timestamps of abnormal fluctuations were aligned with the error events in the logs. If multiple error events occurred within the same physical address or logical block address range within a time window, that address was marked as an anomaly. The frequency of each anomaly during the test was statistically analyzed. When the frequency exceeded a preset threshold, the point was determined as a fault point, and its specific location was identified, including the flash memory chip number, logical cell number, plane number, block address, and page address. This specific location was output as the potential fault location for subsequent steps in environmental variable collection and comprehensive test case generation.

[0051] Through the above-mentioned process of layered testing, deep monitoring, log alignment, and frequency threshold judgment, this application achieves precise location from performance bottlenecks to physical fault points, providing a clear objective for subsequent targeted testing.

[0052] Step S5: Collect environmental variable data based on the location of potential fault points, and use an integrated parameter fusion algorithm to combine the corrected values ​​of voltage parameters and timing settings to obtain a comprehensive test case set.

[0053] The comprehensive test case set obtained in step S5 includes: directional collection of environmental variables based on the location of potential fault points; extraction of key fields related to the fault from the collected data to obtain an environmental variable dataset; merging of the environmental variable dataset with recorded voltage parameter values ​​using an integrated parameter fusion algorithm to determine the fused parameter combination; obtaining correction values ​​for timing settings through the fused parameter combination; standardizing these correction values ​​to obtain adjusted timing configuration data; generating input conditions for test cases based on the adjusted timing configuration data; extracting key constraints from the input conditions to determine the framework structure of the comprehensive test cases; and filling and refining the content of the test cases based on the framework structure of the comprehensive test cases and the intermediate results of data processing to obtain a complete comprehensive test case set.

[0054] After obtaining the complete comprehensive test case set, the process also includes: using the complete comprehensive test case set to simulate and map the operating scenarios of the hardware components, extracting potential anomalies from the simulation mapping, marking the configuration of the relevant components when the distribution of anomalies exceeds the preset distribution threshold, obtaining a marked risk list, and using the risk list as supplementary information to the comprehensive test case set.

[0055] Specifically, to address the technical problem that a single fault location cannot cover abnormal hardware performance under the coupling of complex environmental factors, resulting in insufficient test case targeting and omission of potential risks, this application adopts an integrated parameter fusion algorithm to fuse potential fault location, environmental variables, voltage correction values, and timing correction values ​​at multiple levels to generate a comprehensive test case set covering the interaction of multiple factors, and further extracts a risk list through simulation mapping.

[0056] In practice, based on the potential fault location determined in the above steps, including the flash memory chip number, block address, page address, etc., the physical environment of the location is collected in a targeted manner. Targeted collection means reading real-time environmental variable data such as temperature, humidity, and power supply voltage ripple in the vicinity of the fault point through onboard temperature sensors, humidity sensors, and registers of the power management chip, and extracting key fields related to the time of the fault occurrence, such as the temperature change rate and voltage drop depth in the milliseconds before the fault occurs, to form an environmental variable dataset.

[0057] Subsequently, an integrated parameter fusion algorithm is used to merge the environmental variable dataset, the corrected values ​​of voltage parameters (i.e., the final adjustment amount in the dynamic voltage correction sequence generated in step S2), and the corrected values ​​of timing settings (i.e., the difference between the optimized timing parameters and the original parameters in step S3) with the original parameters. In this embodiment, the integrated parameter fusion algorithm adopts a weighted linear fusion strategy. The principle is as follows: parameters from different physical dimensions are regarded as independent fusion sources. First, the correlation coefficient between each parameter and the severity of the fault is calculated. The calculation method is as follows: the values ​​of each parameter, such as temperature and voltage correction step size, in multiple tests are paired with the fault severity indicators such as the error rate or number of retries at the fault point location in the corresponding test. The linear correlation between the two is calculated using the Pearson correlation coefficient formula, which serves as the weight basis for subsequent weighted fusion. Then, the values ​​of each parameter are weighted and summed to obtain the fused parameter combination. The algorithm input is the temperature, humidity, and voltage ripple feature values ​​in the environmental variable dataset, as well as the voltage correction step size and timing offset compensation amount. The output is the fused parameter combination vector, where each element represents a comprehensive excitation value in a test dimension.

[0058] By directly extracting the timing setting correction components from the fused parameter combination, these values ​​are standardized. These correction components are elements in the fused parameter combination vector directly corresponding to the timing settings, extracted directly through vector indexing. Their values ​​originate from the independent components retained by each timing correction value during weighted linear fusion in this step. The standardization process employs min-max normalization to map timing correction values ​​of different dimensions to a unified interval, eliminating the influence of dimensions and obtaining adjusted timing configuration data. Based on the adjusted timing configuration data, input conditions for test cases are generated, such as setting read / write operations. The command sending interval, data verification mode, address transition rules, etc., are used as input conditions. Key constraints, including maximum allowable delay, minimum throughput requirement, and error tolerance threshold, are extracted from these input conditions to determine the framework structure of the integrated test cases. This framework specifies the boundary conditions and evaluation criteria of the test cases. Based on this framework structure, and combined with the intermediate results of data processing, namely the weight allocation records and standardized parameter tables generated during the fusion process, the content of the test cases is filled in and refined. For example, specific voltage bias values, timing offsets, and environmental temperature and humidity setpoints are assigned to each test step, ultimately resulting in a complete set of integrated test cases.

[0059] After obtaining a complete set of integrated test cases, the operating scenarios of the hard drive hardware components are simulated and mapped using this test case set. Simulation mapping refers to mapping each parameter combination in the test cases to an executable sequence of hardware operations. For example, voltage bias is converted into register write values ​​of the power management chip, and timing offset is converted into configuration values ​​of the timing controller of the main control chip. During the mapping process, test cases are automatically executed and hardware feedback is monitored to extract potential anomalies, such as data verification errors or command timeouts under certain parameter combinations. The spatial distribution of all anomalies is statistically analyzed by chip, block, page, and parameter distribution by voltage, timing, and temperature. When the spatial distribution density or frequency of anomalies exceeds a preset distribution threshold, the configuration of the relevant hardware components is marked, generating a marked risk list. This risk list records parameter combinations that are prone to failure and their corresponding hardware locations, serving as supplementary information to the integrated test case set, allowing for the priority selection of high-risk subsets during subsequent iterative testing.

[0060] Through the complete process of targeted data collection, weighted linear fusion, standardization, framework construction, simulation mapping, and risk labeling described above, this application achieves automated transformation from fault location to multi-factor test case generation, significantly improving the test coverage depth and risk detection capability.

[0061] Step S6: Select a subset of test cases from the comprehensive test case set that meets diverse needs and inject it into the hard disk test environment. Monitor the overall performance limit response. If the response coverage is lower than the preset coverage threshold, iteratively adjust the feedback mechanism to obtain the final reliability assessment report.

[0062] The process of obtaining the final reliability assessment report in step S6 includes: selecting a subset of test cases adapted to diverse needs from the comprehensive test case set, injecting it into the hard disk test environment, constructing a performance monitoring process, obtaining response data at performance limits, and determining the preliminary response coverage, where the response coverage rate is the ratio of the number of triggered hardware state types to the preset total number of hardware state types; comparing the preliminary response coverage with a preset coverage threshold, and activating a feedback mechanism when the response coverage rate is lower than the preset coverage threshold, returning the response coverage rate as feedback information to step S2 or step S3, re-optimizing the voltage parameters and timing settings, and regenerating the comprehensive test case set based on the optimized parameters; re-injecting the adjusted test parameters into the hard disk test environment, monitoring performance under various scenarios, obtaining updated response data, until the response coverage rate meets the preset coverage threshold; analyzing the fluctuation of performance limits based on the response data that finally meets the coverage threshold, generating comprehensive reliability assessment data, and generating a reliability assessment report for the hard disk test environment based on the comprehensive data.

[0063] Specifically, to address the technical problem that although the comprehensive test case set covers known fault points and environmental factors, it cannot guarantee that it can trigger all potential hardware state responses of the hard drive, resulting in blind spots in testing and incomplete reliability assessment, this application introduces an iterative feedback mechanism based on response coverage. This mechanism quantitatively evaluates the coverage of the hardware state space by the test case set and dynamically adjusts the feedback loop until the coverage meets the requirements, ultimately generating a complete reliability assessment report.

[0064] In practice, a subset suitable for diverse needs is first selected from the comprehensive test case set generated in the above steps. The selection strategy for the subset is as follows: the test cases are sorted in descending order according to the risk level in the risk list, and high-risk test cases are selected first. At the same time, the diversity of parameter combinations is considered to ensure that representative subsets of different voltage, timing, and environmental parameter combinations are selected. The selected subset is injected into the hard disk test environment through the debugging interface of the main control chip or standardized test commands. This test environment is an independent offline workstation that runs pre-configured load scripts.

[0065] During test case execution, a performance monitoring process is constructed to collect real-time data on hard drive read / write latency, throughput, error rate, retry count, and status code changes in the hardware feedback log. After all test cases are executed, the monitoring data is aggregated, and performance limit response data is extracted, i.e., the hardware state type triggered by each test case, such as "read interference trigger," "write abort," "ECC error correction overrun," and "temperature protection frequency reduction." The number of all triggered hardware state types is counted and divided by the preset total number of hardware state types, which is predefined based on the hard drive specifications and historical failure mode analysis, to obtain the response coverage. The response coverage reflects the depth of the current test case set's exploration of the hard drive's potential hardware states; a higher value indicates more thorough testing.

[0066] The calculated response coverage is compared with a preset coverage threshold. If the response coverage is lower than the threshold, it indicates that the current test case set has failed to fully stimulate the hardware state space of the hard drive. At this time, the feedback mechanism is activated. The specific operation of the feedback mechanism is as follows: the response coverage, the list of currently uncovered hardware state types, and the potential fault location information determined in step S4 are used together as feedback information, and the feedback is selectively returned to step S2 or step S3. If returning to step S2, step S2 adjusts the error driving parameters of the feedback control algorithm based on the type of state not covered and the location of the fault point. For example, when the fault point is located in a specific flash memory block and there is a lack of "read interference" triggering, the perturbation amplitude of the corresponding address range in the voltage correction sequence is increased. If returning to step S3, step S3 modifies the search boundary of the adaptive timing optimization algorithm based on the type of state not covered. For example, when there is a lack of "write abort" near the fault point, the exploration range of timing parameters is expanded to the limit boundary of the specification, and the timing parameters of the physical region where the fault point is located are finely optimized first. Based on the adjusted parameters, steps S2 to S5 are re-executed to generate a new comprehensive test case set. Then, the adjusted test parameters, i.e., the newly generated test case set, are re-injected into the hard disk test environment, and the performance is monitored again to obtain the updated response data. The above iterative process is repeated until the response coverage meets the preset coverage threshold.

[0067] Once the response coverage meets the target, the performance limits are analyzed based on the response data that ultimately satisfy the threshold conditions. This includes identifying which extreme parameter combinations cause the hard drive to reach a performance inflection point and which hardware states consistently fail to trigger stably in multiple tests. These analysis results are then compiled to generate comprehensive reliability assessment data, such as the minimum trigger conditions for each hardware state type, performance degradation trend curves, and failure probability distributions. Finally, a reliability assessment report for the hard drive's test environment is generated based on the comprehensive data. The report includes a description of the test coverage, risk warnings for uncovered states, performance boundaries for each parameter combination, and suggested optimization directions.

[0068] Through the aforementioned coverage-driven closed-loop iteration, this application ensures the sufficiency of testing and the comprehensiveness of evaluation, providing an objective and quantitative basis for the reliability verification of solid-state drives.

[0069] Through the coordination of the above steps, this application achieves adaptive dynamic optimization and accurate fault location in flash memory testing.

[0070] Example 2: The above describes a flash memory testing method using a solid-state drive controller chip according to an embodiment of this application. The following describes a flash memory testing system using a solid-state drive controller chip according to an embodiment of this application. Figure 4As shown, a flash memory testing system utilizing a solid-state drive controller chip in an embodiment of this application includes: The feature extraction module is used to collect voltage fluctuation data and timing response signals during hard disk operation, and extract feature vectors to obtain an initial hardware state description.

[0071] The performance monitoring module is used to analyze the interaction between voltage parameters and timing settings based on the initial hardware state description and a feedback control algorithm to determine the adjustment range threshold. If the voltage fluctuation exceeds the preset range threshold, a dynamic voltage correction sequence is generated and injected into the hard drive controller module. The real-time performance indicator change trend is obtained by monitoring the stability of read and write operations.

[0072] The timing configuration module is used to extract timing setting deviation values ​​from the changing trends of real-time performance indicators, and to process the timing setting deviation values ​​using an adaptive timing optimization algorithm to obtain an optimized timing configuration scheme.

[0073] The fault location module is used to perform multi-dimensional read and write stress tests on the hard disk media layer using the optimized timing configuration scheme. If the performance bottleneck index exceeds the preset index threshold, a hardware feedback loop is triggered to determine the location of potential fault points.

[0074] The test case generation module is used to collect environmental variable data based on the location of potential fault points, and use an integrated parameter fusion algorithm to merge the corrected values ​​of voltage parameters and timing settings to obtain a comprehensive test case set.

[0075] The performance evaluation module is used to select a subset of test cases from the comprehensive test case set to meet diverse needs and inject them into the hard disk test environment to monitor the overall performance limit response. If the response coverage is lower than the preset coverage threshold, the feedback mechanism is iteratively adjusted to obtain the final reliability evaluation report.

[0076] Through the synergistic cooperation of the above components, this application further achieves adaptive dynamic optimization and accurate fault location in flash memory testing.

[0077] In summary, the flash memory testing method and system utilizing solid-state drive controller chips provided in this application effectively solves the core problems in existing technologies, such as statically fixed test parameters, neglect of voltage and timing coupling, lack of hardware state awareness, and unquantifiable test coverage. This is achieved by constructing a complete technical solution from real-time hardware status perception, voltage-timing co-optimization, multi-dimensional stress testing and fault location, to comprehensive test case generation and response coverage-driven closed-loop iterative testing. The method first establishes an initial hardware state description using voltage fluctuations and timing response signals. Then, it dynamically generates a voltage correction sequence and optimizes timing configuration using feedback control and adaptive timing optimization algorithms, significantly improving the stability of read / write operations and the realism of the test. Based on this, through layered stress testing and hardware log alignment, it achieves precise location from performance bottlenecks to specific physical fault points. An integrated parameter fusion algorithm merges environmental variables, voltage, and timing correction values ​​into a comprehensive test case set, and introduces response coverage as a quantitative indicator. A closed-loop iterative feedback mechanism drives the continuous improvement of test cases until the coverage meets the requirements. The final reliability assessment report includes test coverage, performance boundaries, and risk warnings, providing objective and quantifiable technical evidence for the reliability verification of solid-state drives under complex operating conditions.

[0078] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system and unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0079] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0080] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A flash memory testing method using a solid-state drive controller chip, characterized in that, The method includes: Step S1: Collect voltage fluctuation data and timing response signals during hard disk operation, and extract feature vectors to obtain an initial hardware state description; Step S2: Based on the initial hardware state description, a feedback control algorithm is used to analyze the mutual influence between voltage parameters and timing settings, and to determine the adjustment amplitude threshold. If the voltage fluctuation exceeds the preset amplitude threshold, a dynamic voltage correction sequence is generated and injected into the hard disk controller module. The real-time performance index change trend is obtained by monitoring the stability of read and write operations. Step S3: Extract timing setting deviation values ​​from the real-time performance index change trend, process the timing setting deviation values ​​using an adaptive timing optimization algorithm, and obtain an optimized timing configuration scheme; Step S4: Apply the optimized timing configuration scheme to perform multi-dimensional read and write stress tests on the hard disk media layer. If the performance bottleneck index exceeds the preset index threshold, trigger the hardware feedback loop to determine the location of potential fault points. Step S5: Collect environmental variable data based on the location of the potential fault point, and use an integrated parameter fusion algorithm to merge the corrected values ​​of voltage parameters and timing settings to obtain a comprehensive test case set; Step S6: Select a subset of test cases from the comprehensive test case set that meets diverse needs and inject it into the hard disk test environment. Monitor the overall performance limit response. If the response coverage is lower than the preset coverage threshold, iteratively adjust the feedback mechanism to obtain the final reliability assessment report.

2. The flash memory testing method using a solid-state drive controller chip according to claim 1, characterized in that, Step S1 further includes: Voltage fluctuation data and timing response signals are acquired by collecting data during hard drive operation to construct a basic dataset and obtain preliminary signal records. Based on these preliminary signal records, signal processing methods are used to denoise the voltage fluctuation data, extract stable fluctuation patterns, and determine a set of fluctuation features. For this set of fluctuation features, combined with the timing response signals, a support vector machine algorithm is used to classify the feature vectors and determine the distribution of hardware state categories. If the distribution of hardware state categories exceeds a preset threshold range, the feature vectors are extracted a second time to obtain more refined signal segments, resulting in a refined state description. Based on this refined state description, the correlation between voltage fluctuations and timing responses is analyzed to construct a detailed model of the initial hardware state, which serves as the initial hardware state description.

3. The flash memory testing method using a solid-state drive controller chip according to claim 1, characterized in that, The generation of the dynamic voltage correction sequence in step S2 includes: Based on the initial hardware state description, a feedback control algorithm is used to decompose the interaction between voltage parameters and timing settings to obtain the correlation pattern between them. According to the correlation pattern, a reference boundary for the adjustment amplitude is calculated for the voltage parameter variation range to determine a preliminary threshold range. If the preliminary threshold range deviates from the preset benchmark threshold range, the voltage fluctuation data segments are segmented and extracted to obtain local features of the fluctuation signal. Using these local features, combined with the response period of the timing settings, abnormal points in the voltage fluctuation are marked to determine their distribution pattern. Based on the distribution pattern of the abnormal points, an initial framework for a dynamic correction sequence is generated, and the priority order of each correction unit in the sequence is determined. The execution logic of the dynamic correction sequence is adjusted according to the priority order to obtain the final voltage correction scheme.

4. The flash memory testing method using a solid-state drive controller chip according to claim 3, characterized in that, The real-time performance indicator change trend obtained in step S2 includes: The dynamic voltage correction sequence is injected into the hard disk controller module to complete the initial voltage adjustment process and obtain the module's preliminary response state. Based on the preliminary response state, the execution data of read and write operations are acquired, and the stability of the operation process is monitored to determine the stability parameters of the operation. The fluctuation of real-time performance is analyzed through the stability parameters, and the index changes are classified using a support vector machine algorithm to determine whether the fluctuation exceeds a preset performance fluctuation threshold. If it does, the data segments of index changes are extracted hierarchically to obtain the local pattern of the change trajectory. Based on the local pattern and combined with the time-series data of performance feedback, the priority order of the operation response is adjusted to determine the adjusted response strategy. Based on the response strategy, the voltage adjustment logic of the hard disk controller module is updated to obtain the updated voltage configuration and generate a real-time performance index change trend.

5. The flash memory testing method using a solid-state drive controller chip according to claim 1, characterized in that, Step S3 further includes: The timing characteristics are obtained from the real-time performance index change trends to determine the preliminary timing deviation distribution. Based on the preliminary timing deviation distribution, key time points in the deviation data are extracted, and an adaptive timing optimization algorithm is used to iteratively optimize the timing parameters corresponding to the key time points to determine the optimized timing parameters. For the optimized timing parameters, combined with the performance monitoring feedback data, the residual offset of the deviation data is analyzed, and the timing configuration is compensated and adjusted according to the residual offset to obtain the adjusted timing configuration. The current timing configuration scheme is updated using the adjusted timing configuration to obtain the optimized timing configuration scheme. The optimized timing configuration scheme is used to match and verify the real-time performance monitoring data to obtain the matched performance feedback result. If the matched performance feedback result indicates the existence of a new timing deviation, the new timing deviation is used as input to continue iterative optimization of the timing parameters until the matched performance feedback result meets the preset stability requirements.

6. The flash memory testing method using a solid-state drive controller chip according to claim 1, characterized in that, Step S4 further includes: Applying the optimized timing configuration scheme, layered read / write pressure tests are performed on the hard disk media layer. Preliminary data on performance bottlenecks are obtained under different load scenarios to determine the distribution range of bottleneck indicators. Based on the distribution range of bottleneck indicators, the response latency and throughput of the hard disk media are deeply monitored. Abnormal fluctuations in read / write pressure are extracted from the monitoring data to obtain preliminary clues of potential faults. Using these preliminary clues of potential faults, combined with log records from hardware feedback, abnormal points in the read / write pressure test are analyzed. When the frequency of occurrence of abnormal points exceeds a preset frequency threshold, the specific location of the fault point is determined, and the specific location of the fault point is taken as the location of the potential fault point.

7. The flash memory testing method using a solid-state drive controller chip according to claim 1, characterized in that, The comprehensive test case set obtained in step S5 includes: Based on the location of the potential fault point, environmental variables are collected in a targeted manner. Key fields related to the fault are extracted from the collected data to obtain an environmental variable dataset. For this environmental variable dataset, combined with the recorded values ​​of voltage parameters, an integrated parameter fusion algorithm is used to merge the data and determine the fused parameter combination. Using the fused parameter combination, correction values ​​for timing settings are obtained, and these correction values ​​are standardized to obtain adjusted timing configuration data. Based on the adjusted timing configuration data, input conditions for test cases are generated, and key constraints are extracted from these input conditions to determine the framework structure of the comprehensive test cases. Based on the framework structure of the comprehensive test cases and the intermediate results of data processing, the content of the test cases is filled in and refined to obtain a complete comprehensive test case set.

8. The flash memory testing method using a solid-state drive controller chip according to claim 7, characterized in that, After obtaining the complete integrated test case set in step S5, the following steps are also included: The complete set of comprehensive test cases is used to simulate and map the operating scenarios of hardware components. Potential anomalies are extracted from the simulation and mapping. When the distribution of anomalies exceeds a preset distribution threshold, the configuration of the relevant components is marked to obtain a risk list. The risk list is used as supplementary information to the comprehensive test case set.

9. The flash memory testing method using a solid-state drive controller chip according to claim 1, characterized in that, The final reliability assessment report obtained in step S6 includes: A subset suitable for diverse needs is selected from the comprehensive test case set and injected into the hard disk test environment to construct a performance monitoring process. Response data at performance limits is obtained to determine the initial response coverage, where the response coverage rate is the ratio of the number of triggered hardware state types to the preset total number of hardware state types. Based on the initial response coverage, a comparison is made with a preset coverage threshold. When the response coverage rate is lower than the preset coverage threshold, a feedback mechanism is activated, and the response coverage rate is returned as feedback information to step S2 or step S3. The voltage parameters and timing settings are then re-optimized, and a new comprehensive test case set is generated based on the optimized parameters. The adjusted test parameters are re-injected into the hard drive test environment, and the performance under various scenarios is monitored to obtain updated response data until the response coverage meets the preset coverage threshold. Based on the response data that finally meets the coverage threshold, the fluctuation of performance limits is analyzed, comprehensive data for reliability assessment is generated, and a reliability assessment report for the hard drive test environment is generated based on the comprehensive data.

10. A flash memory testing system utilizing a solid-state drive (SSD) controller chip, used to implement the flash memory testing method utilizing a SSD controller chip as described in any one of claims 1-9, characterized in that, The system includes: The feature extraction module is used to collect voltage fluctuation data and timing response signals during hard disk operation, and extract feature vectors to obtain an initial hardware state description; The performance monitoring module is used to analyze the interaction between voltage parameters and timing settings based on the initial hardware state description and a feedback control algorithm to determine the adjustment range threshold. If the voltage fluctuation exceeds the preset range threshold, a dynamic voltage correction sequence is generated and injected into the hard disk controller module. The real-time performance indicator change trend is obtained by monitoring the stability of read and write operations. The timing configuration module is used to extract timing setting deviation values ​​from the changing trends of the real-time performance indicators, process the timing setting deviation values ​​using an adaptive timing optimization algorithm, and obtain an optimized timing configuration scheme. The fault location module is used to perform multi-dimensional read and write stress tests on the hard disk media layer using the optimized timing configuration scheme. If the performance bottleneck index exceeds the preset index threshold, a hardware feedback loop is triggered to determine the location of potential fault points. The test case generation module is used to collect environmental variable data based on the location of the potential fault point, and use an integrated parameter fusion algorithm to merge the correction values ​​of voltage parameters and timing settings to obtain a comprehensive test case set; The performance evaluation module is used to select a subset of test cases from the comprehensive test case set that meet diverse needs and inject them into the hard disk test environment to monitor the overall performance limit response. If the response coverage is lower than the preset coverage threshold, the feedback mechanism is iteratively adjusted to obtain the final reliability evaluation report.

Images