A gain converted image sensor and a method and system for controlling the same
By introducing a comparator into the image sensor for gain determination and adjustment, the problem of low frame rate and high power consumption caused by multiple readouts of signals in the prior art is solved, achieving high frame rate and low power consumption within a high dynamic range.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 创睛半导体(成都)有限公司
- Filing Date
- 2024-11-28
- Publication Date
- 2026-05-29
AI Technical Summary
Existing dual-conversion-gain image sensors require multiple readouts when acquiring signals, resulting in low frame rates and high power consumption.
By introducing a comparator into the image sensor, the pixel signal is compared with a set voltage signal to generate a control signal DFD, thereby realizing gain judgment and adjustment. Only the pixel signal under the corresponding gain needs to be read once.
The improved image sensor has increased the frame rate and reduced power consumption, enabling it to achieve high frame rates and low power consumption within a high dynamic range.
Smart Images
Figure CN122120637A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of image sensor technology, and more particularly to an image sensor with pixel gain conversion, and a control method and system for the image sensor. Background Technology
[0002] CMOS image sensors (CIS) are widely used in digital still cameras, cellular phones, security cameras, medical devices, and automobiles. As a crucial parameter of CIS, dynamic range determines all the detail information in the captured image. Image sensors with high dynamic range have larger full-well capacity and higher sensitivity; however, high sensitivity also means that the full-well capacity is limited.
[0003] Currently, multi-gain dual photodiode active pixels can utilize the high gain ratio within the pixel to achieve high sensitivity in low light and high full-well capacity in strong light under a single exposure, thus improving the high dynamic range of image sensors. Low Conversion Gain (LCG) is used in strong light, and High Conversion Gain (HCG) is used in low light. By reading out image data under different conversion gains, a high dynamic range image that simultaneously displays bright and dark areas is finally synthesized. However, this method of achieving high dynamic range requires reading out multiple sets of image data under different gains for each row of pixels, including the dark level signal under high gain, the pixel signal under high gain, the dark level signal under low gain, and the pixel signal under low gain. Therefore, common modes include RSRS, RRSS, and RSSR to read out two sets of data. The high-gain signal is obtained by subtracting the high-gain pixel signal from the high-gain dark level signal; the low-gain signal is obtained in the same way, and finally, a high dynamic range image is synthesized. This method of reading out pixel signals results in a low frame rate and high power consumption for the image sensor because it involves multiple readouts and the readout data needs to be transmitted to the system for processing and judgment.
[0004] Low frame rates can cause image sensors to stutter during shooting, while high frame rates result in smoother, clearer images when shooting fast-paced action scenes. Reducing power consumption is equally important in image sensor applications, as the standby time of an image sensor depends on its power consumption. Low-power products help extend the battery life of image sensors, giving surveillance cameras a competitive edge. Furthermore, low power consumption reduces the negative impact of thermal noise on image quality and reduces the need for heat sinks, lowering the overall cost of the vision system. Therefore, developing high dynamic range, high frame rate, and low power image sensor products is a continuous pursuit in the industry. Summary of the Invention
[0005] The following description illustrates the contribution of this invention to the prior art.
[0006] The problem solved by this invention is that existing dual-conversion gain image sensors require multiple reads when acquiring signals, resulting in low frame rate and high power consumption.
[0007] One object of the present invention is to provide a gain-converting image sensor, which includes a pixel unit 101, a vertical drive circuit 102, a comparator 103, a ramp generation circuit 104, and a counter 105. Each comparator 103 individually generates a control signal DFD for controlling the pixels in the pixel unit 101.
[0008] In one possible design, comparator 103 includes a comparison unit 30 for comparing a pixel signal with a reference ramp signal; and a DFD control signal generation unit 31 for generating a control signal DFD based on the output signal of the comparison unit 30.
[0009] In one possible design, the DFD control signal generation unit 31 includes an AND gate, a D flip-flop, and a level converter. One input of the AND gate is connected to the output of the comparison unit 30, the output of the AND gate is connected to the input of the D flip-flop, the output of the D flip-flop is connected to the input of the level converter, and the output of the level converter is connected to the pixel circuit.
[0010] One input of the AND gate is connected to the output signal of the comparator unit 30, and the other input of the AND gate is connected to the enable signal DFD_EN; the output of the AND gate is connected to the DFD_CK signal, the XR terminal of the D flip-flop is connected to the DFD_RST signal, the XQ terminal of the D flip-flop is connected to the DFD_LV signal, and the output of the level converter outputs the control signal DFD.
[0011] In one possible design, the comparison unit 30 employs a two-stage comparison circuit structure.
[0012] Furthermore, the comparison unit 30 includes a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first capacitor C1, and a second capacitor C2.
[0013] The drain of the ninth NMOS transistor is connected to the source of the eighth NMOS transistor, and the source of the ninth NMOS transistor is grounded. The drain of the eighth NMOS transistor is connected to the common terminal of the sources of the sixth and seventh NMOS transistors. The gate of the sixth NMOS transistor is connected to one plate of the first capacitor C1. The drain of the sixth NMOS transistor is connected to the drain of the first PMOS transistor. The drain of the sixth NMOS transistor is connected to the gate of the sixth NMOS transistor via switch SW1. The gate of the first PMOS transistor is connected to the drain of the first PMOS transistor. The source of the first PMOS transistor is connected to the power supply. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor. The source of the second PMOS transistor is connected to the power supply. The drain of the second PMOS transistor is connected to the drain of the seventh NMOS transistor. The source of the seventh NMOS transistor is connected to the source of the sixth NMOS transistor. The drain of the seventh NMOS transistor is connected to the gate of the seventh NMOS transistor via switch SW2. The gate of the seventh NMOS transistor is connected to one plate of the second capacitor C2.
[0014] The gate of the third PMOS transistor is connected to the drain of the second PMOS transistor, the source of the third PMOS transistor is connected to the power supply, the drain of the third PMOS transistor is connected to the drain of the tenth NMOS transistor, the source of the tenth NMOS transistor is grounded, the source of the eleventh NMOS transistor is grounded, the drain of the eleventh NMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the fourth PMOS transistor is connected to the power supply. The gate of the fourth PMOS transistor is connected to the gate of the eleventh NMOS transistor, and the common terminal of the two gates is connected to the common terminal of the drains of the third PMOS transistor and the tenth NMOS transistor. The common terminal of the drains of the fourth PMOS transistor and the eleventh NMOS transistor is connected to the signal output terminal OUT3.
[0015] The other plate of the first capacitor C1 is connected to the ramp signal V. dac The other plate of the second capacitor C2 is connected to the pixel signal V. pix The gate of the eighth NMOS transistor is connected to the signal STB, the gate of the ninth NMOS transistor is connected to the signal Vbias1, and the gate of the tenth NMOS transistor is connected to the signal Vbias2.
[0016] In one possible design, pixel unit 101 employs a gain-adjustable pixel circuit.
[0017] As one possible implementation, the circuit structure of the pixel in the pixel unit 101 includes: a photodiode PD, a transmission transistor MN1, a reset transistor MN2, a dual floating diffused DFD transistor MN3, a transfer transistor MN4, a source follower transistor MN5, a first capacitor C1, and a second capacitor C2.
[0018] The cathode of the photodiode PD is connected to the drain of the transmission transistor MN1. The source of the transmission transistor MN1 is connected to the source of the double floating diffused DFD transistor MN3. The drain of the double floating diffused DFD transistor MN3 is connected to the source of the reset transistor MN2. The drain of the reset transistor MN2 is connected to the power supply. The common terminal of the drain of the double floating diffused DFD transistor and the source of the reset transistor MN2 is connected to the upper plate of the second capacitor C2. The lower plate of the second capacitor C2 is grounded. The common terminal of the source of the transmission transistor MN1 and the source of the double floating diffused DFD transistor MN3 is simultaneously connected to the upper plate of the first capacitor C1 and the gate of the transfer transistor MN4. The lower plate of the second capacitor C2 is grounded. The drain of the transfer transistor MN4 is connected to the power supply, and its source is connected to the drain of the source follower transistor MN5. The source of the source follower transistor MN5 is connected to the bit line.
[0019] The gate of the transmission transistor MN1 is connected to the control signal TX, the gate of the double floating diffused DFD transistor MN3 is connected to the control signal DFD, the gate of the reset transistor MN2 is connected to the control signal RST, and the gate of the source follower transistor MN5 is connected to the control signal SX.
[0020] Another object of the present invention is to provide a control method for the above-described image sensor system, the control method comprising:
[0021] During T0, electrons are completely removed from the transistor;
[0022] During T1, a dark level signal is read out at high conversion gain;
[0023] Gain determination is performed during T2;
[0024] During T3, the pixel signal at the corresponding gain is read out based on the gain determination result.
[0025] In one possible design, the following steps are included during T2:
[0026] Adjusting the reference ramp signal V dac The voltage is reduced to the set voltage value V. ref (V dac =V ref This sets the TX signal to a high level, turning on the transmission transistor;
[0027] When pixel signal V pix >V ref When the output signal voltage OUT3 of the comparator unit is high, after passing through the logic circuit, the control signal DFD is high, the dual floating diffused DFD transistor is turned on, and the image sensor switches from high conversion gain to low conversion gain.
[0028] When pixel signal V pix <V refAt this time, the dual floating diffused DFD transistor remains off and does not perform gain switching; then, the TX signal is set high again, the transmission transistor turns on for the second time, and the remaining electrons in the photodiode flow into the floating diffused region FD, and the pixel signal V... pix The voltage continues to decrease, and once it stabilizes, it enters period T3.
[0029] Furthermore, when the judgment result during T2 is high conversion gain, the pixel signal under high conversion gain is read out during T3.
[0030] Furthermore, when the judgment result during T2 is low conversion gain, the control method also includes turning on the reset transistor RST during T4, clearing all electrons in the floating diffusion region FD, and reading out the dark level signal under low conversion gain.
[0031] Another object of the present invention is to provide a control system for an image sensor, the system comprising:
[0032] The cleaning unit is used to remove electrons from the transistor during T0.
[0033] The readout unit is used to read out the dark level signal at high conversion gain during T1;
[0034] The judgment unit is used to perform gain judgment during T2;
[0035] The readout unit is also used to read out the pixel signal under the corresponding gain according to the gain judgment result during T3.
[0036] The improved image sensor of this invention compares the pixel signal with a set voltage signal using a comparator and outputs a control signal DFD to achieve gain judgment and adjustment. This overcomes the technical problems of existing technologies, such as multiple signal readouts and increased power consumption due to signal quantization. The improved image sensor only needs to read the pixel signal at the corresponding gain once, thus ensuring high dynamic range, improving frame rate, and reducing power consumption.
[0037] The design concept, principle, and implementation means of the present invention will be described below with reference to the accompanying drawings and embodiments, so as to more clearly describe the technical features and beneficial effects of the present invention. Attached Figure Description
[0038] The accompanying drawings provided herein are used to further illustrate embodiments of the present invention and constitute a part of this application, but do not constitute a limitation on the embodiments of the present invention.
[0039] Figure 1 This is a schematic diagram of the image sensor system according to Embodiment 1 of the present invention;
[0040] Figure 2 This is a schematic diagram of the pixel structure in Embodiment 1 of the present invention;
[0041] Figure 3 This is a schematic diagram of the comparator in Embodiment 1 of the present invention;
[0042] Figure 4 The operating timing of the circuit in Embodiment 2 of the present invention when the conversion gain is low;
[0043] Figure 5 The timing diagram of the circuit in Embodiment 2 of the present invention is shown for high conversion gain. Detailed Implementation
[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific examples and accompanying drawings. The illustrative embodiments and descriptions of this invention are for illustrative purposes only. However, those skilled in the art should understand that well-known structures, materials, or operating methods have not been shown or described in detail to avoid obscuring specific content.
[0045] Example 1
[0046] On the one hand, a gain-converting image sensor is provided, such as Figure 1 As shown, the image sensor includes a pixel unit 101, a vertical drive circuit 102, a comparator 103, a ramp generation circuit 104, and a counter 105. The pixel unit 101 consists of M rows and N columns of pixels. Each comparator 103 corresponds to one column of pixels in the pixel unit 101, and each comparator 103 generates a separate control signal DFD to control the pixels in the pixel unit 101. When reading the pixel signals row by row, the control signal DFD can individually control each corresponding pixel.
[0047] The main difference between this image sensor and existing technologies is that the pixel control signal (DFD) is not provided by the vertical drive circuit, but is output separately by the column comparator. The advantage of this improvement is that the comparator can adjust its output signal (DFD) based on the pixel's output voltage, thereby controlling the pixel's DFD. Specifically, when the pixel's output voltage is less than a set voltage, the signal is weak, and the DFD is off; when the pixel's output voltage is greater than the set voltage, the signal is strong, and the DFD is on. The switching of the pixel's DFD adjusts the image sensor to enter either low or high conversion gain mode. Since the pixel units in the image sensor are read row by row, the image signal of each pixel in a row at its corresponding gain can be read out in one pass, i.e., one signal stage (also called the S-stage). Traditional pixel signal readout processes require reading the pixel signal at high conversion gain and the pixel signal at low conversion gain separately, i.e., two signal stages.
[0048] Compared with traditional pixel signal readout methods, the above technical solution eliminates one signal stage readout, thereby increasing the signal readout speed and the sensor frame rate. At the same time, because one counter count is reduced, the power consumption of signal readout is also reduced.
[0049] It should be noted that the gain of the aforementioned image sensor is adjustable; a dual-conversion-gain image sensor, a triple-conversion-gain image sensor, or a multi-conversion-gain image sensor can be used. The higher the conversion gain, the greater the increase in frame rate and the greater the power saving.
[0050] As one possible implementation, this embodiment also provides a pixel circuit structure suitable for the above-described image sensor, such as... Figure 2 As shown, this pixel circuit structure is suitable for image sensors with dual conversion gain.
[0051] The pixel circuit structure includes a photodiode PD, a transfer transistor MN1, a reset transistor MN2, a double floating diffused DFD transistor MN3, a transfer transistor MN4, a source follower transistor MN5, a first capacitor C1, and a second capacitor C2. The cathode of the photodiode PD is connected to the drain of the transfer transistor MN1. The source of the transfer transistor MN1 is connected to the source of the double floating diffused DFD transistor MN3. The drain of the double floating diffused DFD transistor MN3 is connected to the source of the reset transistor MN2. The drain of the reset transistor MN2 is connected to the power supply. The common terminal of the drain of the double floating diffused DFD transistor and the source of the reset transistor MN2 is connected to the upper plate of the second capacitor C2, and the lower plate of the second capacitor C2 is grounded. The common terminal of the source of the transfer transistor MN1 and the source of the double floating diffused DFD transistor MN3 is simultaneously connected to the upper plate of the first capacitor C1 and the gate of the transfer transistor MN4. The lower plate of the second capacitor C2 is grounded. The drain of the transfer transistor MN4 is connected to the power supply, and its source is connected to the drain of the source follower transistor MN5. The source of the source follower transistor MN5 is connected to the bit line.
[0052] The gate of the transmission transistor MN1 is connected to the control signal TX, the gate of the double floating diffused DFD transistor MN3 is connected to the control signal DFD, the gate of the reset transistor MN2 is connected to the control signal RST, and the gate of the source follower transistor MN5 is connected to the control signal SX.
[0053] The pixel circuit works as follows: when the photodiode generates fewer electrons, the dual floating diffusion DFD transistor is off, and the capacitance of the floating diffusion region FD is C1. At this time, the pixel's conversion gain is high, allowing for the reading of darker image signals. When the photodiode generates more electrons, the dual floating diffusion DFD transistor is on, and the capacitance of the floating diffusion region FD is C1 + C2. At this time, the pixel's conversion gain is low, allowing for the reading of brighter image signals. By switching the dual floating diffusion DFD transistor on and off, the dynamic range of the image sensor is increased.
[0054] On the other hand, this embodiment provides a comparator circuit structure suitable for the above-mentioned image sensor, such as... Figure 3 As shown, the comparator circuit includes a comparison unit 30, which compares the pixel signal and the reference ramp signal, and outputs the compared signal to the counter; and a DFD control signal generation unit 31, which generates a DFD control signal based on the output signal of the comparison unit 30.
[0055] The comparison unit 30 can adopt a conventional comparator structure, whose function is to compare the magnitudes of the two input voltages and output the different voltage results. Any comparator structure capable of achieving this basic function can be used in the aforementioned comparator. As one possible implementation, Figure 3 A comparator structure is provided, wherein the comparator unit 30 includes a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first capacitor C1, and a second capacitor C2.
[0056] The drain of the ninth NMOS transistor is connected to the source of the eighth NMOS transistor, and the source of the ninth NMOS transistor is grounded. The drain of the eighth NMOS transistor is connected to the common terminal of the sources of the sixth and seventh NMOS transistors. The gate of the sixth NMOS transistor is connected to one plate of the first capacitor C1. The drain of the sixth NMOS transistor is connected to the drain of the first PMOS transistor. The drain of the sixth NMOS transistor is connected to the gate of the sixth NMOS transistor via switch SW1. The gate of the first PMOS transistor is connected to the drain of the first PMOS transistor. The source of the first PMOS transistor is connected to the power supply. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor. The source of the second PMOS transistor is connected to the power supply. The drain of the second PMOS transistor is connected to the drain of the seventh NMOS transistor. The source of the seventh NMOS transistor is connected to the source of the sixth NMOS transistor. The drain of the seventh NMOS transistor is connected to the gate of the seventh NMOS transistor via switch SW2. The gate of the seventh NMOS transistor is connected to one plate of the second capacitor C2.
[0057] The gate of the third PMOS transistor is connected to the drain of the second PMOS transistor, the source of the third PMOS transistor is connected to the power supply, the drain of the third PMOS transistor is connected to the drain of the tenth NMOS transistor, the source of the tenth NMOS transistor is grounded, the source of the eleventh NMOS transistor is grounded, the drain of the eleventh NMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the fourth PMOS transistor is connected to the power supply. The gate of the fourth PMOS transistor is connected to the gate of the eleventh NMOS transistor, and the common terminal of the two gates is connected to the common terminal of the drains of the third PMOS transistor and the tenth NMOS transistor. The common terminal of the drains of the fourth PMOS transistor and the eleventh NMOS transistor is connected to the signal output terminal OUT3.
[0058] The other plate of the first capacitor C1 is connected to the ramp signal V. dac The other plate of the second capacitor C2 is connected to the pixel signal V. pix The gate of the eighth NMOS transistor is connected to the signal STB, the gate of the ninth NMOS transistor is connected to the signal Vbias1, and the gate of the tenth NMOS transistor is connected to the signal Vbias2.
[0059] The DFD control signal generation unit 31 includes an AND gate, a D flip-flop, and a level converter. One input of the AND gate is connected to the output of the comparison unit 30, the output of the AND gate is connected to the input of the D flip-flop, the output of the D flip-flop is connected to the input of the level converter, and the output of the level converter is connected to the pixel circuit.
[0060] One input of the AND gate is connected to the output signal of the comparator unit 30, and the other input of the AND gate is connected to the enable signal DFD_EN; the output of the AND gate is connected to the DFD_CK signal, the XR terminal of the D flip-flop is connected to the DFD_RST signal, the XQ terminal of the D flip-flop is connected to the DFD_LV signal, and the output of the level converter outputs the control signal DFD.
[0061] Example 2
[0062] The difference between this embodiment and Embodiment 1 is that this embodiment provides a control method for the image sensor with gain conversion as described in Embodiment 1, such as... Figure 4 and Figure 5 As shown.
[0063] The signal readout phase of an image sensor includes the following stages:
[0064] During T0 reset, the pixel's RST, TX, and DFD control signals are all high, and the reset transistor, transmission transistor, and double floating diffused DFD transistor are all turned on to clear the electrons in the transistors. After clearing, the TX, DFD, and RST signals are sequentially adjusted to low levels.
[0065] During dark level readout at high conversion gain T1, the transmission transistor, dual floating diffused DFD transistor, and reset transistor remain off, while the input reference ramp signal V... dac Read the dark level signal when the conversion gain is high;
[0066] During the T2 gain determination period, adjust the reference ramp signal V. dac The voltage, the adjustment amount is the reference voltage V ref Set the TX signal high to turn on the transmission transistor; when the pixel signal V... pix >V ref When the output signal voltage OUT3 of the comparator unit is high, after passing through the logic circuit, the control signal DFD is high, the dual floating diffused DFD transistor is turned on, and the image sensor switches from high conversion gain to low conversion gain.
[0067] Conversely, when the pixel signal V pix <V ref At this time, the dual floating diffused DFD transistor remains off and does not perform gain switching; then, the TX signal is set high again, the transmission transistor turns on for the second time, and the remaining electrons in the photodiode flow into the floating diffused region FD, and the pixel signal V... pix The voltage continues to decrease, and once it stabilizes, it enters stage T3.
[0068] During the T3 pixel signal readout period (Signal phase),
[0069] When a low conversion gain is selected in stage T2, the pixel signal with that low conversion gain is read out at this time.
[0070] When the T2 stage has a high conversion gain, the pixel signal with the high conversion gain is read out.
[0071] During the dark level readout at low conversion gain T4, with DFD on, the reset transistor RST is turned on, all electrons in the floating diffusion region FD are cleared, and the dark level signal at low conversion gain is read out.
[0072] It should be noted that since T1 reads a dark level under high conversion gain, if a low conversion gain is selected during T2, then T4 cannot be omitted; conversely, if T2 is a high conversion gain, then T4 can be omitted. When the readout action during T4 is omitted, power consumption will be further reduced.
[0073] The image sensor control method described above controls each pixel individually through the control signal DFD, and controls the opening or closing of the dual floating diffused DFD transistors in the pixel circuit based on the illumination conditions of different pixels, thereby adjusting the pixel readout mode of each individual pixel to match its illumination intensity.
[0074] In another embodiment of this application, a control system for an image sensor is also disclosed, the system comprising:
[0075] The cleaning unit is used to remove electrons from the transistor during T0.
[0076] The readout unit is used to read out the dark level signal at high conversion gain during T1;
[0077] The judgment unit is used to perform gain judgment during T2;
[0078] The readout unit is also used to read out the pixel signal under the corresponding gain according to the gain judgment result during T3.
[0079] The various technical features of the embodiments described above can be combined arbitrarily. For the sake of brevity, not all possible combinations of the various technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered to be within the scope of this specification. Moreover, the terms "having," "comprising," "including," and similar terms should be understood as "comprising," unless otherwise specifically stated. In addition, the accompanying drawings are provided for the purpose of explaining to those skilled in the art, and the drawings are not necessarily drawn to scale.
Claims
1. An image sensor with gain conversion, characterized in that, It includes a pixel unit (101), a vertical driving circuit (102), a comparator (103), a ramp generation circuit (104), and a counter (105), wherein each comparator (103) generates a control signal DFD to control the pixel unit (101).
2. The image sensor according to claim 1, characterized in that, The comparator (103) includes: The comparison unit (30) is used to compare the pixel signal with the reference ramp signal; The DFD control signal generation unit (31) generates the control signal DFD based on the output signal of the comparison unit (30).
3. The image sensor according to claim 2, characterized in that, The DFD control signal generation unit (31) includes an AND gate, a D flip-flop, and a level converter. One input of the AND gate is connected to the output of the comparison unit (30), the output of the AND gate is connected to the input of the D flip-flop, the output of the D flip-flop is connected to the input of the level converter, and the output of the level converter is connected to the pixel circuit. One input of the AND gate is connected to the output signal of the comparison unit (30), and the other input of the AND gate is connected to the enable signal DFD_EN; the output of the AND gate is connected to the DFD_CK signal, the XR terminal of the D flip-flop is connected to the DFD_RST signal, the XQ terminal of the D flip-flop is connected to the DFD_LV signal, and the output of the level converter outputs the control signal DFD.
4. The image sensor according to claim 2, characterized in that, The comparison unit (30) adopts a two-stage comparison circuit structure.
5. The image sensor according to claim 1, characterized in that, The pixel unit (101) employs a gain-adjustable pixel circuit.
6. The image sensor according to claim 5, characterized in that, The circuit structure of the pixel in the pixel unit (101) includes: photodiode PD, transmission transistor MN1, reset transistor MN2, double floating diffused DFD transistor MN3, transfer transistor MN4, source follower transistor MN5, first capacitor C1, and second capacitor C2. The cathode of the photodiode PD is connected to the drain of the transmission transistor MN1. The source of the transmission transistor MN1 is connected to the source of the double floating diffused DFD transistor MN3. The drain of the double floating diffused DFD transistor MN3 is connected to the source of the reset transistor MN2. The drain of the reset transistor MN2 is connected to the power supply. The common terminal of the drain of the double floating diffused DFD transistor and the source of the reset transistor MN2 is connected to the upper plate of the second capacitor C2. The lower plate of the second capacitor C2 is grounded. The common terminal of the source of the transmission transistor MN1 and the source of the double floating diffused DFD transistor MN3 is simultaneously connected to the upper plate of the first capacitor C1 and the gate of the transfer transistor MN4. The lower plate of the second capacitor C2 is grounded. The drain of the transfer transistor MN4 is connected to the power supply, and its source is connected to the drain of the source follower transistor MN5. The source of the source follower transistor MN5 is connected to the bit line. The gate of the transmission transistor MN1 is connected to the control signal TX, the gate of the double floating diffused DFD transistor MN3 is connected to the control signal DFD, the gate of the reset transistor MN2 is connected to the control signal RST, and the gate of the source follower transistor MN5 is connected to the control signal SX.
7. A control method for an image sensor as described in any one of claims 1-6, characterized in that, The method includes: During T0, electrons are completely removed from the transistor; During T1, a dark level signal is read out at high conversion gain; Gain determination is performed during T2; During T3, the pixel signal at the corresponding gain is read out based on the gain determination result.
8. The control method for an image sensor according to claim 7, characterized in that, The T2 period includes the following steps: Adjusting the reference ramp signal V dac The voltage is reduced to the set voltage value V. ref (V dac =V ref The TX signal is set to high, turning on the transmission transistor; When pixel signal V pix >V ref When the output signal voltage OUT3 of the comparator unit is high, after passing through the logic circuit, the control signal DFD is high, the dual floating diffused DFD transistor is turned on, and the image sensor switches from high conversion gain to low conversion gain. When pixel signal V pix <V ref At this time, the dual floating diffused DFD transistor remains off and does not perform gain switching; then, the TX signal is set high again, the transmission transistor turns on for the second time, and the remaining electrons in the photodiode flow into the floating diffused region FD, and the pixel signal V... pix The voltage continues to decrease, and once it stabilizes, it enters period T3.
9. The control method for the image sensor according to claim 7, characterized in that, When the judgment result during T2 is high conversion gain, the pixel signal under high conversion gain is read out during T3. When the judgment result during T2 is low conversion gain, the control method also includes turning on the reset transistor RST during T4, clearing all electrons in the floating diffusion region FD, and reading out the dark level signal under low conversion gain.
10. A control system for an image sensor, characterized in that, The system includes: The cleaning unit is used to remove electrons from the transistor during T0. The readout unit is used to read out the dark level signal at high conversion gain during T1; The judgment unit is used to perform gain judgment during T2; The readout unit is also used to read out the pixel signal under the corresponding gain according to the gain judgment result during T3.