Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same are disclosed. The semiconductor structure includes a substrate, an isolation component, and a first-type component. The isolation component is disposed in a trench adjacent to a first peripheral region of the substrate. The isolation component includes first, second, and third liner layers and a fill layer. The first liner layer covers sidewalls of the trench adjacent to the first peripheral region. The second liner layer covers the first liner layer and lower portions of the sidewalls. The third liner layer covers exposed portions of the first liner layer. The fill layer fills the trench and covers the second and third liner layers. The first-type component is formed in the first peripheral region. In a direction substantially perpendicular to a top surface of the substrate, a first bottom surface of a first source / drain region of the first-type component is located between the top surface of the substrate and a second bottom surface of the third liner layer.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods for forming them, and particularly to isolation components of semiconductor structures and methods for forming them. Background Technology

[0002] To increase component density and improve overall performance within integrated circuit devices, manufacturing technologies continue to focus on miniaturizing component dimensions. As component dimensions shrink, numerous challenges arise. For example, as transistor channel lengths continue to shrink, further improvements are needed to address the voltage drop (Vt roll-off) phenomenon. Summary of the Invention

[0003] This invention provides a semiconductor structure including a substrate, a first isolation member, and a first-type device. The substrate has a first peripheral region. The first isolation member is disposed in a first trench of the substrate adjacent to the first peripheral region. The first trench has a first sidewall adjacent to the first peripheral region. The first isolation member includes a first liner, a second liner, a third liner, and a fill layer. The first liner conformally covers the first sidewall of the first trench. The second liner conformally covers the first liner and covers the lower portion of the first sidewall, such that a portion of the first liner is exposed from the second liner. The third liner conformally covers the portion of the first liner exposed from the second liner. The fill layer fills the first trench and covers the second and third liners. The first-type device is formed in the first peripheral region. In a direction substantially perpendicular to the top surface of the substrate, a first bottom surface of a first source-drain region of the first-type device is located between the top surface of the substrate and the second bottom surface of the third liner.

[0004] This invention provides a method for forming a semiconductor structure, including providing a substrate having a first peripheral region; forming a first trench in the substrate adjacent to the first peripheral region, the first trench having a first sidewall adjacent to the first peripheral region; and forming a first isolation member in the first trench. The first isolation member includes a first liner, a second liner, a third liner, and a fill layer. The first liner conformally covers the first sidewall of the first trench. The second liner conformally covers the first liner and covers the lower portion of the first sidewall, such that a portion of the first liner is exposed from the second liner. The third liner conformally covers the portion of the first liner exposed from the second liner. The fill layer fills the first trench and covers the second and third liners. The method further includes forming a first-type component in the first peripheral region, wherein, in a direction substantially perpendicular to the top surface of the substrate, a first bottom surface of a first source-drain region of the first-type component is located between the top surface of the substrate and the second bottom surface of the third liner.

[0005] Some embodiments of the semiconductor structure of this invention create locally deformed N-type metal-oxide-semiconductor field-effect transistor (MOSFET) component regions by changing the substrate material of a portion of the isolation component. This increases electron mobility in the MOSFET channel region, thereby suppressing the decline of the MOSFET's threshold voltage. Since the semiconductor structure of some embodiments of this invention only has specific stress in designated component regions, it does not affect the electrical properties of electronic components in other component regions. Attached Figure Description

[0006] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure according to some embodiments of the present invention.

[0007] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 For the formation of some embodiments of the present invention Figure 1 A schematic cross-sectional view of the intermediate stage of the semiconductor structure shown.

[0008] Symbol Explanation

[0009] 200: Substrate

[0010] 200T, 212T: Top surface

[0011] 201: First Trap

[0012] 202: Second Trap

[0013] 203: Third Trap

[0014] 204, 204-1, 204-2, 204-3, 204-4, 204-5: Trench

[0015] 204-1B, 204-2B, 204-4B, 211-B, 428NB: Bottom surface

[0016] 204-1S1, 204-1S2, 204-2S1, 204-2S2, 204-4S1, 204-4S2: Sidewall

[0017] 205b: Doped region

[0018] 206, 206-1, 206-2, 206-3, 206-4, 206-5: Isolation components

[0019] 206-1A, 206-2A, 206-4A: Insulation Structure

[0020] 206-1L, 206-2L: First Half

[0021] 206-1R, 206-2R: Second Half

[0022] 208: First Liner

[0023] 210: Second Liner

[0024] 211: Third Liner

[0025] 212: Fill layer

[0026] 212-1S, 212-2S, 212-4S1, 212-4S2: Side view

[0027] 213, 242: Insulating cover layer

[0028] 230: Word Line

[0029] 248a, 248b: Contact plugs

[0030] 250: Bit Line

[0031] 260: Storage capacitor

[0032] 270, 278: Photoresist pattern

[0033] 274, 276-1, 276-2, 276-3: Opening

[0034] 400: Array area

[0035] 406: Surrounding Area

[0036] 402: First Surrounding Area

[0037] 404: Second Surrounding Area

[0038] 410: Memory Array

[0039] 412N: Type I component

[0040] 412P: Type II Component

[0041] 424N: First gate structure

[0042] 428N: First source / drain region

[0043] 424P: Second gate structure

[0044] 428P: Second source and drain regions

[0045] 500: Semiconductor Structure

[0046] A1, A2, A3: Active Zone

[0047] C1, C2: Central axis

[0048] D1, D2, D3: Depth Detailed Implementation

[0049] When the component size of existing integrated circuit devices with complementary metal-oxide-semiconductor field-effect transistors (CMOS) is miniaturized, N-type CMOS MOSFETs experience a short-channel effect due to the continuous reduction in channel length, causing a drop in the component's critical voltage. P-type CMOS MOSFETs, however, do not exhibit this phenomenon. To address this issue, some embodiments of the present invention utilize semiconductor structures that modify a portion of the substrate material of the isolation component to create locally deformed N-MOSFET component regions. This enhances electron mobility within the N-MOSFET channel region, thereby suppressing the drop in the N-MOSFET critical voltage. Since the semiconductor structures of some embodiments of the present invention only exhibit specific stress in designated component regions, they do not affect the electrical properties of electronic components in other component regions.

[0050] Reference Figure 1 The semiconductor structure 500 includes a memory array and peripheral components. The memory array includes a dynamic random access memory (DRAM) array or other suitable memory array. The peripheral components include metal-oxide-semiconductor field-effect transistors (MOSFETs) or other suitable peripheral components. The semiconductor structure 500 includes a substrate 200, isolation components 206 (including isolation components 206-1, 206-2, 206-3, 206-4, 206-5), a first well 201, a second well 202, a third well 203, active regions A1, A2, A3, a memory array 410, a first-type component 412N, and a second-type component 412P.

[0051] Semiconductor structure 500 has an array region 400 and a peripheral region 406 adjacent to the array region 400. The peripheral region 406 includes a first peripheral region 402 adjacent to the array region 400 and a second peripheral region 404 adjacent to the first peripheral region 402. For example, the array region 400 is used as a formation region for a memory array 410, the first peripheral region 402 is a formation region for a first-type component 412N, and the second peripheral region 404 is a formation region for a second-type component 412P. In some embodiments, the first-type component 412N and the second-type component 412P have opposite conductivity types. For example, the first-type component 412N is an N-type metal-oxide-semiconductor field-effect transistor, and the second-type component 412P is a P-type metal-oxide-semiconductor field-effect transistor.

[0052] The substrate 200 may be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In some embodiments, the substrate 200 may be a semiconductor-on-insulator (SOI) substrate. In some embodiments, the conductivity type of the substrate 200 may be P-type or N-type, depending on the design requirements.

[0053] Semiconductor structure 500 may include a first well 201, a second well 202, and a third well 203 in substrate 200. The first well 201 is located in array region 400, the second well 202 is located in a first peripheral region 402, and the third well 203 is located in a second peripheral region 404. In some embodiments, the first well 201 and the second well 202 may have the same conductivity type and doping concentration. The first well 201 (or the second well 202) and the third well 203 may have opposite conductivity types.

[0054] Multiple isolation components 206 are disposed in corresponding multiple trenches 204 (including trenches 204-1, 204-2, 204-3, 204-4, 204-5) of the substrate 200. The isolation components 206 can define multiple active regions A1, A2, A3 of the array region 400, the first peripheral region 402, and the second peripheral region 404. Furthermore, the isolation components 206 disposed within the array region 400, the first peripheral region 402, or the second peripheral region 404 can be used as electrical isolation components for components in the active regions A1, A2, or A3. For example, isolation component 206-1 is disposed in trench 204-1 between the array region 400 and the first peripheral region 402. Trench 204-1 has sidewalls 204-1S1 and 204-1S2 adjacent to the array region 400 and the first peripheral region 402, respectively, and a bottom surface 204-1B. Therefore, isolation member 206-1 defines the active region A1 of array region 400 and the active region A2 of first peripheral region 402. Isolation member 206-2 is disposed in trench 204-2 between first peripheral region 402 and second peripheral region 404. Furthermore, trench 204-2 has sidewalls 204-2S1, 204-2S2 and bottom surface 204-2B adjacent to the first peripheral region 402 and the second peripheral region 404, respectively. Therefore, isolation member 206-2 defines the active region A2 of first peripheral region 402 and the active region A3 of second peripheral region 404. Isolation member 206-3 is disposed in trench 204-3 within array region 400 and can serve as an electrical isolation member for dynamic random access memory formed in active region A1. Isolation component 206-4 is disposed in trench 204-4 within the first peripheral region 402, and can serve as an electrical isolation component for an N-type metal-oxide-semiconductor field-effect transistor formed in the active region A2. Isolation component 206-5 is disposed in trench 204-5 within the second peripheral region 404, and can serve as an electrical isolation component for a P-type metal-oxide-semiconductor field-effect transistor formed in the active region A3. For example... Figure 1 As shown, the bottom surface of the isolation component 206 (including the bottom surface 204-1B of isolation component 206-1 and the bottom surface 204-2B of isolation component 206-2) is located within the first well 201, the second well 202, and the third well 203. In some embodiments, any number of isolation components 206-3, 206-4, and 206-5 may be provided within the array region 400, the first peripheral region 402, and the second peripheral region 404, as required by the design.

[0055] In some embodiments, the isolation member 206 may be a shallow trench isolation (STI). Each of the isolation members 206-1, 206-2, 206-3, 206-4, and 206-5 may include at least a first liner 208, a second liner 210, and a filler layer 212. In the isolation members 206-1, 206-2, 206-3, 206-4, and 206-5, the first liner 208 conformally covers the bottom surface and opposite sidewalls of the trenches 204-1, 204-2, 204-3, 204-4, and 204-5, and the second liner 210 conformally covers the first liner 208. Furthermore, the filler layer 212 fills the trenches 204-1, 204-2, 204-3, 204-4, and 204-5 and covers the second liner 210.

[0056] like Figure 1 As shown, the isolation components 206-1 and 206-2 used to define the first peripheral region 402 differ from the isolation components 206-3 and 206-5 located in the array region 400 and the second peripheral region 404 in that: isolation component 206-1 has sidewalls (adjacent sidewalls 204-1S1 and 204-1S2) and a bottom surface (adjacent bottom surface 204-1B) that are opposite to each other, and isolation component 206-2 has sidewalls (adjacent sidewalls 204-2S1 and 204-2S2) and a bottom surface (adjacent bottom surface 204-2B) that are opposite to each other. The second liner 210 of the isolation components 206-1 and 206-2 completely covers the sidewalls 204-1S1 and 204-2S2 and the bottom surfaces 204-1B and 204-2B of all trenches 204-1 and 204-2, and extends from the sidewalls 204-1S1 and 204-2S2 to cover the lower part of the sidewalls 204-1S2 and 204-2S1 (near the bottom surfaces 204-1B and 204-2B), so that a portion of the first liner 208 of the isolation components 206-1 and 206-2 is exposed from the second liner 210. The second liner 210 of the isolation components 206-3 and 206-5 completely covers the opposite sidewalls of trenches 204-3 and 204-5.

[0057] The isolation component 206-4 located in the first peripheral region 402 differs from the isolation components 206-3 and 206-5 located in the array region 400 and the second peripheral region 404 in that: the isolation component 206-4 has opposing sidewalls (adjacent to sidewalls 204-4S1 and 204-4S2) and a bottom surface (adjacent to bottom surface 204-4B). The second liner 210 of the isolation component 206-4 extends from the lower part of the sidewall 204-4S1 (near the bottom surface 204-4B) and covers the lower part of the sidewall 204-4S2 (near the bottom surface 204-4B) so that a portion of the first liner 208 of the isolation component 206-4 is exposed from the second liner 210.

[0058] Furthermore, isolation components 206-1, 206-2, and 206-4 may further include a third liner 211. The third liner 211 of isolation components 206-1 and 206-2 is disposed on the sidewalls 204-1S2 and 204-2S1 of trenches 204-1 and 204-2 adjacent to the first peripheral region 402. The third liner 211 of isolation component 206-4 is disposed on the opposite sidewalls 204-4S1 and 204-4S2 of trench 204-4. The third liner 211 of the isolation components 206-1, 206-2, and 206-4 is located between the first liner 208 and the filling layer 212, and is arranged side by side with the second liner 210 along the sidewalls 204-1S2 and 204-2S1 of the trenches 204-1 and 204-2 and the opposite sidewalls 204-4S1 and 204-4S2 of the trench 204-4, so that the interface between the second liner 210 and the third liner 211 (the interface position is the same as the bottom surface 211-B of the third liner 211) is located between the top surface 200T of the substrate 200 and the bottom surfaces 204-1B, 204-2B, and 204-4B of the trenches 204-1, 204-2, and 204-4. The third liner 211 of the isolation components 206-1, 206-2, and 206-4 conformally covers the upper portions of the sidewalls 204-1S2, 204-2S1, 204-4S1, and 204-4S2, as well as the first liner 208 exposed from the second liner 210. In some embodiments, the first liner 208, the second liner 210, and the filler layer 212 of the isolation components 206-1, 206-2, and 206-4 contact different surfaces of the third liner 211. The filling layer 212 of the isolation components 206-1, 206-2, 206-4 is close to the different parts of the sidewalls 204-1S2, 204-2S1, 204-4S1, 204-4S2 of the trenches 204-1, 204-2, 204-4, covering and contacting the second liner 210 and the third liner 211.

[0059] like Figure 1As shown, isolation components 206-1 and 206-2 may have asymmetrical structures. For example, isolation component 206-1, located between array region 400 and first peripheral region 402, is divided along the central axis C1, substantially perpendicular to the top surface 200T of substrate 200, into a first half 206-1L adjacent to array region 400 and a second half 206-1R adjacent to first peripheral region 402. The first half 206-1L and the second half 206-1R are asymmetrical along the central axis C1. Isolation component 206-2, located between first peripheral region 402 and second peripheral region 404, is divided along the central axis C2, substantially perpendicular to the top surface 200T of substrate 200, into a first half 206-2L adjacent to first peripheral region 402 and a second half 206-2R adjacent to second peripheral region 404. The first half 206-2L and the second half 206-2R are asymmetrical along the central axis C2. In addition, the isolation components 206-3, 206-4, and 206-5 located in the array region 400, the first peripheral region 402, and the second peripheral region 404 may have a left-right symmetrical structure.

[0060] In some embodiments, the first substrate 208, the second substrate 210, the third substrate 211, and the fill layer 212 may comprise insulating materials such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or combinations thereof. In some embodiments, the first substrate 208, the third substrate 211, and the fill layer 212 are formed of a first material, the second substrate 210 is formed of a second material, and the first material is different from the second material. For example, the first substrate 208, the third substrate 211, and the fill layer 212 may comprise silicon oxide, and the second substrate 210 may comprise silicon nitride. In some embodiments, the isolation component 206 is formed using a patterning process and subsequent deposition and planarization processes. The patterning process includes photolithography and etching processes. The deposition process includes chemical vapor deposition (CVD) and / or atomic layer deposition (ALD). The planarization process includes chemical mechanical polishing (CMP) and / or etch-back.

[0061] In embodiments where the first peripheral region 402 is an N MOSFET device region, the first substrate 208, the third substrate 211, and the fill layer 212 are silicon oxide layers, and the second substrate 210 is a silicon nitride layer, the third substrate 211 can be used to replace a portion of the second substrate 210 adjacent to the isolation components 206-1 and 206-2 of the first peripheral region 402. In some embodiments, the third substrate 211 formed of silicon oxide itself has compressive stress, which can apply tensile stress to the adjacent first peripheral region 402 (e.g., the channel region of the N MOSFET), thereby improving the electron mobility in the N MOSFET channel region. When the N MOSFET device size is miniaturized, the drop in the device threshold voltage (Vt roll-off) can be suppressed. In addition, in the embodiment where the array region 400 is a dynamic random access memory array region and the second peripheral region 404 is a P MOSFET component region, the first liner 208, the second liner 210 and the fill layer 212 of the isolation components adjacent to the array region 400 or the second peripheral region 404 maintain a silicon oxide-silicon nitride-silicon oxide composite structure, which can maintain the stress of the array region 400 and the second peripheral region 404 as well as the electrical properties (e.g., threshold voltage) of the memory array (e.g., DRAM array) and the second type component (e.g., PMOSFET).

[0062] like Figure 1 As shown, the third liner 211 of the isolation members 206-1 and 206-2 has a bottom surface 211-B adjacent to the bottom surfaces 204-1B and 204-2B of the trenches 204-1 and 204-2. In some embodiments, the depth D1 of the bottom surfaces 204-1B and 204-2B of the trenches 204-1 and 204-2 from the top surface 200T of the substrate 200 is greater than the depth D2 of the bottom surface 211-B of the third liner 211 from the top surface 200T of the substrate 200. In some embodiments, the ratio of depth D2 to depth D1 can range from about 1.3:2 to about 1.3:7. If the ratio of depth D2 to depth D1 is less than 1.3:7, the depth of the third liner 211 may be too small to apply sufficient compressive stress to the first peripheral region 402; if the ratio of depth D2 to depth D1 is greater than 1.3:2, the depth of the third liner 211 may exceed the depth D1 of the trenches 204-1 and 204-2 (e.g., the ratio of depth D2 to depth D1 is greater than 1:1), which is not allowed by the process.

[0063] A memory array 410 is formed in an array region 400. The memory cells of the memory array 410 may include word lines 230, contact plugs 248a and 248b, bit lines 250, and storage capacitors 260. The word lines 230 are embedded in word line trenches (not shown) of the substrate 200 within the array region 400 and extend across the active region A1 and isolation members 206-3. Furthermore, the word lines 230 are disposed in a first well 201.

[0064] The storage capacitor 260 of the memory array 410 is disposed above the substrate 200 and the contact plug 248b, and is electrically connected to the doped region 205b via the contact plug 248b.

[0065] One or more first-type components 412N are formed in the active region A2 of the first peripheral region 402. For example, the first-type component 412N of an N-type metal-oxide-semiconductor field-effect transistor may include a first gate structure 424N and a first source-drain region 428N. The first gate structure 424N is disposed on the substrate 200 within the second well 202.

[0066] The first source-drain region 428N of the first type component 412N is disposed in the substrate 200 and adjacent to the opposite side of the first gate structure 424N. The first source-drain region 428N has a bottom surface 428NB. In some embodiments, the depth D3 of the bottom surface 428NB of the first source-drain region 428N from the top surface 200T of the substrate 200 is less than or equal to the depth D2. If the depth D3 of the first source-drain region 428N is greater than the depth D2 of the third liner 211, the third liner 211 may not be able to apply compressive stress to the entire channel region of the first type component 412N (the portion of the active region A2 located below the first gate structure 424N and between the first source-drain regions 428N).

[0067] One or more second-type components 412P are formed in the active region A3 of the second peripheral region 404. For example, the second-type component 412P of a P-type metal-oxide-semiconductor field-effect transistor may include a second gate structure 424P and a second source-drain region 428P. The second gate structure 424P is disposed on the substrate 200 within the third well 203. The first source-drain region 428N and the second source-drain region 428P have dopants of opposite conductivity types.

[0068] The following uses Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 This describes the method for forming semiconductor structure 500. (Reference) Figure 2A substrate 200 is provided. Next, a multi-pass ion implantation process is performed to implant a first dopant of a first conductivity type (e.g., P-type) into the substrate 200 within the array region 400 and the adjacent first peripheral region 402, and to implant a second dopant of a second conductivity type (e.g., N-type) into the substrate 200 within the second peripheral region 404, thereby forming a first well 201, a second well 202, and a third well 203 in the substrates 200 of the array region 400, the first peripheral region 402, and the second peripheral region 404. Furthermore, a dopant of a second conductivity type opposite to the first conductivity type is implanted into the substrate 200 of the array region 400 to form a doped region 205b on the first well 201.

[0069] Subsequently, a patterning process is performed to form multiple trenches 204 in the substrate 200 to define the formation positions of multiple isolation components 206. Specifically, the above patterning process forms trenches 204-1 in the substrate 200 between the array region 400 and the first peripheral region 402, trenches 204-2 in the substrate 200 between the first peripheral region 402 and the second peripheral region 404, trenches 204-3 in the substrate 200 within the array region 400, trenches 204-4 in the substrate 200 within the first peripheral region 402, and trenches 204-5 in the substrate 200 within the second peripheral region 404.

[0070] Next, a deposition process and a subsequent planarization process are performed to form insulating structures and isolation components in trench 204. Specifically, the deposition and planarization processes form insulating structures 206-1A, 206-2A, and 206-4A and isolation components 206-3 and 206-5 in trenches 204-1, 204-2, 204-3, 204-4, and 204-5, respectively. Insulating structures 206-1A, 206-2A, and 206-4A, and isolation components 206-3 and 206-5 each include a first substrate 208, a second substrate 210, and a filler layer 212. The first substrate 208 extends downward from the top surface 200T of the substrate 200, conformally covering the bottom surface and opposite sidewalls of trenches 204-1, 204-2, 204-3, 204-4, and 204-5. Furthermore, the first liner 208 extends to cover the top surface 200T of the substrate 200. The second liner 210 extends downward from the top surface 200T of the substrate 200, conformally and completely covering the surfaces of the first liner 208 within the trenches 204-1, 204-2, 204-3, 204-4, and 204-5. The fill layer 212 fills the trenches 204-1, 204-2, 204-3, 204-4, and 204-5, and completely covers the second liner 210 within the trenches 204-1, 204-2, 204-3, 204-4, and 204-5.

[0071] Next, multiple deposition and etching processes are performed to form word lines 230 and insulating capping layers 242 in the active region A1 and isolation components 206-3 of the array region 400.

[0072] Next, a deposition process, such as atomic layer deposition, is performed to form an insulating capping layer 213, for example, silicon nitride, over the substrate 200 and the insulating structures 206-1A, 206-2A, 206-4A and the isolation components 206-3, 206-5. In some embodiments, the first liner 208 and the fill layer 212 are formed of a first material (e.g., silicon oxide), and the second liner 210 and the insulating capping layer 213 are formed of a second material (e.g., silicon nitride) (therefore, there may be no interface between the second liner 210 and the insulating capping layer 213), and the first material is different from the second material.

[0073] Next, as Figure 3 As shown, a photolithography process is performed to form a photoresist pattern 270 on the top surface 200T of the substrate 200. The photoresist pattern 270 covers the array region 400 and the second peripheral region 404, exposing the insulating capping layer 213 of the first peripheral region 402. The exposed insulating capping layer 213 covers part of the insulating structures 206-1A and 206-2A of the sidewalls 204-1S2 and 204-2S1 of the adjacent trenches 204-1 and 204-2, as well as the insulating structure 206-4A in the first peripheral region 402.

[0074] Next, as Figure 4As shown, using the photoresist pattern 270 as an etching mask, an etching process (e.g., wet etching) is performed on the exposed insulating capping layer 213 to remove a portion of the insulating capping layer 213 in the first peripheral region 402. Since the insulating capping layer 213 and the second liner 210 are made of the same material, the above etching process can simultaneously remove a portion of the second liner 210 on the upper part of the sidewalls 204-1S2 and 204-2S1 of the insulating structures 206-1A and 206-2A near the trenches 204-1 and 204-2, and a portion of the second liner 210 on the upper part of the opposite sidewall of the insulating structure 206-4A near the trench 204-4. After the above etching process, an opening 274 is formed in the insulating capping layer 213 to expose the first peripheral region 402, and openings 276-1, 276-2, and 276-3 are formed in the insulating structures 206-1A, 206-2A, and 206-4A, so that the top surface 212T of the filling layer 212 of the insulating structures 206-1A, 206-2A, and 206-4A, as well as the upper part of the first liner 208 and the filling layer 212 near the sidewalls 204-1S2 and 204-2S1 of the trenches 204-1 and 204-2 and the upper part of the opposite sidewalls 204-4S1 and 204-4S2 of the trench 204-4, are exposed from the openings 276-1, 276-2, and 276-3. The photoresist pattern 270 can be removed during the above etching process.

[0075] Next, as Figure 5 As shown, a deposition process such as atomic layer deposition or sub-atmospheric chemical vapor deposition (SACVD) is performed to comprehensively form a third liner 211. The third liner 211 covers the array region 400 and the insulating capping layer 213 of the second peripheral region 404. Furthermore, the third liner 211 covers the active region A2 of the first peripheral region 402, the top surface 212T of the filling layer 212 of the insulating structures 206-1A, 206-2A, and 206-4A, and fills the openings 274, 276-1, 276-2, and 276-3 (…). Figure 4 ).

[0076] Next, as Figure 6 As shown, an etching process (e.g., dry etching or wet etching) is performed to remove the third substrate 211 above the substrate 200. After the etching process described above, the remaining third substrate 211 conformally covers the portion of the first substrate 208 exposed from the second substrate 210 of the insulating structures 206-1A, 206-2A, and 206-4A.

[0077] Next, as Figure 7 As shown, a photolithography process is performed to form a photoresist pattern 278 on the top surface 200T of the substrate 200. The photoresist pattern 278 covers the array region 400 and the first peripheral region 402, exposing the insulating capping layer 213 of the second peripheral region 404.

[0078] Next, as Figure 8 As shown, using photoresist pattern 278 as an etching mask, an etching process (e.g., wet etching) is performed on the exposed insulating capping layer 213 to remove a portion of the insulating capping layer 213 in the second peripheral region 404, exposing the top surface 212T of the filling layer 212 of the insulating structure 206-2A and the isolation member 206-5. The remaining insulating capping layer 213 covers the array region 400. The photoresist pattern 278 can be removed during the etching process described above. After the above process, isolation members 206-1, 206-2, and 206-4 are formed in trenches 204-1, 204-2, and 204-4.

[0079] Next, as Figure 9 As shown, the insulating capping layer 213 in the array region 400 is used as an etching mask to perform a back etching process (e.g., wet etching) to remove the first liner 208 on the top surface 200T of the substrate 200 in the first peripheral region 402 and the second peripheral region 404, thereby exposing the top surface 200T of the substrate 200 in the active regions A2 and A3.

[0080] Next, as Figure 1 As shown, deposition, photolithography, and etching processes are performed to form a first gate structure 424N and a second gate structure 424P on the substrates 200 in the first peripheral region 402 and the second peripheral region 404, respectively. Then, a multi-pass ion implantation process is performed to implant dopants of a second conductivity type (e.g., N-type) into the substrates 200 on opposite sides of adjacent first gate structures 424N to form multiple first source / drain regions 428N, and to implant dopants of a first conductivity type (e.g., P-type) into the substrates 200 on opposite sides of adjacent second gate structures 424P to form multiple second source and drain regions 428P. After the above processes, a first-type component 412N and a second-type component 412P are formed in the first peripheral region 402 and the second peripheral region 404. Furthermore, deposition processes and subsequent removal processes (including planarization processes (e.g., chemical mechanical polishing (CMP)), etch-back processes, or combinations thereof) can be performed to form contact plugs 248a, 248b, bit lines 250, and storage capacitors 260 in the array region 400. After the above processes, a semiconductor structure 500 is formed.

[0081] This invention provides a semiconductor structure and a method for forming the same. The semiconductor structure includes an array region, a first peripheral region, and a second peripheral region for forming a memory array (e.g., a DRAM array) and first-type components (e.g., N-type metal-oxide-semiconductor field-effect transistor components) and second-type components (e.g., P-type metal-oxide-semiconductor field-effect transistor components) of different conductivity types. In the first peripheral region adjacent to the semiconductor or in the isolation components located within the first peripheral region, a third liner, such as a silicon oxide layer, can replace a portion of the second liner, such as a silicon nitride layer, sandwiched between the first liner, such as a silicon oxide layer, and the fill layer. This ensures that the isolation components adjacent to the first peripheral region or located within the first peripheral region and close to the top surface of the substrate are formed of silicon oxide with compressive stress. This can apply tensile stress to the adjacent first peripheral region (e.g., the channel region of an N MOSFET) and improve electron mobility in the N MOSFET. When the size of the first-type component (e.g., an N MOSFET) in the first peripheral region is miniaturized, the voltage drop (Vt roll-off) can be suppressed. In addition, maintaining a silicon oxide-silicon nitride-silicon oxide composite structure in the first liner, second liner, and fill layer of the isolation component adjacent to the array region or the second peripheral region can maintain the stress in the array region and the second peripheral region, as well as the electrical properties (e.g., threshold voltage) of the memory array (e.g., DRAM array) and the second type of component (e.g., P MOSFET).

[0082] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art will be able to make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a first peripheral region; A first isolation member is disposed in a first trench of the substrate adjacent to the first peripheral region, wherein the first trench has a first sidewall adjacent to the first peripheral region, and wherein the first isolation member includes: A first liner that conformally covers the first sidewall of the first trench; A second liner, which conformally covers the first liner and covers the lower part of the first sidewall, such that a portion of the first liner is exposed from the second liner; A third liner, conformally covering the portion of the first liner exposed from the second liner; and A filler layer fills the first trench and covers the second and third lining layers; and A first type component is formed in the first peripheral region, wherein, in a direction substantially perpendicular to a top surface of the substrate, a first bottom surface of a first source-drain region of the first type component is located between the top surface of the substrate and a second bottom surface of the third liner.

2. The semiconductor structure as described in claim 1, characterized in that, The substrate has an array region or a second peripheral region adjacent to the first peripheral region, and the first trench has a second sidewall adjacent to the array region or the second peripheral region, wherein the first isolation member has: The first liner conformally covers the second sidewall of the first trench. The second liner extends from the lower portion of the first sidewall of the first trench and covers the second sidewall.

3. The semiconductor structure as described in claim 1, characterized in that, The first liner, the third liner, and the filler layer are formed of a first material, wherein the second liner is formed of a second material, and the first material is different from the second material.

4. The semiconductor structure as described in claim 3, characterized in that, The first material includes silicon oxide, and the second material includes silicon nitride.

5. The semiconductor structure as described in claim 1, characterized in that, The first bottom surface is at a first depth from the top surface of the substrate that is less than or equal to the second bottom surface at a second depth from the top surface of the substrate.

6. The semiconductor structure as described in claim 5, characterized in that, The first trench has a third bottom surface, and the second depth is less than or equal to a third depth of the third bottom surface from the top surface of the substrate.

7. The semiconductor structure as described in claim 6, characterized in that, The ratio of the second depth to the third depth ranges from 1.3:2 to 1.3:

7.

8. The semiconductor structure as described in claim 1, characterized in that, The first liner, the second liner, and the filler layer contact different surfaces of the third liner.

9. The semiconductor structure as described in claim 1, characterized in that, The filler layer contacts the second liner and the third liner on one side of the first sidewall of the first trench.

10. The semiconductor structure as described in claim 6, characterized in that, An interface between the second liner and the third liner is located between the top surface of the substrate and the third bottom surface of the first trench.

11. The semiconductor structure as described in claim 5, characterized in that, Including: A second isolation member is disposed in a second trench of the substrate within the first peripheral region, wherein the second trench has a third sidewall and a fourth sidewall that are opposite to each other. The first isolation component and the second isolation component each include the first liner, the second liner, the third liner, and the filler layer. The second isolation component includes: The first liner conformally covers the third and fourth sidewalls of the second trench. The second liner conformally covers a portion of the first liner and extends from a lower portion of the third sidewall of the second groove to cover a lower portion of the fourth sidewall, thereby exposing a portion of the first liner from the second liner. The third liner provides shape retention over the first liner exposed from the second liner, and The filler layer fills the second trench and covers the second liner and the third liner.

12. The semiconductor structure as claimed in claim 1, characterized in that, The first type of component further includes a first gate structure disposed on the substrate, wherein the first source and drain regions are adjacent to the first gate structure.

13. The semiconductor structure as described in claim 2, characterized in that, Including: A second type component is formed in the second peripheral region, wherein the first type component and the second type component have opposite conductivity types.

14. The semiconductor structure as described in claim 13, characterized in that, The first type of component has an N-type conductivity, and the second type of component has a P-type conductivity.

15. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate has a first peripheral region; A first trench is formed in the substrate adjacent to the first peripheral region, wherein the first trench has a first sidewall adjacent to the first peripheral region; A first isolation component is formed in the first trench, wherein the first isolation component includes: A first liner that conformally covers the first sidewall of the first trench; A second liner, which conformally covers the first liner and covers the lower part of the first sidewall, such that a portion of the first liner is exposed from the second liner; A third liner, conformally covering the portion of the first liner exposed from the second liner; and A filler layer fills the first trench and covers the second and third lining layers; and A first type component is formed in the first peripheral region, wherein a first bottom surface of a first source-drain region of the first type component is located between the top surface of the substrate and a second bottom surface of the third liner in a direction substantially perpendicular to a top surface of the substrate.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The substrate has an array region or a second peripheral region adjacent to the first peripheral region, and the first trench has a second sidewall adjacent to the array region or the second peripheral region, wherein the first isolation member has: The first liner conformally covers the second sidewall of the first trench. The second liner extends from the lower portion of the first sidewall of the first trench and covers the second sidewall.

17. The method for forming a semiconductor structure as described in claim 15, characterized in that, The first isolation component includes: A first insulating structure is formed in the first trench, wherein the first insulating structure includes the first liner, the second liner and the filler layer, wherein the second liner completely covers the first liner in the first trench; A first insulating capping layer is formed on the substrate and the first insulating structure; Remove a portion of the first insulating cap layer in the first peripheral area, and remove a portion of the second liner layer near the first sidewall from the top surface of the substrate to form a first opening in the first insulating structure, so that a top surface of the fill layer in the first insulating structure and an upper portion of a side surface near the first sidewall are exposed from the first opening; A third liner is formed comprehensively, wherein the third liner covers the filler layer and fills the first opening; and Remove the third liner above the substrate to form a first isolation member in the first trench.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, Including: During the formation of the first trench, a second trench is formed in the substrate within the first peripheral region, the second trench having a third sidewall and a fourth sidewall opposing each other; and During the formation of the first isolation member, a second isolation member is formed in the second trench, wherein forming the second isolation member includes: During the formation of the first insulating structure, a second insulating structure is formed in the second trench, wherein the first insulating structure and the second insulating structure each include the first liner, the second liner, and the filler layer, wherein removing a portion of the second liner includes: The second liner is removed from the top surface of the substrate, near the third and fourth sidewalls of the second trench, to form a plurality of second openings in the second insulating member, exposing a top surface of the filler layer in the second insulating structure and a plurality of upper portions near the third and fourth sidewalls from the plurality of second openings.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, After removing the third liner above the substrate, the second isolation member is formed in the second trench.

20. The method for forming a semiconductor structure as described in claim 15, characterized in that, The first type of component includes: A first gate structure is formed on the substrate; and The first source and drain regions are formed in the substrate adjacent to the first gate structure. The first source / drain region has a first bottom surface, the third liner has a second bottom surface close to the first bottom surface, and the first trench has a third bottom surface. Wherein, the first depth of the first bottom surface from the top surface of the substrate is less than or equal to the second depth of the second bottom surface from the top surface of the substrate. The second depth is less than or equal to a third depth from the third bottom surface to the top surface of the substrate.

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