A gallium oxide-based transistor with a low gate interface state structure and a preparation method thereof

Abstract

The application discloses a gallium oxide-based transistor with a low gate interface state structure and a preparation method thereof, and aims at solving the problems of high gate interface state, poor gate control ability and large parasitic parameters of the existing gallium oxide device. The transistor comprises, from bottom to top, a Fe-doped semi-insulating beta-Ga2O3 substrate, a beta-Ga2O3 UID blocking layer, a beta-Ga2O3 channel layer with a fin array structure, a fin type space, an air bridge, a gate, a source and a drain. The free space gate adopts a hollow structure to replace the traditional solid gate dielectric, eliminates the interface state of the dielectric and the semiconductor, and improves the gate control and reliability of the device. The air bridge is in an arch shape and is suspended over the free space gate area, the bridge body is in contact with the gate at the top of each fin and forms a stable electrical connection. The application significantly optimizes the gate control and working performance of the device, and can be used for manufacturing a gallium oxide MOSFET device with high frequency and high power characteristics.

Description

Technical Field

[0001] This invention belongs to the field of electrical component technology, and further relates to a gallium oxide-based transistor with a low gate interface state structure and its fabrication method in the field of power semiconductor device technology. This invention combines a free-space gate structure, a multi-FIN parallel current-boosting design, and an air-bridge interconnect structure to create a gallium oxide-based transistor and its fabrication method, effectively solving the technical problems of high interface state density in traditional gallium oxide transistors and low current density in traditional FinFET devices. It can be used to fabricate metal-oxide-semiconductor field-effect transistors (MOSFETs) with medium- and high-voltage power switching characteristics. Background Technology

[0002] β-Ga₂O₃, as an ultra-wide bandgap semiconductor material, possesses a breakdown field strength as high as 8 MV / cm, showing significant potential in medium- and high-voltage power electronics applications. Gallium oxide-based FinFET devices have become a research hotspot due to their superior gate control capabilities, which can effectively improve device breakdown voltage. However, existing gallium oxide-based FinFET devices still face challenges in practical applications, including high gate interface states, low current density, and a power figure of merit (PFOM) that falls far short of the theoretical limit.

[0003] The Institute of Microelectronics, Chinese Academy of Sciences, disclosed a fin field-effect transistor and its fabrication method in its patent application "A Fin Field-Effect Transistor and Its Fabrication Method" (application number 201610663545.x, publication number CN 106206318 A). When fabricating a FinFET device using this method, a silicon fin and an isolation portion are first formed. Then, the silicon fin is etched in situ to reserve space for the formation of silicon-germanium (SGF) and germanium (G) fins. Finally, the SGF and GGF fins are formed sequentially through epitaxial growth. Because the SGF acts as a strain buffer between the silicon substrate and the GGF fin, it reduces the lattice mismatch between germanium and silicon, thus establishing the preconditions for the formation of the GGF fin. This avoids the situation where germanium material is directly filled into the small gaps between the isolation portions, resulting in insufficient filling of the gaps and morphological defects in the GGF fin, which would lead to a decrease in the reliability of the FinFET device. However, the shortcomings of this preparation method are that it mainly makes local improvements to the problems of material lattice mismatch and reliability, and is still based on traditional solid gate dielectric coverage. It does not fundamentally change the modulation mechanism of the gate to the channel. Its gate-channel structure is still limited by interface states, making it difficult to completely solve key problems such as unstable threshold voltage and high on-resistance.

[0004] The Institute of Microelectronics, Chinese Academy of Sciences, disclosed a semiconductor device and its manufacturing method with high driving capability and steep subthreshold swing characteristics in its patent application "Semiconductor Device with High Driving Capability and Steep Subthreshold Swing Characteristics and Manufacturing Method" (Application No. 202210131205.8, Publication No. CN 114566549 A). The semiconductor device includes: a substrate; a channel portion comprising: a first portion of a fin-like structure protruding relative to the substrate and a second portion above and spaced apart from the first portion, comprising one or more spaced-apart nanowires and nanosheets; source / drain portions disposed on opposite sides of the channel portion in a first direction and connected to the channel portion; and a gate stack extending on the substrate in a second direction intersecting the first direction to intersect the channel portion. This device emphasizes improving driving capability and obtaining a steeper subthreshold swing characteristic, enhancing switching performance through specific structural design and fabrication processes. However, the patent still has shortcomings. It still belongs to the traditional gate control structure system. The control of the gate still depends on the modulation of channel carriers by the solid gate dielectric layer. The influence of interface trap states on performance has not been completely eliminated. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of the prior art by providing a gallium oxide-based transistor with low gate interface states and its fabrication method. This aims to solve the following core problems existing in current gallium oxide-based power transistors: First, the high interface states introduced by traditional solid gate dielectrics lead to deterioration of device gate control performance, threshold voltage drift, and decreased long-term reliability; second, the high parasitic capacitance and resistance of traditional multi-fin structures restrict the improvement of high-frequency characteristics and high-power output capabilities; third, the existing fin-type parallel air bridge process parameters are unstable, the structure is prone to collapse and failure, and there is a contradiction between process temperature and production efficiency, making it difficult to adapt to the needs of large-scale mass production.

[0006] The technical approach to achieving the objective of this invention is as follows:

[0007] First, in response to the defect of high interface states introduced by traditional solid gate dielectrics, this invention adopts a dielectric-free free space gate structure to replace the traditional solid gate dielectric. This structure eliminates the generation path of interface states between the gate dielectric and the semiconductor, and solves problems such as gate control degradation and threshold voltage drift caused by interface states. Thus, it overcomes the defects of high gate interface states and poor gate control stability in the prior art.

[0008] Secondly, to address the performance limitations caused by the high parasitic parameters of multi-fin structures, this invention adopts a design scheme of an arched metal air bridge and a multi-fin parallel channel. The parasitic capacitance of the arched air bridge is lower than that of the traditional dielectric bridge, and the interconnect parasitic resistance can be reduced by electroplating a thick metal layer. This optimizes the parasitic parameters of the device from both capacitance and resistance dimensions. Combined with the characteristic of increasing current through multi-fin parallel connection, this effectively improves the device's cutoff frequency, maximum oscillation frequency, and output power density, overcoming the performance deficiencies caused by the high parasitic parameters of existing technologies.

[0009] Third, addressing the shortcomings of existing fin-type parallel air bridge structures, such as easy collapse and failure, and unstable process parameters, this invention employs a precise photolithography shaping and electroplating molding process to fabricate an arched metal air bridge. By precisely controlling the exposure focal length, baking temperature, and time, an arched structure with regular morphology and excellent mechanical properties is formed. This structure can decompose external forces into circumferential support forces for the bridge body, significantly improving its resistance to collapse and deformation. At the same time, the optimized medium-temperature short-time baking shaping scheme avoids electrical damage caused by high-temperature baking and eliminates the need for long-term low-temperature treatment, greatly shortening the process time and ensuring compatibility with existing production line processes. This overcomes the shortcomings of existing technologies in fabricating fin-type parallel air bridges, such as easy failure and poor process adaptability.

[0010] The gallium oxide-based transistor of the present invention comprises, from bottom to top, an Fe-doped semi-insulating β-Ga2O3 substrate, a β-Ga2O3 UID barrier layer, and a β-Ga2O3 channel layer with a fin array structure; the fin space is located on both sides of the fins and in the gap between the fins of the β-Ga2O3 channel layer, and is a trench structure without a gate dielectric layer, filled with air, nitrogen or vacuum to replace the traditional solid gate dielectric to eliminate the interface state between the gate dielectric and the semiconductor; the gate electrode is disposed on the top of the fins of the β-Ga2O3 channel layer, forming a corresponding independent gate control unit, responsible for the gate voltage control of a single fin channel; the air bridge is arched and suspended above the fin space, and the bottom of the air bridge is in contact with the gate on the top of each fin. A stable electrical connection is formed, interconnecting all independent gate control units into one, realizing synchronous gate control of the entire fin array. At the same time, air is used as the inter-bridge medium to significantly reduce the parasitic capacitance of the device. The source and drain are respectively located at both ends of the fin array of the β-Ga2O3 channel layer, forming good ohmic contact with the channel layer material. By designing a dielectric-free free space gate structure and an air bridge structure that interconnects the independent free space gate units, the influence of the gate interface state is eliminated while ensuring the gate control performance of the device, reducing the parasitic parameters of the device, and improving the gate control stability and high-frequency high-power performance of the device.

[0011] Furthermore, the Fe-doped semi-insulating β-Ga2O3 substrate can have any known crystal orientation such as (010), (100), (001), etc., and the thickness of the substrate is 500 nm to 1.5 μm.

[0012] Furthermore, the β-Ga2O3 UID barrier layer has the same shape as the β-Ga2O3 substrate, a thickness of 100 nm to 300 nm, and a carrier concentration ≤ 1 × 10⁻⁶. 16 cm -3 .

[0013] Furthermore, the β-Ga2O3 channel layer is formed by dry etching of Si-doped β-Ga2O3 above the barrier layer to create a fin array. Each fin has the same size, is an elongated protrusion along the gate width, has a thickness of 200 nm to 500 nm, and a carrier concentration of 1 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 The fins have a depth-to-width ratio of 3:1 to 6:1, a width of 50 nm to 90 nm, and a spacing of 80 nm to 150 nm between adjacent fins.

[0014] Furthermore, the gate is a Ni / Au metal stack from bottom to top, with thicknesses of 30~50 nm / 300~400 nm, respectively; the source and drain are Ti / Al / Ni / Au metal stacks from bottom to top, with thicknesses of 20 nm / 100 nm / 30 nm / 400 nm, respectively.

[0015] Furthermore, the fin-like space is laterally distributed in the gaps between adjacent fins in the channel layer and on the sidewalls on both sides of the fin array, forming a continuous and hollow groove structure without any solid gate dielectric filling inside.

[0016] Furthermore, the support ends at both ends of the air bridge are respectively fixed to the top of each fin of the channel layer, forming a regular arch that spans directly above the fin space, with the lower surface of the air bridge opposite to the hollow area of ​​the fin space.

[0017] The steps of the method for fabricating gallium oxide-based transistors of the present invention include the following:

[0018] Step 1, Substrate pretreatment:

[0019] Fe-doped semi-insulating β-Ga2O3 substrate was selected. After cleaning with HF acid and organic solvent to remove the surface oxide layer and organic impurities, it was rinsed with deionized water and dried with nitrogen.

[0020] Step 2, epitaxial layer growth:

[0021] A β-Ga2O3 UID barrier layer and a Si-doped β-Ga2O3 channel layer are epitaxially grown sequentially on the substrate.

[0022] Step 3, etching of the multi-fin structure:

[0023] A mask is formed by photolithography, and the channel layer is etched to the surface of the barrier layer by ICP etching process. The ICP etching process uses Cl2 / BCl3 mixed gas with a volume ratio of 3:1 to form the free space region between the multi-fin structure and the fins. After resist removal and cleaning, the free space gate region is kept free of impurities.

[0024] Step 4, Gate fabrication:

[0025] Photolithography is used to form a photoresist mask on the top of each fin of the multi-fin structure. Ni / Au metal stack is deposited by electron beam evaporation and then the gate is formed after a lift-off process.

[0026] Step 5, Fabrication of the arched photoresist bridge:

[0027] Positive photoresist is spin-coated onto the surface of the multi-fin structure and free space gate region. After photolithography, a photoresist baking process is performed to make the photoresist expand and ellipse uniformly under heat, forming a regular arched photoresist bridge.

[0028] Step 6, Fabrication of the arched metal air bridge:

[0029] A Ti / Au metal stack is deposited on the surface of the arched shaping bridge as an electroplating seed layer. After the electroplating area is defined by photolithography, an Au layer is deposited by electroplating process to form an arched metal air bridge that is completely consistent with the morphology of the photoresist bridge.

[0030] Step 7, Source / Drain Electrode Fabrication:

[0031] A photoresist mask is formed by photolithography, and a metal stack is deposited by electron beam evaporation and rapidly annealed at a temperature of 480~600℃ for 30~60 s under a nitrogen atmosphere; source and drain electrodes are fabricated at both ends of the channel layer.

[0032] Step 8, Device post-processing:

[0033] After cleaning the sample with argon plasma, the interconnection and extraction of each electrode were completed, and the device was fabricated after drying with nitrogen.

[0034] Furthermore, the spin-coating thickness of the positive photoresist is 3.7 μm, the exposure focal length is controlled at 0 μm during the photolithography process, and the baking parameters are 145℃ and 120 s.

[0035] Furthermore, the thickness of the Ti layer in the electroplated seed layer is 20 nm to 30 nm, and the thickness of the Au layer is 50 nm to 100 nm; the thickness of the electroplated Au layer is controlled to be 300 nm to 500 nm.

[0036] Compared with the prior art, the present invention has the following advantages:

[0037] First, this invention employs a dielectric-free free-space gate structure, replacing the traditional high-dielectric-constant solid gate dielectric with a low-dielectric-constant dielectric such as air. This eliminates the drawbacks of threshold voltage drift, increased gate leakage current, and gate control performance degradation caused by interface states between the gate dielectric and the semiconductor. Therefore, this invention effectively eliminates the influence of gate interface states, improving gate control stability and device reliability.

[0038] Secondly, this invention designs a multi-fin gate structure connected in parallel via metal air bridges. The parasitic capacitance of the air bridges is lower than that of traditional dielectric bridges, and the thick metal plating layer reduces parasitic resistance, overcoming the problem of poor high-frequency performance caused by high parasitic parameters in traditional multi-fin devices. This allows the multi-fin parallel structure of this invention to increase current, reduce parasitic parameters, and significantly optimize the device's high-frequency and high-power output capabilities. Furthermore, the low-parasitic air bridge interconnect process effectively improves the device's cutoff frequency, maximum oscillation frequency, and output power density, making it suitable for high-frequency and high-power applications.

[0039] Third, this invention employs a precise photolithography and electroplating process to fabricate an arched metal air bridge, resulting in a well-formed arched structure with stable bridging parameters. This structure decomposes external forces into circumferential supporting forces, exhibiting excellent resistance to collapse and deformation under high temperatures and complex conditions. This overcomes the problems of easy failure and unstable process parameters inherent in traditional air bridge structures. Furthermore, the use of a medium-temperature, short-time baking and setting scheme avoids electrical damage caused by high temperatures and shortens the process time, ensuring compatibility with existing production line processes and meeting the requirements for industrial application. The air bridge structure exhibits excellent mechanical properties, strong process compatibility, and high adaptability. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the gallium oxide-based transistor of the present invention;

[0041] Figure 2 This is a side view schematic diagram of the structure of the gallium oxide-based transistor of the present invention;

[0042] Figure 3 This is a flowchart illustrating the fabrication process of the gallium oxide-based transistor of this invention; Detailed Implementation

[0043] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0044] Reference Figure 1 The structure of the gallium oxide-based transistor in the embodiments of the present invention will be described in detail.

[0045] The device structure of this invention includes an Fe-doped semi-insulating β-Ga₂O₃ substrate 1, a β-Ga₂O₃ UID barrier layer 2, a β-Ga₂O₃ channel layer 3, a gate 4, a finned space 5, a source 6, a drain 7, and an air bridge 8. Wherein:

[0046] The Fe-doped semi-insulating β-Ga2O3 substrate 1 has a crystal phase that can be any known crystal orientation such as (010), (100), (001), and has a thickness of 500 nm to 1.5 μm.

[0047] The β-Ga2O3UID barrier layer 2 has a thickness of 100 nm to 300 nm and a carrier concentration of ≤1×10⁻⁶. 16 cm -3 It is located on Fe-doped semi-insulating β-Ga2O3 substrate 1.

[0048] The β-Ga2O3 channel layer 3 is formed by etching Si-doped β-Ga2O3 above the β-Ga2O3 UID barrier layer 2, with a thickness of 200 nm to 500 nm and a carrier concentration of 1 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 The fin depth-to-width ratio is 3:1 to 6:1, the width of a single fin is 50 nm to 90 nm, and the distance between adjacent fins is 80 nm to 150 nm.

[0049] The gate 4 is a Ni / Au metal stack and is located above the β-Ga2O3 channel layer 3.

[0050] The fin-shaped space 5 is located on both sides and above the channel layer 3, and has a trench structure with a trench width of 80 nm to 150 nm; for details, please refer to Figure 2 It can clearly present the groove morphology, spatial arrangement and internal structural details of the free space grid region.

[0051] The source 6 and drain 7 are both made of Ti / Al / Ni / Au metal stack and are located in the ohmic regions at both ends of the channel layer 3.

[0052] The air bridge 8, made of Ni / Au metal stack, is located above the free space gate region and spans the multi-fin array in a bridge shape.

[0053] Reference Figure 3 The present invention provides a detailed description of three embodiments of the gallium oxide-based transistor fabrication method.

[0054] Example 1: Fabrication of a low-gate-interface-state gallium oxide-based transistor with a fin aspect ratio of 3:1, a fin width of 50 nm, a fin pitch of 80 nm, and a free-space gate trench width of 80 nm. Specific steps are as follows:

[0055] Step 1: Select a Fe-doped semi-insulating β-Ga2O3 substrate with a crystal phase of (010) and a thickness of 500 nm to 1.5 μm. Clean it sequentially with HF acid, acetone and ethanol using ultrasonic cleaning, rinse it with deionized water and dry it with nitrogen.

[0056] Step 2: An 100 nm to 300 nm β-Ga₂O₃UID barrier layer is epitaxially grown on the substrate using MOCVD technology, with a carrier concentration ≤1×10⁻⁶. 16 cm -3 Subsequently, a 200 nm to 500 nm Si-doped β-Ga₂O₃ channel layer was epitaxially grown, with a Si doping concentration of 1 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 .

[0057] Step 3: Electron beam lithography is used to form a multi-fin pattern mask with a single fin width of 50 nm and a spacing of 80 nm. The channel layer is etched using ICP etching with a Cl2 / BCl3 volume ratio of 3:1. The upper and lower electrode powers are 300 W and 50 W, respectively, and the pressure is 10 mTorr. The etching depth is the same as the channel layer thickness, forming a multi-fin array with a depth-to-width ratio of 3:1. The mask is removed by ultrasonic acetone and then cleaned and dried.

[0058] Step 4: Spin-coat photoresist onto the surface, obtain an air bridge pattern by electron beam lithography, and then perform a photoresist baking process to make the photoresist expand and ellipse uniformly under heat, forming a smooth arched photoresist bridge.

[0059] Step 5: Deposit a Ti / Au metal stack using electron beam evaporation as a seed layer for electroplating. Use electron beam lithography to lithographically determine the areas to be electroplated, retaining only the air bridge body and interconnect lead-out areas. Then, deposit an Au layer using electroplating to form a bridge structure, ensuring that its morphology is completely aligned with the photoresist bridge.

[0060] Step 6: On the surface of the electroplated arched bridge, an electron beam evaporation deposition of Ni / Au metal stack is performed. After photolithography and lift-off processes, an air bridge structure is formed that interconnects the gate arms on both sides and the top gate.

[0061] Step 7: Photolithography is used to form a photoresist mask, electron beam evaporation is used to evaporate the Ti / Al / Ni / Au metal stack, and then a lift-off process is used to form the source and drain electrodes. Finally, a rapid annealing furnace is used to anneal the electrodes to form ohmic contacts.

[0062] Step 8: The sample is washed sequentially with acetone, ethanol, and deionized water, dried with nitrogen, and then subjected to plasma cleaning to complete the interconnection and lead-out of each electrode, thus completing the device fabrication.

[0063] Example 2: Fabrication of a low-gate-interface-state gallium oxide-based transistor with a fin aspect ratio of 4:1, a fin width of 70 nm, a fin pitch of 120 nm, and a free-space gate trench width of 100 nm. Specific steps are as follows:

[0064] Step A: Select an Fe-doped semi-insulating β-Ga2O3 substrate with a crystal phase of (010) and a thickness of 500 nm to 1.5 μm. The cleaning process is the same as in Example 1.

[0065] Step B involves epitaxially growing a 100 nm–300 nm β-Ga₂O₃UID barrier layer on top of the substrate using MOCVD technology, with a carrier concentration ≤1 × 10⁻⁶. 16 cm -3 Subsequently, a 200 nm to 500 nm Si-doped β-Ga₂O₃ channel layer was epitaxially grown, with a Si doping concentration of 1 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 .

[0066] Step C: Electron beam lithography is used to form a multi-fin pattern mask with a single fin width of 70 nm and a spacing of 120 nm. The channel layer is etched using ICP etching with a Cl2 / BCl3 volume ratio of 3:1. The upper and lower electrode powers are 320 W and 60 W, respectively, and the pressure is 12 mTorr. The etching depth is the same as the channel layer thickness, forming a multi-fin array with a depth-to-width ratio of 4:1. After removing the mask with acetone, the mask is cleaned and dried.

[0067] Step D involves spin-coating photoresist onto the surface, obtaining an air bridge pattern via electron beam lithography, and then performing a photoresist baking process to heat the photoresist to uniformly expand and ellipse, forming a smooth, arched photoresist bridge.

[0068] Step E: A Ti / Au metal stack is deposited using electron beam evaporation as a seed layer for electroplating. The area to be electroplated is lithographically etched using electron beam lithography, retaining only the air bridge body and interconnect lead-out area. An Au layer is deposited using electroplating to form a bridge structure, so that its morphology is completely aligned with the photoresist bridge.

[0069] Step F: On the surface of the electroplated arched bridge, an electron beam evaporation deposition of a Ni / Au metal stack is performed. After photolithography and lift-off processes, an air bridge structure is formed that interconnects the two side gate arms and the top gate.

[0070] Step G involves photolithography to form a photoresist mask, electron beam evaporation of a Ti / Al / Ni / Au metal stack, followed by a lift-off process to form source and drain electrodes, and finally annealing in a rapid annealing furnace to form ohmic contacts.

[0071] In step H, the sample is washed sequentially with acetone, ethanol, and deionized water, dried with nitrogen, and then subjected to plasma cleaning to complete the interconnection and lead-out of each electrode, thus completing the device fabrication.

[0072] Example 3: Fabrication of a low-gate-interface-state gallium oxide-based transistor with a fin aspect ratio of 6:1, a fin width of 90 nm, a fin pitch of 150 nm, and a free-space gate trench width of 150 nm. Specific steps are as follows:

[0073] Step 1: Select an Fe-doped semi-insulating β-Ga2O3 substrate with a crystal phase of (010) and a thickness of 500 nm to 1.5 μm. The cleaning process is the same as in Example 1.

[0074] Step 2: An 100 nm to 300 nm β-Ga₂O₃UID barrier layer is epitaxially grown on the substrate using MOCVD technology, with a carrier concentration ≤1×10⁻⁶. 16 cm -3 Subsequently, a 200 nm to 500 nm Si-doped β-Ga₂O₃ channel layer was epitaxially grown, with a Si doping concentration of 1 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 .

[0075] Step 3: Electron beam lithography is used to form a multi-fin pattern mask with a single fin width of 90 nm and a spacing of 150 nm. The channel layer is etched using ICP etching with a Cl2 / BCl3 volume ratio of 3:1. The upper and lower electrode powers are 350 W and 80 W, respectively, and the pressure is 15 mTorr. The etching depth is the same as the channel layer thickness, forming a multi-fin array with an aspect ratio of 6:1. After removing the mask with acetone, the mask is cleaned and dried.

[0076] Step four: spin-coat photoresist on the surface, obtain the air bridge pattern by electron beam lithography, and then perform a photoresist baking process to make the photoresist expand and ellipse evenly under heat, forming a smooth arched photoresist bridge.

[0077] Step 5: Deposit a Ti / Au metal stack using electron beam evaporation as a seed layer for electroplating. Use electron beam lithography to lithographically determine the areas to be electroplated, retaining only the air bridge body and interconnect lead-out areas. Then, deposit an Au layer using electroplating to form a bridge structure, ensuring that its morphology is completely aligned with the photoresist bridge.

[0078] Step 6: On the surface of the electroplated arched bridge, an electron beam evaporation deposition of Ni / Au metal stack is performed. After photolithography and lift-off processes, an air bridge structure is formed that interconnects the gate arms on both sides and the top gate.

[0079] Step 7: Photolithography is used to form a photoresist mask, electron beam evaporation is used to evaporate the Ti / Al / Ni / Au metal stack, and then a lift-off process is used to form the source and drain electrodes. Finally, a rapid annealing furnace is used to anneal the electrodes to form ohmic contacts.

[0080] Step 8: The sample is washed sequentially with acetone, ethanol, and deionized water, dried with nitrogen, and then subjected to plasma cleaning to complete the interconnection and lead-out of each electrode, thus completing the device fabrication.

[0081] The above descriptions are merely three specific embodiments of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, can make various modifications and changes in form and detail without departing from the principles and structure of the present invention. For example, the number of fins can be adjusted within a certain range according to current requirements; the free space gate region can be filled with other inert gases; the air bridge support layer material can be replaced with other highly insulating and mechanically strong dielectrics; the metal stack of the source / drain electrodes and the gate can be adjusted to other reasonable combinations according to process compatibility. However, these modifications and changes based on the concept of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A gallium oxide-based transistor with a low gate interface state structure, characterized in that, From bottom to top: Fe-doped semi-insulating β-Ga2O3 substrate (1), β-Ga2O3 UID The barrier layer (2) and the β-Ga2O3 channel layer (3) of the fin array structure are arranged in a barrier layer (2). The fin space (5) is located on both sides of the fins and between the fins of the β-Ga2O3 channel layer (3). It is a trench structure without a gate dielectric layer and is filled with air, nitrogen or vacuum. The gate electrode (4) is located on the top of the fins of the β-Ga2O3 channel layer (3) to form a corresponding independent gate control unit, which is responsible for the gate voltage regulation of the single fin channel. The air bridge (8) is suspended in an arch shape above the fin space (5). The bottom of the air bridge (8) is in contact with the gate (4) on the top of each fin and forms a stable electrical connection, interconnecting all independent gate control units into one, realizing synchronous gate control of the entire fin array, and at the same time, using air as the inter-bridge medium greatly reduces the parasitic capacitance of the device. The source (6) and drain (7) are located at both ends of the fin array of the β-Ga2O3 channel layer (3) and form a good ohmic contact with the channel layer material.

2. The gallium oxide-based transistor with a low gate interface state structure according to claim 1, characterized in that, The Fe-doped semi-insulating β-Ga2O3 substrate (1) can have any known crystal orientation such as (010), (100), (001), etc., and the thickness of the substrate (1) is 500 nm to 1.5 μm.

3. The gallium oxide-based transistor with a low gate interface state structure according to claim 1, characterized in that, The β-Ga2O3 UID barrier layer (2) has the same shape as the β-Ga2O3 substrate (1), a thickness of 100 nm to 300 nm, and a carrier concentration ≤ 1 × 10⁻⁶. 16 cm -3 .

4. The gallium oxide-based transistor with a low gate interface state structure according to claim 1, characterized in that, The β-Ga2O3 channel layer (3) is formed by dry etching of Si-doped β-Ga2O3 above the barrier layer (2) to form a fin array. Each fin has the same size, is a long strip protrusion along the gate width, and has a thickness of 200 nm to 500 nm. The carrier concentration is 1 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 The fins have a depth-to-width ratio of 3:1 to 6:1, a width of 50 nm to 90 nm, and a spacing of 80 nm to 150 nm between adjacent fins.

5. The low gate interface state gallium oxide-based transistor according to claim 1, characterized in that, The gate (4) is a Ni / Au metal stack from bottom to top with thicknesses of 30~50 nm / 300~400 nm respectively; the source (6) and drain (7) are Ti / Al / Ni / Au metal stacks from bottom to top with thicknesses of 20 nm / 100 nm / 30 nm / 400 nm respectively.

6. The low gate interface state gallium oxide-based transistor according to claim 1, characterized in that, The fin space (5) is laterally distributed in the gap between adjacent fins of the channel layer (3) and on the sidewalls on both sides of the fin array, forming a continuous and hollow groove structure without any solid grid medium filling inside.

7. The low-gate-interface-state gallium oxide-based transistor according to claim 1, characterized in that, The support ends of the air bridge (8) are fixed to the top of each fin of the channel layer (3) respectively, and are suspended in a regular arch shape directly above the fin space (5). The lower surface of the air bridge is opposite to the hollow area of ​​the fin space (5).

8. A method for fabricating a gallium oxide-based transistor with a low gate interface state structure according to claim 1, characterized in that, The preparation method includes the following steps: Step 1, Substrate pretreatment: Fe-doped semi-insulating β-Ga2O3 substrate (1) was selected. After cleaning with HF acid and organic solvent to remove the surface oxide layer and organic impurities, it was rinsed with deionized water and dried with nitrogen. Step 2, epitaxial layer growth: A β-Ga2O3 UID barrier layer (2) and a Si-doped β-Ga2O3 channel layer (3) are epitaxially grown sequentially on a substrate (1). Step 3, etching of the multi-fin structure: A mask is formed by photolithography, and the channel layer (3) is etched to the surface of the barrier layer by ICP etching process. The ICP etching process uses Cl2 / BCl3 mixed gas with a volume ratio of 3:1 to form a free space region between the multi-fin structure and the fins. After removing the resist and cleaning, the free space gate region is kept free of impurities. Step 4, Gate fabrication: Photoresist masks are formed on the top of each fin of the multi-fin structure by photolithography, Ni / Au metal stacks are deposited by electron beam evaporation, and gates are formed after a stripping process (4). Step 5, Fabrication of the arched photoresist bridge: Positive photoresist is spin-coated onto the surface of the multi-fin structure and free space gate region. After photolithography, a photoresist baking process is performed to make the photoresist expand and ellipse uniformly under heat, forming a regular arched photoresist bridge. Step 6, Fabrication of the arched metal air bridge: A Ti / Au metal stack was deposited on the surface of the arch-shaped bridge as an electroplating seed layer. After the electroplating area was defined by photolithography, an Au layer was deposited by electroplating process to form an arch-shaped metal air bridge that is completely consistent with the morphology of the photoresist bridge (8). Step 7, Source / Drain Electrode Fabrication: Photoresist mask is formed by photolithography, metal stack is deposited by electron beam evaporation and rapidly annealed at a temperature of 480~600℃ for 30~60 s under a nitrogen atmosphere; source (6) and drain (7) are prepared at both ends of the channel layer. Step 8, Device post-processing: After cleaning the sample with argon plasma, the interconnection and extraction of each electrode were completed, and the device was fabricated after drying with nitrogen.

9. The preparation method according to claim 6, characterized in that, In step 5, the spin coating thickness of the positive photoresist is 3.7 μm, the exposure focal length is controlled to be 0 μm during the photolithography process, and the baking parameters are 145℃ and 120 s.

10. The preparation method according to claim 6, characterized in that, In step 6, the thickness of the Ti layer of the electroplated seed layer is 20 nm to 30 nm, and the thickness of the Au layer is 50 nm to 100 nm; the thickness of the electroplated Au layer is controlled to be 300 nm to 500 nm.

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