Transistor structure and method of manufacturing the same

Abstract

The application provides a transistor structure and a preparation method thereof, relates to the technical field of semiconductors, and aims to improve the on performance of a transistor. The transistor structure comprises a substrate and a shallow trench isolation structure. The substrate comprises a containing groove, a first active region and a second active region. The containing groove is located on opposite sides of the first active region and the second active region. The opposite sides of the first active region comprise a step structure. The shallow trench isolation structure is at least partially arranged in the containing groove and is at least located on the opposite sides of the first active region and the opposite sides of the second active region. One side of the shallow trench isolation structure close to the first active region has a recess, and the recess exposes the step structure of the first active region. One side of the shallow trench isolation structure close to the second active region has a protrusion. The transistor structure is applied to a chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a transistor structure and its fabrication method. Background Technology

[0002] As process nodes shrink, strained silicon (SSi) technology has been widely used in semiconductor transistors. SSi technology improves the carrier mobility in the transistor channel by “tuning” silicon energy, thereby increasing the device’s on-state current.

[0003] The Dual Stress Liner (DSL) technique improves channel carrier mobility by depositing a tensile stress film on the surface of an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) to introduce tensile stress in its channel and depositing a compressive stress film on the surface of a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) to introduce compressive stress in its channel.

[0004] However, the process of simultaneously depositing tensile stress films and compressive stress films on the same silicon wafer is quite complex. Therefore, how to introduce tensile stress and compressive stress into NMOSFETs and PMOSFETs respectively to improve carrier mobility has become an urgent problem to be solved in the field. Summary of the Invention

[0005] This application proposes a transistor structure and its fabrication method, aiming to improve carrier mobility and enhance the transistor's conduction performance.

[0006] To achieve the above objectives, embodiments of this application provide the following technical solutions: On one hand, a transistor structure is provided, the transistor structure including a substrate, a shallow trench isolation structure, a first gate, and a second gate. The substrate includes a first surface and a second surface opposite to each other, and the substrate further includes a first active region, a second active region, and a receiving trench disposed on the first surface. Along a first direction parallel to the first surface, the receiving trench is located on opposite sides of the first active region and opposite sides of the second active region; along the first direction, the opposite sides of the first active region include a stepped structure.

[0007] The shallow trench isolation structure is at least partially disposed within the receiving groove, and is located at least on opposite sides of the first active region along the first direction, and at least on opposite sides of the second active region along the first direction. The shallow trench isolation structure has a recess on the side near the first active region, the recess exposing the stepped structure of the first active region. The shallow trench isolation structure also has a protrusion on the side near the second active region, the protrusion being located on the side of the first surface away from the second surface. A first gate is disposed on the first active region, the first direction being the width direction of the first gate, and a second gate is disposed on the second active region.

[0008] In the above embodiments of this application, by setting stepped structures on opposite sides of the first active region and forming recesses in the shallow trench isolation structures on opposite sides of the first active region, the recesses expose the stepped structures of the first active region. During the fabrication process, only a tensile stress layer can be formed, which covers the first active region and its stepped structures. It can be understood that the stepped structures are located on opposite sides of the first active region along the first direction. During the process, the tensile stress layer covering the stepped structures is equivalent to covering the sides of the first active region. In the high-temperature annealing process, the tensile stress layer restricts the first active region from expanding outward along the first direction, thereby generating compressive stress on the first active region. Furthermore, the stepped structures can achieve stress concentration in local areas, which can amplify the compressive stress on the first active region, which is beneficial to improving the carrier mobility of the channel in the first active region and increasing the conduction current of the transistor.

[0009] Furthermore, the shallow trench isolation structure has a protrusion on the side near the second active region. The tensile stress layer also covers the second active region and the protrusion of the shallow trench isolation structure. The tensile stress layer generates tensile stress in the second active region along the first direction. Moreover, the protrusion can achieve stress concentration in a local area, which can amplify the tensile stress on the second active region. This is beneficial to improving the carrier mobility of the channel in the second active region and increasing the conduction current of the transistor.

[0010] In some embodiments, along the first direction, the opposite sides of the first active region are a source region and a drain region, respectively, and the step structures on the opposite sides of the first active region are a first step structure and a second step structure, respectively. The source region includes the first step structure, and the drain region includes the second step structure. Along the direction perpendicular to the first surface, the source region includes a first interface and a second interface, and the first step structure is located between the first interface and the second interface, that is, the first step structure is formed in the source region, and the first step structure can achieve stress concentration in the source region. Along the direction perpendicular to the first surface, the drain region includes a third interface and a fourth interface, and the second step structure is located between the third interface and the fourth interface, that is, the second step structure is formed in the drain region, and the second step structure can achieve stress concentration in the drain region, thereby amplifying the compressive stress of the tensile stress layer on the source region and the drain region, as well as the compressive stress on the channel region located between the source region and the drain region, further improving the carrier mobility of the channel in the first active region and increasing the conduction current of the transistor.

[0011] In some embodiments, the second interface is located on the side of the first interface near the second surface, and the fourth interface is located on the side of the third interface near the second surface. The recess of the shallow trench isolation structure includes a bottom surface near the second surface. The bottom surface of the recess is on the same plane as the second interface, or the bottom surface of the recess is located on the side of the second interface near the second surface. That is, the bottom surface of the recess is set to have the same depth as the second interface, or the bottom surface of the recess is set to be deeper than the second interface, so as to ensure that the recess can completely expose the side of the source region, thereby ensuring that the tensile stress layer can completely cover the side of the source region and the first step structure, which is beneficial to improving the compressive stress generated by the tensile stress layer on the source region.

[0012] And / or, the bottom surface of the recess is on the same plane as the fourth interface, or the bottom surface of the recess is located on the side of the fourth interface closer to the second surface, that is, the bottom surface of the recess is set to have the same depth as the fourth interface, or the bottom surface of the recess is set to be deeper than the fourth interface, so as to ensure that the recess can completely expose the side of the leak area, thereby ensuring that the tensile stress layer can completely cover the side of the leak area and the second step structure, which is beneficial to improving the compressive stress generated by the tensile stress layer on the leak area.

[0013] In some embodiments, the first step structure includes a multi-level step surface along a direction perpendicular to the first surface, the multi-level step surface being located between the first interface and the second interface; and / or, the second step structure includes a multi-level step surface along a direction perpendicular to the first surface, the multi-level step surface being located between the third interface and the fourth interface.

[0014] In some embodiments, the recess of the shallow trench isolation structure includes a bottom surface near the second surface. The bottom surface of the recess has a stepped structure. The tensile stress layer covers the stepped structure of the bottom surface of the recess. The stepped structure can achieve stress concentration in a local area and can amplify the compressive stress applied by the tensile stress layer to the first active region.

[0015] In some embodiments, the receiving trench is also located on opposite sides of the first active region along a second direction, the second direction being parallel to and intersecting the first surface, and the second direction being the length direction of the first gate. Along the second direction, the opposite sides of the first active region also include stepped structures, which can amplify the compressive stress applied to the first active region by the tensile stress layer in the second direction; the shallow trench isolation structure is also located on opposite sides of the first active region along the second direction.

[0016] In some embodiments, the first gate extends along the second direction and spans stepped structures on opposite sides of the first active region. The surface of the first gate near the first active region is adapted to the surface shape of the stepped structure, which can increase the relative area between the first gate and the first active region, improve the control capability of the first gate over the channel region, effectively reduce leakage current, and improve device performance.

[0017] In some embodiments, the receiving groove is disposed around the first active region, and the outer edge of the first active region located on the first surface is surrounded by a stepped structure. The stepped structure can achieve stress concentration around the first active region, further amplifying the compressive stress applied to the first active region by the tensile stress layer. The shallow trench isolation structure is disposed around the first active region.

[0018] In some embodiments, the receiving groove is also located on opposite sides of the second active region along a second direction, the second direction being parallel to and intersecting the first surface, and the second direction being the length direction of the first gate. The shallow trench isolation structure is also located on opposite sides of the second active region along the second direction, and the protrusions of the shallow trench isolation structure are also located on opposite sides of the second active region along the second direction.

[0019] In the above embodiments, in the second direction, the tensile stress layer also covers the protrusions of the shallow trench isolation structure. The protrusions can achieve stress concentration in local areas and amplify the tensile stress on the second active region in the second direction.

[0020] In some embodiments, along the second direction, a groove is formed between the protrusions on opposite sides of the second active region, at least a portion of the second gate is embedded in the groove, and the portion of the second gate embedded in the groove can form a downward protrusion, which can also achieve stress concentration in a local area and amplify the tensile stress on the second active region.

[0021] In some embodiments, the receiving groove is disposed around the second active region, the shallow trench isolation structure is disposed around the second active region, and the protrusions of the shallow trench isolation structure surround the second active region. The protrusions can achieve stress concentration around the second active region, further amplifying the tensile stress exerted by the tensile stress layer on the second active region.

[0022] In some embodiments, the transistor structure further includes a tensile stress layer that at least covers the first active region, the stepped structure of the first active region, the second active region, and the protrusions of the shallow trench isolation structure. The tensile stress layer can apply compressive stress to the first active region and tensile stress to the second active region.

[0023] On the other hand, a method for fabricating a transistor structure is also provided, the method comprising: A substrate is provided, the substrate including opposing first and second surfaces, wherein a first active region and a second active region are defined on the first surface.

[0024] A receiving groove is formed on the first surface; along a first direction parallel to the first surface, the receiving groove is located on opposite sides of the first active region and on opposite sides of the second active region.

[0025] A dielectric layer is formed, which fills the receiving groove.

[0026] The dielectric layer is etched at a rate greater than that of the first active region to form a depression in the dielectric layer and a stepped structure at the edge of the first active region; the portion of the dielectric layer near the second active region is retained to form a protrusion located on the side of the first surface away from the second surface.

[0027] A tensile stress layer is formed, which at least covers the first active region, the stepped structure of the first active region, the second active region, and the protrusions of the dielectric layer.

[0028] A first gate and a second gate are formed, wherein the first gate is located on the side of the first active region away from the second surface, and the second gate is located on the side of the second active region away from the second surface.

[0029] The fabrication method provided in the above embodiments of this application forms a stepped structure by etching the edge of the first active region. Only one mask is needed to form a tensile stress layer. The tensile stress layer covers the first active region and its stepped structure. In the high-temperature annealing process, the tensile stress layer restricts the first active region from expanding outward along the first direction, thereby generating compressive stress on the first active region. Furthermore, the stepped structure can achieve stress concentration in local areas, which can amplify the compressive stress on the first active region. This is beneficial to improving the carrier mobility of the channel in the first active region and increasing the conduction current of the transistor.

[0030] Furthermore, a protrusion is formed near the second active region, and the tensile stress layer also covers the second active region and the protrusion. The tensile stress layer generates tensile stress in the second active region along the first direction. Moreover, the protrusion can achieve stress concentration in a local area, which can amplify the tensile stress on the second active region, which is beneficial to improving the carrier mobility of the channel in the second active region and increasing the conduction current of the transistor.

[0031] Furthermore, compared to forming tensile stress films and compressive stress films separately using two photomasks, this application only requires one photomask to form the tensile stress layer, which is simple and has a lower cost.

[0032] In some embodiments, forming a receiving groove on the first surface includes: forming a first mask layer having a first opening, the first mask layer covering the first active region and the second active region; and etching the substrate through the first opening to form the receiving groove on the first surface.

[0033] After forming a receiving groove on the first surface, the fabrication method further includes: etching the side of the first opening to form a second opening, the second opening exposing the edge of the first active region, and the dielectric layer further filling the second opening.

[0034] Etching the portion of the dielectric layer near the first active region and etching the edge of the first active region includes: forming a second mask layer having a third opening, the second mask layer covering the side of the dielectric layer near the second active region, and the third opening exposing the side of the dielectric layer near the first active region; etching the edges of the dielectric layer and the first active region through the third opening; and removing the first mask layer and the second mask layer.

[0035] In some embodiments, after forming a depression in the dielectric layer, the fabrication method further includes: etching the bottom surface of the depression to form a stepped structure; after forming the tensile stress layer, the tensile stress layer also covers the stepped structure of the bottom surface of the depression, wherein the stepped structure can achieve stress concentration in a local area and can amplify the compressive stress applied by the tensile stress layer to the first active region.

[0036] As described above, this application provides a transistor structure and its fabrication method. By setting a stepped structure in the active region of a P-type transistor, an unexpected effect is that only a tensile stress layer can be formed. The tensile stress layer covers the active region and the stepped structure of the P-type transistor. During the high-temperature annealing process, the tensile stress layer restricts the outward expansion of the active region, thereby generating compressive stress on the active region. Furthermore, the stepped structure can achieve stress concentration in local areas, which can amplify the compressive stress on the active region, thus improving the carrier mobility of the channel of the P-type transistor and increasing the conduction current of the P-type transistor.

[0037] Furthermore, protrusions are provided on both sides of the active region of the N-type transistor, and the tensile stress layer also covers the active region and protrusions of the N-type transistor. The tensile stress layer generates tensile stress in the active region, and the protrusions can achieve stress concentration in local areas, which can amplify the tensile stress on the active region. This is beneficial to improving the carrier mobility of the N-type transistor channel and increasing the conduction current of the N-type transistor.

[0038] As can be seen, this application only requires the setting of a tensile stress layer and does not require the setting of a compressive stress layer. The tensile stress layer covers both P-type transistors and N-type transistors. The tensile stress layer can apply compressive stress to the active region of the P-type transistor and tensile stress to the active region of the N-type transistor. The process is simple and the cost is low. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0040] Figure 1 A top view of a transistor structure provided in an embodiment of this application; Figure 2 for Figure 1 A cross-sectional view of the transistor structure along section line AA'; Figure 3 for Figure 1 Another cross-sectional view of the transistor structure along section line AA'; Figure 4 for Figure 1 A cross-sectional view of the transistor structure along section line BB'; Figure 5 for Figure 1 Another cross-sectional view of the transistor structure along section line BB'; Figure 6 for Figure 1 A cross-sectional view of the transistor structure along section line CC'; Figure 7 for Figure 1 Another cross-sectional view of the transistor structure along section line CC'; Figure 8 A cross-sectional view along section line AA' of another transistor structure provided in an embodiment of this application; Figure 9 A cross-sectional view along section line AA' of yet another transistor structure provided in an embodiment of this application; Figure 10 A cross-sectional view along section line AA' of yet another transistor structure provided in an embodiment of this application; Figure 11A A step diagram illustrating the steps of providing a substrate provided in the embodiments of this application; Figure 11B A step diagram illustrating the formation of the first mask layer provided in an embodiment of this application; Figure 11C A step diagram illustrating the formation of the first opening provided in an embodiment of this application; Figure 11D A step diagram illustrating the formation of the receiving groove provided in an embodiment of this application; Figure 11E A step diagram illustrating the formation of the second opening provided in an embodiment of this application; Figure 11F A step diagram illustrating the formation of an adhesion layer provided in an embodiment of this application; Figure 11G A step diagram illustrating the deposition medium material provided in the embodiments of this application; Figure 11H A step diagram illustrating the formation of a dielectric layer provided in an embodiment of this application; Figure 11I A step diagram illustrating the formation of the second mask layer provided in an embodiment of this application; Figure 11J A step diagram illustrating the formation of recesses, protrusions, and stepped structures provided in an embodiment of this application; Figure 11K A step diagram illustrating the removal of the first mask layer and the second mask layer provided in this application embodiment; Figure 11L A step diagram illustrating the overall thinning of silicon oxide on the surface of a structure, provided for an embodiment of this application; Figure 11M A step diagram illustrating the thermal oxidation process for forming a silicon oxide layer, provided in an embodiment of this application; Figure 11N This is a step diagram illustrating the formation of a laminated structure provided in an embodiment of this application; Figure 11OA step diagram illustrating the formation of the source and drain regions provided in this application embodiment; Figure 11P A step diagram illustrating the formation of a tensile stress layer provided in an embodiment of this application; Figure 11Q A step diagram illustrating the removal of the tensile stress layer provided in an embodiment of this application; Figure 11R A step diagram illustrating the process of replacing a virtual gate with a gate, provided in an embodiment of this application; Figure 12A A step diagram illustrating the steps of forming a stepped structure on a recessed bottom surface, provided for an embodiment of this application; Figure 12B A diagram illustrating the steps for forming a tensile stress layer provided in an embodiment of this application.

[0041] Figure label: 1. Transistor structure; 2. First transistor; 20. First active region; 21a. First step structure; 21b. Second step structure; 22. Third step structure; 3. Second transistor; 30. Second active region; 4. Substrate; 5. Receptacle trench; 6. Shallow trench isolation structure; 60. Recess; 61. Bottom surface of the recess; 62. Fourth step structure; 7. Protrusion; 71. Groove; 8. First gate; 9. Second gate; 10. Tensile stress layer; 11. Adhesion layer; 12. Dielectric layer; 120 13. Dielectric material; 14. First silicon oxide layer; 15. Second silicon oxide layer; 16. High dielectric constant material layer; 17. Virtual gate; 18. First insulating layer; 19. Second insulating layer; 10. Sidewall; S. Source region; S1. First interface; S2. Second interface; D. Drain region; D1. Third interface; D2. Fourth interface; P1. First surface; P2. Second surface; K1. First mask layer; K2. Second mask layer; H1. First opening; H2. Second opening; H3. Third opening. Detailed Implementation

[0042] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0043] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0044] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0045] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0046] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0047] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0048] Dual Stress Liner (DSL) technology introduces tensile stress into the channel of an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) by depositing a tensile stress film, which is beneficial for improving the channel carrier mobility of the NMOSFET. Similarly, depositing a compressive stress film into the channel of a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) introduces compressive stress, which is beneficial for improving the channel carrier mobility of the PMOSFET.

[0049] However, the process of simultaneously depositing tensile stress films and compressive stress films on the same substrate is complex and requires two masks to form the tensile stress film and compressive stress film respectively, resulting in high process costs.

[0050] To address the aforementioned problems, embodiments of this application provide a transistor structure. Figure 1 A top view of a transistor structure provided in an embodiment of this application; Figure 2 for Figure 1 A cross-sectional view of the transistor structure along section line AA'; Figure 3 for Figure 1 Another cross-sectional view of the transistor structure along section line AA'; Figure 4 for Figure 1 A cross-sectional view of the transistor structure along section line BB'; Figure 5 for Figure 1 Another cross-sectional view of the transistor structure along section line BB'; Figure 6 for Figure 1 A cross-sectional view of the transistor structure along section line CC'; Figure 7 for Figure 1 Another cross-sectional view of the transistor structure along section line CC'.

[0051] See Figure 1 The transistor structure 1 includes a first transistor 2 and a second transistor 3. For example, the first transistor 2 can be a P-type metal-oxide-semiconductor field-effect transistor, and the second transistor 3 can be an N-type metal-oxide-semiconductor field-effect transistor.

[0052] See Figure 1 and Figure 2 The transistor structure 1 also includes a substrate 4, which includes a first surface P1 and a second surface P2 opposite to each other. The substrate 4 also includes a receiving groove 5 disposed on the first surface P1, a first active region 20 of the first transistor 2 disposed on the first surface P1, and a second active region 30 of the second transistor 3 disposed on the first surface P1. It can be understood that the receiving groove 5, the first active region 20 and the second active region 30 extend from the first surface P1 into the substrate 4, that is, the receiving groove 5, the first active region 20 and the second active region 30 all have a certain depth.

[0053] Along the first direction X parallel to the first surface P1, the receiving groove 5 is located on opposite sides of the first active region 20, and the receiving groove 5 is also located on opposite sides of the second active region 30. The receiving groove 5 is used to separate the first active region 20 and the second active region 30 with different conductivity types in the first direction X, so as to ensure that there is no interference between the first transistor 2 and the second transistor 3.

[0054] See also Figure 2 Along the first direction X, the opposite sides of the first active region 20 include stepped structures, namely a first stepped structure 21a and a second stepped structure 21b. The number of steps in the stepped structure can be single or multiple. The number of steps in the first stepped structure 21a and the second stepped structure 21b can be the same or different. The first stepped structure 21a and the second stepped structure 21b can be symmetrical or asymmetrical. The embodiments of this application do not limit this. The transistor structure 1 also includes a shallow trench isolation structure 6. At least a portion of the shallow trench isolation structure 6 is disposed in the receiving groove 5, and the shallow trench isolation structure 6 is located at least on the opposite sides of the first active region 20 along the first direction X. The side of the shallow trench isolation structure 6 near the first active region 20 has a recess 60. The bottom surface 61 of the recess 60 is located on the side of the first surface P1 near the second surface P2, that is, the bottom surface 61 of the recess 60 is lower than the first surface P1, and the recess 60 exposes the stepped structure of the first active region 20.

[0055] See also Figure 2 The shallow trench isolation structure 6 is also located at least on opposite sides of the second active region 30 along the first direction X. The side of the shallow trench isolation structure 6 closest to the second active region 30 has a protrusion 7. The protrusion 7 is located on the side of the first surface P1 away from the second surface P2, that is, the protrusion 7 extends beyond the first surface P1.

[0056] It should be noted that, see Figure 1 and Figure 2 A P-type metal-oxide-semiconductor field-effect transistor can be placed on the left side of the first transistor 2 (the side away from the second transistor 3), or an N-type metal-oxide-semiconductor field-effect transistor can be placed, or an external structure (e.g., a virtual transistor structure, an isolation structure, or a guard ring) can be placed. Figure 2 The shallow trench isolation structure 6 has a protrusion 7 on the side away from the first active region 20, i.e. Figure 2 The illustration shows an N-type metal-oxide-semiconductor field-effect transistor disposed to the left of the first transistor 2, but the embodiments of this application are not limited thereto.

[0057] Similarly, a P-type metal-oxide-semiconductor field-effect transistor can be disposed on the right side of the second transistor 3 (the side away from the first transistor 2), or an N-type metal-oxide-semiconductor field-effect transistor can be disposed, or an external structure (e.g., a virtual transistor structure, an isolation structure, or a guard ring, etc.) can be disposed. Figure 2 The shallow trench isolation structure 6 has a recess 60 on the side away from the second active region 30, i.e. Figure 2The illustration shows a case where a P-type metal-oxide-semiconductor field-effect transistor is disposed to the right of the second transistor 3, but the embodiments of this application are not limited thereto.

[0058] See Figure 1 and Figure 2 The transistor structure 1 further includes a first gate 8 of the first transistor 2 and a second gate 9 of the second transistor 3. The first gate 8 is disposed on the side of the first active region 20 away from the second surface P2, that is, the first gate 8 is disposed above the first active region 20, and the first direction X is the width direction of the first gate 8. The second gate 9 is disposed on the side of the second active region 30 away from the second surface P2, that is, the second gate 9 is disposed above the second active region 30.

[0059] The above embodiments of this application, by providing stepped structures on opposite sides of the first active region 20 and forming recesses 60 in the shallow trench isolation structures 6 on opposite sides of the first active region 20, expose the stepped structures of the first active region 20 in the recesses 60, combined with Figure 3 and Figure 4 It is possible to form only a tensile stress layer 10, which covers the first active region 20 and its stepped structure. It can be understood that the stepped structure is located on two opposite sides of the first active region 20 along the first direction X. The tensile stress layer 10 covering the stepped structure is equivalent to covering the sides of the first active region 20. In the high-temperature annealing process, the tensile stress layer 10 will restrict the first active region 20 from expanding outward along the first direction X, thereby generating compressive stress on the first active region 20. Furthermore, the stepped structure can achieve stress concentration in local areas, which can amplify the compressive stress on the first active region 20. This is beneficial to improving the carrier mobility of the channel in the first active region 20 and increasing the conduction current of the first transistor 2.

[0060] For example, the thermal expansion coefficients of the materials of the tensile stress layer 10 and the substrate 4 are both positive. During the high-temperature annealing process, the tensile stress layer 10 restricts the first active region 20 from expanding outward along the first direction X, thereby generating compressive stress on the first active region 20. For example, the material of the tensile stress layer 10 includes silicon nitride, and the material of the substrate 4 includes silicon. The thermal expansion coefficients of both silicon nitride and silicon are positive.

[0061] Furthermore, on both sides of the second active region 30, the shallow trench isolation structure 6 has a protrusion 7 on the side closer to the second active region 30, combined with... Figure 3 and Figure 4The tensile stress layer 10 also covers the second active region 30 and the protrusions 7 of the shallow trench isolation structure 6. The tensile stress layer 10 generates tensile stress in the second active region 30 along the first direction X. Furthermore, the protrusions 7 can achieve stress concentration in local areas, which can amplify the tensile stress on the second active region 30, which is beneficial to improving the carrier mobility of the channel in the second active region 30 and increasing the conduction current of the second transistor 3.

[0062] As can be seen, this application only needs to provide a tensile stress layer 10 and does not need to provide a compressive stress layer. The tensile stress layer 10 covers both P-type transistors and N-type transistors. The tensile stress layer 10 can apply compressive stress to the active region of the P-type transistor and tensile stress to the active region of the N-type transistor.

[0063] In some embodiments, see Figure 2 Along the first direction X, the two sides of the first active region 20 are the source region S and the drain region D, respectively. The source region S includes a first step structure 21a. Along the direction Z perpendicular to the first surface P1, the source region S includes a first interface S1 and a second interface S2. The first step structure 21a is located between the first interface S1 and the second interface S2, that is, the first step structure 21a is formed in the source region S.

[0064] See also Figure 2 The leaking region D includes a second step structure 21b along the direction Z perpendicular to the first surface P1. The leaking region D includes a third interface D1 and a fourth interface D2. The second step structure 21b is located between the third interface D1 and the fourth interface D2, that is, the second step structure 21b is formed in the leaking region D.

[0065] It is understandable that by forming the first step structure 21a in the source region S and the second step structure 21b in the drain region D, the first step structure 21a can achieve stress concentration in the source region S, and the second step structure 21b can achieve stress concentration in the drain region D. This can amplify the compressive stress of the tensile stress layer 10 on the source region S and the drain region D, as well as the compressive stress on the channel region located between the source region S and the drain region D, further improving the carrier mobility of the channel in the first active region 20 and increasing the conduction current of the first transistor 2.

[0066] In some embodiments, see Figure 2The second interface S2 is located on the side of the first interface S1 near the second surface P2. Exemplarily, the first interface S1 is located within the first surface P1. The recess 60 of the shallow trench isolation structure 6 includes a bottom surface 61 near the second surface P2. The bottom surface 61 of the recess 60 can be located on the side of the second interface S2 near the second surface P2, meaning the bottom surface 61 of the recess 60 is deeper than the second interface S2. Alternatively, the bottom surface 61 of the recess 60 can also be on the same plane as the second interface S2, meaning the bottom surface 61 of the recess 60 has the same depth as the second interface S2.

[0067] It is understandable that by setting the bottom surface 61 of the recess 60 to be the same depth as the second interface S2, or by setting the bottom surface 61 of the recess 60 to be deeper than the second interface S2, the recess 60 can be fully exposed to the side of the source region S, thereby ensuring that the tensile stress layer 10 can fully cover the side of the source region S and the first step structure 21a, which is beneficial to increasing the compressive stress generated by the tensile stress layer 10 on the source region S.

[0068] In some embodiments, see Figure 2 The fourth interface D2 is located on the side of the third interface D1 closer to the second surface P2. For example, the third interface D1 is located within the first surface P1. The bottom surface 61 of the recess 60 can be located on the side of the fourth interface D2 closer to the second surface P2, meaning the bottom surface 61 of the recess 60 is deeper than the fourth interface D2. Alternatively, the bottom surface 61 of the recess 60 can be on the same plane as the fourth interface D2, meaning the bottom surface 61 of the recess 60 has the same depth as the fourth interface D2.

[0069] It is understandable that by setting the bottom surface 61 of the recess 60 to be the same depth as the fourth interface D2, or by setting the bottom surface 61 of the recess 60 to be deeper than the fourth interface D2, the recess 60 can be fully exposed to the side of the leak area D, thereby ensuring that the tensile stress layer 10 can completely cover the side of the leak area D and the second step structure 21b, which is beneficial to increasing the compressive stress generated by the tensile stress layer 10 on the leak area D.

[0070] In some embodiments, see Figure 2 The second interface S2 is located on the side of the first interface S1 near the second surface P2. Exemplarily, the first interface S1 is located within the first surface P1. The recess 60 of the shallow trench isolation structure 6 includes a bottom surface 61 near the second surface P2. The bottom surface 61 of the recess 60 can be located on the side of the second interface S2 near the second surface P2, meaning the bottom surface 61 of the recess 60 is deeper than the second interface S2. Alternatively, the bottom surface 61 of the recess 60 can also be on the same plane as the second interface S2, meaning the bottom surface 61 of the recess 60 has the same depth as the second interface S2.

[0071] Furthermore, the fourth interface D2 is located on the side of the third interface D1 closer to the second surface P2. For example, the third interface D1 is located within the first surface P1. The bottom surface 61 of the recess 60 can be located on the side of the fourth interface D2 closer to the second surface P2, meaning the bottom surface 61 of the recess 60 is deeper than the fourth interface D2. Alternatively, the bottom surface 61 of the recess 60 can be on the same plane as the fourth interface D2, meaning the bottom surface 61 of the recess 60 has the same depth as the fourth interface D2.

[0072] It is understandable that by setting the bottom surface 61 of the recess 60 to have the same depth as the second interface S2 and the fourth interface D2, or by setting the bottom surface 61 of the recess 60 to be deeper than the second interface S2 and the fourth interface D2, the recess 60 can be made to fully expose the sides of the source region S and the drain region D, thereby ensuring that the tensile stress layer 10 can fully cover the sides of the source region S and the first step structure 21a, the sides of the drain region D and the second step structure 21b, which is beneficial to increasing the compressive stress generated by the tensile stress layer 10 on the source region S and the drain region D.

[0073] In some embodiments, see Figure 4 The receiving trench 5 is also located on opposite sides of the first active region 20 along the second direction Y. The second direction Y is parallel to the first surface P1 and intersects the first direction X. Exemplarily, the second direction Y is perpendicular to the first direction X, and the second direction Y is the length direction of the first gate 8. The receiving trench 5 is also used to separate the active regions along the second direction Y to ensure that no interference occurs between transistors. Along the second direction Y, the opposite sides of the first active region 20 also include a third step structure 22, and the shallow trench isolation structure 6 is also located on opposite sides of the first active region 20 along the second direction Y.

[0074] Understandably, see Figure 5 The tensile stress layer 10 covers the third step structure 22 (without direct contact, but separated by other film layers). The third step structure 22 can also achieve stress concentration in local areas, which can amplify the compressive stress applied by the tensile stress layer 10 to the first active region 20, further improving the carrier mobility of the channel in the first active region 20 and increasing the conduction current of the first transistor 2.

[0075] In some embodiments, see Figure 5 The first gate 8 extends along the second direction Y and crosses the third step structure 22 on both sides of the first active region 20. Furthermore, the surface of the first gate 8 near the first active region 20 is adapted to the surface shape of the third step structure 22. The arrangement of the third step structure 22 can increase the relative area between the first gate 8 and the first active region 20, improve the control capability of the first gate 8 over the channel region, effectively reduce leakage current, and improve device performance.

[0076] In some embodiments, combined with Figure 1 , Figure 2 and Figure 4 The receiving groove 5 is arranged around the first active area 20. The outer edge of the first active area 20 located on the first surface P1 is surrounded by a stepped structure. The shallow trench isolation structure 6 is arranged around the first active area 20.

[0077] It is understandable that the tensile stress layer 10 can cover the stepped structure surrounding the first active region 20. The stepped structure can achieve stress concentration around the first active region 20, further amplifying the compressive stress applied by the tensile stress layer 10 to the first active region 20, which is beneficial to improving the carrier mobility of the channel in the first active region 20 and increasing the conduction current of the first transistor 2.

[0078] For example, the first active region 20 has a rectangular shape as its orthographic projection on the first surface P1. The first active region 20 has a stepped structure on its opposite sides along the first direction X, and a third stepped structure 22 on its opposite sides along the second direction Y. The stepped structure and the third stepped structure 22 are connected to realize the setting of the stepped structure around the first active region 20.

[0079] In some embodiments, see Figure 6 The receiving groove 5 is also located on opposite sides of the second active region 30 along the second direction Y, the shallow trench isolation structure 6 is also located on opposite sides of the second active region 30 along the second direction Y, and the protrusion 7 of the shallow trench isolation structure 6 is also located on opposite sides of the second active region 30 along the second direction Y.

[0080] Understandably, see Figure 7 In the second direction Y, the tensile stress layer 10 also covers the protrusions 7 of the shallow trench isolation structure 6. The protrusions 7 can achieve stress concentration in local areas, amplify the tensile stress on the second active region 30, and help improve the carrier mobility of the channel in the second active region 30 and increase the conduction current of the second transistor 3.

[0081] In some embodiments, see Figure 7 Along the second direction Y, a groove 71 is formed between the protrusions 7 on opposite sides of the second active region 30. At least a portion of the second gate 9 is embedded in the groove 71. It is understood that the portion of the second gate 9 embedded in the groove 71 can form a downward protrusion. This protrusion can also achieve stress concentration in a local area, which can amplify the tensile stress on the second active region 30, which is beneficial to improving the carrier mobility of the channel in the second active region 30 and increasing the conduction current of the second transistor 3.

[0082] In some embodiments, combined with Figure 1 , Figure 2 and Figure 6The receiving groove 5 is arranged around the second active area 30, the shallow trench isolation structure 6 is arranged around the second active area 30, and the protrusion 7 of the shallow trench isolation structure 6 is arranged around the second active area 30.

[0083] It is understandable that the tensile stress layer 10 can cover the protrusion 7 surrounding the second active region 30. The protrusion 7 can achieve stress concentration around the second active region 30, further amplifying the tensile stress applied by the tensile stress layer 10 to the second active region 30, which is beneficial to improving the carrier mobility of the channel in the second active region 30 and increasing the conduction current of the second transistor 3.

[0084] For example, the shape of the orthographic projection of the second active region 30 on the first surface P1 is rectangular. The second active region 30 has protrusions 7 on opposite sides along the first direction X and opposite sides along the second direction Y. The protrusions 7 in the two directions are connected to realize the arrangement of the protrusions 7 around the second active region 30.

[0085] Embodiments of this application also provide a transistor structure. Figure 8 A cross-sectional view along section line AA' of another transistor structure provided in an embodiment of this application; Figure 9 A cross-sectional view along section line AA' of another transistor structure provided in an embodiment of this application.

[0086] See Figure 8 The transistor structure 1 includes a substrate 4, which includes a first surface P1 and a second surface P2 opposite to each other. The substrate 4 also includes a receiving groove 5 disposed on the first surface P1, a first active region 20 disposed on the first surface P1, and a second active region 30 disposed on the first surface P1. It can be understood that the receiving groove 5, the first active region 20 and the second active region 30 extend from the first surface P1 into the substrate 4, that is, the receiving groove 5, the first active region 20 and the second active region 30 all have a certain depth.

[0087] Along the first direction X parallel to the first surface P1, the receiving groove 5 is located on opposite sides of the first active region 20, and the receiving groove 5 is also located on opposite sides of the second active region 30. The receiving groove 5 is used to separate the first active region 20 and the second active region 30 with different conductivity types in the first direction X, so as to ensure that there is no interference between the first transistor 2 and the second transistor 3.

[0088] See also Figure 8Along the first direction X, the first active region 20 has stepped structures on opposite sides. The number of steps in the stepped structure can be single or multiple, and the embodiments of this application do not limit this. The transistor structure 1 also includes a shallow trench isolation structure 6, at least a portion of which is disposed within the receiving groove 5, and the shallow trench isolation structure 6 is located at least on opposite sides of the first active region 20 along the first direction X. The side of the shallow trench isolation structure 6 closest to the first active region 20 has a recess 60, which exposes the stepped structure of the first active region 20.

[0089] See also Figure 8 The shallow trench isolation structure 6 is also located at least on opposite sides of the second active region 30 along the first direction X. The side of the shallow trench isolation structure 6 closest to the second active region 30 has a protrusion 7. The protrusion 7 is located on the side of the first surface P1 away from the second surface P2, that is, the protrusion 7 extends beyond the first surface P1.

[0090] See you again Figure 8 The transistor structure 1 also includes a first gate 8 of the first transistor 2 and a second gate 9 of the second transistor 3. The first gate 8 is disposed on the side of the first active region 20 away from the second surface P2, that is, the first gate 8 is disposed above the first active region 20. The second gate 9 is disposed on the side of the second active region 30 away from the second surface P2, that is, the second gate 9 is disposed above the second active region 30.

[0091] The above embodiments of this application, by providing stepped structures on opposite sides of the first active region 20 and forming recesses 60 in the shallow trench isolation structures 6 on opposite sides of the first active region 20, expose the stepped structures of the first active region 20 in the recesses 60, combined with Figure 3 and Figure 4 It is possible to form only a tensile stress layer 10, which covers the first active region 20 and its stepped structure. It can be understood that the stepped structure is located on two opposite sides of the first active region 20 along the first direction X. The tensile stress layer 10 covering the stepped structure is equivalent to covering the sides of the first active region 20. In the high-temperature annealing process, the tensile stress layer 10 will restrict the first active region 20 from expanding outward along the first direction X, thereby generating compressive stress on the first active region 20. Furthermore, the stepped structure can achieve stress concentration in local areas, which can amplify the compressive stress on the first active region 20. This is beneficial to improving the carrier mobility of the channel in the first active region 20 and increasing the conduction current of the first transistor 2.

[0092] Furthermore, on both sides of the second active region 30, the shallow trench isolation structure 6 has a protrusion 7 on the side closer to the second active region 30, combined with... Figure 3 and Figure 4The tensile stress layer 10 also covers the second active region 30 and the protrusions 7 of the shallow trench isolation structure 6. The tensile stress layer 10 generates tensile stress in the second active region 30 along the first direction X. Furthermore, the protrusions 7 can achieve stress concentration in local areas, which can amplify the tensile stress on the second active region 30, which is beneficial to improving the carrier mobility of the channel in the second active region 30 and increasing the conduction current of the second transistor 3.

[0093] and Figure 2 The difference in transistor structure lies in, Figure 8 The shallow trench isolation structure 6 has a recess 60 with a fourth step structure 62 on its bottom surface. The fourth step structure 62 can have one or more steps, and the embodiments of this application do not limit this. It is understood that the shallow trench isolation structure 6 has a recess 60 on the side near the first active region 20, and the bottom surface of the recess 60 has a fourth step structure 62, so that the fourth step structure 62 is close to the side of the first active region 20.

[0094] Combination Figure 8 and Figure 9 The tensile stress layer 10 also covers the fourth step structure 62 on the bottom surface of the recess 60. The fourth step structure 62 can achieve stress concentration in local areas and amplify the compressive stress applied by the tensile stress layer 10 to the first active region 20, which is beneficial to improve the carrier mobility of the channel in the first active region 20 and increase the conduction current of the first transistor 2.

[0095] Embodiments of this application also provide a transistor structure. Figure 10 A cross-sectional view along section line AA' of another transistor structure provided in an embodiment of this application.

[0096] In some embodiments, see Figure 10 The first step structure 21a includes a multi-level step surface along the direction Z perpendicular to the first surface P1. The multi-level step surface of the first step structure 21a is located between the first interface S1 and the second interface S2. It can be understood that, apart from the step surface of the first step structure 21a on the first interface S1 (first surface P1), the first step structure 21a also includes a multi-level step surface located between the first interface S1 and the second interface S2.

[0097] By setting the first step structure 21a to have a multi-level step surface, the stress concentration effect of the step structure in the local area can be enhanced, the compressive stress on the first active region 20 can be further amplified, which is conducive to improving the carrier mobility of the channel in the first active region 20 and increasing the conduction current of the first transistor 2.

[0098] In some embodiments, see Figure 10The second step structure 21b includes a multi-level step surface along the direction Z perpendicular to the first surface P1. The multi-level step surface of the second step structure 21b is located between the third interface D1 and the fourth interface D2. It can be understood that, apart from the step surface of the second step structure 21b on the third interface D1 (first surface P1), the second step structure 21b also includes a multi-level step surface located between the third interface D1 and the fourth interface D2.

[0099] By setting the second step structure 21b to have a multi-level step surface, the stress concentration effect of the step structure in the local area can be enhanced, and the compressive stress on the first active region 20 can be further amplified. This is beneficial to improving the carrier mobility of the channel in the first active region 20 and increasing the conduction current of the first transistor 2.

[0100] In some embodiments, see Figure 10 The first step structure 21a includes a multi-level step surface along the direction Z perpendicular to the first surface P1, and the multi-level step surface of the first step structure 21a is located between the first interface S1 and the second interface S2. Furthermore, the second step structure 21b includes a multi-level step surface along the direction Z perpendicular to the first surface P1, and the multi-level step surface of the second step structure 21b is located between the third interface D1 and the fourth interface D2.

[0101] By setting both the first step structure 21a and the second step structure 21b to have multi-level step surfaces, the stress concentration effect of the step structure in the local area can be enhanced, further amplifying the compressive stress on the first active region 20, which is beneficial to improving the carrier mobility of the channel in the first active region 20 and increasing the conduction current of the first transistor 2.

[0102] For example, the number of stages of the first step structure 21a and the second step structure 21b can be the same, so that the compressive stress on both sides of the first active region 20 is approximately equal, thereby improving the uniformity of the force on the channel and making the mobility of charge carriers in each region of the channel approximately equal, thus avoiding local overheating and affecting the reliability of the device.

[0103] For example, the first step structure 21a and the second step structure 21b are symmetrical structures, which makes the compressive stress on both sides of the first active region 20 equal, which can further improve the uniformity of the force on the channel, make the mobility of charge carriers in each region of the channel equal, and avoid local overheating that affects the reliability of the device.

[0104] Embodiments of this application also provide a method for fabricating a transistor structure. Figures 11A-11R The diagram shows the steps involved in fabricating a transistor structure, as provided in the embodiments of this application.

[0105] The method for fabricating a transistor structure includes the following steps S10~S60: Step S10: See Figure 11A A substrate 4 is provided, which includes a first surface P1 and a second surface P2 opposite to each other. A first active region 20 and a second active region 30 are defined on the first surface P1. It should be noted that the first active region 20 and the second active region 30 are not formed in this step. Instead, the positions of the first active region 20 and the second active region 30 on the first surface P1 are defined first so as to form a receiving groove in the area outside the active region.

[0106] Step S20: See Figures 11B-11D A receiving groove 5 is formed on the first surface P1. Along the first direction X parallel to the first surface P1, the receiving groove 5 is located on opposite sides of the first active region 20, and the receiving groove 5 is also located on opposite sides of the second active region 30.

[0107] For example, step S20 includes: See Figure 11B First, a first mask layer K1 is formed on the first surface P1. The first mask layer K1 can be, for example, a stacked silicon oxide layer and a silicon nitride layer (hard mask, HM). The silicon oxide layer is in contact with the first surface P1, and the silicon nitride layer is located on the side of the silicon oxide layer away from the substrate 4.

[0108] See Figure 11C A first opening H1 is formed in the first mask layer K1, which covers the first active region 20 and the second active region 30. For example, a photolithography process can be used to etch the first mask layer K1 to form the first opening H1.

[0109] See Figure 11C and Figure 11D The substrate 4 is etched through the first opening H1 to form a receiving trench 5 on the first surface P1. For example, the substrate 4 can be etched using a dry etching process or a wet etching process.

[0110] For example, after step S20, the preparation method further includes the following steps: See Figure 11D and Figure 11E The side of the first opening H1 is etched to form the second opening H2, which exposes the edge of the first active region 20. For example, a wet etching process can be used to etch the silicon nitride layer. Taking advantage of the isotropic nature of the wet etching process, the side of the silicon nitride layer can be etched while thinning the silicon nitride layer, thereby achieving the pullback of the first opening H1.

[0111] For example, after forming the second opening H2, the preparation method further includes the following steps: See Figure 11E and Figure 11FAn adhesion layer 11 is formed on the surface of the receiving tank 5. For example, the substrate 4 is made of silicon, and a thermal oxidation process can be used to oxidize the silicon on the surface of the receiving tank 5 into silicon oxide. During the subsequent filling of the receiving tank 5 with dielectric material, the silicon oxide can serve as the adhesion layer 11 to improve the adhesion of the dielectric material.

[0112] Step S30: See Figures 11G to 11H A dielectric layer 12 is formed, which fills the receiving groove 5.

[0113] For example, step S30 includes: See Figure 11G A dielectric material 120 is deposited, filling the containment trench 5 and the second opening H2. The dielectric material also covers the side of the first mask layer K1 away from the substrate 4. For example, the containment trench 5 has a large depth-to-width ratio, exceeding 10:1. A high aspect ratio (HARP) process can be used to achieve void-free and uniform gap filling of the containment trench 5 and the second opening H2 by the dielectric material, thereby meeting the requirements of advanced integrated circuit nodes for device performance and reliability.

[0114] Then, the structure is annealed to eliminate internal stress in the medium material and improve the filling quality of the medium material for the receiving groove 5 and the second opening H2.

[0115] See Figure 11G and Figure 11H Using the first mask layer K1 as a stop layer, the portion of the dielectric material 120 covering the first mask layer K1 is removed by grinding. The remaining portion of the dielectric material 120 becomes the dielectric layer 12, and the upper surface of the dielectric layer 12 is flush with the upper surface of the first mask layer K1. For example, a chemical mechanical polishing (CMP) process is used to grind the portion of the dielectric material 120 covering the first mask layer K1 until the upper surface of the first mask layer K1 is exposed.

[0116] Step S40: See Figures 11I to 11K The dielectric layer 12 is etched at a rate greater than that of the first active region 20 to form a depression 60 in the dielectric layer 12 and a stepped structure at the edge of the first active region 20. A portion of the dielectric layer 12 near the second active region 30 is retained to form a protrusion 7, located on the side of the first surface P1 away from the second surface P2.

[0117] For example, step S40 includes: See Figure 11IA second mask layer K2 with a third opening H3 is formed, covering the side of the dielectric layer 12 near the second active region 30, and the third opening H3 exposes the side of the dielectric layer 12 near the first active region 20, or in other words, the third opening H3 exposes the first active region 20. For example, the second mask layer K2 with the third opening H3 is prepared by exposing and developing photoresist (PR).

[0118] See Figure 11J The dielectric layer 12 and the edge of the first active region 20 are etched through the third opening H3 to form a recess 60 on the side of the dielectric layer 12 near the first active region 20 and a protrusion 7 (the portion of the dielectric layer 12 located within the second opening H2 of the first mask layer K1) on the side of the dielectric layer 12 near the second active region 30. A step structure is formed at the edge of the first active region 20. For example, the same etching process is used to simultaneously etch the edges of the dielectric layer 12 and the first active region 20. By controlling the etching rate of the dielectric layer 12 to be greater than the etching rate of the first active region 20, the depth of the recess 60 is greater than the depth of the step structure, ensuring that the recess 60 can expose the step structure.

[0119] Understandable, Figure 11J The step structure formed in the process is a level one. To form multiple levels of steps, the aforementioned process steps can be repeated. For example, the second mask layer K2 can be removed, and the side of the opening in the first mask layer K1 can be etched to achieve side pushing. Then, a mask layer can be formed again, and the dielectric layer 12 and the first active region 20 can be etched simultaneously, which can increase the number of levels of the step structure by one level.

[0120] See Figure 11J and Figure 11K Remove the first mask layer K1 and the second mask layer K2. For example, if the first mask layer K1 is a stacked silicon oxide layer and a silicon nitride layer, and the second mask layer K2 is a photoresist, the second mask layer K2 can be stripped first using a stripping solution, and then a wet etching process can be used, in which the etching solution may include phosphoric acid, to etch and remove the silicon nitride layer in the first mask layer K1.

[0121] For example, after step S40, the preparation method further includes the following steps: See Figure 11K and Figure 11L An etching process is used to thin the silicon oxide layer on the surface of the structure as a whole, so as to remove the first silicon oxide layer 13 on the surface of the first active region 20 and the second active region 30.

[0122] See Figure 11MA thermal oxidation process is used to thermally oxidize the silicon on the surfaces of the first active region 20 and the second active region 30 to form a high-quality second silicon oxide layer 14. Alternatively, a thin film deposition process can be used to form a high-quality second silicon oxide layer 14 on the surfaces of the first active region 20 and the second active region 30.

[0123] It is understandable that the aforementioned process steps will have an adverse effect on the quality of the first silicon oxide layer 13 on the surface of the first active region 20 and the second active region 30. The surface of the first active region 20 and the second active region 30 needs to be prepared with high-quality silicon oxide as the gate insulating layer to ensure that the gate insulating layer will not be electrically broken down during the operation of the transistor. Based on this, the low-quality first silicon oxide layer 13 on the surface of the first active region 20 and the second active region 30 can be removed and a high-quality second silicon oxide layer 14 can be formed again.

[0124] For example, after step S40, the preparation method further includes the following steps: See Figure 11N A stacked structure is formed above the first active region 20 and the second active region 30, respectively. The stacked structure includes a high dielectric constant material layer (High K, HK) 15, a dummy gate 16, a first insulating layer 17, and a second insulating layer 18 stacked sequentially. Then, a sidewall 19 is formed on the side of the stacked structure.

[0125] See Figure 11O Using the sidewall 19 as a self-aligned structure, ion implantation is performed on the first active region 20 and the second active region 30 respectively to form the source region S and the drain region D in the first active region 20 and the second active region 30.

[0126] Step S50: See Figure 11P A tensile stress layer 10 is formed, which at least covers the first active region 20, the stepped structure of the first active region 20, the second active region 30, and the protrusion 7. The tensile stress layer 10 restricts the outward expansion of the first active region 20 along the first direction X, thereby generating compressive stress on the first active region 20. Furthermore, the stepped structure can achieve stress concentration in local areas, which can amplify the compressive stress on the first active region 20, thereby improving the carrier mobility of the channel in the first active region 20 and increasing the conduction current of the first transistor 2.

[0127] Furthermore, the tensile stress layer 10 generates tensile stress along the first direction X on the second active region 30. The protrusion 7 can achieve stress concentration in local areas, which can amplify the tensile stress on the second active region 30, which is beneficial to improve the carrier mobility of the channel in the second active region 30 and increase the conduction current of the second transistor 3.

[0128] For example, after step S50, the preparation method further includes the following steps: See Figure 11Q The tensile stress layer 10 is removed by etching. For example, the material of the tensile stress layer 10 includes silicon nitride, and a wet etching process can be used. The etching solution may include phosphoric acid to etch and remove the tensile stress layer 10.

[0129] Step S60: See Figure 11Q and Figure 11R A first gate 8 and a second gate 9 are formed. The first gate 8 is located on the side of the first active region 20 away from the second surface P2, and the second gate 9 is located on the side of the second active region 30 away from the second surface P2.

[0130] For example, the material of the dummy gate 16 includes polysilicon. The dummy gate 16 can be etched away to form a cavity, and then a conductive material can be deposited in the cavity to form the gate.

[0131] Embodiments of this application also provide another method for fabricating a transistor structure. Figures 12A-12B The diagram shows the steps involved in fabricating another transistor structure, as provided in the embodiments of this application.

[0132] The difference from the aforementioned fabrication method is that the transistor structure fabrication method includes the following steps S70~S80: Step S70: See Figure 12A After etching the dielectric layer 12 to form the recess 60, the bottom surface of the recess 60 is etched to form a fourth step structure 62 on the bottom surface of the recess 60. For example, a photolithography process can be used to etch the bottom surface of the recess 60 to form the fourth step structure 62.

[0133] Step S80: See Figure 12B After the tensile stress layer 10 is formed, the tensile stress layer 10 also covers the fourth step structure 62 on the bottom surface of the depression 60. The fourth step structure 62 can achieve stress concentration in local areas and amplify the compressive stress applied by the tensile stress layer 10 to the first active region 20, which is beneficial to improve the carrier mobility of the channel in the first active region 20 and increase the conduction current of the first transistor 2.

[0134] The transistor structure and fabrication method provided in the embodiments of this application, by setting a stepped structure in the active region of the P-type transistor, unexpectedly achieve the effect of forming only a tensile stress layer. The tensile stress layer covers the active region and the stepped structure of the P-type transistor. In the high-temperature annealing process, the tensile stress layer restricts the outward expansion of the active region, thereby generating compressive stress on the active region. Furthermore, the stepped structure can achieve stress concentration in local areas, which can amplify the compressive stress on the active region, thus improving the carrier mobility of the P-type transistor and increasing the conduction current.

[0135] Furthermore, protrusions are provided on both sides of the active region of the N-type transistor, and the tensile stress layer also covers the active region and protrusions of the N-type transistor. The tensile stress layer generates tensile stress in the active region, and the protrusions can achieve stress concentration in local areas, which can amplify the tensile stress on the active region, which is beneficial to improving the carrier mobility of the N-type transistor and increasing the conduction current.

[0136] As can be seen, this application only needs to set a tensile stress layer and does not need to set a compressive stress layer. The tensile stress layer covers both P-type transistors and N-type transistors. The tensile stress layer can apply compressive stress to the active region of the P-type transistor and tensile stress to the active region of the N-type transistor.

[0137] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A transistor structure, characterized in that, include: The substrate has a first surface and a second surface opposite to each other. The substrate further includes a first active region, a second active region, and a receiving groove disposed on the first surface. Along a first direction parallel to the first surface, the receiving groove is located on opposite sides of the first active region and opposite sides of the second active region. Along the first direction, the opposite sides of the first active region include a stepped structure. A shallow trench isolation structure is at least partially disposed within the receiving groove. The shallow trench isolation structure is located at least on opposite sides of the first active region along the first direction and at least on opposite sides of the second active region along the first direction. The side of the shallow trench isolation structure closest to the first active region has a recess that exposes the stepped structure of the first active region. The side of the shallow trench isolation structure closest to the second active region has a protrusion located on the side of the first surface away from the second surface. A first gate, the first gate being disposed on the first active region, the first direction being the width direction of the first gate; and The second gate is disposed on the second active region; Wherein, along the first direction, the opposite sides of the first active region are a source region and a drain region, respectively; along the direction perpendicular to the first surface, the source region includes a first interface and a second interface, the second interface being located on the side of the first interface closer to the second surface; along the direction perpendicular to the first surface, the drain region includes a third interface and a fourth interface, the fourth interface being located on the side of the third interface closer to the second surface. The shallow trench isolation structure includes a bottom surface near the second surface, wherein the bottom surface of the recess is on the same plane as the second interface, or, the bottom surface of the recess is located on the side of the second interface near the second surface; and / or, The bottom surface of the recess is on the same plane as the fourth interface, or the bottom surface of the recess is located on the side of the fourth interface closer to the second surface.

2. The transistor structure according to claim 1, characterized in that, The step structures on opposite sides of the first active region are a first step structure and a second step structure, respectively. The source region includes the first step structure, and the drain region includes the second step structure. The first step structure is located between the first interface and the second interface; The second step structure is located between the third interface and the fourth interface.

3. The transistor structure according to claim 2, characterized in that, The first step structure includes multiple first step surfaces, which are located between the first interface and the second interface along a direction perpendicular to the first surface; and / or, The second step structure includes multiple second step surfaces, which are located between the third interface and the fourth interface along a direction perpendicular to the first surface.

4. The transistor structure according to claim 1, characterized in that, The recess of the shallow trench isolation structure includes a bottom surface near the second surface, and the bottom surface of the recess has a stepped structure.

5. The transistor structure according to claim 1, characterized in that, The receiving groove is also located on opposite sides of the first active region along the second direction, which is parallel to the first surface and intersects the first direction; the second direction is the length direction of the first gate. Along the second direction, the first active region also includes stepped structures on opposite sides; the shallow trench isolation structure is also located on opposite sides of the first active region along the second direction.

6. The transistor structure according to claim 5, characterized in that, The first gate extends along the second direction and crosses the stepped structure on both sides of the first active region; The surface of the first gate near the first active region is adapted to the surface shape of the stepped structure.

7. The transistor structure according to claim 1, characterized in that, The receiving groove is arranged around the first active area, and the outer edge of the first active area located on the first surface is surrounded by a stepped structure. The shallow trench isolation structure is arranged around the first active area.

8. The transistor structure according to claim 1, characterized in that, The receiving groove is also located on opposite sides of the second active region along the second direction, which is parallel to the first surface and intersects the first direction; the second direction is the length direction of the first gate. The shallow trench isolation structure is also located on opposite sides of the second active region along the second direction, and the protrusions of the shallow trench isolation structure are also located on opposite sides of the second active region along the second direction.

9. The transistor structure according to claim 8, characterized in that, Along the second direction, a groove is formed between the protrusions on opposite sides of the second active region, and at least a portion of the second gate is embedded in the groove.

10. The transistor structure according to claim 1, characterized in that, The receiving groove is arranged around the second active region, the shallow trench isolation structure is arranged around the second active region, and the protrusion of the shallow trench isolation structure surrounds the second active region.

11. The transistor structure according to claim 1, characterized in that, The transistor structure further includes a tensile stress layer, which at least covers the first active region, the stepped structure of the first active region, the second active region, and the protrusions of the shallow trench isolation structure.

12. A method for fabricating a transistor structure, characterized in that, include: A substrate is provided, the substrate including opposing first and second surfaces, wherein a first active region and a second active region are defined on the first surface; A receiving groove is formed on the first surface; Along a first direction parallel to the first surface, the receiving groove is located on opposite sides of the first active region and on opposite sides of the second active region; A dielectric layer is formed, which fills the receiving groove; The portion of the dielectric layer near the first active region is etched, and the edge of the first active region is etched. The etching rate of the dielectric layer is greater than the etching rate of the first active region, so as to form a depression in the dielectric layer and a stepped structure at the edge of the first active region. A portion of the dielectric layer near the second active region is retained to form a protrusion, the protrusion being located on the side of the first surface away from the second surface; A tensile stress layer is formed, which at least covers the first active region, the stepped structure of the first active region, the second active region, and the protrusions of the dielectric layer; A first gate and a second gate are formed, wherein the first gate is located on the side of the first active region away from the second surface, and the second gate is located on the side of the second active region away from the second surface.

13. The method for fabricating a transistor structure according to claim 12, characterized in that, Forming a receiving groove on the first surface includes: A first mask layer with a first opening is formed, the first mask layer covering the first active region and the second active region; The substrate is etched through the first opening to form the receiving groove on the first surface; After forming the receiving groove on the first surface, the preparation method further includes: The side of the first opening is etched to form a second opening, the second opening exposing the edge of the first active region, and the dielectric layer is also filled in the second opening; Etching the portion of the dielectric layer near the first active region and etching the edge of the first active region includes: A second mask layer with a third opening is formed, the second mask layer covering the side of the dielectric layer near the second active region, and the third opening exposing the side of the dielectric layer near the first active region; The edges of the dielectric layer and the first active region are etched through the third opening; Remove the first mask layer and the second mask layer.

14. The method for fabricating a transistor structure according to claim 12, characterized in that, After forming a depression in the dielectric layer, the preparation method further includes: The bottom surface of the recess is etched to form a stepped structure; After the tensile stress layer is formed, the tensile stress layer also covers the stepped structure of the recessed bottom surface.

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