A back contact cell and method of manufacturing the same and a battery assembly

Abstract

The present application belongs to the technical field of back contact cells, and particularly relates to a back contact cell, a preparation method thereof and a battery assembly, which further comprises a continuous or discontinuous ultrathin nickel layer and a conductive film layer arranged in sequence from outside along the film layer thickness direction on the back, the ultrathin nickel layer covering at least the outer surface of a corresponding doped silicon layer of P type, the conductive film layer and the corresponding ultrathin nickel layer thereof being provided with a separation groove for separating a first semiconductor region and a second semiconductor region, and a gate line electrode; the ultrathin nickel layer is at least one of metal nickel, nickel oxide or nickel-silicon alloy, the maximum thickness of the ultrathin nickel layer is 0.1-1.8 nm, and the ratio of the maximum thickness of the ultrathin nickel layer to the thickness of the corresponding doped silicon layer of P type and the thickness of the conductive film layer is 1:(10-600):(30-800). The present application reduces the contact resistance, improves the open circuit voltage, and simultaneously improves the overall battery efficiency while maintaining the double-sided rate at a high level.

Description

Technical Field

[0001] This invention belongs to the field of back contact battery technology, specifically relating to a back contact battery, its preparation method, and battery assembly. Background Technology

[0002] Currently, commonly used finger-shaped cross-structure back contact battery structures generally include a silicon wafer, a first semiconductor layer and a second semiconductor layer disposed on the back side of the silicon wafer; a conductive film layer (such as ITO) and a metal gate line disposed on the outer surfaces of the first semiconductor layer and the second semiconductor layer respectively, which have a transition region where the two semiconductors are superimposed; and a passivation layer and an optional anti-reflection layer disposed sequentially on the front side of the silicon wafer.

[0003] However, when the conductive film is directly deposited on the corresponding doped silicon layers of the N-type and P-type semiconductor regions, a Schottky barrier easily forms at the interface due to the significant difference in their work functions. This hinders carrier transport at the interface, resulting in a non-ohmic contact. In this case, the contact resistance is high, affecting carrier transport capability and conductivity, especially lateral conductivity. A thicker conductive film (e.g., 30-80 nm) and a thicker N-type doped semiconductor layer (e.g., 80-120 nm) are typically required to meet the overall conductivity requirements of both the N-type and P-type semiconductor regions; however, the overall cell efficiency remains low.

[0004] Furthermore, the contact resistivity between the conductive film layer (such as ITO) and the N-type doped polycrystalline silicon layer on the first semiconductor layer and the P-type doped amorphous silicon layer on the second semiconductor layer is very high, severely affecting battery efficiency. Currently, laser-induced crystallization is generally performed on the P-type doped amorphous silicon layer of the second semiconductor layer to reduce the contact resistivity between the P-type doped amorphous silicon layer and the conductive film layer (such as ITO), but this cannot reduce the contact resistivity between the N-type doped polycrystalline silicon layer and the conductive film layer (such as ITO). In summary, existing back-contact batteries cannot simultaneously address the contact resistivity between the conductive film layer (such as ITO) and both the N-type and P-type semiconductor regions, thus impacting battery efficiency.

[0005] In order to avoid using expensive low-temperature silver paste (which is usually used as fine grid electrode and main grid electrode) and conductive film layer, existing technologies use a thicker silicon alloy layer (thickness above 2nm). However, 1. The thicker silicon alloy layer affects the back transmittance, resulting in a decrease in bifaciality; 2. The thicker silicon alloy layer increases parasitic absorption, thereby reducing the battery short-circuit current and thus affecting battery efficiency.

[0006] It should be noted that this part of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or known technology. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of existing technologies, such as low battery efficiency and inability to achieve bifaciality in back contact batteries with grid electrodes. This invention provides a back contact battery, its preparation method, and battery assembly. This invention reduces contact resistance, increases open-circuit voltage, and simultaneously improves overall battery efficiency while maintaining a high bifaciality.

[0008] To achieve the above objectives, in a first aspect, the present invention provides a back-contact battery, comprising a silicon wafer having a front side and a back side, a first semiconductor region and a second semiconductor region disposed alternately on the back side of the silicon wafer, the first semiconductor region comprising a first doped silicon layer, the second semiconductor region comprising a second doped silicon layer, and an end of the second doped silicon layer extending to the outer surface of an adjacent end of the first doped silicon layer to form a transition region, wherein one of the first doped silicon layer and the second doped silicon layer is N-type and the other is P-type; further comprising: a continuous or discontinuous ultrathin nickel layer disposed sequentially outward along the film thickness direction on the back side, a conductive layer, and a conductive layer. The film layer, an ultrathin nickel layer, covers at least the outer surface of the corresponding doped silicon layer of the P-type. The conductive film layer and its corresponding ultrathin nickel layer are provided with isolation trenches for isolating the first semiconductor region and the second semiconductor region, and gate electrodes are respectively provided on the outer surfaces of the corresponding conductive film layers of the first semiconductor region and the second semiconductor region. The ultrathin nickel layer is at least one of metallic nickel, nickel oxide or nickel-silicon alloy. The maximum thickness of the ultrathin nickel layer is 0.1-1.8 nm. The ratio of the maximum thickness of the ultrathin nickel layer to the thickness of the corresponding doped silicon layer of the P-type and the thickness of the conductive film layer is 1:(10-600):(30-800).

[0009] In some preferred embodiments of the present invention, the absolute value of the work function difference between the ultrathin nickel layer and the corresponding doped silicon layer or conductive film layer of the P-type is 0-0.7 eV, and / or the work function of the ultrathin nickel layer is 4.5-5.2 eV.

[0010] In some preferred embodiments of the present invention, the ultrathin nickel layer is a continuously distributed nickel-silicon alloy with a resistivity of 12-30 μΩ·cm.

[0011] In some preferred embodiments of the present invention, an ultrathin nickel layer is also covered on the outer surface of the corresponding N-type doped silicon layer, and the ratio of the maximum thickness of the ultrathin nickel layer to the thickness of the corresponding N-type doped silicon layer is 1:(15-650).

[0012] In some preferred embodiments of the present invention, the thickness of the conductive film layer is 20-300 nm, and / or the conductive film layer is at least one of a transparent conductive film, a metal conductive film, and a metal alloy conductive film.

[0013] Preferably, the isolation groove is disposed on the transition region; and / or, the conductive film layer covers the entire back surface except for the isolation groove.

[0014] In some preferred embodiments of the present invention, the thickness of the corresponding N-type doped silicon layer is 30-200 nm, and the thickness of the corresponding P-type doped silicon layer is 5-40 nm; and / or, the first doped silicon layer is N-type doped and the second doped silicon layer is P-type doped.

[0015] In some preferred embodiments of the present invention, the ultrathin nickel layer further contains doping elements, including boron or phosphorus.

[0016] In some preferred embodiments of the present invention, the ultrathin nickel layer is a nickel-silicon alloy containing Ni2Si.

[0017] In some preferred embodiments of the present invention, the outer surface of the corresponding doped silicon layer of the P-type has a partially loose region.

[0018] In some preferred embodiments of the present invention, the depth of the loose region is 1%-100% of the thickness of the corresponding doped silicon layer of the P-type.

[0019] In some preferred embodiments of the present invention, a second semiconductor opening region is formed in the region between adjacent first doped silicon layers, and the width W3 of the loose region is smaller than the width W1 of the second semiconductor opening region.

[0020] In some preferred embodiments of the present invention, the ratio of the width W3 of the loose region to the width W1 of the first semiconductor opening region is (20-95):100.

[0021] In some preferred embodiments of the present invention, the back contact battery further includes a metal transition layer disposed outside the conductive film layer, wherein the metal transition layer is a metal or a metal alloy.

[0022] In some preferred embodiments of the present invention, the thickness of the metal transition layer is 0.2-1 nm, and / or the metal transition layer is a nickel layer or a copper-nickel alloy layer.

[0023] In some preferred embodiments of the present invention, the first semiconductor region further includes a first passivation layer located between the back side of the silicon wafer and the first doped silicon layer, and the second semiconductor region includes a second passivation layer located between the back side of the silicon wafer and the second doped silicon layer, wherein the first passivation layer and the second passivation layer are each independently silicon oxide or intrinsic amorphous silicon.

[0024] In some preferred embodiments of the present invention, the back contact battery further has at least one of the following structures:

[0025] Structure 1: The first semiconductor region further includes a tunneling oxide layer located between the back side of the silicon wafer and the first doped silicon layer; the second semiconductor region includes an intrinsic amorphous silicon layer located between the back side of the silicon wafer and the second doped silicon layer; the two ends of the intrinsic amorphous silicon layer extend along the ends of the second doped silicon layer to the outer surface of the adjacent ends of the first doped silicon layer to form a transition region.

[0026] Structure 2: The first doped silicon layer is an N-type doped polycrystalline silicon layer, and the second doped silicon layer is a P-type doped amorphous silicon layer;

[0027] Structure 3: The back contact cell also includes a front passivation and anti-reflection layer disposed on the front side of the silicon wafer facing outwards;

[0028] Structure 4: The area of ​​the first doped silicon layer not covered by the second doped silicon layer forms the first semiconductor opening region; the back surface of the silicon wafer located at the second semiconductor opening region is a textured surface; and the back surface of the silicon wafer located at the position corresponding to the first semiconductor layer is a polished surface.

[0029] Structure 5: The front side of the silicon wafer is textured.

[0030] Secondly, the present invention provides a method for preparing a back contact battery, comprising the following steps:

[0031] S100. A silicon wafer is provided with a first semiconductor region and a second semiconductor region alternately arranged on the back side. The first semiconductor region includes a first doped silicon layer, the second semiconductor region includes a second doped silicon layer, and the end of the second doped silicon layer extends to the outer surface of the end of the adjacent first doped silicon layer to form a transition region. One of the first doped silicon layer and the second doped silicon layer is N-type and the other is P-type.

[0032] S110. Using thermal evaporation or magnetron sputtering, an ultrathin nickel layer is formed on at least the outer surface of the corresponding doped silicon layer of the P-type back side obtained in S100.

[0033] S120. A conductive film layer is formed on the outside of the ultrathin nickel layer by magnetron sputtering, wherein the substrate temperature is controlled to be maintained at 150-200℃ during the formation of the conductive film layer; the ratio of the maximum thickness of the ultrathin nickel layer to the thickness of the corresponding doped silicon layer of the P-type and the thickness of the conductive film layer is 1:(10-600):(30-800), and the maximum thickness of the ultrathin nickel layer is 0.1-1.8nm;

[0034] S130. An insulating groove is formed on the portion of the ultrathin nickel layer corresponding to the transition region and its corresponding conductive film layer.

[0035] S140, gate electrodes are formed on the outer surfaces of corresponding regions on the outer surfaces of the first semiconductor region and the second semiconductor region, respectively.

[0036] In some preferred embodiments of the present invention, the preparation method further includes: after S100, performing laser patterning on the corresponding doped silicon layer of the P-type corresponding to the non-transition region, so that the corresponding doped silicon layer of the P-type in the laser patterned region is in a loose state; and then performing S110.

[0037] In some preferred embodiments of the present invention, the conditions for laser marking processing include: a laser wavelength of 325-1100 nm and an energy density of 1-200 mJ / cm². 2 ; and / or, the laser used for laser marking is a nanosecond, picosecond, or femtosecond laser.

[0038] In some preferred embodiments of the present invention, the preparation method further includes: after S110, laser irradiation of the back ultrathin nickel layer, followed by S120.

[0039] In some preferred embodiments of the present invention, the laser irradiation conditions include: a laser wavelength of 325-1100 nm and an energy density of 1-200 mJ / cm². 2 ; and / or, the laser used for laser irradiation is a nanosecond, picosecond, or femtosecond laser.

[0040] In some preferred embodiments of the present invention, the preparation method further includes: controlling the conductive film layer to be a transparent conductive film layer, and after S130, sputtering a metal transition layer on the outside of the transparent conductive film layer, and then performing S130.

[0041] In some preferred embodiments of the present invention, in S110, the deposition rate of the thermal evaporation process is controlled to be 0.02-0.05 nm / s; and / or, the conditions of the thermal evaporation process include: using a target metal target, and a base vacuum <5×10⁻⁶. -4 Pa.

[0042] In some preferred embodiments of the present invention, the conditions of the magnetron sputtering process in S110 include: the deposition rate is controlled at 0.03-0.08 nm / s, and the substrate temperature is maintained at 150-200°C;

[0043] And / or, the conditions for the magnetron sputtering process in S110 include: using a target metal target, introducing argon gas, a process pressure of 0.5-1.0 Pa, and a DC power supply of 20-50 W.

[0044] Preferably, the working pressure of magnetron sputtering during the formation of the conductive film layer in S120 is 0.3-0.8 Pa.

[0045] In some preferred embodiments of the present invention, S110 further includes: first performing a surface pretreatment on the back side obtained in S100 to remove oxides and contaminants from the back side, and then performing the step of forming an ultrathin nickel layer.

[0046] In some preferred embodiments of the present invention, the surface pretreatment is performed by immersion in HF solution or vacuum plasma cleaning, wherein...

[0047] The conditions for soaking in HF solution include: the volume concentration of HF in the HF solution is 0.5%-1%, and the soaking time is 10-30 s;

[0048] The conditions for vacuum plasma cleaning include: in a vacuum environment, in the presence of an inert gas, with an inert gas flow rate of 20-50 sccm, a power of 30-80 W, a pressure of 0.5-2 Pa, and a plasma bombardment cleaning time of 30-60 s.

[0049] In some preferred embodiments of the present invention, S110 further includes: after performing the step of forming the ultrathin nickel layer, a short-time low-temperature annealing is also performed; wherein,

[0050] The conditions for short-time low-temperature annealing include: annealing temperature of 180-200℃ and time of 5-10 min;

[0051] And / or, short-time low-temperature annealing is carried out in an atmosphere including nitrogen or a forming gas containing nitrogen and hydrogen.

[0052] In some preferred embodiments of the present invention, the preparation method further includes at least one of the following processes:

[0053] In process 1, an ultrathin nickel layer is formed on the outer surface of both the first doped silicon layer and the second doped silicon layer in S110.

[0054] Process 2, the preparation method also includes depositing a front passivation antireflection layer on the front side of the silicon wafer;

[0055] Process 3, S100, provides a silicon wafer with alternating first and second semiconductor regions arranged on the back side, specifically including:

[0056] S101, provides double-sided polished silicon wafers;

[0057] S102. A first semiconductor layer and a mask layer are sequentially formed on the back side of the silicon wafer;

[0058] S103. A first etching opening is made on the back side obtained in S102 to form a second semiconductor opening region;

[0059] S104. Texturing and cleaning: A texturing surface is formed on the front side of the silicon wafer and the second semiconductor opening area, and then the mask layer is completely removed or a portion of the mask layer is retained.

[0060] S106. Deposit a second semiconductor layer on the back side;

[0061] S107. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0062] In process four, S100, the first semiconductor region further includes a tunneling oxide layer located between the back side of the silicon wafer and the first doped silicon layer, and the second semiconductor region includes an intrinsic amorphous silicon layer located between the back side of the silicon wafer and the second doped silicon layer. The two ends of the intrinsic amorphous silicon layer extend along the ends of the second doped silicon layer to the outer surface of the adjacent ends of the first doped silicon layer to form a transition region.

[0063] Thirdly, the present invention provides a back contact battery, which is prepared by the back contact battery preparation method described in the second aspect.

[0064] Fourthly, the present invention provides a battery assembly comprising the back contact battery described in the first aspect, or the back contact battery described in the third aspect.

[0065] Beneficial effects:

[0066] In existing conventional back-contact batteries, N-regions, P-regions, conductive films, and grid electrodes (i.e., fine grid electrodes and main grid electrodes) are arranged. The contact resistivity differs between the N-region and the conductive film, and between the P-region and the conductive film, making it difficult to achieve a balance. In particular, the high contact resistance at the interface between the P-region and the conductive film is a known bottleneck in optimizing HBC battery efficiency. Extensive research has revealed that the root cause lies in the bandgap mismatch and interface states between the P-region (e.g., pa-Si:H) and the conductive film (transparent conductive film such as ITO): On one hand, there is a work function mismatch: the work function of pa-Si:H is approximately 5.0-5.3 eV, while that of transparent conductive film (e.g., ITO) is approximately 4.3-4.7 eV. This difference forms a Schottky barrier at the interface, hindering hole transport. On the other hand, there is sputtering damage to the conductive film: the conductive film is typically deposited using magnetron sputtering, and high-energy particle bombardment can cause damage and defect states on the surface of the P-region, such as pa-Si:H, further increasing interface recombination and contact resistance.

[0067] In response, this invention addresses this issue by employing the aforementioned technical solution, particularly by setting an ultrathin nickel layer of a specific and suitable thickness between the corresponding doped silicon layer and the conductive film layer of the P-type semiconductor. This improves electrical contact without sacrificing optical performance, achieving good contact with the P-type semiconductor region and low-resistance connection with the conductive film layer, thus reducing contact resistance. Furthermore, the combination of the ultrathin nickel layer, the conductive film layer, and the corresponding doped silicon layer of the P-type semiconductor with a suitable thickness ratio enhances the longitudinal conductivity from the semiconductor to the gate electrode, thereby increasing the open-circuit voltage and improving the overall battery efficiency. Simultaneously, the suitable ultrathin nickel layer ensures sufficient light transmittance on the back side, while also improving the bifaciality of the battery.

[0068] The ultrathin nickel layer achieves good contact with the P-type semiconductor region and low-resistance connection with the conductive film layer, reducing contact resistance. This is because the ultrathin nickel layer, combined with the thickness ratio of its corresponding doped silicon layer and conductive film layer to the P-type semiconductor region within the aforementioned range, can form ohmic or low-barrier contacts with the corresponding doped silicon layer of the P-type semiconductor region, significantly reducing hole transport resistance. At the same time, the ultrathin nickel layer, as a metallic material, can form good electrical contact with the conductive film layer, ultimately decomposing the original single high-resistance interface (pa-Si:H / ITO) into two low-resistance interfaces (such as pa-Si:H / ultrathin nickel layer, ultrathin nickel layer / ITO), achieving a significant reduction in overall contact resistance. If the ratio of the maximum thickness of the ultrathin nickel layer to the thickness of the corresponding P-type doped silicon layer and the conductive film layer is not within the aforementioned range, it is difficult to simultaneously achieve good interfacial contact performance and device optical performance. Specifically, when the ultrathin nickel layer is too thin, it is difficult to form a stable interfacial transition layer, making it difficult to form a good ohmic contact with the underlying P-type doped silicon layer. This results in a still high interfacial barrier, increasing the interfacial contact resistance and hindering the effective transport of charge carriers. Conversely, when the ultrathin nickel layer is too thick, such as exceeding 2 nm, it increases the absorption or reflection of light by the layer, reducing the light transmittance of the device. It also weakens the utilization efficiency of back incident light, thus adversely affecting the bifacial power generation capability of the battery and causing a decrease in bifaciality. Therefore, by controlling the thickness of the ultrathin nickel layer within the aforementioned range, this invention can ensure the formation of good ohmic contact while avoiding adverse effects on light transmittance and bifaciality, thereby achieving synergistic optimization of the device's electrical and optical performance.

[0069] Meanwhile, this invention controls the thickness of the ultrathin nickel layer to ≤1.8nm, which can avoid the risk that metals (such as Ni atoms) in the ultrathin nickel layer will introduce deep energy recombination centers in the band gap and seriously increase the interface recombination rate, leading to a drop in open circuit voltage, by penetrating the corresponding doped silicon layer of the P-type layer (such as the pa-Si:H layer) and diffusing into the passivation layer (such as the intrinsic silicon layer). In addition, with the appropriate thickness ratio of the ultrathin nickel layer to the corresponding doped silicon layer of the P-type layer, the metal in the ultrathin nickel layer can penetrate and diffuse through the corresponding doped silicon layer of the P-type layer with an appropriate thickness ratio, providing a natural diffusion buffer.

[0070] In the preparation method of the present invention, an ultrathin nickel layer is first formed on at least the outer surface of the corresponding doped silicon layer of the P-type, and then the sputtering heat budget of the conductive film layer is used to promote at least part of the ultrathin nickel layer to be more compact, forming an ultrathin layer with a thickness of 0.1-1.8 nm (when the ultrathin nickel layer is a nickel-silicon alloy, the compaction is manifested in that the unreacted metal in the ultrathin nickel layer further reacts in situ to generate a metal silicide (such as NiSix) interface layer to form a more compact ultrathin nickel layer with a thickness of 0.2-1.8 nm), which is beneficial to significantly reduce the contact resistance while maintaining optical transmittance. The reason for the significant reduction in contact resistance is speculated to be that, taking the ultrathin nickel layer as a nickel-silicon alloy as an example, the S110 ultrathin nickel layer does not form a continuous metal silicide (such as NiSix) film on the surface of the corresponding doped silicon layer of the P-type, but rather a large number of nanoscale metal silicide (such as NiSix) contact islands. After the conductive film layer is sputtered and covered, these islands form a denser ultrathin nickel layer with a thickness of 0.1-1.8 nm and multiple parallel low-resistance conductive channels. The overall effect is equivalent to a large area of ​​low-resistance contact. This nano-island structure helps to maintain the optical transmittance of the film layer. This nano-island distribution ensures both electrical improvement and minimizes optical loss. Moreover, the work function of the ultrathin nickel layer formed by this method is closer to that of the corresponding doped silicon layer of the P-type (such as pa-Si:H) than that of the conductive film layer. This can effectively reduce the hole barrier, significantly reduce the interface contact resistance, and improve the transverse and longitudinal conductivity, thereby improving the open circuit voltage and the overall battery efficiency. At the same time, the suitable ultrathin nickel layer ensures sufficient light transmittance on the back side, which also improves the bifaciality of the battery. Moreover, during the sputtering process of the conductive film, the unreacted metal in the ultrathin nickel layer further reacts in situ to generate metal silicides to form a dense ultrathin nickel layer. This process consumes only a small portion of the silicon in the semiconductor region, effectively avoiding sputtering damage to the corresponding doped silicon layer of the P-type by the conductive film, and does not affect the passivation effect of the semiconductor region. This ensures both high overall battery efficiency and bifaciality.

[0071] In addition, the present invention controls the substrate temperature to be maintained at 150-200°C during the formation of the conductive film layer. This thermal budget is sufficient to form a denser ultrathin nickel layer with a thickness of 0.1-1.8 nm, but insufficient to drive the continued deep diffusion of the metal to avoid damage to the passivation layer, while ensuring the crystallinity and electrical properties of the conductive film layer.

[0072] In a preferred embodiment of the present invention, an ultrathin nickel layer is also covered on the outer surface of the corresponding doped silicon layer of the N-type semiconductor, which can simultaneously reduce the contact resistivity between the corresponding doped silicon layer of the N-type semiconductor and the conductive film layer, and achieve good contact in the N-region. This can effectively balance the low contact resistivity between the conductive film layer (such as ITO) and the N-type semiconductor region and the P-type semiconductor region, further improving battery efficiency while also taking into account a high bifaciality. Attached Figure Description

[0073] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0074] Figure 1 This is a schematic diagram of a specific embodiment of the present invention.

[0075] Figure 2 This is a schematic diagram of the structure after setting a loose region in another specific embodiment of the present invention.

[0076] Figure 3 for Figure 2 A schematic diagram of the structure after the metal electrode is formed.

[0077] Explanation of reference numerals in the attached figures

[0078] 1. Silicon wafer, 2. Tunneling oxide layer, 3. First doped silicon layer, 4. Intrinsic amorphous silicon layer, 5. Second doped silicon layer, 51. Loose region, 6. Ultrathin nickel layer, 7. Conductive film layer, 8. Gate electrode, 9. Passivation layer, 10. Antireflection layer. Detailed Implementation

[0079] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0080] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0081] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of the ranges, the endpoint values ​​of the ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. The terms "optional" and "optional" mean that they may or may not be included (or may or may not be present).

[0082] In this invention, the area closer to the silicon wafer is considered the inside, and the area farther from the silicon wafer is considered the outside. In application, incident light enters from the front of the back-contact battery.

[0083] In a first aspect, the present invention provides a back-contact battery, comprising a silicon wafer having a front side and a back side, and a first semiconductor region and a second semiconductor region disposed alternately on the back side of the silicon wafer, the first semiconductor region comprising a first doped silicon layer, the second semiconductor region comprising a second doped silicon layer, and the end of the second doped silicon layer extending to the outer surface of the adjacent end of the first doped silicon layer to form a transition region, wherein one of the first doped silicon layer and the second doped silicon layer is N-type and the other is P-type; further comprising: a continuous or discontinuous ultrathin nickel layer and a conductive film layer sequentially disposed outward along the film thickness direction on the back side. A thin nickel layer covers at least the outer surface of the corresponding doped silicon layer of the P-type. An isolation trench for isolating the first semiconductor region and the second semiconductor region is provided on the conductive film layer and its corresponding ultrathin nickel layer. Gate electrodes are respectively provided on the outer surface of the corresponding conductive film layer of the first semiconductor region and the second semiconductor region. The ultrathin nickel layer is at least one of metallic nickel, nickel oxide or nickel-silicon alloy. The maximum thickness of the ultrathin nickel layer is 0.1-1.8 nm. The ratio of the maximum thickness of the ultrathin nickel layer to the thickness of the corresponding doped silicon layer of the P-type and the thickness of the conductive film layer is 1:(10-600):(30-800).

[0084] The continuous or discontinuous ultrathin nickel layer mentioned in this invention refers to the fact that the ultrathin nickel layer can be a continuous film layer or a discontinuous film layer, or even a discontinuous atomic layer. When the ultrathin nickel layer is discontinuous, the maximum thickness of the ultrathin nickel layer refers to the maximum thickness of the different portions of the nickel layer contained in the discontinuous ultrathin nickel layer.

[0085] The maximum thickness of the ultrathin nickel layer is 0.1-1.8 nm, specifically 0.1 nm, 0.2 nm, 0.3 nm, 0.4 nm, 0.5 nm, 0.55 nm, 0.6 nm, 0.65 nm, 0.7 nm, 0.75 nm, 0.8 nm, 0.85 nm, 0.9 nm, 0.95 nm, 0.99 nm, 1.00 nm, 1.10 nm, 1.20 nm, 1.30 nm, 1.40 nm, 1.50 nm, 1.60 nm, 1.70 nm, or 1.80 nm, as well as any range between two values.

[0086] In this invention, the ratio of the maximum thickness of the ultrathin nickel layer to the thickness of the corresponding doped silicon layer of the P-type and the thickness of the conductive film layer is 1:(10-600):(30-800), specifically, it can be 1:(10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 74, 75, 78, 80, 85, 90, 95, 100, 110, 120, 130, 140, 1 The range of values ​​is 50, 160, 170, 180, 200, 250, 300, 350, 400, 450, 500, 550, or 600, and any two points between these values. This invention employs an ultra-thin nickel layer with a suitable thickness ratio, a corresponding doped silicon layer of the P-type, and a conductive film layer. This improves the interfacial electrical contact performance without sacrificing optical performance, thus balancing the electrical and optical performance of the battery.

[0087] In some preferred embodiments of the present invention, the absolute value of the work function difference between the ultrathin nickel layer and the corresponding doped silicon layer or conductive film layer of the P-type is between 0 and 0.7 eV, specifically, it can be independently 0 eV, 0.05 eV, 0.1 eV, 0.2 eV, 0.3 eV, 0.4 eV, 0.5 eV, 0.6 eV, or 0.7 eV, or any range between any two points. By adopting this preferred embodiment, the present invention achieves a smaller absolute value of the work function difference between the ultrathin nickel layer and the corresponding doped silicon layer or conductive film layer of the P-type, which is more conducive to better matching of the two semiconductor regions (especially the P-type semiconductor region) for good contact and low-resistance connection with the conductive film layer.

[0088] Preferably, the work function of the ultrathin nickel layer in this invention is between 4.5 and 5.2 eV, specifically 4.5 eV, 4.55 eV, 4.6 eV, 4.65 eV, 4.7 eV, 4.75 eV, 4.8 eV, 4.85 eV, 4.9 eV, 5.0 eV, 5.1 eV, or 5.2 eV, or any range between two points. By adopting this preferred embodiment, the work function of the ultrathin nickel layer is closer to that of a p-type semiconductor region (e.g., the work function of Pa-Si:H is approximately 5.0-5.3 eV) than that of conductive film layers (e.g., the work function of ITO is approximately 4.3-4.7 eV), thereby further significantly reducing the hole barrier and further reducing the contact resistance.

[0089] In some preferred embodiments of the present invention, the ultrathin nickel layer is a continuously distributed nickel-silicon alloy with a resistivity of 12-30 μΩ·cm, specifically, values ​​of 12 μΩ·cm, 13 μΩ·cm, 14 μΩ·cm, 15 μΩ·cm, 16 μΩ·cm, 17 μΩ·cm, 18 μΩ·cm, 19 μΩ·cm, 20 μΩ·cm, 21 μΩ·cm, 22 μΩ·cm, 23 μΩ·cm, 24 μΩ·cm, 25 μΩ·cm, 26 μΩ·cm, 27 μΩ·cm, 28 μΩ·cm, 29 μΩ·cm, or 30 μΩ·cm, or any range between any two values. The ultrathin nickel layer of the preferred embodiment of the present invention has a low resistivity, which facilitates good contact between the two semiconductor regions (especially the P-type semiconductor region) and low-resistance connection with the conductive film layer.

[0090] In some preferred embodiments of the present invention, an ultrathin nickel layer is also coated on the outer surface of the corresponding doped silicon layer of the N-type. Preferably, the ultrathin nickel layer covers the surfaces of the first and second doped silicon layers of the N / P type, which facilitates the formation of good ohmic contacts between the ultrathin nickel layer and the corresponding doped silicon layers. Simultaneously, the ultrathin nickel layer, as a transition interface layer, has a more matched work function relationship with the conductive film layer above, forming good electrical contact, which is more conducive to improving battery efficiency while also achieving a high bifaciality.

[0091] More preferably, the ratio of the maximum thickness of the ultrathin nickel layer to the thickness of the corresponding N-type doped silicon layer is 1:(15-650), for example, it can be 1:15, 1:20, 1:30, 1:50, 1:70, 1:100, 1:110, 1:120, 1:130, 1:150, 1:170, 1:200, 1:300, 1:400, 1:500, 1:600, 1:630 or 1:650, etc., and any range between two points. Using this preferred embodiment of the present invention is more conducive to ensuring the stability and controllability of the reaction between metal (such as nickel) and silicon in metal silicides, and can further reduce the interface contact resistance while protecting the passivation effect of the tunneling oxide layer.

[0092] In some preferred embodiments of the present invention, the thickness of the conductive film layer is 20-300 nm, specifically 20 nm, 30 nm, 40 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 99 nm, 100 nm, 120 nm, 150 nm, 170 nm, 200 nm, 220 nm, 250 nm, 270 nm, 290 nm or 300 nm, and any range between two point values.

[0093] When the ultrathin nickel layer is a nickel-silicon alloy, the thickness of the conductive film layer is preferably 50-100 nm. In this preferred embodiment, the present invention can use a thinner conductive film layer in conjunction with the ultrathin nickel layer, which can improve both the transverse and longitudinal conductivity, while ensuring sufficient light transmittance on the back side, thereby improving both the bifaciality and efficiency of the battery.

[0094] Preferably, the conductive film layer of the present invention is at least one of a transparent conductive film, a metal conductive film, and a metal alloy conductive film.

[0095] More preferably, the transparent conductive film layer is an indium oxide-based thin film doped with at least one element selected from tin, tungsten, titanium, zinc, and gallium, or a zinc oxide-based thin film doped with at least one element selected from aluminum, gallium, and boron.

[0096] More preferably, the metal conductive film includes at least one of a nickel layer, an aluminum layer, a copper layer, a silver layer, and a zinc layer.

[0097] More preferably, the metal alloy conductive film is at least one of nickel-copper alloy, nickel-chromium alloy, and copper-aluminum alloy.

[0098] Preferably, the isolation groove is disposed in the transition region of the present invention.

[0099] In this invention, the conductive film layer can cover a portion or the entire back surface. In one specific embodiment, the conductive film layer covers the entire back surface except for the isolation groove.

[0100] Preferably, the thickness of the corresponding doped silicon layer of the P-type is 5-40 nm, specifically 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 17 nm, 20 nm, 22 nm, 25 nm, 28 nm, 30 nm, 32 nm, 35 nm, 37 nm, 39 nm or 40 nm, and any range between two points.

[0101] In some preferred embodiments, the thickness of the corresponding doped silicon layer of the P-type is 5-15 nm, more preferably 10-15 nm, which is more conducive to providing a safe buffer for metal diffusion in the ultrathin nickel layer and avoiding excessive diffusion that would affect the passivation effect. Although the thickening of the corresponding doped silicon layer of the P-type will slightly increase optical parasitic absorption, it has little effect on the back structure of the back contact battery (since light is incident from the front).

[0102] In some preferred embodiments of the present invention, the thickness of the corresponding doped silicon layer of the N-type is 30-200nm, more preferably 30-130nm, and even more preferably 30-70nm. For example, it can be 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 69nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, or 200nm, as well as any range between two point values. This invention incorporates an ultrathin nickel layer between the N-type doped silicon layer and the conductive film layer, resulting in a more matched work function relationship and a low-barrier contact structure at the interface. This significantly reduces the interface contact resistance and improves carrier transport conditions. Therefore, while ensuring good electrical contact performance, a thinner (30-70nm thick) corresponding N-type doped silicon layer can be used. This not only reduces parasitic light absorption of the polycrystalline silicon layer, thereby improving the optical utilization efficiency and bifacial power generation capability of the device, but also reduces material consumption and shortens deposition time, thereby reducing costs and improving process efficiency.

[0103] Preferably, in this invention, the first doped silicon layer is N-type doped and the second doped silicon layer is P-type doped.

[0104] In this invention, the effective doping concentrations of the first doped silicon layer and the second doped silicon layer can refer to the ranges in the prior art; for example, they can each be independently 1e18cm. -3 -9e19cm -3 .

[0105] In some preferred embodiments of the present invention, the ultrathin nickel layer further contains doping elements, including boron or phosphorus. This preferred embodiment allows for better control of carrier concentration, improved electron mobility, and reduced resistance, thus enhancing the stability of the fabrication process and the overall performance of the battery.

[0106] Furthermore, the effective doping concentration of the doping element in the ultrathin nickel layer is 5e15 cm⁻¹. -3 -5e17 cm -3 .

[0107] Preferably, the ultrathin nickel layer in this invention is a nickel-silicon alloy. Compared to metallic nickel and nickel oxide, the use of a nickel-silicon alloy for the ultrathin nickel layer is more conducive to reducing the contact resistance between the conductive film layer and the corresponding N-type / P-type doped silicon layer and achieving a better balance, thereby further improving battery efficiency.

[0108] When the ultrathin nickel layer is a nickel-silicon alloy, the nickel-silicon alloy includes metallic nickel silicide and may also inevitably contain elemental nickel or nickel alloys. This is because during preparation, such as when sputtering a nickel target with magnetron sputtering, part of the sputtered nickel will react with the silicon on the surface of the semiconductor layer to form metallic nickel silicide. It may also be doped with unreacted elemental nickel and its alloy form with elements such as silicon.

[0109] More preferably, the nickel-silicon alloy contains Ni₂Si. The nickel-silicon alloy may or may not contain NiSi. Compared to other non-nickel alloys, the preferred Ni₂Si-containing nickel-silicon alloy used in this invention is more conducive to forming a low-barrier contact interface between the doped silicon layer and the conductive film layer.

[0110] In this invention, a second semiconductor opening region is formed in the region between adjacent first doped silicon layers. The width W1 of the second semiconductor opening region is preferably 400-800µm.

[0111] In some preferred embodiments of the present invention, the portion of the first doped silicon layer not covered by the second doped silicon layer forms a first semiconductor opening region. The width W2 of the first semiconductor opening region is preferably 100-250µm.

[0112] In some preferred embodiments of the present invention, the outer surface of the corresponding doped silicon layer of the P-type has a partially porous region. In this invention, a porous region refers to a region with a lower material density compared to other regions of the corresponding doped silicon layer of the P-type (e.g., larger pores, an uneven distribution, or a discontinuous shape, as long as the material density is lower than that of adjacent regions within the same layer). By employing the preferred embodiment of the present invention with a porous region, the corresponding doped silicon layer of the P-type is more porous, which is more conducive to increasing the contact area and making it easier to form an ultra-thin nickel layer (especially a nickel-silicon alloy) with nickel, further reducing contact resistance, thereby reducing power loss and improving battery efficiency.

[0113] In some preferred embodiments of the present invention, the depth of the porous region is 1%-100% of the thickness of the corresponding doped silicon layer of the P-type, specifically, it can be 1%, 2%, 5%, 7%, 10%, 13%, 15%, 18%, 20%, 22%, 25%, 27%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, 99%, or 100%, or any range between any two points. Using this preferred depth ratio for the porous region is more conducive to increasing the contact area between the conductive film layer and the corresponding doped silicon layer of the N-type / P-type, thereby further reducing the contact resistance.

[0114] In some preferred embodiments of the present invention, the width W3 of the loose region is smaller than the width W1 of the second semiconductor opening region.

[0115] In some preferred embodiments of the present invention, the ratio of the width W3 of the loose region to the width W1 of the first semiconductor opening region is (20-95):100, specifically, it can be 20:100, 25:100, 30:100, 35:100, 40:100, 45:100, 50:100, 55:100, 60:100, 65:100, 70:100, 75:100, 80:100, 85:100, 90:100, or 95:100, or any range between any two values. This preferred embodiment is more conducive to increasing the contact area, thereby further reducing the contact resistance and further improving battery efficiency.

[0116] In some preferred embodiments of the present invention, the back contact battery further includes a metal transition layer disposed outside the conductive film layer, wherein the metal transition layer is a metal or a metal alloy. In this preferred embodiment, the present invention further provides a metal transition layer outside the conductive film layer, which can significantly reduce the contact resistance between the conductive film layer and the grid line electrode, and is suitable for silver-copper paste electrodes, and can use low-silver electrodes or pure copper electrodes.

[0117] In the metal transition layer, the metal can be, for example, nickel, silver, tin, etc., and the metal alloy can be, for example, copper-nickel alloy, nickel-chromium alloy, etc.

[0118] Preferably, the metal transition layer of this invention is a nickel layer or a copper-nickel alloy layer, which is more conducive to reducing contact resistance and is suitable for silver-copper paste electrodes.

[0119] In some preferred embodiments of the present invention, the thickness of the metal transition layer is 0.2-1 nm, specifically, it can be 0.2 nm, 0.3 nm, 0.4 nm, 0.5 nm, 0.55 nm, 0.6 nm, 0.65 nm, 0.7 nm, 0.75 nm, 0.8 nm, 0.85 nm, 0.9 nm, 0.95 nm, 0.99 nm, or 1.00 nm, or any range between any two values. The present invention uses a thinner metal transition layer, which is more conducive to reducing parasitic absorption and further improving battery efficiency.

[0120] In some preferred embodiments of the present invention, the first semiconductor region further includes a first passivation layer located between the back side of the silicon wafer and the first doped silicon layer, and the second semiconductor region includes a second passivation layer located between the back side of the silicon wafer and the second doped silicon layer. The first passivation layer and the second passivation layer are each independently silicon oxide or intrinsic amorphous silicon. The first passivation layer and the second passivation layer can both be attached to the back side of the silicon wafer, or portions of the first passivation layer and the second passivation layer can be respectively attached to the back side of the silicon wafer, with portions stacked in the thickness direction. The first doped silicon layer and the second doped silicon layer can be amorphous silicon, microcrystalline silicon, or polycrystalline silicon of corresponding doping types.

[0121] Furthermore, the thickness of silicon oxide and intrinsic amorphous silicon can refer to the range in the prior art and can both be used in this invention. For example, the thickness of silicon oxide is 1-2 nm and the thickness of the intrinsic amorphous silicon layer is 5-15 nm.

[0122] In some preferred embodiments of the present invention, the first semiconductor region further includes a tunneling oxide layer located between the back side of the silicon wafer and the first doped silicon layer, and the second semiconductor region includes an intrinsic amorphous silicon layer located between the back side of the silicon wafer and the second doped silicon layer. The two ends of the intrinsic amorphous silicon layer extend along the ends of the second doped silicon layer to the outer surface of the adjacent ends of the first doped silicon layer to form a transition region (i.e., partially stacked in the thickness direction). The present invention can be used in back contact batteries with a combined passivation structure. The scheme of the present invention uses an ultrathin nickel layer, which can avoid the metal depth diffusion in the ultrathin nickel layer into the intrinsic amorphous silicon layer in the combined passivation structure, thus avoiding affecting the passivation effect.

[0123] In some preferred embodiments of the present invention, the first doped silicon layer is an N-type doped polycrystalline silicon layer, and the second doped silicon layer is a P-type doped amorphous silicon layer. In this structure, the N-type polycrystalline silicon has high lateral conductivity and easily forms a good ohmic contact with the conductive film layer; the P-type amorphous silicon has poor lateral conductivity and is more likely to form a non-ohmic contact with the conductive film layer, resulting in a higher contact resistance. However, by combining the specific ultrathin nickel layer of the present invention with its appropriate thickness ratio to the P-type doped amorphous silicon layer and the conductive film layer, it is possible to achieve good contact between the two semiconductor regions (especially the P-type semiconductor region) and a low-resistance connection with the conductive film layer.

[0124] In some preferred embodiments of the present invention, the back contact battery further includes a front passivation antireflection layer disposed on the front side of the silicon wafer facing outwards. The front passivation antireflection layer can be, for example, a stack of a passivation layer and an antireflection layer, and its type and thickness can refer to the range in the prior art, all of which can be used in the present invention. For example, the passivation layer can be one or more of silicon oxide, amorphous silicon, and aluminum oxide, and the passivation layer thickness can be, for example, 2-30 nm. For example, the antireflection layer can be, for example, a silicon dielectric film, such as silicon nitride, silicon oxynitride, silicon oxide, etc., and the antireflection layer thickness is 50-180 nm.

[0125] Preferably, in this invention, the back surface of a portion of the silicon wafer located at the second semiconductor opening region is a textured surface, and the back surface of a portion of the silicon wafer located at the position corresponding to the first semiconductor layer is a polished surface.

[0126] In some preferred embodiments of the present invention, the front side of the silicon wafer is a textured surface.

[0127] More preferably, the pyramid height of each velvet surface in the present invention is independently 0.1-5μm.

[0128] In this invention, the gate electrode includes a fine gate electrode. This invention can also incorporate conventional structures such as the main gate electrode and optional insulating layer, as required by existing technologies, which will not be elaborated upon here.

[0129] Secondly, the present invention provides a method for preparing a back contact battery, comprising the following steps:

[0130] S100. A silicon wafer is provided with a first semiconductor region and a second semiconductor region alternately arranged on the back side. The first semiconductor region includes a first doped silicon layer, the second semiconductor region includes a second doped silicon layer, and the end of the second doped silicon layer extends to the outer surface of the end of the adjacent first doped silicon layer to form a transition region. One of the first doped silicon layer and the second doped silicon layer is N-type and the other is P-type.

[0131] S110. Using thermal evaporation or magnetron sputtering, an ultrathin nickel layer is formed on at least the outer surface of the corresponding doped silicon layer of the P-type back side obtained in S100.

[0132] S120. A conductive film layer is formed on the outer surface of the ultrathin nickel layer by magnetron sputtering. In this invention, while forming the conductive film layer by magnetron sputtering, the heat from the magnetron sputtering can also promote at least a portion of the ultrathin nickel layer to become more dense or promote further reaction of unreacted metals therein, forming an ultrathin nickel layer with a maximum thickness of 0.1-1.8 nm. The magnetron sputtering in this step of the present invention can also simultaneously promote the formation of a denser film layer of the ultrathin nickel layer.

[0133] In this invention, the ultrathin nickel layer can be continuously or discontinuously distributed, and can be controlled by adjusting the power, pulse switching ratio, transmission speed, gas flow rate, process pressure, etc.

[0134] In one specific embodiment of the present invention, the thickness of the ultrathin nickel layer obtained in S110 is slightly thicker than that of the ultrathin nickel layer finally obtained in S120. After the ultrathin nickel layer is formed by magnetron sputtering in S120, the thickness becomes thinner and denser. The thickness of the ultrathin nickel layer of the present invention only needs to meet the requirement of forming an ultrathin nickel layer with a final thickness of 0.1-1.8 nm.

[0135] Preferably, the substrate temperature is maintained at 150-200°C during the formation of the conductive film layer.

[0136] Preferably, the ratio of the maximum thickness of the ultrathin nickel layer to the thickness of the corresponding doped silicon layer of the P-type and the thickness of the conductive film layer is 1:(10-600):(30-800).

[0137] In this invention, the preparation method further includes S130, forming an insulating groove on a portion of the ultrathin nickel layer corresponding to the transition region and its corresponding conductive film layer.

[0138] Preferably, the fabrication method of this invention further includes step S140, forming gate line electrodes on the outer surfaces of corresponding regions on the outer surfaces of the first semiconductor region and the second semiconductor region, respectively. Here, the gate line electrodes are conventional fine gate electrodes.

[0139] In some preferred embodiments of the present invention, the preparation method further includes: after S100, performing laser marking on the corresponding doped silicon layer of the P-type corresponding to the non-transition region, so that the corresponding doped silicon layer of the P-type in the laser-marked region is in a loose state; and then performing S110. The present invention uses laser marking to obtain a loose region in the corresponding doped silicon layer of the P-type, which is more conducive to reducing contact resistance.

[0140] In some preferred embodiments of the present invention, the conditions for laser marking processing include: a laser wavelength of 325-1100 nm and an energy density of 1-200 mJ / cm². 2 ; and / or, the laser used for laser marking is a nanosecond, picosecond, or femtosecond laser. Laser marking under these preferred conditions is more conducive to reducing contact resistance and further improving battery efficiency.

[0141] In some preferred embodiments of the present invention, the preparation method further includes: after S110, laser irradiating the back ultrathin nickel layer, followed by S120. This preferred approach further improves the silanization rate of the metal in the ultrathin nickel layer and reduces the contact resistance.

[0142] In some preferred embodiments of the present invention, the laser irradiation conditions include: a laser wavelength of 325-1100 nm and an energy density of 1-200 mJ / cm². 2 And / or, the laser used for laser irradiation is a nanosecond, picosecond, or femtosecond laser. Laser irradiation under these preferred conditions is more conducive to reducing contact resistance and further improving battery efficiency.

[0143] In some preferred embodiments of the present invention, the preparation method further includes: controlling the conductive film layer to be a transparent conductive film layer, and after S130, sputtering a metal transition layer on the outside of the transparent conductive film layer, and then performing S130. The preferred scheme of the transparent conductive film layer and the metal transition layer in the present invention is more conducive to reducing contact resistance and further improving battery efficiency. The type and thickness of the metal transition layer are the same as those in the first aspect, and will not be repeated here.

[0144] In some preferred embodiments of the present invention, in S110, the deposition rate of the thermal evaporation process is controlled to be 0.02-0.05 nm / s. The present invention employs a low deposition rate thermal evaporation process, which is more conducive to controlling the precision and thickness of the ultrathin nickel layer and improving the uniformity of the film.

[0145] In some preferred embodiments of the present invention, the conditions for the thermal evaporation process include: using a target metal target material, and a base vacuum of <5×10⁻⁶. -4 Pa. Background vacuum <5×10⁻⁶ Pa. -4 Pa is more conducive to reducing the oxidation of metals (such as Ni) in ultrathin nickel layers.

[0146] In some preferred embodiments of the present invention, the deposition rate of magnetron sputtering in S110 is controlled to be 0.03-0.08 nm / s. The use of low deposition rate magnetron sputtering in S110 of the present invention is more conducive to effectively avoiding damage to the surface of the corresponding doped silicon layer of the P-type layer that may be caused by high-energy Ar ions and sputtering particles from magnetron sputtering, thereby helping to ensure higher battery efficiency.

[0147] Preferably, in S110, the substrate temperature during magnetron sputtering is maintained at 150-200°C, which helps to avoid thermal damage to other film layers and ensures the passivation effect.

[0148] In some preferred embodiments of the present invention, the conditions for the magnetron sputtering process in S110 include: using a target metal target, introducing argon gas, a process pressure of 0.5-1.0 Pa, and a DC power supply of 20-50 W. The magnetron sputtering process in S110 of the present invention uses extremely low DC power, suitable process pressure, and an argon atmosphere, which is more conducive to reducing the energy and deposition rate of sputtered particles, thereby achieving precise control over the thickness of the ultrathin nickel layer. More preferably, the flow rate of the introduced argon gas is 100-5000 sccm.

[0149] In this invention, the target metal target can be determined based on the material of the target ultrathin nickel layer, such as a nickel metal target, a nickel oxide target, or a nickel-containing alloy target. The metal target is a high-purity target, and one or more targets can be used for co-sputtering. Multiple targets can be one of the aforementioned types along with other non-metallic targets such as silicon targets. Preferably, the metal target used in the thermal evaporation process has a purity ≥99.99%. Preferably, the metal target used in the magnetron sputtering process has a purity ≥99.95%. In this invention, when the desired ultrathin nickel layer is nickel oxide, it can be achieved by using a nickel oxide target or by introducing argon and oxygen into the magnetron sputtering process in S110, with the oxygen flow rate determined by the generation of the target nickel oxide. For example, the oxygen flow rate can be 10-1000 sccm.

[0150] In some preferred embodiments of the present invention, an ultrathin nickel layer is formed on the outer surfaces of both the first doped silicon layer and the second doped silicon layer in S110.

[0151] Magnetron sputtering typically employs a simultaneous deposition and transport method, with the target thickness usually achieved within 20-30 seconds. In this invention, the magnetron sputtering time can be adjusted according to actual needs until the target thickness is reached.

[0152] Preferably, the working pressure of magnetron sputtering during the formation of the conductive film layer in S120 is 0.3-0.8 Pa. It is understood that the target material for magnetron sputtering during the formation of the conductive film layer is determined according to the material of the target conductive film layer. For example, if the material of the conductive film layer is ITO, the target material is In by mass percentage. 2 O 3 :SnO 2 = 90:10.

[0153] Further research revealed that a thin layer of native oxide forms on the surface of each semiconductor region during transport, acting as an additional barrier layer and increasing contact resistance. Therefore, in some preferred embodiments of the present invention, step S110 further includes: performing a surface pretreatment on the back side obtained in S100 to remove oxides and contaminants before proceeding with the step of forming the ultrathin nickel layer. Surface pretreatment ensures direct contact between the semiconductor region surface and the ultrathin nickel layer, which is more conducive to the subsequent formation of a high-quality ultrathin nickel layer.

[0154] In some preferred embodiments of the present invention, the surface pretreatment is performed by immersion in HF solution or vacuum plasma cleaning.

[0155] Preferably, the conditions for soaking in HF solution include: the volume concentration of HF in the HF solution is 0.5%-1%, and the soaking time is 10-30 s.

[0156] Preferably, the conditions for vacuum plasma cleaning include: a vacuum environment, the presence of an inert gas, a flow rate of 20-50 sccm, and a pressure of 0.5-2 Pa. The vacuum plasma cleaning of this invention employs a full vacuum process, ensuring the surface is no longer exposed to the atmosphere and preventing re-oxidation.

[0157] Preferably, the plasma bombardment cleaning time for vacuum plasma cleaning is 30-60 s.

[0158] Preferably, the power of the vacuum plasma cleaning is 30-80 W. This invention uses low-power vacuum plasma cleaning, which is more conducive to preventing damage to the semiconductor silicon layer (such as the first doped silicon layer and the second doped silicon layer).

[0159] In some preferred embodiments of the present invention, S110 further includes annealing after the step of forming the ultrathin nickel layer, to promote the reaction in S120 that forms the ultrathin nickel layer. Annealing is preferably short-time low-temperature annealing. Of course, if the magnetron sputtering heat budget in the process of forming the conductive film layer in S120 is sufficient to promote the formation of the ultrathin nickel layer, then the annealing step is unnecessary.

[0160] Preferably, the conditions for short-time low-temperature annealing include: an annealing temperature of 180-200℃ and a time of 5-10 min. Low-temperature annealing not exceeding 200℃ is beneficial for protecting the film layer (such as N / P semiconductors) from damage and for rapidly forming a high-quality film layer in a shorter time.

[0161] Preferably, the short-time low-temperature annealing is carried out in an atmosphere including nitrogen or a forming gas containing nitrogen and hydrogen, which is more conducive to avoiding oxidation.

[0162] In some preferred embodiments of the present invention, the preparation method further includes depositing a front passivation antireflection layer on the front side of the silicon wafer.

[0163] In some preferred embodiments of the present invention, S100, providing a silicon wafer with alternating first and second semiconductor regions arranged on the back side, specifically includes:

[0164] S101, provides double-sided polished silicon wafers;

[0165] S102. A first semiconductor layer and a mask layer are sequentially formed on the back side of the silicon wafer;

[0166] S103. A first etching opening is made on the back side obtained in S102 to form a second semiconductor opening region;

[0167] S104. Texturing and cleaning: A texturing surface is formed on the front side of the silicon wafer and the second semiconductor opening area, and then the mask layer is completely removed or a portion of the mask layer is retained.

[0168] S106. Deposit a second semiconductor layer on the back side;

[0169] S107. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0170] The mask layer described in S102 can be a silicon dielectric layer, such as at least one of phosphosilicate glass (which can be a PSG layer naturally formed during the formation of the first semiconductor layer), silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the mask layer can refer to existing technologies, all of which can be used in this invention, and will not be elaborated further here.

[0171] In some preferred embodiments of the present invention, in S100, the first semiconductor region further includes a tunneling oxide layer located between the back side of the silicon wafer and the first doped silicon layer, and the second semiconductor region includes an intrinsic amorphous silicon layer located between the back side of the silicon wafer and the second doped silicon layer, wherein the two ends of the intrinsic amorphous silicon layer extend along the end of the second doped silicon layer to the outer surface of the adjacent end of the first doped silicon layer to form a transition region.

[0172] Thirdly, the present invention provides a back contact battery, which is prepared by the method for preparing a back contact battery described in the second aspect. The structure and performance of the back contact battery of the third aspect of the present invention are the same as those of the back contact battery of the first aspect, and will not be described again here.

[0173] Fourthly, the present invention provides a battery assembly comprising the back contact battery described in the first aspect, or the back contact battery described in the third aspect.

[0174] The embodiments of the present invention described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0175] Example 1

[0176] A back-contact battery, the structure of which is as follows Figure 1 As shown, the wafer includes a first semiconductor region and a second semiconductor region disposed alternately on the back side of the silicon wafer 1. The first semiconductor region includes a tunneling oxide layer 2 with a thickness of 1.5 nm and a first doped silicon layer 3 (specifically, an N-type doped polysilicon layer with a thickness of 120 nm and an effective doping concentration of 4e19cm) disposed sequentially. -3 The second semiconductor region includes an intrinsic amorphous silicon layer 4 with a thickness of 10 nm and a second doped silicon layer 5 (specifically a P-type doped amorphous silicon layer with a thickness of 12 nm and an effective doping concentration of 3e19cm) sequentially disposed thereon. -3The silicon wafer 1 consists of a first semiconductor region and a second semiconductor region. The second doped silicon layer 5 extends to the outer surface of the adjacent first doped silicon layer 3 to form a transition region. The wafer also includes a non-continuous ultrathin nickel layer 6 (specifically, an ultrathin nickel-silicon alloy layer with a maximum thickness of 0.2 nm and a work function of 4.8 eV) covering the outer surfaces of the first and second semiconductor regions and arranged outwards, and a conductive film layer 7 (specifically, a transparent conductive film layer of ITO) with a thickness of 50 nm. Insulating grooves are formed on the portion of the ultrathin nickel layer 6 corresponding to the transition region and its corresponding conductive film layer 7. Gate electrodes 8 are respectively disposed outside the corresponding conductive film layers 7 on the outer surfaces of the first and second semiconductor regions. A passivation layer 9 and an anti-reflection layer 10 are sequentially disposed on the front side of the silicon wafer 1. The absolute values ​​of the work function difference between the ultrathin nickel layer 6 and the second doped silicon layer 5, and between the ultrathin nickel layer 6 and the conductive film layer 7, are 0.2 eV and 0.3 eV, respectively.

[0177] It is prepared by the following method:

[0178] S100 includes: S101, a silicon wafer 1 that is provided for double-sided polishing;

[0179] S102, A first semiconductor layer and a mask layer are sequentially formed on the back side of silicon wafer 1;

[0180] S103. A first etching opening is made on the back side obtained in S102 to form a second semiconductor opening region;

[0181] S104. Texturing and cleaning: A texturing surface is formed on the front side of silicon wafer 1 and the second semiconductor opening area, and then the mask layer is completely removed; the width W1 of the second semiconductor opening area is 500µm.

[0182] S106. A passivation layer 9 and an anti-reflection layer 10 are deposited on the front side of silicon wafer 1, and a second semiconductor layer is deposited on the back side.

[0183] S107. A second etching opening is made on a portion of the second semiconductor layer on the back side of silicon wafer 1 to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region. The width W2 of the first semiconductor opening region is 200µm.

[0184] S110. First, perform surface pretreatment on the back side obtained in S100 to remove oxides and contaminants. The surface pretreatment method is to soak in an HF solution with a volume concentration of 0.7% for 15 seconds.

[0185] Then, an ultrathin nickel layer 6 (specifically an ultrathin nickel-silicon alloy layer) was formed on the back side of the S100 using a magnetron sputtering process. The conditions for the magnetron sputtering process included: using a target metal target (specifically a nickel target with a mass purity ≥ 99.99%), introducing argon gas at 500 sccm, a process pressure of 0.8 Pa, a DC power supply of 30 W, a substrate temperature of 150℃, and a deposition rate of 0.03 nm / s.

[0186] S120. A conductive film layer 7 is formed on the outer surface of the ultrathin nickel layer 6 by magnetron sputtering (using a transport-while-deposit method), while simultaneously promoting the further reaction of unreacted metals in the ultrathin nickel layer 6 to form metal silicides to create an ultrathin nickel-silicon alloy layer; wherein, the magnetron sputtering conditions during the formation of the conductive film layer 7 are controlled as follows: by mass percentage, the target material is In. 2 O 3 :SnO 2 = 90:10 ITO, substrate temperature maintained at 180℃, working pressure at 0.5 Pa, deposited to the target thickness;

[0187] S130. An insulating groove is formed on the portion of the ultrathin nickel layer 6 corresponding to the transition region and its corresponding conductive film layer 7.

[0188] S140, gate electrodes 8 are formed on the outer surfaces of the corresponding conductive film layers 7 of the first semiconductor region and the second semiconductor region, respectively.

[0189] Example 2

[0190] The process was carried out in accordance with Example 1, except that the magnetron sputtering time in S110 was adjusted to 34 s so that the maximum thickness of the final ultrathin nickel layer 6 was 1 nm. At this time, the work function of the final ultrathin nickel layer 6 was 4.82 eV.

[0191] Example 3

[0192] The process was carried out in accordance with Example 1, except that the sputtering substrate temperature in S110 was adjusted to 180°C, so that the work function of the final ultrathin nickel layer 6 was 4.86 eV and the thickness remained unchanged.

[0193] Example 4

[0194] The same procedure was followed as in Example 1, except that the thickness of the conductive film layer 7 was adjusted to 100 nm.

[0195] Example 5

[0196] The procedure was carried out in accordance with Example 1, except that the work function of the second doped silicon layer 5 was adjusted to 5.1 eV by changing the effective doping concentration of the second doped silicon layer 5. After conversion, the absolute value of the difference in work function between the ultrathin nickel layer 6 and the P-type second doped silicon layer 5 is 0.3 eV.

[0197] Example 6

[0198] The procedure is carried out in accordance with Example 1, except that the outer surface of the second doped silicon layer 5 of the P-type type has a partially loose region 51, such as... Figure 2 As shown, the depth of the loose region 51 is 50% of the thickness of the second doped silicon layer 5 of the P-type, and the width W3 of the loose region 51 is smaller than the width W1 of the second semiconductor opening region, W3:W1=80:100. The corresponding fabrication process and parameters that need to be adjusted to meet this condition are as follows: After S107, the P-type second doped silicon layer 5 of the second semiconductor opening region is laser-etched to make the P-type second doped silicon layer 5 of the laser-etched region loose; then S110-S140 are performed, and the final battery structure is shown below. Figure 3 As shown, the conditions for laser marking include: using a laser with a pulse width of 100 ns, a wavelength of 532 nm, a flat-topped laser spot, and a laser energy density of 100 mJ / cm². 2 The final absolute value of the work function difference between the ultrathin nickel layer 6 and the second doped silicon layer 5 is 0.1 eV.

[0199] Example 7

[0200] The procedure is carried out in accordance with Example 1, except that after S120, a metal transition layer with a thickness of 0.2 nm is formed on the outside of the conductive film layer 7 by magnetron sputtering. The metal transition layer is a nickel layer; then S130-S140 are performed.

[0201] Example 8

[0202] The procedure was carried out in accordance with Example 1, except that after S110, the ultrathin nickel layer 6 on the back side was further irradiated with a laser to further increase the silane content of the metal and thus further reduce the resistance, followed by S120-S140. The laser irradiation conditions included: using a laser with a pulse width of 20 ps, ​​a wavelength of 532 nm, a flat-top laser spot, and a laser energy density of 5 mJ / cm². 2 In this embodiment, the resulting ultrathin nickel layer 6 is continuously distributed and has a resistivity of 12 μΩ·cm and a work function of 5.0 eV. The absolute value of the work function difference between the ultrathin nickel layer 6 and the second doped silicon layer 5, and the absolute value of the work function difference between the ultrathin nickel layer 6 and the conductive film layer 7 are 0 eV and 0.5 eV, respectively.

[0203] Example 9

[0204] The process was carried out in accordance with Example 1, except that the ultrathin nickel layer 6 was nickel oxide of the same thickness. To meet this condition, the corresponding preparation process and parameters needed to be adjusted as follows: in S110, argon gas was introduced at 450 sccm and oxygen gas at 50 sccm, and the process pressure was 0.8 Pa. The work function of the final ultrathin nickel layer 6 obtained in this example was 5.2 eV. The absolute values ​​of the work function difference between the ultrathin nickel layer 6 and the second doped silicon layer 5, and the absolute values ​​of the work function difference between the ultrathin nickel layer 6 and the conductive film layer 7, were 0.2 eV and 0.7 eV, respectively.

[0205] Example 10

[0206] The process was carried out in accordance with Example 1, except that the conductive film layer 7 was replaced with a composite film layer consisting of a 50 nm thick transparent conductive film layer (specifically ITO) and a 100 nm thick metal conductive film (specifically copper). To meet this requirement, the corresponding preparation process and parameters needed to be adjusted as follows: in S120, after depositing the ITO film layer, a 100 nm thick copper metal film was deposited by magnetron sputtering. The absolute value of the work function difference between the ultrathin nickel layer 6 and the conductive film layer 7 is 0.1 eV, and the calculated thickness ratio is 1:750.

[0207] Example 11

[0208] The same procedure was performed as in Example 1, except that the thickness of the first doped silicon layer 3, i.e., the N-type doped polysilicon layer, was adjusted to 50 nm, while the doping concentration remained unchanged.

[0209] Comparative Example 1

[0210] The procedure is carried out in accordance with Example 1, except that the ultrathin nickel layer 6 is not provided, and correspondingly, S110 is not performed.

[0211] Comparative Example 2

[0212] The procedure was carried out in accordance with Example 1, except that the transparent conductive film layer 7 was not provided, and the thickness of the ultrathin nickel layer 6 was adjusted to be continuously distributed and of a normal thickness of 4 nm. In this case, the resistivity of the ultrathin nickel layer 6 was 15 μΩ·cm.

[0213] Comparative Example 3

[0214] The process was carried out in accordance with Example 1, except that the thickness of the ultrathin nickel layer 6 was set to a normal thickness of 4 nm. To meet this condition, the S110 preparation process and parameters that needed to be adjusted were: a magnetron sputtering nickel plating time of 134 s.

[0215] Comparative Example 4

[0216] The same procedure was performed as in Example 1, except that the thickness of the second doped silicon layer 5 of the P-type was adjusted to 40 nm. At this time, the ratio of the maximum thickness of the ultrathin nickel layer 6 to the thickness of the second doped silicon layer 5 was 1:200.

[0217] Comparative Example 5

[0218] The experiment was carried out in accordance with Example 1, except that the substrate temperature during the formation of the conductive film layer 7 in S120 was kept at 250°C, and the thickness of the resulting conductive film layer 7 was 75 nm. The final ultrathin nickel layer 6 had a resistivity of 24 μΩ·cm, a work function of 4.85 eV, and a maximum thickness of 5 nm.

[0219] Comparative Example 6

[0220] The same procedure is followed as in Example 1, except that the ultrathin nickel layer 6 is not provided, and S110 is not performed accordingly. At the same time, the thickness of the first doped silicon layer 3, i.e. the N-type doped polysilicon layer, is adjusted to 100 nm, and the thickness of ITO is 120 nm.

[0221] Test case

[0222] The back contact batteries obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1.

[0223] Table 1

[0224] Performance indicators Open circuit voltage (mV) Minority birth lifetime (µs) Contact resistivity ρc (Ω·cm²) FF (%) Battery efficiency (%) Double-sidedness (%) Example 1 749.5 5900 0.015 87.1 27.55 72 Example 2 747.8 5480 0.011 86.9 27.36 70 Example 3 749.2 6000 0.012 87.1 27.53 72 Example 4 748.8 5950 0.013 87.1 27.51 72 Example 5 749.3 6050 0.012 87.1 27.54 72 Example 6 746.9 5880 0.009 87.2 27.60 72 Example 7 750.5 5910 0.010 87.15 27.59 71 Example 8 750.8 5908 0.013 87.1 27.58 72 Example 9 750.2 5890 0.012 86.9 27.47 73 Example 10 748.5 5850 0.011 87.15 27.57 70 Example 11 750.1 5860 0.012 87.2 27.57 74 Comparative Example 1 747.5 5850 0.065 86.2 27.15 75 Comparative Example 2 741.0 4200 0.180 81.0 25.30 51 Comparative Example 3 744.0 4700 0.009 85.9 26.98 45 Comparative Example 4 742.8 4300 0.028 85.7 26.85 72 Comparative Example 5 743.8 4100 0.014 86.1 27.0 71 Comparative Example 6 747.2 5750 0.045 86.5 27.20 74

[0225] The results above show that, compared with the comparative example, the embodiment of the present invention reduces the contact resistance, increases the open-circuit voltage, and simultaneously improves the overall battery efficiency to over 27.10% and the bifaciality to over 70%.

[0226] In Comparative Example 3, the silicon alloy layer thickness was increased to 4 nm. Although a thicker silicon alloy layer can further reduce local contact resistivity, an excessively thick silicon alloy layer increases light absorption and affects the interface passivation quality, leading to a decrease in open-circuit voltage and minority carrier lifetime, ultimately reducing battery efficiency. In the embodiments of this invention, the silicon alloy layer thickness needs to be controlled within a reasonable range to improve battery efficiency while maintaining bifaciality.

[0227] In Comparative Example 5, the substrate temperature during ITO deposition was increased to 250°C. While higher temperatures are beneficial for improving the density of the ITO film, they can cause thermal damage to the underlying doped silicon layer and passivation layer, thereby reducing minority carrier lifetime and open-circuit voltage, ultimately leading to a decrease in cell efficiency. In contrast, the substrate temperature in this embodiment of the invention is maintained at 150-200°C, which avoids heat loss from the underlying film layers and facilitates higher cell efficiency.

[0228] Furthermore, as can be seen from Examples 1 and 2-10, the preferred scheme of the present invention is more conducive to improving the overall battery efficiency while maintaining a high bifaciality.

[0229] The preferred embodiments of the present invention have been described in detail above; however, the present invention is not limited thereto. Within the scope of the inventive concept, various simple modifications can be made to the technical solutions of the present invention, including combinations of various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in the present invention and are all within the protection scope of the present invention.

Claims

1. A back-contact battery, comprising a silicon wafer having a front side and a back side, a first semiconductor region and a second semiconductor region disposed alternately on the back side of the silicon wafer, the first semiconductor region comprising a first doped silicon layer, the second semiconductor region comprising a second doped silicon layer, and an end of the second doped silicon layer extending to the outer surface of an adjacent end of the first doped silicon layer to form a transition region, wherein one of the first doped silicon layer and the second doped silicon layer is N-type and the other is P-type; characterized in that, Also includes: A continuous or discontinuous ultrathin nickel layer and a conductive film layer are sequentially disposed outward along the thickness direction on the back side. The ultrathin nickel layer at least covers the outer surface of the corresponding doped silicon layer of the P-type. Isolation trenches for isolating the first semiconductor region and the second semiconductor region are disposed on the conductive film layer and the corresponding ultrathin nickel layer, and gate electrodes are respectively disposed on the outer surface of the corresponding conductive film layer of the first semiconductor region and the second semiconductor region. The ultrathin nickel layer is at least one of metallic nickel, nickel oxide or nickel-silicon alloy. The maximum thickness of the ultrathin nickel layer is 0.1-1.8 nm, and the ratio of the maximum thickness of the ultrathin nickel layer to the thickness of the corresponding doped silicon layer of the P-type and the thickness of the conductive film layer is 1:(10-600):(30-800).

2. The back contact battery according to claim 1, characterized in that, The absolute value of the work function difference between the ultrathin nickel layer and the corresponding doped silicon layer or conductive film layer of the P-type is 0-0.7 eV, and / or the work function of the ultrathin nickel layer is 4.5-5.2 eV.

3. The back contact battery according to claim 1, characterized in that, The ultrathin nickel layer is a continuously distributed nickel-silicon alloy with a resistivity of 12-30 μΩ·cm; and / or, The ultrathin nickel layer also covers the outer surface of the corresponding N-type doped silicon layer, and the ratio of the maximum thickness of the ultrathin nickel layer to the thickness of the corresponding N-type doped silicon layer is 1:(15-650).

4. The back contact battery according to claim 1, characterized in that, The thickness of the conductive film is 20-300 nm.

5. The back contact battery according to claim 1 or 4, characterized in that, An isolation trench is disposed on the transition region; and / or, a conductive film layer covers the entire back surface except for the isolation trench.

6. The back contact battery according to claim 1, characterized in that, The thickness of the corresponding doped silicon layer for N-type is 30-200 nm, and the thickness of the corresponding doped silicon layer for P-type is 5-40 nm. And / or, the first doped silicon layer is N-type doped and the second doped silicon layer is P-type doped.

7. The back contact battery according to claim 1, characterized in that, The ultrathin nickel layer also contains doping elements, including boron or phosphorus.

8. The back contact battery according to claim 1, characterized in that, The ultrathin nickel layer is a nickel-silicon alloy containing Ni2Si.

9. The back contact battery according to claim 1, characterized in that, The outer surface of the corresponding doped silicon layer of the P-type has a partially loose region.

10. The back contact battery according to claim 9, characterized in that, The depth of the loose region is 1%-100% of the thickness of the corresponding doped silicon layer of the P-type.

11. The back contact battery according to claim 9 or 10, characterized in that, The region between adjacent first doped silicon layers forms a second semiconductor opening region, and the width W3 of the loose region is smaller than the width W1 of the second semiconductor opening region.

12. The back contact battery according to claim 11, characterized in that, The ratio of the width W3 of the loose region to the width W1 of the first semiconductor opening region is (20-95):

100.

13. The back contact battery according to claim 1 or 4, characterized in that, The back contact battery also includes a metal transition layer disposed outside the conductive film layer.

14. The back contact battery according to claim 13, characterized in that, The thickness of the metal transition layer is 0.2-1 nm, and / or the metal transition layer is a nickel layer or a copper-nickel alloy layer.

15. The back contact battery according to claim 1, characterized in that, The first semiconductor region further includes a first passivation layer located between the back side of the silicon wafer and the first doped silicon layer, and the second semiconductor region includes a second passivation layer located between the back side of the silicon wafer and the second doped silicon layer, wherein the first passivation layer and the second passivation layer are each independently silicon oxide or intrinsic amorphous silicon.

16. The back contact battery according to claim 1, characterized in that, The back contact battery also has at least one of the following structures: Structure 1: The first semiconductor region further includes a tunneling oxide layer located between the back side of the silicon wafer and the first doped silicon layer; the second semiconductor region includes an intrinsic amorphous silicon layer located between the back side of the silicon wafer and the second doped silicon layer; the two ends of the intrinsic amorphous silicon layer extend along the ends of the second doped silicon layer to the outer surface of the adjacent ends of the first doped silicon layer to form a transition region. Structure 2: The first doped silicon layer is an N-type doped polycrystalline silicon layer, and the second doped silicon layer is a P-type doped amorphous silicon layer; Structure 3: The back contact cell also includes a front passivation and anti-reflection layer disposed on the front side of the silicon wafer facing outwards; Structure 4: The area of ​​the first doped silicon layer not covered by the second doped silicon layer forms the first semiconductor opening region; the back surface of the silicon wafer located at the second semiconductor opening region is a textured surface; and the back surface of the silicon wafer located at the position corresponding to the first semiconductor layer is a polished surface. Structure 5: The front side of the silicon wafer is textured.

17. A method for preparing a back-contact battery, characterized in that, Includes the following steps: S100. A silicon wafer is provided with a first semiconductor region and a second semiconductor region alternately arranged on the back side. The first semiconductor region includes a first doped silicon layer, the second semiconductor region includes a second doped silicon layer, and the end of the second doped silicon layer extends to the outer surface of the end of the adjacent first doped silicon layer to form a transition region. One of the first doped silicon layer and the second doped silicon layer is N-type and the other is P-type. S110. Using thermal evaporation or magnetron sputtering, an ultrathin nickel layer is formed on at least the outer surface of the corresponding doped silicon layer of the P-type back side obtained in S100. S120. A conductive film layer is formed on the outside of the ultrathin nickel layer by magnetron sputtering, wherein the substrate temperature is controlled to be maintained at 150-200℃ during the formation of the conductive film layer; the ratio of the maximum thickness of the ultrathin nickel layer to the thickness of the corresponding doped silicon layer of the P-type and the thickness of the conductive film layer is 1:(10-600):(30-800), and the maximum thickness of the ultrathin nickel layer is 0.1-1.8nm; S130. An insulating groove is formed on the portion of the ultrathin nickel layer corresponding to the transition region and its corresponding conductive film layer. S140, gate electrodes are formed on the outer surfaces of corresponding regions on the outer surfaces of the first semiconductor region and the second semiconductor region, respectively.

18. The method for preparing a back contact battery according to claim 17, characterized in that, The preparation method further includes: after S100, laser marking is performed on the corresponding doped silicon layer of the P-type corresponding to the non-transition region, so that the corresponding doped silicon layer of the P-type in the laser marking region is in a loose state; then S110 is performed.

19. The method for preparing a back contact battery according to claim 18, characterized in that, The conditions for laser marking include: laser wavelength of 325-1100 nm and energy density of 1-200 mJ / cm³. 2 ; and / or, the laser used for laser marking is a nanosecond, picosecond, or femtosecond laser.

20. The method for preparing a back contact battery according to claim 17, characterized in that, The preparation method also includes: after S110, laser irradiation is performed on the back ultrathin nickel layer, followed by S120.

21. The method for preparing a back contact battery according to claim 20, characterized in that, The conditions for laser irradiation include: laser wavelength of 325-1100nm and energy density of 1-200mJ / cm³. 2 ; and / or, the laser used for laser irradiation is a nanosecond, picosecond, or femtosecond laser.

22. The method for preparing a back contact battery according to claim 17, characterized in that, The preparation method further includes: controlling the conductive film layer to be a transparent conductive film layer, and after S130, sputtering a metal transition layer on the outside of the transparent conductive film layer, and then performing S130.

23. The method for preparing a back contact battery according to claim 17, characterized in that, In S110, the deposition rate of the thermal evaporation process is controlled to be 0.02-0.05 nm / s; and / or, the conditions for the thermal evaporation process include: using a target metal target and a base vacuum <5×10⁻⁶. -4 Pa.

24. The method for preparing a back contact battery according to claim 17, characterized in that, The conditions for the magnetron sputtering process in S110 include: a deposition rate controlled at 0.03-0.08 nm / s and a substrate temperature maintained at 150-200℃; And / or, the conditions for the magnetron sputtering process in S110 include: using a target metal target, introducing argon gas, a process pressure of 0.5-1.0 Pa, and a DC power supply of 20-50 W.

25. The method for preparing a back contact battery according to claim 17, characterized in that, The working pressure of magnetron sputtering during the formation of the conductive film layer of S120 is 0.3-0.8 Pa.

26. The method for preparing a back contact battery according to claim 17, characterized in that, S110 also includes: first performing surface pretreatment on the back side obtained in S100 to remove oxides and contaminants from the back side, and then performing the step of forming an ultrathin nickel layer.

27. The method for preparing a back contact battery according to claim 26, characterized in that, Surface pretreatment methods include immersion in HF solution or vacuum plasma cleaning, wherein... The conditions for soaking in HF solution include: the volume concentration of HF in the HF solution is 0.5%-1%, and the soaking time is 10-30 s; The conditions for vacuum plasma cleaning include: in a vacuum environment, in the presence of an inert gas, with an inert gas flow rate of 20-50 sccm, a power of 30-80 W, a pressure of 0.5-2 Pa, and a plasma bombardment cleaning time of 30-60 s.

28. The method for preparing a back contact battery according to claim 17 or 26, characterized in that, S110 also includes: after performing the step of forming the ultrathin nickel layer, a short-time low-temperature annealing is also performed; wherein, The conditions for short-time low-temperature annealing include: annealing temperature of 180-200℃ and time of 5-10 min; And / or, short-time low-temperature annealing is carried out in an atmosphere including nitrogen or a forming gas containing nitrogen and hydrogen.

29. The method for preparing a back contact battery according to claim 17, characterized in that, The preparation method also includes at least one of the following processes: In process 1, an ultrathin nickel layer is formed on the outer surface of both the first doped silicon layer and the second doped silicon layer in S110. Process 2, the preparation method also includes depositing a front passivation antireflection layer on the front side of the silicon wafer; Process 3, S100, provides a silicon wafer with alternating first and second semiconductor regions arranged on the back side, specifically including: S101, provides double-sided polished silicon wafers; S102. A first semiconductor layer and a mask layer are sequentially formed on the back side of the silicon wafer; S103. A first etching opening is made on the back side obtained in S102 to form a second semiconductor opening region; S104, texturing and cleaning, forming a textured surface on the front side of the silicon wafer and the second semiconductor opening area, and then completely removing the mask layer or retaining part of the mask layer. S106. Deposit a second semiconductor layer on the back side; S107. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region. In process four, S100, the first semiconductor region further includes a tunneling oxide layer located between the back side of the silicon wafer and the first doped silicon layer, and the second semiconductor region includes an intrinsic amorphous silicon layer located between the back side of the silicon wafer and the second doped silicon layer. The two ends of the intrinsic amorphous silicon layer extend along the ends of the second doped silicon layer to the outer surface of the adjacent ends of the first doped silicon layer to form a transition region.

30. A back-contact battery, characterized in that, It is prepared by the method for preparing a back contact battery as described in any one of claims 17-29.

31. A battery assembly, characterized in that, It includes the back contact battery as described in any one of claims 1-16, or the back contact battery as described in claim 30.

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