Flip high-voltage LED chip and preparation method thereof

Abstract

The present application relates to the technical field of LED, and discloses a flip high-voltage LED chip and a preparation method thereof.The flip high-voltage LED chip comprises a substrate and an epitaxial layer stacked on the substrate, a bonding layer is arranged between the substrate and the epitaxial layer, a P-type conductive step and an isolation groove are formed on the bonding layer, an ohmic contact layer, a first passivation layer, a bridging metal layer and a second passivation layer are arranged on the bonding layer, and an electrode layer is arranged on the second passivation layer; wherein the isolation groove comprises a first isolation groove and a second isolation groove, a thimble buffer layer is formed on the bonding layer, the thimble buffer layer is arranged in the second isolation groove, the thimble buffer layer comprises a Ti layer and an Al layer arranged in sequence, and an oxide layer is formed on the Al layer. By implementing the present application, cracks caused by thimble impact in the functional layer of the flip high-voltage LED chip can be avoided, the leakage rate is reduced, the reliability is improved, and the service life of the thimble is prolonged.

Description

Technical Field

[0001] This invention relates to the field of LED chip technology, and in particular to a flip-chip high-voltage LED chip and its fabrication method. Background Technology

[0002] AlGaInP-based red and yellow light and AlGaAs-based near-infrared flip-chip high-voltage LED chips typically use a transparent bonding layer to bond the epitaxial layer to a transparent sapphire substrate. However, the sapphire substrate is a heterogeneous non-native substrate, which is different from the structure of GaN-based LEDs that are directly grown on a native sapphire substrate. As a result, the overall structural strength of the epitaxial layer of this type of flip-chip high-voltage LED chip is relatively weak, and it is prone to damage during subsequent processing.

[0003] Meanwhile, during the die bonding process, the sapphire substrate side (back side) of the flip-chip high-voltage LED faces upwards, while the electrode side (front side) faces downwards, ensuring precise bonding with the substrate. In practice, the die bonder's pins need to lift the chip from the front side to complete pick-up, placement, and positioning. The impact force of the pins acts directly on the front side of the chip, easily damaging the flip-chip high-voltage LED. In particular, when the pin tip strikes the trench area, the insulating protective layer on the trench sidewalls is prone to cracking, and even the epitaxial layer may crack, leading to potential reliability issues such as leakage after die bonding.

[0004] Therefore, there is an urgent need for a technical solution to address the damage to the trench area caused by pin impact during the die bonding process, in order to improve the structural stability of flip-chip high-voltage LEDs in the die bonding process, avoid reliability risks such as leakage, and ensure the production yield and performance of the chips. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a flip-chip high voltage LED chip and its preparation method, which can avoid cracks in the functional layer of the flip-chip high voltage LED chip caused by the impact of the ejector pin, reduce the leakage rate, thereby improving its reliability and extending the service life of the ejector pin.

[0006] To address the aforementioned technical problems, the first aspect of the present invention provides a flip-chip high-voltage LED chip, comprising a substrate and an epitaxial layer stacked on the substrate, wherein a bonding layer is provided between the substrate and the epitaxial layer;

[0007] The bonding layer has P-type conductive steps and isolation trenches, and the isolation trenches divide the flip-chip high-voltage LED into several light-emitting units;

[0008] The bonding layer is provided with an ohmic contact layer, a first passivation layer, a bridging metal layer and a second passivation layer. The first passivation layer covers the ohmic contact layer. The bridging metal layer is disposed on the first passivation layer and is connected to the ohmic contact layer of the adjacent light-emitting unit through a first via and a second via. The second passivation layer covers the bridging metal layer.

[0009] An electrode layer is provided on the second passivation layer, and the electrode layer is connected to the ohmic contact layer through a third through hole and a fourth through hole;

[0010] The isolation trench includes a first isolation trench and a second isolation trench. A pin buffer layer is formed on the bonding layer. The pin buffer layer is disposed in the second isolation trench. The pin buffer layer includes a Ti layer and an Al layer arranged sequentially. An oxide layer is formed on the Al layer.

[0011] As an improvement to the above scheme, the growth thickness of the Ti layer is 5nm-200nm;

[0012] The Al layer has a growth thickness of 100nm-3000nm;

[0013] The oxide layer is an Al2O3 layer formed by plasma surface treatment of an Al layer, and the thickness of the oxide layer is 10Å-200Å.

[0014] As an improvement to the above solution, the ohmic contact layer includes a P-type ohmic contact layer and an N-type ohmic contact layer. One end of the bridging metal layer is connected to the P-type ohmic contact layer of the light-emitting unit through the first through-hole, and the other end of the bridging metal layer is connected to the N-type ohmic contact layer of the adjacent light-emitting unit through the second through-hole.

[0015] The electrode layer includes a P-type electrode layer and an N-type electrode layer. The P-type electrode layer is connected to the P-type ohmic contact layer of the light-emitting unit through the third through-hole, and the N-type electrode layer is connected to the N-type ohmic contact layer of the light-emitting unit through the fourth through-hole.

[0016] As an improvement to the above scheme, the bonding layer includes an Al2O3 layer and a SiO2 layer arranged sequentially, wherein the ratio of the thickness of the Al2O3 layer to the thickness of the SiO2 layer is 1:1 to 1:10000.

[0017] As an improvement to the above scheme, the growth thickness of the Al2O3 layer in the bonding layer is 50Å-5000Å;

[0018] The SiO2 layer has a growth thickness of 5000Å-50000Å.

[0019] As an improvement to the above solution, the P-type ohmic contact layer includes a P-type ohmic contact metal layer, a P-type pad layer, and a P-type passivation protection layer arranged sequentially; the P-type ohmic contact metal layer is selected from one or more of Au layer, AuBe layer, and AuZn layer; the P-type pad layer is selected from one or more of Ti layer, Al layer, Ni layer, Cr layer, TiW layer, and AlCu layer; and the P-type passivation protection layer is selected from Pt layer and / or Au layer.

[0020] As an improvement to the above scheme, the N-type ohmic contact layer includes an N-type ohmic contact metal layer and an etch barrier layer arranged sequentially. The N-type ohmic contact metal layer is selected from one or more of Au layer, Ni layer, AuGe layer, and AuGeNi layer, and the etch barrier layer is selected from one or more of Ti layer, Pt layer, TiW layer, and Ni layer.

[0021] A second aspect of the present invention provides a method for preparing the aforementioned flip-chip high-voltage LED, comprising the following steps:

[0022] A temporary substrate is provided, and an epitaxial layer is prepared on the temporary substrate;

[0023] A bonding layer is deposited on the surface of the epitaxial layer;

[0024] A substrate is provided, the substrate is bonded to an epitaxial layer, and the temporary substrate is removed;

[0025] The epitaxial layer is etched to form a P-type conductive step and an isolation trench region, and an ohmic contact layer is prepared on the surface of the epitaxial layer.

[0026] The isolation trench area is etched until the bonding layer is exposed to form the first isolation trench and the second isolation trench.

[0027] A first passivation layer is prepared on the surface of the epitaxial layer to cover the ohmic contact layer, and the first passivation layer is etched to form a first through-hole and a second through-hole that penetrate into the ohmic contact layer.

[0028] A bridging metal layer is prepared on the surface of the first passivation layer, at the first via and the second via, to connect adjacent light-emitting units;

[0029] A second passivation layer is prepared on the surface of the first passivation layer to cover the bridging metal layer, and the second passivation layer is etched to form a third and a fourth through hole that penetrate to the ohmic contact layer and expose the second isolation trench.

[0030] Electrode layers are prepared within the third and fourth through holes;

[0031] Prepare a pin buffer layer in the second isolation groove;

[0032] The ejector pin buffer layer includes a Ti layer and an Al layer arranged sequentially, and an oxide layer is formed on the Al layer.

[0033] As an improvement to the above solution, the preparation of the ejector pin buffer layer in the second isolation groove specifically includes:

[0034] The second isolation trench is subjected to photolithography and etching until the bonding layer is exposed;

[0035] Metallic Ti and metallic Al are deposited sequentially to form stacked Ti and Al layers, and then plasma surface treatment is performed to form an oxide layer;

[0036] Remove the photoresist by peeling;

[0037] The plasma surface treatment includes: introducing oxygen as the reactant gas, using a radio frequency power of 200W-2000W, a chamber pressure of 20Pa-100Pa, and a duration of 10min-30min.

[0038] As an improvement to the above scheme, the preparation of the ohmic contact layer on the surface of the epitaxial layer specifically includes:

[0039] A material for a P-type ohmic contact layer is deposited on the surface of the epitaxial layer and then annealed.

[0040] The material of the N-type ohmic contact layer is deposited on the surface of the epitaxial layer, and part of the epitaxial layer is removed, followed by annealing.

[0041] The annealing process includes: in a nitrogen atmosphere, treating the epitaxial layer of the material with the deposited P-type ohmic contact layer and / or N-type ohmic contact layer at a temperature of 280℃-500℃ for 1min-20min.

[0042] Implementing this invention has the following beneficial effects:

[0043] In this application, an independent pin buffer layer is fabricated at the isolation trench in the center of the flip-chip high-voltage LED chip where it may be struck by the pin. The pin buffer layer is located on the bonding layer. The LED epitaxial layer, passivation layer, bridging metal layer and other functional layers in this area are etched away. This can effectively avoid the problem of functional layer breakage on the side wall and bottom of the flip-chip high-voltage LED chip isolation trench caused by the impact of the die bonder pin, reduce leakage current, and improve the reliability and die bond yield of the flip-chip high-voltage LED chip. Attached Figure Description

[0044] Figure 1 A schematic diagram of a flip-chip high-voltage LED in the prior art;

[0045] Figure 2A schematic diagram of the appearance of a flip-chip high-voltage LED in the prior art;

[0046] Figure 3 A typical physical image of a flip-chip high-voltage LED in the prior art;

[0047] Figure 4 : A schematic diagram of the structure obtained after step (2) in this invention;

[0048] Figure 5 : A schematic diagram of the appearance of a flip-chip high-voltage LED chip in this invention;

[0049] Figure 6 A typical physical image of a flip-chip high-voltage LED chip according to the present invention;

[0050] Figure 7 : A schematic diagram of the structure of the ejector pin buffer layer in this invention;

[0051] Figure 8 : A schematic diagram of the epitaxial layer in this invention.

[0052] Figure reference numerals: 10-Substrate; 20-Epipolar layer; 21-GaAs buffer layer; 22-GaInP etch stop layer; 23-N-type layer; 231-N-type GaAs ohmic contact layer; 232-N-type current spreading layer; 233-N-type confinement layer; 24-Active layer; 25-P-type layer; 251-P-type confinement layer; 252-P-type GaP layer; 30-Bonding layer; 31-P-type conductive step; 32-Isolation trench; 321-First isolation trench ; 322-Second isolation groove; 40-Ohmic contact layer; 41-P-type ohmic contact layer; 42-N-type ohmic contact layer; 50-First passivation layer; 51-First through hole; 52-Second through hole; 60-Bridging metal layer; 70-Second passivation layer; 71-Third through hole; 72-Fourth through hole; 80-Electrode layer; 81-P-type electrode layer; 82-N-type electrode layer; 90-Ejector pin buffer layer; 91-Ti layer; 92-Al layer; 93-Oxide layer. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described in further detail below.

[0054] AlGaInP-based red and yellow flip-chip high-voltage LED chips and AlGaAs-based near-infrared flip-chip high-voltage LED chips consist of multiple light-emitting units connected in series through a bridging metal layer 60 to form a high-voltage circuit. Adjacent light-emitting units are electrically isolated through an isolation slot 32 to ensure that each light-emitting unit works independently and that current is transmitted stably.

[0055] Specifically, please refer to Figures 1-3In the prior art, the flip-chip high-voltage LED includes a substrate 10 and an epitaxial layer 20 stacked on the substrate 10. A bonding layer 30 is provided between the substrate 10 and the epitaxial layer 20. A P-type conductive step 31 and an isolation trench 32 are formed on the bonding layer 30. The isolation trench 32 divides the flip-chip high-voltage LED into several independent light-emitting units. An ohmic contact layer 40, a first passivation layer 50, a bridging metal layer 60, and a second passivation layer 70 are provided on the bonding layer 30. The first passivation layer 50 covers the ohmic contact layer 40. The bridging metal layer 60 is disposed on the first passivation layer 50 and is connected to the ohmic contact layer 40 through a first via 51 and a second via 52 to connect adjacent light-emitting units. The second passivation layer 70 covers the bridging metal layer 60. An electrode layer 80 is provided on the second passivation layer 70. The electrode layer 80 is connected to the ohmic contact layer 40 through a third via 71 and a fourth via 72.

[0056] In this type of flip-chip high-voltage LED chip, the corresponding area of ​​the isolation trench 32 is provided with a first passivation layer 50, a bridging metal layer 60 and a second passivation layer 70. When the chip is lifted from the front of the chip, the ejector pin directly acts on the second passivation layer 70, which can easily cause the second passivation layer 70, or even the bridging metal layer 60 and the first passivation layer 50, to crack, thereby reducing the reliability of the flip-chip high-voltage LED chip.

[0057] To address the above problems, the first aspect of this invention provides a flip-chip high-voltage LED chip. Please refer to [link / reference]. Figures 4-6 The LED chip includes a substrate 10 and an epitaxial layer 20 stacked on the substrate 10. A bonding layer 30 is provided between the substrate 10 and the epitaxial layer 20. A P-type conductive step 31 and an isolation trench 32 are formed on the bonding layer 30. The isolation trench 32 divides the flip-chip high-voltage LED into several light-emitting units. An ohmic contact layer 40, a first passivation layer 50, a bridging metal layer 60, and a second passivation layer 70 are provided on the bonding layer 30. The first passivation layer 50 covers the ohmic contact layer 40, and the bridging metal layer 60 is disposed on the first passivation layer 70. The second passivation layer 70 covers the bridging metal layer 60 and is connected to the ohmic contact layer 40 of the adjacent light-emitting unit through the first through hole 51 and the second through hole 52. The second passivation layer 70 is provided with an electrode layer 80, which is connected to the ohmic contact layer 40 through the third through hole 71 and the fourth through hole 72. The isolation groove 32 includes a first isolation groove 321 and a second isolation groove 322. A pin buffer layer 90 is formed on the bonding layer 30 and is disposed in the second isolation groove 322.

[0058] In this application, a pin buffer layer 90 is fabricated at the isolation groove 32 in the center of the flip-chip high-voltage LED chip, where it may be struck by the pin. The pin buffer layer 90 is disposed on the bonding layer 30, which has the advantage of resisting pin impact. Moreover, the pin buffer layer 90 in this invention is fabricated independently, that is, the pin buffer layer 90 and the epitaxial layer 20 and the first passivation layer 50 are spatially independent. The LED epitaxial layer 20, passivation layer, bridging metal layer 60 and other functional layers in this area are all etched away, which can effectively avoid the problem of functional layer breakage on the side wall and bottom of the isolation groove 32 of the flip-chip high-voltage LED chip caused by the impact of the die bonder pin, reduce leakage current, and improve the reliability and die bond yield of the flip-chip high-voltage LED chip.

[0059] Specifically, the ohmic contact layer 40 includes a P-type ohmic contact layer 41 and an N-type ohmic contact layer 42. One end of the bridging metal layer 60 is connected to the P-type ohmic contact layer 41 of the light-emitting unit through the first through-hole 51, and the other end of the bridging metal layer 60 is connected to the N-type ohmic contact layer 42 of the adjacent light-emitting unit through the second through-hole 52. The bridging metal layer 60 allows several light-emitting units to be connected in series.

[0060] Specifically, the electrode layer 80 includes a P-type electrode layer 81 and an N-type electrode layer 82. The P-type electrode layer 81 is connected to the P-type ohmic contact layer 41 of the light-emitting unit through the third through-hole 71, and the N-type electrode layer 82 is connected to the N-type ohmic contact layer 42 of the light-emitting unit through the fourth through-hole 72. It can be understood that the P-type electrode layer 81 and the N-type electrode layer 82 are respectively disposed in the first and last light-emitting units of the entire flip-chip high-voltage LED chip.

[0061] In fully automated LED die bonding operations, the long-term, trouble-free automatic operation of the die bonder is crucial for ensuring output per unit time and reducing production costs. However, wear or contamination of the ejector pin tips will cause the die bonder to stop for cleaning or replacement, resulting in reduced efficiency and increased material and labor costs for the ejector pins. Please refer to [link / reference]. Figure 7 The ejector pin buffer layer 90 includes a Ti layer 91 and an Al layer 92 sequentially disposed. An oxide layer 93 is formed on the Al layer 92, which enables the ejector pin buffer layer 90 to resist ejector pin impact, prevent contamination of the ejector pin tip, and extend ejector pin life. The Ti layer 91 promotes the adhesion strength of the ejector pin buffer layer 90 to the bonding layer 30. The Al layer 92 has good ductility, enabling the ejector pin buffer layer 90 to resist ejector pin impact. The oxide layer 93 formed on the Al layer 92 acts as a protective layer, preventing contamination of the ejector pin tip. Even after the ejector pin impacts the ejector pin buffer layer 90, aluminum debris will not adhere to the tip, further extending the ejector pin's lifespan. This significantly contributes to reducing the frequency of pin cleaning and replacement in the die bonder.

[0062] Furthermore, the growth thickness of the Ti layer 91 is 5nm-200nm, ensuring a stable bond between the Al layer 92 and the bonding layer 30, while also guaranteeing the overall structural stability of the ejector pin buffer layer 90. Under external forces such as ejector pin impacts, interlayer separation will not easily occur. The exemplary growth thickness of the Ti layer 91 is 5nm, 10nm, 15nm, 20nm, 100nm, 125nm, 150nm, 175nm, or 200nm, but is not limited to these.

[0063] Furthermore, the Al layer 92 has a growth thickness of 100nm-3000nm, which can further improve the impact resistance of the ejector pin buffer layer 90, thereby effectively buffering energy and protecting the functional layer of the LED chip from damage, without affecting the heat dissipation performance of the flip-chip high-voltage LED chip. The growth thickness of the Al layer 92 is exemplarily 100nm, 300nm, 500nm, 1000nm, 1500nm, 2000nm, 2500nm, and 3000nm, but is not limited to these.

[0064] Furthermore, the oxide layer 93 is an Al2O3 layer formed by plasma surface treatment of the Al layer 92. Plasma surface treatment is a simple and precise process with controllable thickness, and aluminum is a relatively reactive metal, resulting in rapid oxide layer formation. Specifically, the formation of the oxide layer 93 is based on consuming the Al layer 92, so an aluminum oxide protective layer is only formed in the area of ​​the ejector pin buffer layer 90. The oxide layer 93 will not form in other areas of the LED chip wafer outside the ejector pin buffer layer 90. This process is simpler than atomic layer deposition (ALD) or electron beam evaporation deposition (EBD) of Al2O3, avoiding photolithography and etching operations after the Al2O3 layer covers the entire wafer surface, thus preventing reduced yield due to process complexity. The oxide layer 93 has a thickness of 10Å-200Å, which, while ensuring its impact resistance, further improves its integrity, thereby further enhancing the protection of the ejector pin tip. The growth thickness of the oxide layer 93 is exemplarily 10 Å, 30 Å, 50 Å, 70 Å, 90 Å, 100 Å, 120 Å, 140 Å, 160 Å, 180 Å, and 200 Å, but is not limited thereto. If the structures of the Ti layer 91 and the Al layer 92 are interchanged, so that the ejector pin buffer layer 90 includes the Al layer 92, the Ti layer 91, and the oxide layer 93 arranged sequentially, and the corresponding oxide layer 93 is a titanium oxide layer formed by plasma surface treatment of the Ti layer 91, it will not only affect ejector pin wear and contamination, but also the formation rate of the oxide layer 93 is relatively slow, which will reduce production efficiency.

[0065] Preferably, the bonding layer 30 comprises an Al2O3 layer and a SiO2 layer sequentially disposed. During the bonding process, a high-strength oxide bond can be formed, resulting in high bonding quality between the epitaxial layer 20 and the substrate 10, strong adhesion between the epitaxial layer 20 and the ejector pin buffer layer 90, and high transparency of the bonded layer 30, reducing light scattering and not increasing interface defects. Specifically, since Al atoms can fill the Ga vacancies in the P-type GaP layer 252 to form covalent bonds, the Al2O3 layer, acting as an intercalation layer between the P-type GaP layer 252 and the SiO2 layer, effectively improves the adhesion strength compared to the direct contact between GaP and SiO2.

[0066] Furthermore, the ratio of the thickness of the Al2O3 layer to the thickness of the SiO2 layer is 1:1 to 1:10000, which can form a high-strength oxide bond and improve the stability of the flip-chip high-voltage LED. In some embodiments, the growth thickness of the Al2O3 layer in the bonding layer 30 is 50Å-5000Å, exemplarily 50Å, 200Å, 1000Å, 2000Å, and 5000Å, but not limited thereto. In some embodiments, the growth thickness of the SiO2 layer is 5000Å-50000Å, exemplarily 5000Å, 10000Å, 20000Å, 25000Å, 30000Å, 40000Å, and 50000Å, but not limited thereto.

[0067] Preferably, the P-type ohmic contact layer 41 includes a P-type ohmic contact metal layer, a P-type pad layer, and a P-type passivation protection layer sequentially disposed therefrom; wherein, the P-type ohmic contact metal layer is selected from one or more of Au layer, AuBe layer, and AuZn layer, which can reduce the barrier height between the metal and semiconductor and form a low contact resistance with the P-type semiconductor layer; the P-type pad layer is selected from one or more of Ti layer, Al layer, Ni layer, Cr layer, TiW layer, and AlCu layer, which can increase the thickness of the P-type electrode, reduce resistance, thereby making the current injection more uniform and the LED chip generating less heat; the P-type passivation protection layer is selected from a metal with low reactivity, which can protect the P-type ohmic contact layer 41 from oxidation or corrosion and improve the stability of the flip-chip high-voltage LED chip, and the P-type passivation protection layer includes, but is not limited to, Ti layer, Pt layer, and Au layer.

[0068] Furthermore, the growth thickness of the P-type ohmic contact metal layer is 500 Å-10000 Å, and the growth thickness of the P-type passivation protective layer is 50 Å-5000 Å. Understandably, the growth thickness of the P-type pad layer is designed based on the height of the P-electrode step region, laying the foundation for the final P-type electrode layer 81 and N-type electrode layer 82 to be of equal height.

[0069] Preferably, the N-type ohmic contact layer 42 includes an N-type ohmic contact metal layer and an etch barrier layer sequentially disposed therefrom. The N-type ohmic contact metal layer is selected from one or more of Au, Ni, AuGe, and AuGeNi layers, and can form a low-resistance ohmic contact with the N-type semiconductor layer to reduce the interface resistance. The etch barrier layer is selected from one or more of Ti, Pt, TiW, and Ni layers, and can ensure that the structure of the N-type ohmic contact metal layer and the epitaxial layer 20 is not damaged when etching other areas. At the same time, it can better bond the N-type ohmic contact metal layer with the first passivation layer 50, preventing delamination, peeling, and other problems from occurring in subsequent processes or during use.

[0070] Furthermore, the growth thickness of the N-type ohmic contact metal layer is 500 Å-10000 Å, with exemplary growth thicknesses of 500 Å, 1000 Å, 2000 Å, 5000 Å, 7500 Å, and 10000 Å, but not limited thereto; the growth thickness of the etching barrier layer is 50 Å-5000 Å, with exemplary growth thicknesses of 50 Å, 100 Å, 500 Å, 1000 Å, 2000 Å, 3000 Å, 4000 Å, and 5000 Å, but not limited thereto.

[0071] Accordingly, a second aspect of the present invention provides a method for fabricating the aforementioned flip-chip high-voltage LED, comprising the following steps:

[0072] (1) A temporary substrate is provided, and an epitaxial layer 20 is prepared on the temporary substrate;

[0073] (2) A bonding layer 30 is deposited on the surface of the epitaxial layer 20;

[0074] (3) Provide a substrate 10, bond the substrate 10 to the epitaxial layer 20, and remove the temporary substrate;

[0075] (4) The epitaxial layer 20 is etched to form a P-type conductive step 31 and an isolation trench region, and an ohmic contact layer 40 is prepared on the surface of the epitaxial layer 20.

[0076] (5) The isolation trench area is etched to expose the bonding layer 30, forming the first isolation trench 321 and the second isolation trench 322;

[0077] (6) A first passivation layer 50 is prepared on the surface of the epitaxial layer 20 to cover the ohmic contact layer 40, and the first passivation layer 50 is etched to form a first through hole 51 and a second through hole 52 that penetrate to the ohmic contact layer 40.

[0078] (7) A bridging metal layer 60 is prepared on the surface of the first passivation layer 50, at the first through hole 51 and the second through hole 52 to connect adjacent light-emitting units;

[0079] (8) A second passivation layer 70 is prepared on the surface of the first passivation layer 50 to cover the bridging metal layer 60, and the second passivation layer 70 is etched to form a third through hole 71 and a fourth through hole 72 that penetrate to the ohmic contact layer 40, and exposes the second isolation groove 322.

[0080] (9) An electrode layer 80 is prepared in the third through hole 71 and the fourth through hole 72;

[0081] (10) Prepare a pin buffer layer 90 in the second isolation groove 322.

[0082] Each step will be explained in detail below.

[0083] Regarding step (1), a temporary substrate is provided, and an epitaxial layer 20 is prepared on the temporary substrate;

[0084] Preferably, please refer to Figure 8 The epitaxial layer 20 includes a GaAs buffer layer 21, a GaInP etch stop layer 22, an N-type layer 23, an active layer 24, and a P-type layer 25 stacked sequentially. The N-type layer 23 includes an N-type GaAs ohmic contact layer 231, an N-type current spreading layer 232, and an N-type confinement layer 233 stacked sequentially. The P-type layer 25 includes a P-type confinement layer 251 and a P-type GaP layer 252.

[0085] Optionally, the temporary substrate may be a GaAs temporary substrate, etc.

[0086] In this step, the GaAs buffer layer 21, GaInP corrosion stop layer 22, N-type GaAs ohmic contact layer 231, N-type current spreading layer 232, N-type confinement layer 233, active layer 24, P-type confinement layer 251 and P-type GaP layer 252 can be prepared by deposition or other existing known methods. For example, metal-organic chemical vapor deposition (MOCVD) can be used, which will not be described in detail in this document.

[0087] Regarding step (2), a bonding layer 30 is deposited on the surface of the epitaxial layer 20;

[0088] This step specifically includes: roughening the surface of the P-type GaP layer 252, and then sequentially depositing Al2O3 and SiO2 on the roughened surface of the P-type GaP layer 252 to form a bonding layer 30.

[0089] In this application, the surface roughening treatment of the P-type GaP layer 252 can remove surface particulate impurities and enhance the adhesion between the bonding layer 30 and the P-type GaP layer 252.

[0090] Optionally, the roughening treatment may be performed by applying a roughening liquid to the surface of the P-type GaP layer 252, or by applying a mechanical process such as grinding to the surface of the P-type GaP layer 252. This application does not specifically limit the method.

[0091] Optionally, the deposition process of the bonding layer 30 includes, but is not limited to, electron beam evaporation (E-Beam), plasma enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD), and this application does not specifically limit it.

[0092] Regarding step (3), a substrate 10 is provided, the substrate 10 is bonded to the epitaxial layer 20, and the temporary substrate is removed;

[0093] This step specifically includes performing surface planarization and activation treatment on the bonding layer 30, then bonding it to the substrate 10, performing high-temperature and high-pressure bonding, and finally removing the temporary substrate.

[0094] In some embodiments, the substrate 10 is a sapphire flat substrate. Specifically, the bonding layer 30 can be bonded to the polished surface of a sapphire flat substrate of the same diameter and subjected to high-temperature and high-pressure bonding. The bonding temperature is 400℃-550℃, the bonding pressure is 10000Kgf-20000Kgf, and the bonding time is 20min-60min, which can form a high-strength oxide bond.

[0095] In some embodiments, removing the temporary substrate includes removing the temporary substrate, GaAs buffer layer 21, and GaInP etch stop layer 22 to expose the N-type GaAs ohmic contact layer 231.

[0096] Regarding step (4), the epitaxial layer 20 is etched to form a P-type conductive step 31 and an isolation trench region, and an ohmic contact layer 40 is prepared on the surface of the epitaxial layer 20.

[0097] This step specifically includes:

[0098] (41) The epitaxial layer 20 is etched to form a P-type conductive step 31 and an isolation trench region;

[0099] The isolation groove area includes a first isolation groove area and a second isolation groove area, wherein the second isolation groove area is the area where the ejector pin buffer layer 90 is set.

[0100] For example, photoresist is coated on the N-type GaAs ohmic contact layer 231. After exposure and development, the N-type GaAs ohmic contact layer 231 is etched into the interior of the P-type GaP layer 252 to remove the photoresist, forming a P-type conductive step 31 and an isolation trench region.

[0101] In some embodiments, the sidewall of the P-type conductive step 31 is a beveled sidewall with an elevation angle of less than or equal to 70°, which can prevent cracks from forming in the passivation protective layer. It should be noted that the elevation angle of the sidewall of the P-type conductive step 31 refers to the acute angle formed by the sidewall and the bottom horizontal line.

[0102] In some embodiments, the isolation groove area is a beveled sidewall with an elevation angle of less than or equal to 70°, which can prevent cracks from forming in the passivation protective layer. It should be noted that the elevation angle of the sidewall refers to the acute angle formed by the sidewall of the isolation groove 32 and the bottom horizontal line.

[0103] Optionally, the etching process can be dry etching or wet etching. More preferably, the etching process uses dry etching, which can better control the size of the P-type conductive step 31 and the isolation trench area. An exemplary dry etching process is inductively coupled plasma etching (ICP) etching, etc.

[0104] (42) An ohmic contact layer 40 is prepared on the surface of the epitaxial layer 20;

[0105] The ohmic contact layer 40 includes a P-type ohmic contact layer 41 and an N-type ohmic contact layer 42. The P-type ohmic contact layer 41 can be prepared first and then the N-type ohmic contact layer 42 can be prepared later, or the N-type ohmic contact layer 42 can be prepared first and then the P-type ohmic contact layer 41 can be prepared later.

[0106] This step specifically includes:

[0107] (421) Deposit the material of the P-type ohmic contact layer 41 on the surface of the epitaxial layer 20 and perform annealing treatment;

[0108] For example, the preparation method of the P-type ohmic contact layer 41 specifically includes: coating photoresist on the surfaces of the P-type GaP layer 252, the N-type GaAs ohmic contact layer 231, the P-type conductive step 31, and the isolation trench area; after exposure and development, removing part of the photoresist to expose the P-type GaP layer 252; then sequentially depositing the material of the P-type ohmic contact metal layer, the material of the P-type pad layer, and the material of the P-type passivation protective layer; and using a stripping process to remove the material on the photoresist, followed by removing the photoresist to form the P-type ohmic contact layer 41; finally, performing an annealing process to fuse the P-type ohmic contact layer 41 with the P-type GaP layer 252 to form an ohmic contact.

[0109] Preferably, the annealing treatment includes: treating the epitaxial layer 20 of the material with the deposited P-type ohmic contact layer 41 at a temperature of 280℃-500℃ for 1 min-20 min in a nitrogen atmosphere. Specifically, the epitaxial layer 20 of the material with the deposited P-type ohmic contact layer 41 is treated at a temperature of 320℃-500℃ for 1 min-20 min in a nitrogen atmosphere.

[0110] Optionally, the deposition process of the P-type ohmic contact layer 41 can be electron beam evaporation, and the stripping process can be a lift-off process.

[0111] (422) Deposit the material of the N-type ohmic contact layer 42 on the surface of the epitaxial layer 20, remove part of the epitaxial layer 20, and then perform annealing.

[0112] For example, the method for preparing the N-type ohmic contact layer 42 specifically includes: coating photoresist on the surfaces of the P-type GaP layer 252, the N-type GaAs ohmic contact layer 231, the P-type conductive step 31, and the isolation trench region; after exposure and development, removing part of the photoresist to expose the N-type GaAs ohmic contact layer 231; then sequentially depositing the material of the N-type ohmic contact metal layer and the material of the etch barrier layer; removing the material on the photoresist using a stripping process; and then removing the photoresist to form the N-type ohmic contact layer 42; next, using the formed N-type ohmic contact metal layer and the etch barrier layer as a mask, etching away the remaining N-type GaAs ohmic contact layer 231; and finally performing an annealing process to fuse the N-type ohmic contact layer 42 with the N-type GaAs ohmic contact layer 231 to form an ohmic contact.

[0113] Preferably, the annealing treatment includes: treating the epitaxial layer 20 of the material for depositing the N-type ohmic contact layer 42 at a temperature of 280℃-500℃ for 1 min-20 min in a nitrogen atmosphere. Specifically, the epitaxial layer 20 of the material for depositing the N-type ohmic contact layer 42 is treated at a temperature of 280℃-380℃ for 1 min-20 min in a nitrogen atmosphere.

[0114] In some embodiments, annealing is not performed after step (421), but can be performed uniformly after step (422), that is, combined into one annealing process.

[0115] Optionally, the deposition process of the N-type ohmic contact layer 42 can be electron beam evaporation, and the stripping process can be a lift-off stripping process.

[0116] Optionally, etching away the remaining N-type GaAs ohmic contact layer 231 can prevent the N-type GaAs ohmic contact layer 231 from absorbing the light emitted by the active layer 24. The etching process can be dry etching or wet etching, and this application does not specifically limit it.

[0117] Regarding step (5), the isolation trench area is etched until the bonding layer 30 is exposed to form the first isolation trench 321 and the second isolation trench 322;

[0118] This step specifically includes:

[0119] Photoresist is coated on the surface of the ohmic contact layer 40 and its uncovered P-type GaP layer 252, N-type current spreading layer 232, P-type conductive step 31, and isolation trench area. After exposure and development, part of the photoresist is removed to expose the P-type GaP layer 252 corresponding to the isolation trench 32 area. Then, the exposed part is etched away to expose the bonding layer 30, and the photoresist is removed to form the first isolation trench 321 and the second isolation trench 322.

[0120] Optionally, the etching process can be dry etching, and an exemplary dry etching process can be ICP etching, which is not specifically limited in this application.

[0121] In one embodiment, see Figure 4 The isolation groove 32 divides the epitaxial layer 20 into four independent light-emitting units, namely a first light-emitting unit, a second light-emitting unit, a third light-emitting unit, and a fourth light-emitting unit. The first isolation groove 321 is disposed between the first and second light-emitting units, the third and fourth light-emitting units, and the second isolation groove 322 is disposed between the second and third light-emitting units.

[0122] Regarding step (6), a first passivation layer 50 is prepared on the surface of the epitaxial layer 20 to cover the ohmic contact layer 40, and the first passivation layer 50 is etched to form a first through hole 51 and a second through hole 52 that penetrate to the ohmic contact layer 40.

[0123] This step specifically includes:

[0124] Material for a first passivation layer 50 is deposited on the surface of the ohmic contact layer 40 and its uncovered P-type GaP layer 252, N-type current spreading layer 232, P-type conductive step 31, and isolation trench 32 to form the first passivation layer 50. Subsequently, photoresist is coated on the surface of the first passivation layer 50. After exposure and development, some photoresist is removed. Then, the exposed areas to be etched are etched until the N-type ohmic contact layer 42 and the P-type ohmic contact layer 41 are exposed. The photoresist is then removed, forming a first via 51 and a second via 52. At this point, the first via 51 and the second via 52 can form conductive channels. The first via 51 includes three vias disposed on the P-type ohmic contact layer 41 of the second, third, and fourth light-emitting units. The second via 52 includes three vias disposed on the N-type ohmic contact layer 42 of the first, second, and third light-emitting units.

[0125] Optionally, the first passivation layer 50 can provide insulation and passivation protection for several light-emitting units of the flip-chip high-voltage LED. The material of the first passivation layer 50 can be alumina, silicon oxide, silicon nitride, or other insulating materials. This application does not make specific limitations on this. The thickness of the first passivation layer 50 can be flexibly adjusted according to the actual situation. This application does not make specific limitations on this. The deposition process of the first passivation layer 50 includes, but is not limited to, PECVD.

[0126] The etching process includes, but is not limited to, dry etching, and can be exemplified by ICP dry etching.

[0127] Regarding step (7), a bridging metal layer 60 is prepared on the surface of the first passivation layer 50, at the first through hole 51 and the second through hole 52 to connect adjacent light-emitting units;

[0128] This step specifically includes:

[0129] Photoresist is coated at the first passivation layer 50, the first via 51, and the second via 52. After exposure and development, part of the photoresist is removed to expose the first via 51, the second via 52, and the first passivation layer 50 between the first via 51 and the second via 52. Subsequently, the material of the bridging metal layer 60 is deposited. Finally, the material of the bridging metal layer 60 on the photoresist is removed using a stripping process, and the photoresist is removed to form the bridging metal layer 60.

[0130] At this time, one end of the bridging metal layer 60 is electrically connected to the P-type ohmic contact layer 41 through the first through hole 51, and the other end is electrically connected to the N-type ohmic contact layer 42 through the second through hole 52, thereby connecting the first light-emitting unit, the second light-emitting unit, the third light-emitting unit and the fourth light-emitting unit in series.

[0131] Optionally, the deposition process of the bridging metal layer 60 includes, but is not limited to, electron beam evaporation, and the lift-off process can be a lift-off process.

[0132] Optionally, the material of the bridging metal layer 60 can be a metallic material, such as one or more of Ti, Al, Ni, Cr, Ag, TiW, AlCu, Au, AuBe, AuZn, AuGe, etc. This application does not make specific limitations on this.

[0133] Regarding step (8), a second passivation layer 70 is prepared on the surface of the first passivation layer 50 to cover the bridging metal layer 60, and the second passivation layer 70 is etched to form a third through hole 71 and a fourth through hole 72 that penetrate to the ohmic contact layer 40, and exposes the second isolation groove 322.

[0134] This step specifically includes:

[0135] Material for a second passivation layer 70 is deposited on the bridging metal layer 60 and the uncovered first passivation layer 50 to form the second passivation layer 70. Subsequently, photoresist is coated on the surface of the second passivation layer 70. After exposure and development, part of the photoresist is removed to expose part of the second passivation layer 70, including the second passivation layer 70 corresponding to the second isolation trench 322. Then, the exposed second passivation layer 70 is etched until the N-type ohmic contact layer 42 and the P-type ohmic contact layer 41 are exposed, forming the third via 71 and the fourth via 72. The area of ​​the second passivation layer 70 corresponding to the exposed second isolation trench 322 is etched until the bonding layer 30 is exposed, that is, the second isolation trench 322 is exposed.

[0136] At this time, the third through hole 71 is provided on the P-type ohmic contact of the first light-emitting unit, and the fourth through hole 72 is provided on the N-type ohmic contact of the fourth light-emitting unit.

[0137] Optionally, the second passivation layer 70 can be used as a DBR reflective layer. On the one hand, it can reflect light, enhance the light output of the substrate 10, and improve the luminous efficiency of the flip-chip high voltage LED. On the other hand, it can provide insulation and passivation protection for the flip-chip high voltage LED. The material of the second passivation layer 70 can be a conventional passivation layer material, including but not limited to SiO2 and Si3N4, or other materials. This application does not make specific limitations on this. The thickness of the second passivation layer 70 can be flexibly adjusted according to the actual situation. This application does not make specific limitations on this. The deposition process of the second passivation layer 70 includes but is not limited to PECVD.

[0138] The etching process includes, but is not limited to, dry etching, and can be exemplified by ICP dry etching.

[0139] Regarding step (9), an electrode layer 80 is prepared in the third through hole 71 and the fourth through hole 72;

[0140] Photoresist is coated on the surface of the second passivation layer 70 and the uncovered third via 71, fourth via 72 and second isolation trench 322. After exposure and development, the photoresist around the third via 71 and the fourth via 72, as well as the second isolation trench 322, are removed. Then, the material of the electrode layer 80 is deposited. Finally, the material of the electrode layer 80 on the photoresist is removed by a stripping process, and the photoresist is removed. A P-type electrode layer 81 is formed around the third via 71, and an N-type electrode layer 82 is formed at the fourth via 72.

[0141] At this time, the P-type electrode layer 81 is electrically connected to the P-type ohmic contact layer 41 through the third through-hole 71, and the N-type electrode layer 82 is electrically connected to the N-type ohmic contact layer 42 through the fourth through-hole 72, and the heights of the P-type electrode layer 81 and the N-type electrode layer 82 are equal. The material of the electrode layer 80 can be a conventional material in the art, and this application does not make specific limitations.

[0142] Optionally, the deposition process of the electrode layer 80 includes, but is not limited to, electron beam evaporation, and the stripping process can be a lift-off stripping process.

[0143] In some embodiments, the preparation of the electrode layer 80 within the third through-hole 71 and the fourth through-hole 72 further includes: annealing the formed structure so that the P-type electrode layer 81 and the N-type electrode layer 82 fuse with the underlying metal through the third through-hole 71 and the fourth through-hole 72 to form a good conductive channel. The annealing process includes: treating the structure obtained in step (9) at a temperature of 280℃-500℃ for 1 min-20 min in a nitrogen atmosphere. Specifically, for the P-type electrode layer 81, the annealing temperature can be 320℃-500℃ and the time can be 1 min-20 min; for the N-type electrode layer 82, the annealing temperature can be 280℃-380℃ and the time can be 1 min-20 min. It is understood that the P-type electrode layer 81 can be annealed first, followed by the N-type electrode layer 82, or the P-type electrode layer 81 and the N-type electrode layer 82 can be combined into a single annealing process.

[0144] Regarding step (10), prepare the ejector pin buffer layer 90 in the second isolation groove 322;

[0145] This step specifically includes:

[0146] (101) Perform photolithography and etching on the second isolation trench 322 until the bonding layer 30 is exposed;

[0147] For example, photoresist is coated on the surface of the second passivation layer 70 and the uncovered electrode layer 80 and the second isolation trench 322. After exposure and development, the photoresist at the second isolation trench 322 is removed, and then the exposed area is etched until the bonding layer 30 is exposed.

[0148] (102) Metal Ti and metal Al are deposited sequentially to form a stacked Ti layer 91 and Al layer 92, and plasma surface treatment is performed to form an oxide layer 93;

[0149] The plasma surface treatment includes: introducing oxygen as the reaction gas, using a radio frequency power of 200W-2000W, a chamber pressure of 20Pa-100Pa, and a duration of 10min-30min, so that the formed oxide layer 93 is a dense film layer, without the generation of Al debris, and with a moderate thickness and good resistance to pin impact.

[0150] Optionally, the deposition process includes, but is not limited to, electron beam evaporation.

[0151] (103) Stripping away the photoresist;

[0152] For example, the material of the ejector pin buffer layer 90 on the photoresist can be removed using a lift-off process, and the photoresist can be removed to form the ejector pin buffer layer 90 in the second isolation trench 322. In this application, by performing plasma surface treatment on the ejector pin buffer layer 90 before the lift-off process, the surfaces of the P-type electrode layer 81 and the N-type electrode layer 82 can be effectively prevented from being oxidized by oxygen plasma.

[0153] In some embodiments, the method for preparing the flip-chip high voltage LED further includes: performing processes such as thinning, cutting, and splitting the substrate 10 on the obtained flip-chip high voltage LED.

[0154] The present invention will be further described below with reference to specific embodiments:

[0155] Example 1

[0156] This embodiment provides a flip-chip high voltage LED chip, including a substrate and an epitaxial layer stacked on the substrate, with a bonding layer provided between the substrate and the epitaxial layer;

[0157] P-type conductive steps and isolation trenches are formed on the bonding layer. The isolation trenches divide the flip-chip high-voltage LED into several light-emitting units.

[0158] The bonding layer is provided with an ohmic contact layer, a first passivation layer, a bridging metal layer and a second passivation layer. The first passivation layer covers the ohmic contact layer, and the bridging metal layer is disposed on the first passivation layer. The ohmic contact layer includes a P-type ohmic contact layer and an N-type ohmic contact layer. One end of the bridging metal layer is connected to the P-type ohmic contact layer of the light-emitting unit through a first via, and the other end is connected to the N-type ohmic contact layer of the adjacent light-emitting unit through a second via.

[0159] The second passivation layer is provided with an electrode layer, which includes a P electrode layer and an N electrode layer. The P electrode layer is connected to the P-type ohmic contact layer of the light-emitting unit through a third through-hole, and the N electrode layer is connected to the N-type ohmic contact layer of the light-emitting unit through a fourth through-hole.

[0160] The isolation groove includes a first isolation groove and a second isolation groove, and a pin buffer layer is formed on the bonding layer, with the pin buffer layer disposed in the second isolation groove;

[0161] The ejector pin buffer layer comprises a Ti layer and an Al layer arranged sequentially, with an oxide layer formed on the Al layer. The growth thickness of the Ti layer is 100 nm, and the growth thickness of the Al layer is 500 nm. The oxide layer is an Al2O3 layer formed by plasma surface treatment of the Al layer. The bonding layer comprises an Al2O3 layer and a SiO2 layer arranged sequentially, with the Al2O3 layer having a thickness of 1000 Å and the SiO2 layer having a thickness of 30000 Å. The P-type ohmic contact layer comprises a P-type ohmic contact metal layer, a P-type pad layer, and a P-type passivation protection layer arranged sequentially. The P-type ohmic contact metal layer is an AuZn layer, the P-type pad layer is an Al layer, and the P-type passivation protection layer is a Pt layer. The N-type ohmic contact layer comprises an N-type ohmic contact metal layer and an etch barrier layer arranged sequentially. The N-type ohmic contact metal layer is a Ni layer, and the etch barrier layer is a Ti layer.

[0162] Accordingly, this embodiment also provides a method for fabricating a light-emitting diode chip, including the following steps:

[0163] S1. Provide a GaAs temporary substrate, and sequentially fabricate an epitaxial layer on the GaAs temporary substrate. The epitaxial layer includes a GaAs buffer layer, a GaInP etching stop layer, an N-type layer, an active layer, and a P-type layer, which are sequentially arranged. The N-type layer includes an N-type GaAs ohmic contact layer, an N-type current spreading layer, and an N-type confinement layer stacked sequentially. The P-type layer includes a P-type confinement layer and a P-type GaP layer.

[0164] S2. The surface of the P-type GaP layer is roughened, and then Al2O3 and SiO2 are deposited sequentially on the surface of the roughened P-type GaP layer to form a bonding layer.

[0165] S3. Provide a sapphire substrate, perform surface planarization and activation treatment on the bonding layer, then bond it to the sapphire substrate, perform high temperature and high pressure bonding, and finally remove the GaAs temporary substrate, GaAs buffer layer and GaInP etching stop layer to expose the N-type GaAs ohmic contact layer; wherein, the bonding temperature is 500℃, the bonding pressure is 15000Kgf, and the bonding time is 40min.

[0166] S4. Photoresist is coated on the N-type GaAs ohmic contact layer. After exposure and development, the N-type GaAs ohmic contact layer is dry etched to the interior of the P-type GaP layer to remove the photoresist and form a P-type conductive step and isolation trench area.

[0167] Photoresist is coated on the surfaces of the P-type GaP layer, the N-type GaAs ohmic contact layer, the P-type conductive step, and the isolation trench region. After exposure and development, some photoresist is removed to expose the P-type GaP layer. Subsequently, the materials for the P-type ohmic contact metal layer, the P-type pad layer, and the P-type passivation protective layer are deposited using an electron beam evaporation device. The material on the photoresist is then removed using a lift-off process, and the photoresist is removed to form the P-type ohmic contact layer. Finally, annealing is performed to fuse the P-type ohmic contact layer with the P-type GaP layer to form an ohmic contact.

[0168] Photoresist is coated on the surfaces of the P-type GaP layer, the N-type GaAs ohmic contact layer, the P-type conductive step, and the isolation trench region. After exposure and development, some photoresist is removed to expose the N-type GaAs ohmic contact layer. Then, the material of the N-type ohmic contact metal layer and the etch stop layer are deposited using an electron beam evaporation device. The material on the photoresist is removed using a lift-off process, and then the photoresist is removed to form the N-type ohmic contact layer. Next, using the formed N-type ohmic contact metal layer and the etch stop layer as a mask, the remaining N-type GaAs ohmic contact layer is removed by dry etching. Finally, annealing is performed to fuse the N-type ohmic contact layer with the N-type GaAs ohmic contact layer to form an ohmic contact.

[0169] S5. Photoresist is coated on the surface of the ohmic contact layer and its uncovered P-type GaP layer, N-type current spreading layer, P-type conductive step, and isolation trench area. After exposure and development, part of the photoresist is removed to expose the P-type GaP layer corresponding to the isolation trench area. Then, dry etching is used to remove the exposed part until the bonding layer is exposed, and the photoresist is removed to form the first isolation trench and the second isolation trench.

[0170] S6. Deposit the material of the first passivation layer on the surface of the ohmic contact layer and its uncovered P-type GaP layer, N-type current spreading layer, P-type conductive step, and isolation trench to form the first passivation layer; then coat the surface of the first passivation layer with photoresist, and after exposure and development, remove part of the photoresist, and then perform dry etching on the exposed area to be etched until the N-type ohmic contact layer and P-type ohmic contact layer are exposed respectively, and remove the photoresist to form the first via and the second via;

[0171] S7. Photoresist is coated at the first passivation layer, the first via, and the second via. After exposure and development, part of the photoresist is removed to expose the first via, the second via, and the first passivation layer between the first and second vias. Then, the material of the bridging metal layer is deposited using an electron beam evaporation device. Finally, the material of the bridging metal layer on the photoresist is removed using a lift-off process, and the photoresist is removed to form the bridging metal layer.

[0172] S8. Deposit the material of the second passivation layer on the bridging metal layer and the first passivation layer that is not covered to form the second passivation layer; then coat the surface of the second passivation layer with photoresist, and after exposure and development, remove part of the photoresist to expose part of the second passivation layer, including the second passivation layer corresponding to the second isolation trench; then perform dry etching on the exposed second insulating adhesive layer until the N-type ohmic contact layer and the P-type ohmic contact layer are exposed respectively to form the third via and the fourth via; and perform dry etching on the second passivation layer area corresponding to the exposed second isolation trench until the second isolation trench is exposed.

[0173] S9. Photoresist is coated on the surface of the second passivation layer and the uncovered third via, fourth via, and second isolation trench. After exposure and development, the photoresist around the third via and the fourth via, as well as the second isolation trench, are removed. Then, the electrode layer material is deposited. Finally, the electrode layer material on the photoresist is removed using a stripping process, and the photoresist is removed. A P-type electrode layer is formed around the third via, and an N-type electrode layer is formed at the fourth via.

[0174] S10. The second isolation trench is subjected to photolithography and etching until the bonding layer is exposed. Then, metal Ti and metal Al are sequentially deposited using an electron beam evaporation device to form a stacked Ti layer and Al layer, and plasma surface treatment is performed to form an oxide layer. The plasma surface treatment includes: introducing oxygen as a reaction gas, with a radio frequency power of 1000W, a cavity pressure of 60Pa, and a duration of 20min. Finally, the metal Ti and metal Al on the photoresist are removed using lift-off, and the photoresist is removed to form a pin buffer layer in the second isolation trench.

[0175] Example 2

[0176] This embodiment provides a flip-chip high-voltage LED chip, which is basically the same as that in Embodiment 1, except that:

[0177] The ejector pin buffer layer includes a Ti layer and an Al layer arranged sequentially. An oxide layer is formed on the Al layer. The growth thickness of the Ti layer is 5 nm. The growth thickness of the Al layer is 100 nm. The oxide layer is an Al2O3 layer formed by plasma surface treatment of the Al layer. The plasma surface treatment includes: introducing oxygen as a reaction gas, with a radio frequency power of 200 W, a cavity pressure of 20 Pa, and a duration of 30 min.

[0178] Example 3

[0179] This embodiment provides a flip-chip high-voltage LED chip, which is basically the same as that in Embodiment 1, except that:

[0180] The ejector pin buffer layer includes a Ti layer and an Al layer arranged sequentially. An oxide layer is formed on the Al layer. The growth thickness of the Ti layer is 200 nm. The growth thickness of the Al layer is 3000 nm. The oxide layer is an Al2O3 layer formed by plasma surface treatment of the Al layer. The plasma surface treatment includes: introducing oxygen as a reaction gas, a radio frequency power of 2000 W, a cavity pressure of 100 Pa, and a duration of 10 min.

[0181] Example 4

[0182] This embodiment provides a flip-chip high-voltage LED chip, which is basically the same as that in Embodiment 1, except that:

[0183] The bonding layers consist of an Al2O3 layer and a SiO2 layer arranged sequentially, with the Al2O3 layer having a growth thickness of 500 Å and the SiO2 layer having a growth thickness of 10000 Å.

[0184] Comparative Example 1

[0185] This comparative example provides a flip-chip high-voltage LED chip, which is basically the same as that in Example 1, except that there is no pin buffer layer on the bonding layer.

[0186] Comparative Example 2

[0187] This comparative example provides a flip-chip high-voltage LED chip, which is basically the same as Example 1, except that the oxide layer is an Al2O3 layer.

[0188] Accordingly, the preparation method is as follows: metallic Ti and metallic Al are sequentially vaporized using an electron beam evaporation device to form a stacked Ti layer and Al layer, and then Al2O3 material is deposited on the Al layer using an atomic layer deposition process to form an Al2O3 layer.

[0189] Comparative Example 3

[0190] This comparative example provides a flip-chip high-voltage LED chip, which is basically the same as that in Example 1, except that:

[0191] The ejector pin buffer layer includes a Ti layer and a Ni layer arranged sequentially. An oxide layer is formed on the Ni layer, which is a nickel oxide layer formed by plasma surface treatment of the Ni layer.

[0192] Performance testing

[0193] The leakage failure rate of the flip-chip high-voltage LED chips obtained in the examples and comparative examples was tested using a more stringent pin pressure test (pin height was 150% of the conventional pin height). Pin height refers to the height difference between the point where the pin contacts the blue film as a reference and then pierces the blue film upwards to lift the chip. The test results are shown in Table 1 below.

[0194] Table 1 Performance test results of the examples and comparative examples

[0195]

[0196] As can be seen from the above results, in this application, a pin buffer layer is provided in the second isolation groove. The pin buffer layer includes a Ti layer and an Al layer arranged in sequence. An oxide layer is formed on the Al layer, which can prevent the flip-chip high voltage LED from cracking in the functional layer due to the impact of the pin, reduce the leakage failure rate, and thus improve its reliability.

[0197] The above description is merely a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A flip-chip high-voltage LED chip, characterized in that, It includes a substrate and an epitaxial layer stacked on the substrate, wherein a bonding layer is provided between the substrate and the epitaxial layer; The bonding layer has P-type conductive steps and isolation trenches, and the isolation trenches divide the flip-chip high-voltage LED into several light-emitting units; The bonding layer is provided with an ohmic contact layer, a first passivation layer, a bridging metal layer and a second passivation layer. The first passivation layer covers the ohmic contact layer. The bridging metal layer is disposed on the first passivation layer and is connected to the ohmic contact layer of the adjacent light-emitting unit through a first via and a second via. The second passivation layer covers the bridging metal layer. An electrode layer is provided on the second passivation layer, and the electrode layer is connected to the ohmic contact layer through a third through hole and a fourth through hole; The isolation trench includes a first isolation trench and a second isolation trench. A pin buffer layer is formed on the bonding layer. The pin buffer layer is disposed in the second isolation trench. The LED epitaxial layer, the first passivation layer, the bridging metal layer, and the second passivation layer in the second isolation trench area are all etched away. The pin buffer layer includes a Ti layer and an Al layer arranged sequentially. An oxide layer is formed on the Al layer. The oxide layer is an Al2O3 layer formed by plasma surface treatment of the Al layer.

2. The flip-chip high-voltage LED chip as described in claim 1, characterized in that, The growth thickness of the Ti layer is 5nm-200nm; The Al layer has a growth thickness of 100nm-3000nm; The thickness of the oxide layer is 10 Å-200 Å.

3. The flip-chip high-voltage LED chip as described in claim 1, characterized in that, The ohmic contact layer includes a P-type ohmic contact layer and an N-type ohmic contact layer. One end of the bridging metal layer is connected to the P-type ohmic contact layer of the light-emitting unit through the first through-hole, and the other end of the bridging metal layer is connected to the N-type ohmic contact layer of the adjacent light-emitting unit through the second through-hole. The electrode layer includes a P-type electrode layer and an N-type electrode layer. The P-type electrode layer is connected to the P-type ohmic contact layer of the light-emitting unit through the third through-hole, and the N-type electrode layer is connected to the N-type ohmic contact layer of the light-emitting unit through the fourth through-hole.

4. The flip-chip high-voltage LED chip as described in claim 1, characterized in that, The bonding layer comprises an Al2O3 layer and a SiO2 layer arranged sequentially, wherein the ratio of the thickness of the Al2O3 layer to the thickness of the SiO2 layer is 1:1 to 1:10000.

5. The flip-chip high-voltage LED chip as described in claim 4, characterized in that, The growth thickness of the Al2O3 layer in the bonding layer is 50 Å-5000 Å; The SiO2 layer has a growth thickness of 5000Å-50000Å.

6. The flip-chip high-voltage LED chip as described in claim 3, characterized in that, The P-type ohmic contact layer includes a P-type ohmic contact metal layer, a P-type pad layer, and a P-type passivation protection layer arranged sequentially; the P-type ohmic contact metal layer is selected from one or more of Au layer, AuBe layer, and AuZn layer; the P-type pad layer is selected from one or more of Ti layer, Al layer, Ni layer, Cr layer, TiW layer, and AlCu layer; and the P-type passivation protection layer is selected from Pt layer and / or Au layer.

7. The flip-chip high-voltage LED chip as described in claim 3, characterized in that, The N-type ohmic contact layer includes an N-type ohmic contact metal layer and an etch barrier layer arranged sequentially. The N-type ohmic contact metal layer is selected from one or more of Au layer, Ni layer, AuGe layer, and AuGeNi layer, and the etch barrier layer is selected from one or more of Ti layer, Pt layer, TiW layer, and Ni layer.

8. A method for fabricating a flip-chip high-voltage LED as described in any one of claims 1-7, characterized in that, Includes the following steps: A temporary substrate is provided, and an epitaxial layer is prepared on the temporary substrate; A bonding layer is deposited on the surface of the epitaxial layer; A substrate is provided, the substrate is bonded to an epitaxial layer, and the temporary substrate is removed; The epitaxial layer is etched to form a P-type conductive step and an isolation trench region, and an ohmic contact layer is prepared on the surface of the epitaxial layer. The isolation trench area is etched until the bonding layer is exposed to form a first isolation trench and a second isolation trench. A first passivation layer is prepared on the surface of the epitaxial layer to cover the ohmic contact layer, and the first passivation layer is etched to form a first through-hole and a second through-hole that penetrate into the ohmic contact layer. A bridging metal layer is prepared on the surface of the first passivation layer, at the first via and the second via, to connect adjacent light-emitting units; A second passivation layer is prepared on the surface of the first passivation layer to cover the bridging metal layer, and the second passivation layer is etched to form a third and a fourth through hole that penetrate to the ohmic contact layer and expose the second isolation trench. Electrode layers are prepared within the third and fourth through holes; Prepare a pin buffer layer in the second isolation groove; The ejector pin buffer layer includes a Ti layer and an Al layer arranged sequentially, and an oxide layer is formed on the Al layer.

9. The method for fabricating a flip-chip high-voltage LED as described in claim 8, characterized in that, The preparation of the ejector pin buffer layer in the second isolation groove specifically includes: The second isolation trench is subjected to photolithography and etching until the bonding layer is exposed; Metallic Ti and metallic Al are deposited sequentially to form stacked Ti and Al layers, and then plasma surface treatment is performed to form an oxide layer; Remove the photoresist by peeling; The plasma surface treatment includes: introducing oxygen as the reactant gas, using a radio frequency power of 200W-2000W, a chamber pressure of 20Pa-100Pa, and a duration of 10min-30min.

10. The method for fabricating a flip-chip high-voltage LED as described in claim 8, characterized in that, The preparation of the ohmic contact layer on the surface of the epitaxial layer specifically includes: A material for a P-type ohmic contact layer is deposited on the surface of the epitaxial layer and then annealed. The material of the N-type ohmic contact layer is deposited on the surface of the epitaxial layer, and part of the epitaxial layer is removed, followed by annealing. The annealing process includes: in a nitrogen atmosphere, treating the epitaxial layer of the material with the deposited P-type ohmic contact layer and / or N-type ohmic contact layer at a temperature of 280℃-500℃ for 1min-20min.

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