Display substrate, preparation method thereof and display device

Abstract

A display substrate, a manufacturing method thereof, and a display device. The display substrate includes a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes at least a first capacitor, a second capacitor, and a third transistor as a driving transistor. The first capacitor includes at least a first plate and a second plate stacked. The second capacitor includes at least a third plate and a fourth plate stacked. The first plate is connected to the third plate. The second plate is connected to a second electrode of the third transistor. The fourth plate is connected to a gate electrode of the third transistor. The first plate and the third plate each include a plurality of edges. A normal projection of the second plate on a plane of the display substrate contains at least one edge of the first plate. A normal projection of the fourth plate on the plane of the display substrate contains at least one edge of the third plate.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Currently, existing OLED display devices suffer from defects such as brightness changes caused by temperature rise. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by this disclosure is to provide a display substrate and its preparation method, as well as a display device, to solve defects such as brightness changes caused by temperature rise.

[0006] On one hand, this disclosure provides a display substrate including multiple circuit units, at least one circuit unit including a pixel driving circuit, the pixel driving circuit including at least a first capacitor, a second capacitor and a third transistor as a driving transistor, the first capacitor including at least a stacked first electrode plate and a second electrode plate, the orthographic projection of the second electrode plate on the display substrate plane at least partially overlapping the orthographic projection of the first electrode plate on the display substrate plane, the second capacitor including at least a stacked third electrode plate and a fourth electrode plate, the orthographic projection of the fourth electrode plate on the display substrate plane at least partially overlapping the orthographic projection of the third electrode plate on the display substrate plane; the first electrode plate is connected to the third electrode plate, the second electrode plate is connected to the second electrode of the third transistor, and the fourth electrode plate is connected to the gate electrode of the third transistor; both the first electrode plate and the third electrode plate include multiple edges, the orthographic projection of the second electrode plate on the display substrate plane includes at least one edge of the first electrode plate, and the orthographic projection of the fourth electrode plate on the display substrate plane includes at least one edge of the third electrode plate.

[0007] In an exemplary embodiment, the third electrode plate is disposed on one side of the first electrode plate in a second direction and is connected to the first electrode plate by an electrode plate connecting strip. In a first direction, the width of the electrode plate connecting strip is smaller than the width of the first electrode plate and the width of the third electrode plate are smaller than the width of the first electrode plate. The first direction and the second direction intersect.

[0008] In an exemplary embodiment, the ratio of the width of the electrode connecting strip to the width of the first electrode is 0.1 to 0.2, and the ratio of the width of the electrode connecting strip to the width of the third electrode is 0.1 to 0.2.

[0009] In an exemplary embodiment, in the first direction, the edges of the first electrode plate, the third electrode plate, and the electrode plate connecting strip on the same side are flush.

[0010] In an exemplary embodiment, the plurality of edges of the first electrode plate include at least a first edge on the side of the third electrode plate in the second direction, a second edge on the side of the third electrode plate away from the third electrode plate in the second direction, a third edge on the side of the electrode plate connecting strip in the first direction, and a fourth edge on the side of the electrode plate connecting strip away from the electrode plate in the first direction, and the orthographic projection of the second electrode plate on the display substrate plane includes at least the first edge.

[0011] In an exemplary embodiment, the orthographic projection of the second electrode plate onto the display substrate plane further includes the second edge, the third edge, and the fourth edge.

[0012] In an exemplary embodiment, the plurality of edges of the third electrode plate include at least a fifth edge on the side of the first electrode plate in the second direction, a sixth edge on the side of the first electrode plate away from the first electrode plate in the second direction, a seventh edge on the side of the electrode plate connecting strip in the first direction, and an eighth edge on the side of the electrode plate connecting strip in the first direction, and the orthographic projection of the fourth electrode plate on the display substrate plane includes at least the fifth edge.

[0013] In an exemplary embodiment, the orthographic projection of the fourth electrode plate onto the display substrate plane further includes the seventh edge.

[0014] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer disposed on a substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, a semiconductor layer disposed on a side of the second conductive layer away from the substrate, a third conductive layer disposed on a side of the semiconductor layer away from the substrate, and a fourth conductive layer disposed on a side of the third conductive layer away from the substrate; the electrode connecting strip is disposed in the first conductive layer, and the orthographic projection of the semiconductor layer on the plane of the display substrate at least partially overlaps with the orthographic projection of the electrode connecting strip on the plane of the display substrate, or the electrode connecting strip is disposed in the fourth conductive layer.

[0015] In an exemplary embodiment, at least one circuit unit further includes a first connection electrode having a first node potential, a second connection electrode having a second node potential, and a third connection electrode having a third node potential. The fourth electrode plate is connected to the gate electrode of the third transistor through the first node electrode, the third electrode plate is connected to the second connection electrode, and the second electrode plate is connected to the second electrode of the third transistor through the third node electrode.

[0016] In an exemplary embodiment, at least one circuit unit further includes a gate connection strip connected to the gate electrode of the third transistor, a first end of the first connection electrode being connected to the fourth electrode plate via a via, and a second end of the first connection electrode being connected to the gate connection strip via a via.

[0017] In an exemplary embodiment, the pixel driving circuit further includes a second transistor as a second reset transistor, the second transistor including at least a second active layer, the first end of the second connection electrode being connected to a second region of the second active layer through a via, and the second end of the second connection electrode being connected to the third electrode plate through a via.

[0018] In an exemplary embodiment, the third transistor includes at least a third active layer, the first end of the third node electrode is connected to the second region of the third active layer through a via, and the second end of the third connection electrode is connected to the second electrode plate through a via.

[0019] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer disposed on a substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, a third conductive layer disposed on a side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on a side of the third conductive layer away from the substrate. The first electrode and the third electrode are disposed in the first conductive layer, the second electrode and the fourth electrode are disposed in the second conductive layer, the gate electrode of the third transistor is disposed in the third conductive layer, and the first connection electrode, the second connection electrode and the third connection electrode are disposed in the fourth conductive layer.

[0020] In an exemplary embodiment, the pixel driving circuit further includes a node coupling capacitor, which includes at least a first coupling plate and a second coupling plate stacked together. The first coupling plate is connected to the gate electrode of the third transistor, and the second coupling plate is connected to the second electrode of the third transistor.

[0021] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer disposed on a substrate, a second conductive layer disposed on the side of the first conductive layer away from the substrate, and a semiconductor layer disposed on the side of the second conductive layer away from the substrate. The fourth electrode plate serves as the first coupling electrode plate and is disposed in the second conductive layer, and the second coupling electrode plate is disposed in the semiconductor layer.

[0022] In an exemplary embodiment, the third transistor includes at least a third active layer disposed in the semiconductor layer and connected to the second coupling plate.

[0023] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer disposed on a substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, a semiconductor layer disposed on a side of the second conductive layer away from the substrate, a third conductive layer disposed on a side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on a side of the third conductive layer away from the substrate. The fourth electrode plate serves as the first coupling electrode plate and is disposed in the second conductive layer. The second coupling electrode plate is disposed in the third conductive layer, or the second coupling electrode plate is disposed in the fourth conductive layer.

[0024] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0025] In another aspect, this disclosure also provides a method for fabricating a display substrate, the display substrate comprising a plurality of circuit units, the fabrication method comprising:

[0026] A pixel driving circuit is formed in at least one circuit unit. The pixel driving circuit includes at least a first capacitor, a second capacitor, and a third transistor as a driving transistor. The first capacitor includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The second capacitor includes at least a third electrode plate and a fourth electrode plate stacked together. The orthographic projection of the fourth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the third electrode plate on the display substrate plane. The first electrode plate is connected to the third electrode plate, the second electrode plate is connected to the second electrode of the third transistor, and the fourth electrode plate is connected to the gate electrode of the third transistor. Both the first electrode plate and the third electrode plate include multiple edges. The orthographic projection of the second electrode plate on the display substrate plane includes at least one edge of the first electrode plate, and the orthographic projection of the fourth electrode plate on the display substrate plane includes at least one edge of the third electrode plate.

[0027] This disclosure provides a display substrate and its preparation method, as well as a display device. By covering the edges of the first and third electrodes with a second electrode and a fourth electrode respectively, the parasitic capacitance of the second node can be effectively reduced, the change in the output current of the pixel driving circuit can be effectively reduced, the change in the luminous brightness can be effectively reduced, and the display quality and display performance can be improved.

[0028] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0029] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0030] Figure 1 This is a schematic diagram of the structure of a display device;

[0031] Figure 2 This is a schematic diagram of a planar structure of a display substrate;

[0032] Figure 3 This is a schematic diagram of a cross-sectional structure of a display substrate;

[0033] Figure 4 This is an equivalent circuit diagram of a pixel driving circuit;

[0034] Figure 5 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0035] Figure 6 for Figure 5A schematic diagram of the capacitor structure;

[0036] Figure 7 This is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to the present disclosure;

[0037] Figure 8A and Figure 8B This is a schematic diagram of a display substrate after the formation of a second conductive layer pattern according to the present disclosure;

[0038] Figure 9A and Figure 9B This is a schematic diagram of a display substrate after a semiconductor layer pattern has been formed.

[0039] Figure 10A and Figure 10B This is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to the present disclosure;

[0040] Figure 11 This is a schematic diagram of a display substrate after the formation of a fourth insulating layer pattern according to the present disclosure;

[0041] Figure 12A and Figure 12B This is a schematic diagram of a display substrate after the formation of a fourth conductive layer pattern according to the present disclosure;

[0042] Figure 13 This is a schematic diagram of a display substrate after the formation of a fifth insulating layer and a first planarization layer pattern according to the present disclosure;

[0043] Figure 14A and Figure 14B This is a schematic diagram of a display substrate after the fifth conductive layer pattern has been formed.

[0044] Explanation of reference numerals in the attached figures:

[0045] 10—First capacitor; 11—First plate; 12—Second plate;

[0046] 13—Third plate; 14—Fourth plate; 15—Fifth plate;

[0047] 16—Electrode connecting strip; 20—Second capacitor; 21—First active layer;

[0048] 22—Second active layer; 23—Third active layer; 24—Fourth active layer;

[0049] 25—Fifth active layer; 26—Sixth active layer; 27—Seventh active layer;

[0050] 28—First active connector; 29—Second active connector; 31—First gate electrode;

[0051] 32—Second gate electrode; 33—Third gate electrode; 34—Fourth gate electrode;

[0052] 35—Fifth gate electrode; 36—Sixth gate electrode; 37—Seventh gate electrode;

[0053] 38—Gate connection bar; 41—First light-emitting signal line; 42—Second light-emitting signal line;

[0054] 51—First connecting electrode; 52—Second connecting electrode; 53—Third connecting electrode;

[0055] 54—Fourth connecting electrode; 55—Fifth connecting electrode; 56—Sixth connecting electrode;

[0056] 61—First scan signal line; 62—Second scan signal line; 63—Third scan signal line;

[0057] 64—Fourth scan signal line; 65—First power supply connection line; 66—Second power supply connection line;

[0058] 71—First initial signal line; 72—Second initial signal line; 73—First initial connection line;

[0059] 74—Second initial connection line; 81—First power line; 82—Second power line;

[0060] 83—Data signal line; 84—Anode connection electrode; 101—Substrate;

[0061] 102—Driving structure layer; 103—Light-emitting structure layer; 104—Encapsulation structure layer. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0063] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0064] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0065] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0066] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0067] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the area through which current primarily flows.

[0068] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0069] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0070] In this specification, "parallel" refers to two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" refers to two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0071] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0072] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances, and may include chamfers, curved edges, and other variations. The term "approximately" in this disclosure means that the limits are not strictly defined, and the values ​​are within the allowable range of process and measurement errors.

[0073] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple first light-emitting signal lines (E1 to Eo). n, m, and o can be natural numbers. The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal. The light-emitting driver can generate transmit signals to be provided to the first light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the first light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0074] Figure 2 This is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0075] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a green sub-pixel (G) that emits green light, and the third sub-pixel P3 can be a blue sub-pixel (B) that emits blue light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner.

[0076] In other exemplary embodiments, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0077] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels within the substrate. Figure 3 As shown, on a plane perpendicular to the display substrate, the display area may include a driving structure layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display area may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0078] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving structure layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include a light-emitting device. The light-emitting device can include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0079] Figure 4 This is an equivalent circuit diagram of a pixel driving circuit. (Example) Figure 4 As shown, the pixel driving circuit adopts a 7T2C structure. Each pixel driving circuit can include 7 transistors (first transistor T1 to seventh transistor T7) and 2 capacitors (first capacitor C1 and second capacitor C2). The pixel driving circuit is connected to 10 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, first light emission signal line EM1, second light emission signal line EM2, first initial signal line INIT1, second initial signal line INIT2, data signal line DATA and first power supply line VDD).

[0080] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second terminal of the first transistor T1, the gate electrode of the third transistor T3, the second terminal of the fourth transistor T4, and the first terminal of the second capacitor C2. The second node N2 is connected to the second terminal of the second transistor T2, the second terminal of the first capacitor C1, and the second terminal of the second capacitor C2. The third node N3 is connected to the second terminal of the third transistor T3, the first terminal of the sixth transistor T6, and the first terminal of the first capacitor C1. The fourth node N4 is connected to the second terminal of the sixth transistor T6 and the second terminal of the seventh transistor T7.

[0081] In an exemplary embodiment, the first transistor T1 may be referred to as the first reset transistor. The gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the first node N1.

[0082] In an exemplary embodiment, the second transistor T2 can be referred to as the second reset transistor. The gate electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the first initial signal line INIT1, and the second electrode of the second transistor T2 is connected to the second node N2.

[0083] In an exemplary embodiment, the third transistor T3 can be referred to as the driving transistor. The gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second electrode of the fifth transistor T5, and the second electrode of the third transistor T3 is connected to the third node N3.

[0084] In an exemplary embodiment, the fourth transistor T4 can be referred to as a data write transistor. The gate electrode of the fourth transistor T4 is connected to the fourth scan signal line S4, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the first node N1.

[0085] In an exemplary embodiment, the fifth transistor T5 can be referred to as the first light-emitting control transistor. The gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line EM1, and the first electrode of the fifth transistor T5 is connected to the first power supply line VDD.

[0086] In an exemplary embodiment, the sixth transistor T6 can be referred to as the second light-emitting control transistor. The gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0087] In an exemplary embodiment, the seventh transistor T7 can be referred to as the third reset transistor. The gate electrode of the seventh transistor T7 is connected to the third scan signal line S3, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0088] In an exemplary embodiment, the first terminal of the first capacitor C1 is connected to the third node N3, and the second terminal of the first capacitor C1 is connected to the second node N2. The first terminal of the second capacitor C2 is connected to the first node N1, and the second terminal of the second capacitor C2 is connected to the second node N2.

[0089] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0090] In an exemplary embodiment, the first power line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS can be configured to provide a constant second voltage signal to the light-emitting device. The voltage of the first voltage signal is greater than the voltage of the second voltage signal, i.e., the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The first initial signal line INIT1 and the second initial signal line INIT2 can be configured to provide constant signals to the pixel driving circuit; this disclosure does not limit the scope of the application.

[0091] In an exemplary embodiment, the seven transistors in the pixel driving circuit can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve the product yield.

[0092] In an exemplary embodiment, all seven transistors in the pixel driving circuit can be oxide transistors. The active layer of the oxide transistor can be oxide semiconductor. Oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage current. Using a display substrate with oxide transistors can achieve low-frequency driving, reduce power consumption, and improve display quality.

[0093] An exemplary embodiment of this disclosure provides a display substrate. In a direction perpendicular to the display substrate, the display substrate may include at least a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. In a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units forming a plurality of cell rows and a plurality of cell columns. Each circuit unit may include at least a pixel driving circuit. The light-emitting structure layer may include a plurality of light-emitting units, each light-emitting unit may include at least a light-emitting device. At least one pixel driving circuit is connected to at least one light-emitting unit, and the pixel driving circuit is configured to provide a driving signal to the connected light-emitting device to drive the corresponding light-emitting device to emit light.

[0094] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0095] The display substrate of the exemplary embodiments of this disclosure may include multiple circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes at least a first capacitor, a second capacitor, and a third transistor as a driving transistor. The first capacitor includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate onto the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate onto the display substrate plane. The second capacitor includes at least a third electrode plate and a fourth electrode plate stacked together. The orthographic projection of the fourth electrode plate onto the display substrate plane at least partially overlaps with the orthographic projection of the third electrode plate onto the display substrate plane. The first electrode plate is connected to the third electrode plate, the second electrode plate is connected to the second electrode of the third transistor, and the fourth electrode plate is connected to the gate electrode of the third transistor. Both the first electrode plate and the third electrode plate include multiple edges. The orthographic projection of the second electrode plate onto the display substrate plane includes at least one edge of the first electrode plate, and the orthographic projection of the fourth electrode plate onto the display substrate plane includes at least one edge of the third electrode plate.

[0096] In an exemplary embodiment, the third electrode plate is disposed on one side of the first electrode plate in a second direction and is connected to the first electrode plate by an electrode plate connecting strip. In a first direction, the width of the electrode plate connecting strip is smaller than the width of the first electrode plate and the width of the third electrode plate are smaller than the width of the first electrode plate. The first direction and the second direction intersect.

[0097] In an exemplary embodiment, at least one circuit unit further includes a first connection electrode having a first node potential, a second connection electrode having a second node potential, and a third connection electrode having a third node potential. The fourth electrode plate is connected to the gate electrode of the third transistor through the first node electrode, the third electrode plate is connected to the second connection electrode, and the second electrode plate is connected to the second electrode of the third transistor through the third node electrode.

[0098] In an exemplary embodiment, the pixel driving circuit further includes a node coupling capacitor, which includes at least a first coupling plate and a second coupling plate stacked together. The first coupling plate is connected to the gate electrode of the third transistor, and the second coupling plate is connected to the second electrode of the third transistor.

[0099] Figure 5 This is a schematic diagram of the structure of a display substrate, illustrating the structure of three circuit units, as an exemplary embodiment of the present disclosure. Figure 6 for Figure 5 A schematic diagram of the capacitor structure. (See diagram below.) Figure 5 and Figure 6As shown, on a plane parallel to the display substrate, the display substrate may include multiple circuit units forming multiple cell rows and multiple cell columns. At least one circuit unit may include a pixel driving circuit, and a first light-emitting signal line 41, a second light-emitting signal line 42, a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a first initial signal line 65, a second initial signal line 66, a first power supply line (not shown), and a data signal line (not shown) connected to the pixel driving circuit. At least one pixel driving circuit may include at least a first capacitor 10, a second capacitor 20, a first transistor T1 as a first reset transistor, a second transistor T2 as a second reset transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, and a seventh transistor T7 as a third reset transistor.

[0100] In an exemplary embodiment, the shapes of the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the first light emission signal line 41, the second light emission signal line 42, the first initial signal line 65, and the second initial signal line 66 can be straight lines or broken lines extending along the first direction X of the main body, and the shapes of the first power line and the data signal line can be straight lines or broken lines extending along the second direction Y of the main body.

[0101] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0102] In an exemplary embodiment, the first light-emitting signal line 41 and the second light-emitting signal line 42 are configured to provide a first light-emitting control signal and a second light-emitting control signal to the pixel driving circuit, respectively; the first scan signal line 61 to the fourth scan signal line 64 are configured to provide a first scan signal to a fourth scan signal to the pixel driving circuit, respectively; the first initial signal line 65 and the second initial signal line 66 are configured to provide a first initial signal and a second initial signal to the pixel driving circuit, respectively; the first power supply line is configured to provide a first power supply signal to the pixel driving circuit; and the data signal line is configured to provide a data signal to the pixel driving circuit.

[0103] In an exemplary embodiment, the first capacitor 10 may include at least a first electrode 11 and a second electrode 12 stacked together, wherein the orthographic projection of the second electrode 12 onto the substrate at least partially overlaps with the orthographic projection of the first electrode 11 onto the substrate. The second capacitor 20 may include at least a third electrode 13 and a fourth electrode 14 stacked together, wherein the orthographic projection of the fourth electrode 14 onto the substrate at least partially overlaps with the orthographic projection of the third electrode 13 onto the substrate.

[0104] In an exemplary embodiment, the third electrode plate 13 may be disposed on one side of the first electrode plate 11 in the second direction Y and connected to each other by the electrode plate connecting strip 16, and the fourth electrode plate 14 may be disposed on one side of the second electrode plate 12 in the second direction Y and spaced apart.

[0105] In an exemplary embodiment, in the first direction X, the width of the electrode connecting strip 16 may be less than the width of the first electrode 11, and the width of the electrode connecting strip 16 may be less than the width of the third electrode 13.

[0106] In an exemplary embodiment, the ratio of the width of the electrode connecting strip 16 to the width of the first electrode 11 can be approximately 0.1 to 0.2, and the ratio of the width of the electrode connecting strip 16 to the width of the third electrode 13 can be approximately 0.1 to 0.2.

[0107] In an exemplary embodiment, in the first direction X, the edges of the first electrode plate 11, the third electrode plate 13, and the electrode plate connecting strip 16 on the same side can be substantially flush.

[0108] In an exemplary embodiment, the first electrode 11 may include multiple edges, the third electrode 13 may include multiple edges, the orthographic projection of the second electrode 12 onto the substrate may include at least one edge of the first electrode 11, and the orthographic projection of the fourth electrode 14 onto the substrate may include at least one edge of the third electrode 13.

[0109] In an exemplary embodiment, the plurality of edges of the first electrode plate 11 may include at least a first edge on the side of the third electrode plate 13 in the second direction Y, a second edge on the side of the third electrode plate 13 away from the third electrode plate 13 in the second direction Y, a third edge on the side of the electrode plate connecting strip 16 in the first direction X, and a fourth edge on the side of the electrode plate connecting strip 16 away from the first direction X. The plurality of edges of the third electrode plate 13 may include at least a fifth edge on the side of the first electrode plate 11 in the second direction Y, a sixth edge on the side of the first electrode plate 11 away from the first electrode plate 11 in the second direction Y, a seventh edge on the side of the electrode plate connecting strip 16 in the first direction X, and an eighth edge on the side of the electrode plate connecting strip 16 away from the first direction X.

[0110] In an exemplary embodiment, the orthographic projection of the second electrode plate 12 onto the substrate may include at least the first edge, that is, the second electrode plate 12 at least covers the edge of the first electrode plate 11 on the side near the third electrode plate 13.

[0111] In an exemplary embodiment, the orthographic projection of the second electrode plate 12 onto the substrate may further include a second edge, a third edge, and a fourth edge, that is, the orthographic projection of the second electrode plate 12 onto the substrate includes the orthographic projection of the first electrode plate 11 onto the substrate.

[0112] In an exemplary embodiment, the orthographic projection of the fourth electrode plate 14 onto the substrate may include at least the fifth edge, that is, the fourth electrode plate 14 at least covers the edge of the third electrode plate 13 on the side close to the first electrode plate 11.

[0113] In an exemplary embodiment, the orthographic projection of the fourth electrode 14 onto the substrate may also include a seventh edge.

[0114] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be oxide transistors. The gate electrode of the first transistor T1 is connected to the first scan signal line 61, the first terminal of the first transistor T1 is connected to the first initial signal line 65, the second terminal of the first transistor T1 and the second terminal of the fourth transistor T4 are interconnected, and are connected to the third gate electrode 33 (the gate electrode of the third transistor T3) through the sixth connection electrode 56. The third gate electrode 33 is connected to the fourth plate 14 through the gate connection bar 38 and the first connection electrode 51. The gate electrode of the second transistor T2 is connected to the second scan signal line 62, the first terminal of the second transistor T2 is connected to the first initial signal line 65, and the second terminal of the second transistor T2 is connected to the third plate 13 through the second connection electrode 52. The first terminal of the third transistor T3 and the second terminal of the fifth transistor T5 are connected, the second terminal of the third transistor T3 and the first terminal of the sixth transistor T6 are connected, and are connected to the second plate 12 through the third connection electrode 53. The gate electrode of the fourth transistor T4 is connected to the fourth scan signal line 64, and the first terminal of the fourth transistor T4 is connected to the data signal line. The gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line 41, and the first electrode of the fifth transistor T5 is connected to the first power supply line. The gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line 42, and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 are connected to each other. The gate electrode of the seventh transistor T7 is connected to the third scan signal line 63, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 66.

[0115] In an exemplary embodiment, the first connecting electrode 51 and the sixth connecting electrode 56 have a first node potential, the second connecting electrode 52 has a second node potential, and the third connecting electrode 53 has a third node potential.

[0116] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a first conductive layer (first gate metal layer) disposed on the substrate, a second conductive layer (second gate metal layer) disposed on the side of the first conductive layer away from the substrate, a semiconductor layer disposed on the side of the second conductive layer away from the substrate, a third conductive layer (third gate metal layer) disposed on the side of the semiconductor layer away from the substrate, and a fourth conductive layer (first source / drain metal layer) disposed on the side of the third conductive layer away from the substrate.

[0117] In an exemplary embodiment, the first electrode plate 11, the third electrode plate 13, and the electrode plate connecting strip 16 can be disposed in the first conductive layer. The first electrode plate 11, the third electrode plate 13, and the electrode plate connecting strip 16 can be an integral structure that is interconnected. The first end of the second connecting electrode 52 is connected to the second electrode (the second region of the second active layer) of the second transistor T2 through a via, and the second end of the second connecting electrode 52 is connected to the third electrode plate 13 through a via. Therefore, the first electrode plate 11 and the third electrode plate 13 have a second node potential. The second node potential refers to the potential of the second node N2 in the pixel driving circuit.

[0118] In an exemplary embodiment, the second electrode plate 12 may be disposed in the second conductive layer, the first end of the third connecting electrode 53 is connected to the second electrode (second region of the third active layer) of the third transistor T3 through a via, and the second end of the third connecting electrode 53 is connected to the second electrode plate 12 through a via, so the second electrode plate 12 has a third node potential, which refers to the potential of the second node N3 in the pixel driving circuit.

[0119] In an exemplary embodiment, a first electrode 11 having a second node potential and a second electrode 12 having a third node potential form a first capacitor C1 of a pixel driving circuit.

[0120] In an exemplary embodiment, the fourth electrode plate 14 may be disposed in the second conductive layer. The first end of the first connecting electrode 51 is connected to the fourth electrode plate 14 through a via, and the second end of the first connecting electrode 51 is connected to the gate connecting strip 38 through a via. The gate connecting strip 38 is connected to the third gate electrode 33 (the gate electrode of the third transistor T3). Therefore, the fourth electrode plate 14 has a first node potential, which refers to the potential of the first node N1 in the pixel driving circuit.

[0121] In an exemplary embodiment, a third electrode 13 having a second node potential and a fourth electrode 14 having a first node potential form a second capacitor C2 of the pixel driving circuit.

[0122] In an exemplary embodiment, the third gate electrode 33 and the gate connecting strip 38 can be disposed in the third conductive layer and are an integral structure that is interconnected.

[0123] In an exemplary embodiment, the first connecting electrode 51, the second connecting electrode 52, and the third connecting electrode 53 may be disposed in the fourth conductive layer.

[0124] In an exemplary embodiment, the pixel driving circuit may further include a node coupling capacitor. The node coupling capacitor may include at least a stacked first coupling plate and a second coupling plate. The first coupling plate is connected to the third gate electrode 33 and has a first node potential. The second coupling plate is connected to the second electrode of the third transistor T3 and has a third node potential. The orthographic projection of the second coupling plate onto the substrate at least partially overlaps with the orthographic projection of the first coupling plate onto the substrate. The first coupling plate with the first node potential and the second coupling plate with the third node potential form a node coupling capacitor between the first node N1 and the third node N3 in the pixel driving circuit.

[0125] In an exemplary embodiment, the fourth electrode 14 disposed in the second conductive layer can serve as the first coupling electrode, and the fifth electrode 15 disposed in the semiconductor layer can serve as the second coupling electrode. The fifth electrode 15 can be connected to the third active layer of the third transistor T3.

[0126] In an exemplary embodiment, the pixel driving circuits in adjacent cell columns can be substantially mirror-symmetrical with respect to the column center line, which can be a broken line located between adjacent cell columns and extending along the second direction Y. For example, the pixel driving circuits in the Nth cell column and the (N+1)th cell column can be substantially mirror-symmetrical with respect to the column center line. Similarly, the pixel driving circuits in the (N+1)th cell column and the (N+2)th cell column can be substantially mirror-symmetrical with respect to the column center line.

[0127] In an exemplary embodiment, at least one circuit unit may further include a first power connection line 65 extending along the first direction X and connected to a first power line. The first power connection line 65 and the first power line form a mesh-like interconnected structure on the display substrate for transmitting a first power signal.

[0128] In an exemplary embodiment, at least one circuit unit may further include a second power connection line 66 extending along the first direction X and connected to a second power line. The second power connection line 66 and the second power line form a mesh-like interconnected structure on the display substrate for transmitting a second power signal.

[0129] In an exemplary embodiment, the fourth scan signal line 64 may be located on the side opposite to the second direction Y of the third gate electrode 33, the second power connection line 66 may be located on the side of the fourth scan signal line 64 away from the third gate electrode 33, and the first power connection line 65 may be located on the side of the second power connection line 66 away from the third gate electrode 33. The first scan signal line 61 may be located on the side of the third gate electrode 33 in the second direction Y, the first initial signal line 65 may be located on the side of the first scan signal line 61 away from the third gate electrode 33, the second scan signal line 62 may be located on the side of the first initial signal line 65 away from the third gate electrode 33, the second initial signal line 66 may be located on the side of the second scan signal line 62 away from the third gate electrode 33, and the third scan signal line 63 may be located on the side of the second initial signal line 66 away from the third gate electrode 33.

[0130] In an exemplary embodiment, the first light-emitting signal line 41 and the second light-emitting signal line 42 may be disposed in the third conductive layer, and the first scan signal line 61, the second scan signal line 62, the third scan signal line 63 and the fourth scan signal line 64 may be disposed in the fourth conductive layer.

[0131] In an exemplary embodiment, the display substrate may further include a fifth conductive layer (second source / drain metal layer) disposed on the side of the fourth conductive layer away from the substrate 101. The fifth conductive layer may include at least a first power line, a second power line, and a data signal line.

[0132] In an exemplary embodiment, the fifth conductive layer may further include a first initial connection line extending along the second direction Y and connected to a first initial signal line 65. The first initial signal line 65 and the first initial connection line form a mesh-like interconnected structure on the display substrate for transmitting the first initial signal.

[0133] In an exemplary embodiment, the fifth conductive layer may further include a second initial connection line extending along the second direction Y and connected to the second initial signal line 66. The second initial signal line 66 and the second initial connection line form a mesh-like interconnected structure on the display substrate for transmitting the second initial signal.

[0134] The following exemplary description illustrates the fabrication process of the display substrate using this exemplary embodiment. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film layer, coating the film layer with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include coating the organic material, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching, and this disclosure does not limit the methods. A "thin film" refers to a thin film made by depositing, coating, or other processes onto a substrate using a certain material. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0135] In an exemplary embodiment, taking three circuit units with one cell row and three cell columns (the Nth cell column, the N+1th cell column, and the N+2th cell column) as an example, the fabrication process of the display substrate in this embodiment may include the following operations.

[0136] (11) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive thin film on a substrate, patterning the first conductive thin film using a patterning process, and forming the first conductive layer pattern on the substrate, such as... Figure 7 As shown. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0137] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate may include at least the first electrode 11 of the first capacitor, the third electrode 13 of the second capacitor, and the electrode connecting strip 16.

[0138] In an exemplary embodiment, the first plate 11 of the first capacitor may be rectangular in shape, and the corners of the rectangle may be provided with chamfers, grooves or protrusions. The first plate 11 is configured as the lower plate of the first capacitor (the second end of the first capacitor C1).

[0139] In an exemplary embodiment, the third plate 13 of the second capacitor can be rectangular in shape, and the corners of the rectangle can be provided with chamfers, grooves or protrusions. The third plate 13 is configured as the lower plate of the second capacitor (the second end of the second capacitor C2).

[0140] In an exemplary embodiment, the third electrode plate 13 can be disposed on one side of the first electrode plate 11 in the second direction Y, and the electrode plate connecting strip 16 can be disposed between the first electrode plate 11 and the third electrode plate 13. The first end of the electrode plate connecting strip 16 is connected to the first electrode plate 11, and the second end of the electrode plate connecting strip 16 is connected to the third electrode plate 13. That is, the third electrode plate 13 is connected to the first electrode plate 11 through the electrode plate connecting strip 16, thereby realizing the mutual connection between the second end of the first capacitor C1 and the second end of the second capacitor C2. In an exemplary embodiment, in at least one circuit unit, the first electrode plate 11, the third electrode plate 13, and the electrode plate connecting strip 16 can be an integral structure that is interconnected.

[0141] In an exemplary embodiment, in at least one circuit unit, the edges of the first electrode 11, the third electrode 13, and the electrode connecting strip 16 on the same side can be substantially flush. For example, in the Nth and N+2th unit columns, the edges of the first electrode 11, the third electrode 13, and the electrode connecting strip 16 on the opposite side of the first direction X can be substantially flush. Similarly, in the N+1th unit column, the edges of the first electrode 11, the third electrode 13, and the electrode connecting strip 16 on the first direction X side can be substantially flush.

[0142] In an exemplary embodiment, the first electrode plate 11 may have a first width L1, the electrode plate connecting strip 16 may have a second width L2, and the third electrode plate 13 may have a third width L3. The second width L2 may be smaller than the first width L1, and the second width L2 may be smaller than the third width L3. The first width L1, the second width L2, and the third width L3 may be dimensions in the first direction X.

[0143] In an exemplary embodiment, the ratio of the second width L2 to the first width L1 can be 0.1 to 0.2, and the ratio of the second width L2 to the third width L3 can be 0.1 to 0.2, meaning the width of the electrode connecting strip 16 is much smaller than the width of the first electrode 11 and the width of the third electrode 13. Since the third electrode 13 is connected to the second electrode of the second transistor T2 through a subsequently formed second connection electrode, the first electrode 11 and the third electrode 13 have a second node potential. This disclosure achieves the connection between the first electrode 11 and the third electrode 13 by setting a electrode connecting strip with a smaller width, which can effectively reduce the overlap capacitance between the structure connecting the first electrode 11 and the third electrode 13 (second node N2) and the related signal lines, and can effectively reduce the parasitic capacitance of the second node N2.

[0144] In an exemplary embodiment, in the second direction Y, the first electrode plate 11 may have a first edge 11-1 near the side of the third electrode plate 13 and a second edge 11-2 away from the side of the third electrode plate 13. In the first direction X, the first electrode plate 11 may have a third edge 11-3 near the side of the electrode plate connecting strip 16 and a fourth edge 11-4 away from the side of the electrode plate connecting strip 16.

[0145] In an exemplary embodiment, in the second direction Y, the third electrode plate 13 may have a fifth edge 13-5 near the first electrode plate 11 and a sixth edge 13-6 away from the first electrode plate 11, and in the first direction X, the third electrode plate 13 may have a seventh edge 13-7 near the electrode plate connecting strip 16 and an eighth edge 13-8 away from the electrode plate connecting strip 16.

[0146] In an exemplary embodiment, in at least one circuit unit, the third edge 11-3, the seventh edge 13-7, and one edge of the electrode connecting strip 16 may be substantially flush.

[0147] In an exemplary embodiment, in at least one circuit unit, the fourth edge 11-4 and the eighth edge 13-8 may be substantially flush.

[0148] In an exemplary embodiment, in at least one circuit unit, the first edge 11-1 and the second edge 11-2 may be substantially parallel, and the third edge 11-3 and the fourth edge 11-4 may be substantially parallel.

[0149] In an exemplary embodiment, in at least one circuit unit, the fifth edge 13-5 and the sixth edge 13-6 may be substantially parallel, and the seventh edge 13-7 and the eighth edge 13-8 may be substantially parallel.

[0150] In an exemplary embodiment, the first conductive layer in adjacent cell columns can be substantially mirror-symmetrical with respect to the column center line. For example, the first conductive layers in the Nth cell column and the (N+1)th cell column can be substantially mirror-symmetrical with respect to the column center line. Similarly, the first conductive layers in the (N+1)th cell column and the (N+2)th cell column can be substantially mirror-symmetrical with respect to the column center line.

[0151] (12) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a first insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a first insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the first insulating layer, such as... Figure 8A and Figure 8B As shown, Figure 8B for Figure 8AA schematic planar view of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0152] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: the second electrode 12 of the first capacitor and the fourth electrode 14 of the second capacitor.

[0153] In an exemplary embodiment, the second electrode plate 12 may be rectangular in shape, and the corners of the rectangle may be provided with chamfers, grooves or protrusions. The orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The second electrode plate 12 is configured as the upper electrode plate of the first capacitor (the first end of the first capacitor C1). The first electrode plate 11 and the second electrode plate 12 constitute the first capacitor C1 of the pixel driving circuit.

[0154] In an exemplary embodiment, the orthographic projection of the second electrode 12 onto the substrate may include at least one edge of the first electrode 11.

[0155] In an exemplary embodiment, the orthographic projection of the second electrode plate 12 onto the substrate may include a first edge 11-1, that is, the second electrode plate 12 at least covers the edge of the first electrode plate 11 on the side near the third electrode plate 13.

[0156] In an exemplary embodiment, the orthographic projection of the second electrode plate 12 onto the substrate may further include the second edge 11-2, the third edge 11-3, and the fourth edge 11-4, that is, the orthographic projection of the second electrode plate 12 onto the substrate includes the orthographic projection of the first electrode plate 11 onto the substrate. This disclosure, by setting the edge of the upper electrode plate 12 to cover the edge of the lower electrode plate 11, forms an upper-wrapped-lower structure, which can effectively reduce the overlap capacitance between multiple edges (second node N2) of the first electrode plate 11 and related signal lines, and can effectively reduce the parasitic capacitance of the second node N2.

[0157] In an exemplary embodiment, the fourth electrode plate 14 of the second capacitor can be rectangular in shape. The corners of the rectangle can be chamfered, grooved, or protruded. It can be located on one side of the second electrode plate 12 in the second direction Y. The orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 on the substrate. The fourth electrode plate 14 is configured as the lower electrode plate of the second capacitor (the first end of the second capacitor C2). The third electrode plate 13 and the fourth electrode plate 14 constitute the second capacitor C2 of the pixel driving circuit.

[0158] In an exemplary embodiment, the third plate 13 is also configured as the first coupling plate of the node coupling capacitor, that is, the second capacitor and the node coupling capacitor share the fourth plate 14.

[0159] In an exemplary embodiment, a groove may be provided at the corner of the fourth electrode plate 14 on the side away from the second electrode plate 12, the groove exposing a portion of the edges of the sixth edge 13-6 and the eighth edge 13-8 in the third electrode plate 13, the groove being configured to accommodate a subsequently formed seventeenth via.

[0160] In an exemplary embodiment, the orthographic projection of the fourth electrode 14 onto the substrate may include at least one edge of the third electrode 13.

[0161] In an exemplary embodiment, the orthographic projection of the fourth electrode plate 14 onto the substrate may include the fifth edge 13-5, that is, the fourth electrode plate 14 at least covers the edge of the third electrode plate 13 on the side close to the first electrode plate 11.

[0162] In an exemplary embodiment, the orthographic projection of the fourth electrode plate 14 onto the substrate may further include the seventh edge 13-7.

[0163] In an exemplary embodiment, the orthographic projection of the fourth electrode plate 14 onto the substrate may further include portions of the sixth edge 13-6 and the eighth edge 13-8. This disclosure, by setting the upper fourth electrode plate 14 to cover the edges of the lower third electrode plate 13, forms an upper-wrapped-lower structure, which effectively reduces the overlap capacitance between multiple edges (second node N2) of the third electrode plate 13 and related signal lines, and effectively reduces the parasitic capacitance of the second node N2.

[0164] In an exemplary embodiment, the second conductive layer in adjacent cell columns can be substantially mirror-symmetrical with respect to the column center line. For example, the second conductive layers in the Nth cell column and the (N+1)th cell column can be substantially mirror-symmetrical with respect to the column center line. Similarly, the second conductive layers in the (N+1)th cell column and the (N+2)th cell column can be substantially mirror-symmetrical with respect to the column center line.

[0165] (13) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a second insulating film and a semiconductor film on a substrate on which the aforementioned pattern is formed; patterning the semiconductor film using a patterning process to form a second insulating layer covering the second conductive layer; and a semiconductor layer pattern disposed on the second insulating layer, such as... Figure 9A and Figure 9B As shown, Figure 9B for Figure 9A A planar schematic diagram of the semiconductor layer.

[0166] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit in the display substrate may include a fifth electrode plate 15, a first active layer 21 of the first transistor T1 to a seventh active layer 27 of the seventh transistor T7, and the first active layer 21, the second active layer 22 and the fourth active layer 24 may be an integral structure interconnected with each other, and the third active layer 23, the fifth active layer 25, the sixth active layer 26 and the seventh active layer 27 may be an integral structure interconnected with each other.

[0167] In an exemplary embodiment, in the first direction X, the first active layer 21, the second active layer 22, and the fourth active layer 24 may be located on the same side of the third active layer 23 in the first direction X. In the second direction Y, the first active layer 21, the second active layer 22, the sixth active layer 26, and the seventh active layer 27 may be located on one side of the third active layer 23 in the second direction Y, and the fifth active layer 25 may be located on the opposite side of the third active layer 23 in the second direction Y.

[0168] In an exemplary embodiment, the second active layer 22 may be located on one side of the first active layer 21 in the second direction Y, and the fourth active layer 24 may be located on the opposite side of the first active layer 21 in the second direction Y, that is, the second active layer 22 and the fourth active layer 24 may be located on both sides of the first active layer 21 in the second direction Y.

[0169] In an exemplary embodiment, the sixth active layer 26 may be located on one side of the third active layer 23 in the second direction Y, the seventh active layer 27 may be located on one side of the sixth active layer 26 in the second direction Y, and the fifth active layer 25 may be located on the opposite side of the third active layer 23 in the second direction Y.

[0170] In an exemplary embodiment, the first active layer 21 to the sixth active layer 26 can be strip-shaped extending along the second direction Y, and the seventh active layer 27 can be L-shaped.

[0171] In an exemplary embodiment, the orthographic projection of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 12 on the substrate, and the second electrode plate 12 can also serve as the bottom gate electrode of the third transistor T3.

[0172] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 21-1 of the first active layer and the first region 22-1 of the second active layer may be interconnected, and the first region 21-1 of the first active layer may serve as the first region 22-1 of the second active layer. The second region 21-2 of the first active layer and the second region 24-2 of the fourth active layer may be interconnected, and the second region 21-2 of the first active layer may serve as the second region 24-2 of the fourth active layer. The first region 23-1 of the third active layer and the second region 25-2 of the fifth active layer may be interconnected, and the first region 23-1 of the third active layer may serve as the second region 25-2 of the fifth active layer. The second region 23-2 of the third active layer and the first region 26-1 of the sixth active layer may be interconnected, and the second region 23-2 of the third active layer may serve as the first region 26-1 of the sixth active layer. The second region 26-2 of the sixth active layer and the second region 27-2 of the seventh active layer can be interconnected, and the second region 26-2 of the sixth active layer can serve as the second region 27-2 of the seventh active layer. The second region 22-2 of the second active layer, the first region 24-1 of the fourth active layer, the first region 25-1 of the fifth active layer, and the first region 27-1 of the seventh active layer can be set independently.

[0173] In some possible embodiments, the first region 21-1 of the first active layer and the first region 22-1 of the second active layer can be set separately, that is, the first region 21-1 of the first active layer and the first region 22-1 of the second active layer are not connected, so as to realize that the first region of the first active layer and the first region of the second active layer are connected to different initial signal lines. This disclosure does not limit this.

[0174] In an exemplary embodiment, in at least one cell row, the first region 27-1 of the seventh active layer in some adjacent circuit cells can be interconnected, and the seventh active layers 27 of two circuit cells can be an integral structure interconnected, and the two circuit cells can share the same first region 27-1 of the seventh active layer. For example, the seventh active layers 27 in the Nth cell column and the seventh active layers 27 in the N+1th cell column can be an integral structure interconnected. By setting some adjacent circuit cells to share the first electrode of the seventh transistor T7, this disclosure can effectively reduce the lateral wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0175] In an exemplary embodiment, the first region 21-1 of the first active layer can serve as the first electrode of the first transistor T1, the second region 21-2 of the first active layer can serve as the second electrode of the first transistor T1, the first region 22-1 of the second active layer can serve as the first electrode of the second transistor T2, the second region 22-2 of the second active layer can serve as the second electrode of the second transistor T2, the first region 23-1 of the third active layer can serve as the first electrode of the third transistor T3, the second region 23-2 of the third active layer can serve as the second electrode of the third transistor T3, and the first region 24-1 of the fourth active layer can serve as the fourth transistor T4. The first electrode of the fourth active layer, the second region 24-2, can be used as the second electrode of the fourth transistor T4; the first region 25-1 of the fifth active layer can be used as the first electrode of the fifth transistor T5; the second region 25-2 of the fifth active layer can be used as the second electrode of the fifth transistor T5; the first region 26-1 of the sixth active layer can be used as the first electrode of the sixth transistor T6; the second region 26-2 of the sixth active layer can be used as the second electrode of the sixth transistor T6; the first region 27-1 of the seventh active layer can be used as the first electrode of the seventh transistor T7; the second region 27-2 of the seventh active layer can be used as the second electrode of the seventh transistor T7.

[0176] In an exemplary embodiment, at least one circuit unit may further include a first active connecting strip 28. The first active connecting strip 28 may be a strip shape extending along a first direction X, and may be disposed between partially adjacent circuit units. For example, the first active connecting strip 28 may be disposed between the Nth unit column and the (N+1)th unit column. A first end of the first active connecting strip 28 is connected to the first region 21-1 of the first active layer and the first region 22-1 of the second active layer in one circuit unit, and a second end of the first active connecting strip 28 is connected to the first region 21-1 of the first active layer and the first region 22-1 of the second active layer in another circuit unit. The first active connecting strip 28 is configured to simultaneously serve as the first region 21-1 of the first active layer and the first region 22-1 of the second active layer shared by both circuit units, that is, the two circuit units may share the same first region 21-1 of the first active layer and the same first region 22-1 of the second active layer.

[0177] In an exemplary embodiment, the first active connecting strip 28 and the first active layer and second active layer in the two circuit units can be an integral structure interconnected. By setting the first active connecting strip 28, this disclosure enables some adjacent circuit units to share the first electrode of the first transistor T1 and the first electrode of the second transistor T2, which can effectively reduce the lateral wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, thus facilitating the achievement of high resolution.

[0178] In an exemplary embodiment, at least one circuit unit may further include a second active connecting strip 29. The second active connecting strip 29 may be a strip shape extending along a first direction X, and may be disposed between partially adjacent circuit units. For example, the second active connecting strip 29 may be disposed between the N+1th unit column and the N+2th unit column. A first end of the second active connecting strip 29 is connected to a first region 25-1 of the fifth active layer in one circuit unit, and a second end of the second active connecting strip 29 is connected to a first region 25-1 of the fifth active layer in another circuit unit. The second active connecting strip 29 is configured to simultaneously serve as a shared first region 25-1 of the fifth active layer for both circuit units, meaning that the two circuit units may share the same first region 25-1 of the fifth active layer.

[0179] In an exemplary embodiment, the second active connecting strip 29 and the fifth active layer in the two circuit units can be an integral structure interconnected. By setting the second active connecting strip 29, this disclosure enables some adjacent circuit units to share the first electrode of the fifth transistor T5, which can effectively reduce the lateral wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, thus facilitating the achievement of high resolution.

[0180] In an exemplary embodiment, the fifth electrode plate 15 may be rectangular in shape, and the corners of the rectangle may be provided with chamfers or grooves. The orthographic projection of the fifth electrode plate 15 on the substrate and the orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlap. The fifth electrode plate 15 is configured as the second coupling electrode plate of the node coupling capacitor, and the fourth electrode plate 14 and the fifth electrode plate 15 constitute the node coupling capacitor.

[0181] In an exemplary embodiment, the fifth electrode plate 15 may be disposed on one side of the sixth active layer 26 in the first direction X or on the opposite side of the first direction X, and connected to the sixth active layer.

[0182] In an exemplary embodiment, in at least one circuit unit, the third active layer 23, the fifth active layer 25, the sixth active layer 26, the seventh active layer 27, and the fifth electrode plate 15 can be an integral structure that is interconnected.

[0183] In an exemplary embodiment, the orthographic projections of the fifth electrode 15 and the sixth active layer 26 on the substrate at least partially overlap with the orthographic projection of the electrode connecting strip 16 on the substrate. Therefore, the semiconductor layer can be disposed between the electrode connecting strip 16 and the subsequently formed related signal lines, which can effectively reduce the overlap capacitance between the electrode connecting strip 16 (second node N2) and the related signal lines, and can effectively reduce the parasitic capacitance of the second node N2.

[0184] In some possible embodiments, while ensuring process stability, the distance between the fourth electrode 14 and the fifth electrode 15 can be reduced by decreasing the thickness of the second insulating layer, thereby effectively increasing the capacitance value of the node coupling capacitor. This disclosure does not limit the scope of the invention.

[0185] In an exemplary embodiment, the semiconductor layers in adjacent cell columns can be substantially mirror-symmetric with respect to the column center line. For example, the semiconductor layers in the Nth cell column and the (N+1)th cell column can be substantially mirror-symmetric with respect to the column center line. Similarly, the semiconductor layers in the (N+1)th cell column and the (N+2)th cell column can be substantially mirror-symmetric with respect to the column center line.

[0186] In an exemplary embodiment, the semiconductor layer can be an oxide layer, i.e., the first transistor T1 to the seventh transistor T7 are oxide transistors. Oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage current. In an exemplary embodiment, the oxide can be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the semiconductor thin film can be indium gallium zinc oxide (IGZO).

[0187] (14) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a third insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a third insulating layer covering the semiconductor layer pattern; and a third conductive layer pattern disposed on the third insulating layer, such as... Figure 10A and Figure 10B As shown, Figure 10B for Figure 10A A schematic diagram of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the third gate metal (GATE3) layer.

[0188] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a fourth gate electrode 34, a fifth gate electrode 35, a sixth gate electrode 36, a seventh gate electrode 37, a gate connection strip 38, a first light-emitting signal line 41, and a second light-emitting signal line 42.

[0189] In an exemplary embodiment, the first gate electrode 31 may be block-shaped (such as rectangular), and the orthographic projection of the first gate electrode 31 on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate. The first gate electrode 31 may serve as the gate electrode of the first transistor T1.

[0190] In an exemplary embodiment, in at least one cell row, the first gate electrodes 31 in some adjacent circuit cells can be interconnected, and the first gate electrodes 31 of two circuit cells can be an integral structure interconnected. For example, the first gate electrode 31 in the Nth cell column and the first gate electrode 31 in the N+1th cell column can be an integral structure interconnected. By setting the first gate electrodes 31 in some adjacent circuit cells to an integral structure interconnected, this disclosure can effectively reduce wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0191] In an exemplary embodiment, the second gate electrode 32 may be block-shaped (such as rectangular) and may be disposed on one side of the first gate electrode 31 in the second direction Y. The orthographic projection of the second gate electrode 32 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The second gate electrode 32 may serve as the gate electrode of the second transistor T2.

[0192] In an exemplary embodiment, in at least one cell row, the second gate electrodes 32 in some adjacent circuit cells can be interconnected, and the second gate electrodes 32 of two circuit cells can be an integral structure interconnected. For example, the second gate electrodes 32 in the Nth cell column and the second gate electrodes 32 in the N+1th cell column can be an integral structure interconnected. By setting the second gate electrodes 32 in some adjacent circuit cells to an integral structure interconnected, this disclosure can effectively reduce wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0193] In an exemplary embodiment, the third gate electrode 33 may be block-shaped (e.g., rectangular), and the orthographic projection of the third gate electrode 33 on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate. The third gate electrode 33 may serve as the top gate electrode of the third transistor T3.

[0194] In an exemplary embodiment, the fourth gate electrode 34 may be block-shaped (such as rectangular) and may be disposed on the side opposite to the second direction Y of the first gate electrode 31. The orthogonal projection of the fourth gate electrode 34 on the substrate at least partially overlaps with the orthogonal projection of the fourth active layer on the substrate. The fourth gate electrode 34 may serve as the gate electrode of the fourth transistor T4.

[0195] In an exemplary embodiment, in at least one cell row, the fourth gate electrodes 34 in some adjacent circuit cells can be interconnected, and the fourth gate electrodes 34 of two circuit cells can be an integral structure interconnected. For example, the fourth gate electrode 34 in the Nth cell column and the fourth gate electrode 34 in the N+1th cell column can be an integral structure interconnected. By setting the fourth gate electrodes 34 in some adjacent circuit cells to an integral structure interconnected, this disclosure can effectively reduce wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0196] In an exemplary embodiment, the fifth gate electrode 35 may be block-shaped (such as rectangular) and may be disposed on the side opposite to the second direction Y of the third gate electrode 33. The orthogonal projection of the fifth gate electrode 35 on the substrate at least partially overlaps with the orthogonal projection of the fifth active layer on the substrate. The fifth gate electrode 35 may serve as the gate electrode of the fifth transistor T5.

[0197] In an exemplary embodiment, the sixth gate electrode 36 may be block-shaped (e.g., rectangular) and may be disposed on one side of the third gate electrode 33 in the second direction Y. The orthographic projection of the sixth gate electrode 36 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer on the substrate. The sixth gate electrode 36 may serve as the gate electrode of the sixth transistor T6.

[0198] In an exemplary embodiment, the seventh gate electrode 37 may be block-shaped (such as rectangular) and may be disposed on one side of the second gate electrode 32 in the second direction Y. The orthographic projection of the seventh gate electrode 37 on the substrate at least partially overlaps with the orthographic projection of the seventh active layer on the substrate. The seventh gate electrode 37 may serve as the gate electrode of the seventh transistor T7.

[0199] In an exemplary embodiment, the gate connection strip 38 may be a strip shape extending along the second direction Y, and may be disposed on one side of the third gate electrode 33 in the second direction Y. The first end of the gate connection strip 38 is connected to the third gate electrode 33, and the second end of the gate connection strip 38 extends in a direction away from the third gate electrode 33. The orthographic projection of the second end of the gate connection strip 38 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 14 on the substrate.

[0200] In an exemplary embodiment, in at least one circuit unit, the third gate electrode 33 and the gate connection bar 38 can be an integral structure that is interconnected.

[0201] In an exemplary embodiment, the shape of the first light-emitting signal line 41 can be a straight line or a broken line extending along the first direction X. It can be disposed on the side of the fourth gate electrode 34 away from the first gate electrode 31. The first light-emitting signal line 41 is connected to the fifth gate electrode 35 in the plurality of circuit units, thereby realizing that the first light-emitting signal line 41 can control the conduction or disconnection of the fifth transistor T5.

[0202] In an exemplary embodiment, in at least one unit row, the first light-emitting signal line 41 and the fifth gate electrode 35 in the plurality of circuit units can be an integral structure that is interconnected.

[0203] In an exemplary embodiment, the shape of the second light-emitting signal line 42 can be a straight line or a broken line extending along the first direction X. It can be disposed between the second gate electrode 32 and the seventh gate electrode 37. The second light-emitting signal line 42 is connected to the sixth gate electrode 36 in a plurality of circuit units, thereby enabling the second light-emitting signal line 42 to control the conduction or disconnection of the sixth transistor T6.

[0204] In an exemplary embodiment, in at least one unit row, the second light-emitting signal line 42 and the sixth gate electrode 36 in the plurality of circuit units can be an integral structure that is interconnected.

[0205] In an exemplary embodiment, in at least one circuit unit, the orthographic projections of the first light-emitting signal line 41 and the second light-emitting signal line 42 on the substrate do not overlap with the orthographic projections of the first electrode plate 11, the second electrode plate 12, the third electrode plate 13, the fourth electrode plate 14, and the fifth electrode plate 15 on the substrate.

[0206] In an exemplary embodiment, the third conductive layer in some adjacent cell columns may be substantially mirror-symmetrical with respect to the column center line. For example, the third conductive layers in the Nth cell column and the (N+1)th cell column may be substantially mirror-symmetrical with respect to the column center line. Similarly, the third conductive layers (excluding the first gate electrode 31 and the second gate electrode 32) in the (N+1)th cell column and the (N+2)th cell column may be substantially mirror-symmetrical with respect to the column center line.

[0207] (15) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein the fourth insulating layer has a plurality of vias, such as... Figure 11 As shown.

[0208] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17.

[0209] In an exemplary embodiment, in the circuit cells of the Nth and N+1th unit columns, the orthographic projection of the first via V1 onto the substrate lies within the range of the orthographic projection of the first active connector 28 onto the substrate. The third and fourth insulating layers within the first via V1 are etched away, exposing the surface of the first active connector 28. The first via V1 is configured to allow the subsequently formed first initial signal line to connect to the first active connector 28 through this via. Since the first active connector 28 simultaneously serves as the first region of the first active layer and the first region of the second active layer shared by the two circuit cells, the two circuit cells share the first via V1. The three circuit cells only require two first via V1s, effectively reducing the number of vias and decreasing the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0210] In an exemplary embodiment, in the circuit cell of the N+2th cell column, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the first active layer (which is also the first region of the second active layer) onto the substrate. The third and fourth insulating layers within the first via V1 are etched away, exposing the surface of the first region of the first active layer (which is also the first region of the second active layer). The first via V1 is configured to allow a subsequently formed first initial signal line to be connected to the first region of the first active layer (which is also the first region of the second active layer) through the via.

[0211] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the second region of the first active layer (which is also the second region of the fourth active layer) onto the substrate. The third and fourth insulating layers within the second via V2 are etched away, exposing the surface of the second region of the first active layer (which is also the second region of the fourth active layer). The second via V2 is configured to allow the subsequently formed sixth connection electrode to be connected to the second region of the first active layer (which is also the second region of the fourth active layer) through the via.

[0212] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the second region of the second active layer onto the substrate. The third and fourth insulating layers within the third via V3 are etched away, exposing the surface of the second region of the second active layer. The third via V3 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the second active layer through the via.

[0213] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The third and fourth insulating layers within the fourth via V4 are etched away, exposing the surface of the first region of the fourth active layer. The fourth via V4 is configured to allow a subsequently formed fourth connection electrode to be connected to the first region of the fourth active layer through the via.

[0214] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is located within the orthographic projection of the second region of the third active layer (which is also the first region of the sixth active layer) onto the substrate. The third and fourth insulating layers within the fifth via V5 are etched away, exposing the surface of the second region of the third active layer (which is also the first region of the sixth active layer). The fifth via V5 is configured to allow a subsequently formed third connection electrode to be connected to the second region of the third active layer (which is also the first region of the sixth active layer) through the via.

[0215] In an exemplary embodiment, in the circuit cell of the Nth cell column, the orthographic projection of the sixth via V6 onto the substrate is within the range of the orthographic projection of the first region of the fifth active layer onto the substrate. The third and fourth insulating layers within the sixth via V67 are etched away, exposing the surface of the first region of the fifth active layer. The sixth via V6 is configured to allow a subsequently formed first power connection line to be connected to the first region of the fifth active layer through the via.

[0216] In an exemplary embodiment, in the circuit cells of the N+1 and N+2 cell columns, the orthographic projection of the sixth via V6 onto the substrate lies within the range of the orthographic projection of the second active connector 29 onto the substrate. The third and fourth insulating layers within the sixth via V6 are etched away, exposing the surface of the second active connector 29. The sixth via V6 is configured to allow the subsequently formed first power connection line to connect to the second active connector 29 through this via. Since the second active connector 29 also serves as the first region of the fifth active layer shared by the two circuit cells, the two circuit cells share the sixth via V6. The three circuit cells only have two sixth via V6s, effectively reducing the number of vias and decreasing the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0217] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) onto the substrate. The third and fourth insulating layers within the seventh via V7 are etched away, exposing the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The seventh via V7 is configured to allow the subsequently formed fifth connection electrode to be connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via.

[0218] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection of the first region of the seventh active layer onto the substrate. The third and fourth insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the seventh active layer. The eighth via V8 is configured to allow the subsequently formed second initial signal line to connect to the first region of the seventh active layer through this via. Since the two circuit units in the Nth and N+1th unit columns share the same first region of the seventh active layer, some adjacent circuit units can share the eighth via V8. With only two eighth vias V8 provided for the three circuit units, the number of vias is effectively reduced, which can decrease the area occupied by the pixel driving circuit and is beneficial for achieving high resolution.

[0219] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is within the range of the orthographic projection of the second electrode plate 12 on the substrate. The second, third, and fourth insulating layers within the ninth via V9 are etched away, exposing the surface of the second electrode plate 12. The ninth via V9 is configured to allow the subsequently formed third connection electrode to be connected to the second electrode plate 12 through the via.

[0220] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is within the range of the orthographic projection of the fourth electrode plate 14 on the substrate. The second, third, and fourth insulating layers within the tenth via V10 are etched away, exposing the surface of the fourth electrode plate 14. The tenth via V10 is configured to allow the subsequently formed first connection electrode to be connected to the fourth electrode plate 14 through the via.

[0221] In an exemplary embodiment, the orthogonal projection of the eleventh via V11 onto the substrate lies within the range of the orthogonal projection of the first gate electrode 31 onto the substrate. The fourth insulating layer within the eleventh via V11 is etched away, exposing the surface of the first gate electrode 31. The eleventh via V11 is configured to allow the subsequently formed first scan signal line to pass through and connect to the substrate. Since the first gate electrodes 31 in two partially adjacent circuit units are interconnected as a single structure, these two partially adjacent circuit units can share the eleventh via V11. With only two eleventh vias V11 provided for the three circuit units, the number of vias is effectively reduced, which can decrease the area occupied by the pixel driving circuit and facilitates the achievement of high resolution.

[0222] In an exemplary embodiment, the orthogonal projection of the twelfth via V12 onto the substrate lies within the range of the orthogonal projection of the second gate electrode 32 onto the substrate. The fourth insulating layer within the twelfth via V12 is etched away, exposing the surface of the second gate electrode 32. The twelfth via V12 is configured to allow a subsequently formed scanning connector to connect to the second gate electrode 32 through this via. Due to the integral structure where the second gate electrodes 32 in two partially adjacent circuit units are interconnected, two partially adjacent circuit units can share the twelfth via V12. Since only two twelfth vias V12 are provided for the three circuit units, the number of vias is effectively reduced, which can reduce the area occupied by the pixel driving circuit and is beneficial for achieving high resolution.

[0223] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is within the range of the orthographic projection of the third gate electrode 33 on the substrate. The fourth insulating layer in the thirteenth via V13 is etched away, exposing the surface of the third gate electrode 33. The thirteenth via V13 is configured to allow the subsequently formed sixth connection electrode to be connected to the third gate electrode 33 through the via.

[0224] In an exemplary embodiment, the orthogonal projection of the fourteenth via V14 onto the substrate lies within the range of the orthogonal projection of the fourth gate electrode 34 onto the substrate. The fourth insulating layer within the fourteenth via V14 is etched away, exposing the surface of the fourth gate electrode 34. The fourteenth via V14 is configured to allow the subsequently formed fourth scan signal line to connect to the fourth gate electrode 34 through this via. Since the fourth gate electrodes 34 in two partially adjacent circuit units are interconnected as a single structure, the two partially adjacent circuit units can share the fourteenth via V14. With only two fourteenth vias V14 provided in the three circuit units, the number of vias is effectively reduced, which can decrease the area occupied by the pixel driving circuit and is beneficial for achieving high resolution.

[0225] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate is located within the range of the orthographic projection of the second end of the gate connector 38 onto the substrate. The fourth insulating layer within the fifteenth via V15 is etched away, exposing the surface of the gate connector 38. The fifteenth via V15 is configured to allow the subsequently formed first connection electrode to be connected to the gate connector 38 through the via.

[0226] In an exemplary embodiment, the orthogonal projection of the sixteenth via V16 onto the substrate is within the range of the orthogonal projection of the seventh gate electrode 37 onto the substrate. The fourth insulating layer within the sixteenth via V16 is etched away, exposing the surface of the seventh gate electrode 37. The sixteenth via V16 is configured to allow the subsequently formed third scan signal line to be connected to the seventh gate electrode 37 through the via.

[0227] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is within the range of the orthographic projection of the third electrode plate 13 on the substrate. The first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the seventeenth via V17 are etched away to expose the surface of the third electrode plate 13. The seventeenth via V17 is configured to allow the subsequently formed second connection electrode to be connected to the third electrode plate 13 through the via.

[0228] (16) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on a fourth insulating layer, such as... Figure 12A and Figure 12B As shown, Figure 12B for Figure 12A A schematic planar view of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0229] In an exemplary embodiment, the fourth conductive layer of each circuit unit in the display substrate includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a first power connection line 65, a second power connection line 66, a first initial signal line 71, and a second initial signal line 72.

[0230] In an exemplary embodiment, the first connecting electrode 51 can be a strip extending along the first direction X. The first end of the first connecting electrode 51 is connected to the fourth electrode plate 14 via a tenth via V10, and the second end of the first connecting electrode 51 is connected to the gate connecting strip 38 via a fifteenth via V15. Since the gate connecting strip 38 is connected to the third gate electrode 33, the first connecting electrode 51 achieves the connection between the fourth electrode plate 14 and the gate electrode of the third transistor T3. In an exemplary embodiment, the first connecting electrode 51 can serve as the first node electrode of this disclosure.

[0231] In an exemplary embodiment, the second connecting electrode 52 can be a strip extending along the first direction X. The first end of the second connecting electrode 52 is connected to the second region of the second active layer through the third via V3, and the second end of the second connecting electrode 52 is connected to the third electrode plate 13 through the seventeenth via V17. Since the first electrode plate 11 and the third electrode plate 13 are connected to each other through the electrode plate connecting strip 16, the second connecting electrode 52 realizes the connection between the second electrode of the second transistor T2, the second end of the first capacitor C1 (first electrode plate 11), and the second end of the second capacitor C2 (third electrode plate 13), forming the second node N2 of the pixel driving circuit, that is, the second connecting electrode 52, the first electrode plate 11, and the third electrode plate 13 have a second node potential. In an exemplary embodiment, the second connecting electrode 52 can serve as the second node electrode of this disclosure.

[0232] In an exemplary embodiment, the third connecting electrode 53 can be a strip extending along the first direction X. The first end of the third connecting electrode 53 is connected to the first region of the second region of the third active layer (which is also the first region of the sixth active layer) through a fifth via V5. The second end of the third connecting electrode 53 is connected to the second electrode plate 12 through a ninth via V9. The third connecting electrode 53 enables the interconnection between the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, and the first end (second electrode plate 12) of the first capacitor C1, forming the third node N3 of the pixel driving circuit. That is, the second electrode plate 12 and the third connecting electrode 53 have a third node potential. In an exemplary embodiment, the third connecting electrode 53 can serve as the third node electrode of this disclosure.

[0233] In an exemplary embodiment, since the fifth electrode plate 15 is connected to the first region of the sixth active layer (which is also the second region of the third active layer), and the second region of the third active layer is connected to the second electrode plate 12 through the third connecting electrode 53, the second electrode plate 12 and the fifth electrode plate 15 have the same third node potential.

[0234] In an exemplary embodiment, since the second electrode plate 12 also serves as the bottom gate electrode of the third transistor T3, the bottom gate electrode of the third transistor T3 has the third node potential of the pixel driving circuit.

[0235] In an exemplary embodiment, the fourth connection electrode 54 may be block-shaped (e.g., rectangular), and the fourth connection electrode 54 is connected to the first region of the fourth active layer through the fourth via V4. The fourth connection electrode 54 is configured to be connected to a subsequently formed data signal line.

[0236] In an exemplary embodiment, the fifth connection electrode 55 may be block-shaped (e.g., rectangular), and the fifth connection electrode 55 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the seventh via V7. The fifth connection electrode 55 is configured to be connected to the subsequently formed anode connection electrode.

[0237] In an exemplary embodiment, the sixth connecting electrode 56 can be a strip extending along the first direction X. The first end of the sixth connecting electrode 56 is connected to the second region of the first active layer (which is also the second region of the fourth active layer) through the second via V2, and the second end of the sixth connecting electrode 56 is connected to the third gate electrode 33 through the thirteenth via V13. Since the fourth electrode plate 14 is connected to the third gate electrode 33 through the first connecting electrode 51, and the third gate electrode 33 is connected to the second region of the first active layer (which is also the second region of the fourth active layer) through the sixth connecting electrode 56, the first connecting electrode 51 and the sixth connecting electrode 56 realize the connection between the second electrode of the first transistor T1, the gate electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first end of the second capacitor C2 (the fourth electrode plate 14), forming the first node N1 of the pixel driving circuit, that is, the first connecting electrode 51, the sixth connecting electrode 56, and the fourth electrode plate 14 have a first node potential.

[0238] In an exemplary embodiment, since the first electrode 11 has a second node potential and the second electrode 12 has a third node potential, the first electrode 11 with the second node potential and the second electrode 12 with the third node potential form the first capacitor C1 of the pixel driving circuit.

[0239] In an exemplary embodiment, since the third electrode plate 13 has a second node potential and the fourth electrode plate 14 has a first node potential, the third electrode plate 13 with the second node potential and the fourth electrode plate 14 with the first node potential form the second capacitor C2 of the pixel driving circuit.

[0240] In an exemplary embodiment, the ratio of the capacitance value of the first capacitor C1 to the capacitance value of the second capacitor C2 can be approximately 0.95 to 1.05.

[0241] In an exemplary embodiment, the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 can be substantially the same, which is beneficial to the stability of the potential of each node.

[0242] In an exemplary embodiment, since the fourth electrode plate (first coupling electrode plate) has a first node potential and the fifth electrode plate 15 (second coupling electrode plate) has a third node potential, the fourth electrode plate 14 with the first node potential and the fifth electrode plate 15 with the third node potential can form a node coupling capacitor between the first node N1 and the third node N3 in the pixel driving circuit.

[0243] In an exemplary embodiment, the shape of the first scan signal line 61 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a unit row. The orthographic projection of the first scan signal line 61 on the substrate at least partially overlaps with the orthographic projection of the first gate electrode 31 on the substrate. The first scan signal line 61 is connected to the first gate electrode 31 in each circuit unit through the eleventh via V11, thus realizing the connection between the first scan signal line 61 and the gate electrode of the first transistor T1 in each circuit unit. The first scan signal line 61 can control the conduction or disconnection of the first transistor T1.

[0244] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first scan signal line 61 on the substrate at least partially overlaps with the orthographic projections of the sixth active layer and the electrode connecting strip on the substrate, and the sixth active layer is disposed between the electrode connecting strip and the first scan signal line. Thus, the sixth active layer can effectively shield the overlapping capacitance between the first scan signal line and the second node N2, and can effectively reduce the parasitic capacitance of the second node N2.

[0245] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first scan signal line 61 on the substrate does not overlap with the orthographic projection of the first connecting electrode 51 on the substrate, and / or, the orthographic projection of the first scan signal line 61 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or, the orthographic projection of the first scan signal line 61 on the substrate does not overlap with the orthographic projection of the sixth connecting electrode 56 on the substrate, and / or, the orthographic projection of the first scan signal line 61 on the substrate does not overlap with the orthographic projection of the fourth electrode plate 14 on the substrate. Since the first connecting electrode 51, the third gate electrode 33, the sixth connecting electrode 56, and the fourth electrode plate 14 all have a first node potential, this disclosure can effectively reduce the overlap capacitance between the first node N1 and the first scan signal line 61 by setting the position of the first scan signal line 61, thereby reducing the parasitic capacitance of the first node N1.

[0246] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first scan signal line 61 on the substrate does not overlap with the orthographic projection of the second connection electrode 52 on the substrate. Since the second connection electrode 52 has a second node potential, this disclosure can effectively reduce the overlap capacitance between the second node N2 and the first scan signal line 61 by setting the position of the first scan signal line 61, thereby reducing the parasitic capacitance of the second node N2.

[0247] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first scan signal line 61 on the substrate does not overlap with the orthographic projection of the third connection electrode 53 on the substrate. Since the third connection electrode 53 has a third node potential, this disclosure can effectively reduce the overlap capacitance between the third node N3 and the first scan signal line 61 by setting the position of the first scan signal line 61, thereby reducing the parasitic capacitance of the third node N3.

[0248] In an exemplary embodiment, the second scan signal line 62 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a unit row. A scan connecting strip 62-1 can be provided on the second scan signal line 62. The shape of the scan connecting strip 62-1 can be a strip extending along the second direction Y. The first end of the scan connecting strip 62-1 is connected to the second scan signal line 62, and the second end of the scan connecting strip 62-1 extends towards the first scan signal line 61 and is connected to the second gate electrode 32 through the twelfth via V12. This achieves the connection between the second scan signal line 62 and the gate electrode of the second transistor T2 in each circuit unit. The second scan signal line 62 can control the conduction or disconnection of the second transistor T2.

[0249] In an exemplary embodiment, in at least one circuit unit, the second scan signal line 62 and the scan connecting bar 62-1 can be an integral structure that is interconnected.

[0250] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second scan signal line 62 on the substrate does not overlap with the orthographic projection of the first connecting electrode 51 on the substrate, and / or, the orthographic projection of the second scan signal line 62 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or, the orthographic projection of the second scan signal line 62 on the substrate does not overlap with the orthographic projection of the gate connecting strip 38 on the substrate, and / or, the orthographic projection of the second scan signal line 62 on the substrate does not overlap with the orthographic projection of the sixth connecting electrode 56 on the substrate, and / or, the orthographic projection of the second scan signal line 62 on the substrate does not overlap with the orthographic projection of the fourth electrode plate 14 on the substrate. Since the first connecting electrode 51, the third gate electrode 33, the gate connecting strip 38, the sixth connecting electrode 56, and the fourth electrode plate 14 have a first node potential, this disclosure can effectively reduce the overlap capacitance between the first node N1 and the second scan signal line 62 by setting the position of the second scan signal line 62, thereby reducing the parasitic capacitance of the first node N1.

[0251] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second scan signal line 62 on the substrate does not overlap with the orthographic projection of the second connecting electrode 52 on the substrate, and / or, the orthographic projection of the second scan signal line 62 on the substrate does not overlap with the orthographic projection of the first electrode 11 on the substrate, and / or, the orthographic projection of the second scan signal line 62 on the substrate does not overlap with the orthographic projection of the third electrode 13 on the substrate. Since the second connecting electrode 52, the first electrode 11, and the third electrode 13 have a second node potential, this disclosure can effectively reduce the overlap capacitance between the second node N2 and the second scan signal line 62 by setting the position of the second scan signal line 62, thereby reducing the parasitic capacitance of the second node N2.

[0252] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second scan signal line 62 on the substrate does not overlap with the orthographic projection of the third connection electrode 53 on the substrate. Since the third connection electrode 53 has a third node potential, this disclosure can effectively reduce the overlap capacitance between the third node N3 and the second scan signal line 62 by setting the position of the second scan signal line 62, thereby reducing the parasitic capacitance of the third node N3.

[0253] In an exemplary embodiment, the shape of the third scan signal line 63 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a unit row. The third scan signal line 63 is connected to the seventh gate electrode 37 in each circuit unit through the sixteenth via V16, thus realizing the connection between the third scan signal line 63 and the gate electrode of the seventh transistor T7 in each circuit unit. The third scan signal line 63 can control the conduction or disconnection of the seventh transistor T7.

[0254] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the third scan signal line 63 on the substrate does not overlap with the orthographic projection of the first connecting electrode 51 on the substrate, and / or, the orthographic projection of the third scan signal line 63 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or, the orthographic projection of the third scan signal line 63 on the substrate does not overlap with the orthographic projection of the gate connecting strip 38 on the substrate, and / or, the orthographic projection of the third scan signal line 63 on the substrate does not overlap with the orthographic projection of the sixth connecting electrode 56 on the substrate, and / or, the orthographic projection of the third scan signal line 63 on the substrate does not overlap with the orthographic projection of the fourth electrode plate 14 on the substrate. Since the first connecting electrode 51, the third gate electrode 33, the gate connecting strip 38, the sixth connecting electrode 56, and the fourth electrode plate 14 have a first node potential, this disclosure can effectively reduce the overlap capacitance between the first node N1 and the third scan signal line 63 by setting the position of the third scan signal line 63, thereby reducing the parasitic capacitance of the first node N1.

[0255] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the third scan signal line 63 on the substrate does not overlap with the orthographic projection of the second connecting electrode 52 on the substrate, and / or, the orthographic projection of the third scan signal line 63 on the substrate does not overlap with the orthographic projection of the first electrode 11 on the substrate, and / or, the orthographic projection of the third scan signal line 63 on the substrate does not overlap with the orthographic projection of the third electrode 13 on the substrate. Since the second connecting electrode 52, the first electrode 11, and the third electrode 13 have a second node potential, this disclosure can effectively reduce the overlap capacitance between the second node N2 and the third scan signal line 63 by setting the position of the third scan signal line 63, thereby reducing the parasitic capacitance of the second node N2.

[0256] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the third scan signal line 63 on the substrate does not overlap with the orthographic projection of the third connection electrode 53 on the substrate. Since the third connection electrode 53 has a third node potential, this disclosure can effectively reduce the overlap capacitance between the third node N3 and the third scan signal line 63 by setting the position of the third scan signal line 63, thereby reducing the parasitic capacitance of the third node N3.

[0257] In an exemplary embodiment, the shape of the fourth scan signal line 64 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a unit row. The fourth scan signal line 64 is connected to the fourth gate electrode 34 in each circuit unit through the fourteenth via V14, thus realizing the connection between the fourth scan signal line 64 and the gate electrode of the fourth transistor T4 in each circuit unit. The fourth scan signal line 64 can control the conduction or disconnection of the fourth transistor T4.

[0258] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the fourth scan signal line 64 on the substrate does not overlap with the orthographic projection of the first connecting electrode 51 on the substrate, and / or, the orthographic projection of the fourth scan signal line 64 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or, the orthographic projection of the fourth scan signal line 64 on the substrate does not overlap with the orthographic projection of the gate connecting strip 38 on the substrate, and / or, the orthographic projection of the fourth scan signal line 64 on the substrate does not overlap with the orthographic projection of the sixth connecting electrode 56 on the substrate, and / or, the orthographic projection of the fourth scan signal line 64 on the substrate does not overlap with the orthographic projection of the fourth electrode plate 14 on the substrate. Since the first connecting electrode 51, the third gate electrode 33, the gate connecting strip 38, the sixth connecting electrode 56, and the fourth electrode plate 14 all have a first node potential, this disclosure can effectively reduce the overlap capacitance between the first node N1 and the fourth scan signal line 64 by setting the position of the first scan signal line 61, thereby reducing the parasitic capacitance of the first node N1.

[0259] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the fourth scan signal line 64 onto the substrate does not overlap with the orthographic projection of the second connection electrode 52 onto the substrate. Since the second connection electrode 52 has a second node potential, this disclosure can effectively reduce the overlap capacitance between the second node N2 and the third scan signal line 63 by setting the position of the fourth scan signal line 64, thereby reducing the parasitic capacitance of the second node N2.

[0260] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the fourth scan signal line 64 on the substrate at least partially overlaps with the orthographic projections of the first electrode 11 and the second electrode 12 on the substrate, and the second electrode 12 is disposed between the first electrode 11 and the fourth scan signal line 64. In this way, the second electrode 12 can effectively shield the overlapping capacitance between the fourth scan signal line 64 and the second node N2, further reducing the parasitic capacitance of the second node N2.

[0261] In an exemplary embodiment, the orthographic projection of the fourth scan signal line 64 onto the substrate does not overlap with the orthographic projection of the third connection electrode 53 onto the substrate. Since the third connection electrode 53 has a third node potential, this disclosure can effectively reduce the overlap capacitance between the third node N3 and the fourth scan signal line 64 by setting the position of the fourth scan signal line 64, thereby reducing the parasitic capacitance of the third node N3.

[0262] This disclosure effectively reduces the resistance of the scan signal lines and lowers the voltage drop of the scan signal by setting the first scan signal line 61, the second scan signal line 62, the third scan signal line 63 and the fourth scan signal line 64 in the first source-drain metal (SD1) layer, thereby improving the compensation speed and display quality.

[0263] In an exemplary embodiment, the first power connection line 65 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a cell row. In the circuit cell of the Nth cell column, the first power connection line 65 is connected to the first region of the fifth active layer through the sixth via V6. In the circuit cells of the N+1 and N+2 cell columns, the first power connection line 65 is connected to the second active connection strip 29 through the sixth via V6. Since the second active connection strip 29 also serves as the first region of the fifth active layer shared by the two circuit cells, the first power connection line 65 is configured to connect to the subsequently formed first power line, thus enabling the first power line to write the first power signal into the first terminal of the fifth transistor T5 in each circuit cell.

[0264] In an exemplary embodiment, a first power connection block 65-1 may be provided on the first power connection line 65. The first power connection block 65-1 may be block-shaped (such as rectangular) and may be connected to the first power connection line 65. The first power connection block 65-1 is configured to be connected to the first power line subsequently formed.

[0265] In an exemplary embodiment, the first power connection block 65-1 can be disposed in the circuit units of the Nth unit column and the N+1th unit column, respectively.

[0266] In an exemplary embodiment, in at least one unit row, the first power connection line 65 and the first power connection block 65-1 can be an integral structure that is interconnected.

[0267] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first power connection line 65 on the substrate does not overlap with the orthographic projection of the first connection electrode 51 on the substrate, and / or, the orthographic projection of the first power connection line 65 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or, the orthographic projection of the first power connection line 65 on the substrate does not overlap with the orthographic projection of the electrode connecting strip 38 on the substrate, and / or, the orthographic projection of the first power connection line 65 on the substrate does not overlap with the orthographic projection of the sixth connection electrode 56 on the substrate, and / or, the orthographic projection of the first power connection line 65 on the substrate does not overlap with the orthographic projection of the fourth electrode plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the electrode connecting strip 38, the sixth connection electrode 56, and the fourth electrode plate 14 have a first node potential, this disclosure can effectively reduce the overlap capacitance between the first node N1 and the first power connection line 65 by setting the position of the first power connection line 65, thereby reducing the parasitic capacitance of the first node N1.

[0268] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first power connection line 65 on the substrate does not overlap with the orthographic projection of the second connection electrode 52 on the substrate, and / or, the orthographic projection of the first power connection line 65 on the substrate does not overlap with the orthographic projection of the first electrode plate 11 on the substrate, and / or, the orthographic projection of the first power connection line 65 on the substrate does not overlap with the orthographic projection of the third electrode plate 13 on the substrate. Since the second connection electrode 52, the first electrode plate 11, and the third electrode plate 13 have a second node potential, this disclosure can effectively reduce the overlap capacitance between the second node N2 and the first power connection line 65 by setting the position of the first power connection line 65, thereby reducing the parasitic capacitance of the second node N2.

[0269] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first power connection line 65 on the substrate does not overlap with the orthographic projection of the third connection electrode 53 on the substrate. Since the third connection electrode 53 has a third node potential, this disclosure can effectively reduce the overlap capacitance between the third node N3 and the first power connection line 65 by adjusting the position of the first power connection line 65, thereby reducing the parasitic capacitance of the third node N3.

[0270] In an exemplary embodiment, the second power connection line 66 may be a straight line or a broken line extending along the first direction X, and may be continuously arranged in a unit row, located between the fourth scan signal line 64 and the first power connection line 65. A second power connection block 66-1 may be provided on the second power connection line 66. The second power connection block 66-1 may be block-shaped (such as rectangular) and connected to the second power connection line 66. The second power connection block 66-1 is configured to connect to the second power line formed subsequently.

[0271] In an exemplary embodiment, the second power connection block 66-1 may be disposed between the N+1th unit column and the N+2th unit column.

[0272] In an exemplary embodiment, in at least one unit row, the second power connection line 66 and the second power connection block 66-1 can be an integral structure that is interconnected.

[0273] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second power connection line 66 on the substrate does not overlap with the orthographic projection of the first connection electrode 51 on the substrate, and / or, the orthographic projection of the second power connection line 66 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or, the orthographic projection of the second power connection line 66 on the substrate does not overlap with the orthographic projection of the electrode connecting strip 38 on the substrate, and / or, the orthographic projection of the second power connection line 66 on the substrate does not overlap with the orthographic projection of the sixth connection electrode 56 on the substrate, and / or, the orthographic projection of the second power connection line 66 on the substrate does not overlap with the orthographic projection of the fourth electrode plate 14 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the electrode connecting strip 38, the sixth connection electrode 56, and the fourth electrode plate 14 have a first node potential, this disclosure can effectively reduce the overlap capacitance between the first node N1 and the second power connection line 66 by setting the position of the second power connection line 66, thereby reducing the parasitic capacitance of the first node N1.

[0274] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second power connection line 66 on the substrate does not overlap with the orthographic projection of the second connection electrode 52 on the substrate. Since the second connection electrode 52 has a second node potential, this disclosure can effectively reduce the overlap capacitance between the second node N2 and the second power connection line 66 by adjusting the position of the second power connection line 66, thereby reducing the parasitic capacitance of the second node N2.

[0275] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second power connection line 66 on the substrate does not overlap with the orthographic projection of the third connection electrode 53 on the substrate. Since the third connection electrode 53 has a third node potential, this disclosure can effectively reduce the overlap capacitance between the third node N3 and the second power connection line 66 by adjusting the position of the second power connection line 66, thereby reducing the parasitic capacitance of the third node N3.

[0276] In an exemplary embodiment, the first initial signal line 65 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a cell row, located between the first scan signal line 61 and the second scan signal line 62. In the circuit cells of the Nth and N+1th cell columns, the first initial signal line 65 is connected to the first active connecting strip 28 through the first via V1. In the circuit cells of the N+2th cell column, the first initial signal line 65 is connected to the first region of the first active layer (which is also the first region of the second active layer) through the first via V1. Since the first active connecting strip 28 serves as both the first region of the first active layer and the first region of the second active layer shared by the two circuit cells, the first initial signal line 65 simultaneously writes the first initial signal into the first terminal of the first transistor T1 and the first terminal of the second transistor T2 in each circuit cell.

[0277] In an exemplary embodiment, a first initial connection block 71-1 may be provided on the first initial signal line 65. The first initial connection block 71-1 may be block-shaped (such as rectangular) and connected to the first initial signal line 65. The first initial connection block 71-1 is configured to connect to the subsequently formed first initial connection line.

[0278] In an exemplary embodiment, the first initial connection block 71-1 may be disposed in the circuit cell of the N+2th cell column.

[0279] In an exemplary embodiment, in at least one unit row, the first initial signal line 65 and the first initial connection block 71-1 can be an integral structure that is interconnected.

[0280] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first initial signal line 65 on the substrate does not overlap with the orthographic projection of the first connecting electrode 51 on the substrate, and / or, the orthographic projection of the first initial signal line 65 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or, the orthographic projection of the first initial signal line 65 on the substrate does not overlap with the orthographic projection of the electrode connecting strip 38 on the substrate, and / or, the orthographic projection of the first initial signal line 65 on the substrate does not overlap with the orthographic projection of the sixth connecting electrode 56 on the substrate. Since the first connecting electrode 51, the third gate electrode 33, the electrode connecting strip 38, and the sixth connecting electrode 56 all have a first node potential, this disclosure can effectively reduce the overlap capacitance between the first node N1 and the first initial signal line 65 by setting the position of the first initial signal line 65, thereby reducing the parasitic capacitance of the first node N1.

[0281] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first initial signal line 65 onto the substrate at least partially overlaps with the orthographic projections of the fourth electrode plate 14 and the fifth electrode plate 15 onto the substrate. The fifth electrode plate 15 is disposed between the fourth electrode plate 14 and the first initial signal line 65 in a direction perpendicular to the substrate. Thus, the fifth electrode plate 15 can effectively shield the overlapping capacitance between the first initial signal line 65 and the first node N1, further reducing the parasitic capacitance of the first node N1.

[0282] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first initial signal line 65 on the substrate does not overlap with the orthographic projections of the second connecting electrode 52 and the first electrode plate 11 on the substrate. Since the second connecting electrode 52 and the first electrode plate 11 have a second node potential, this disclosure can effectively reduce the overlap capacitance between the second node N2 and the second scanning signal line 62 by setting the position of the second scanning signal line 62, thereby reducing the parasitic capacitance of the second node N2.

[0283] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first initial signal line 65 onto the substrate at least partially overlaps with the orthographic projections of the third electrode 13, the fourth electrode 14, and the fifth electrode 15 onto the substrate. In a direction perpendicular to the substrate, the fourth electrode 14 and the fifth electrode 15 are disposed between the third electrode 13 and the first initial signal line 65. Thus, the fourth electrode 14 and the fifth electrode 15 can effectively shield the overlapping capacitance between the first initial signal line 65 and the second node N2, further reducing the parasitic capacitance of the second node N2.

[0284] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first initial signal line 65 onto the substrate does not overlap with the orthographic projection of the third connecting electrode 53 onto the substrate. Since the third connecting electrode 53 has a third node potential, this disclosure can effectively reduce the overlap capacitance between the third node N3 and the first initial signal line 65 by setting the position of the first initial signal line 65, thereby reducing the parasitic capacitance of the third node N3.

[0285] In some possible embodiments, the first region of the first active layer and the first region of the second active layer can be set separately, and the fourth conductive layer may also include a reset signal line. The first initial signal line is connected to the first region of the first active layer through a via, and the reset signal line is connected to the first region of the second active layer through a via. This disclosure does not limit the scope of the invention.

[0286] In an exemplary embodiment, the second initial signal line 66 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a cell row, located between the second scan signal line 62 and the third scan signal line 63. The second initial signal line 66 is connected to the first region of the seventh active layer in each circuit cell through the eighth via V8, thereby enabling the second initial signal line 66 to write the second initial signal into the first terminal of the seventh transistor T7 in each circuit cell.

[0287] In an exemplary embodiment, a second initial connection block 72-1 may be provided on the second initial signal line 66. The second initial connection block 72-1 may be block-shaped (e.g., rectangular) and connected to the second initial signal line 66. The second initial connection block 72-1 is configured to connect to the second initial connection line formed subsequently.

[0288] In an exemplary embodiment, the second initial connection block 72-1 may be disposed in the circuit unit of the Nth unit column.

[0289] In an exemplary embodiment, in at least one unit row, the second initial signal line 66 and the second initial connection block 72-1 can be an integral structure that is interconnected.

[0290] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second initial signal line 66 on the substrate does not overlap with the orthographic projection of the first connecting electrode 51 on the substrate, and / or, the orthographic projection of the second initial signal line 66 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or, the orthographic projection of the second initial signal line 66 on the substrate does not overlap with the orthographic projection of the electrode connecting strip 38 on the substrate, and / or, the orthographic projection of the second initial signal line 66 on the substrate does not overlap with the orthographic projection of the sixth connecting electrode 56 on the substrate, and / or, the orthographic projection of the second initial signal line 66 on the substrate does not overlap with the orthographic projection of the fourth electrode 14 on the substrate. Since the first connecting electrode 51, the third gate electrode 33, the electrode connecting strip 38, the sixth connecting electrode 56, and the fourth electrode 14 all have a first node potential, this disclosure can effectively reduce the overlap capacitance between the first node N1 and the second initial signal line 66 by setting the position of the second initial signal line 66, thereby reducing the parasitic capacitance of the first node N1.

[0291] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second initial signal line 66 on the substrate does not overlap with the orthographic projection of the second connecting electrode 52 on the substrate, and / or, the orthographic projection of the second initial signal line 66 on the substrate does not overlap with the orthographic projection of the first electrode 11 on the substrate, and / or, the orthographic projection of the second initial signal line 66 on the substrate does not overlap with the orthographic projection of the third electrode 13 on the substrate. Since the second connecting electrode 52, the first electrode 11, and the third electrode 13 have a second node potential, this disclosure, through the positioning of the second initial signal line 66, can effectively reduce the overlap capacitance between the second node N2 and the second initial signal line 66, thereby reducing the parasitic capacitance of the second node N2.

[0292] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second initial signal line 66 onto the substrate does not overlap with the orthographic projection of the third connecting electrode 53 onto the substrate. Since the third connecting electrode 53 has a third node potential, this disclosure can effectively reduce the overlap capacitance between the third node N3 and the second initial signal line 66 by setting the position of the second initial signal line 66, thereby reducing the parasitic capacitance of the third node N3.

[0293] In an exemplary embodiment, in at least one circuit unit, the fourth scan signal line 64, the first power connection line 65, and the second power connection line 66 may be located on the side opposite to the second direction Y of the third gate electrode 33, and the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the first initial signal line 65, and the second initial signal line 66 may be located on the side of the second direction Y of the third gate electrode 33.

[0294] In an exemplary embodiment, in at least one circuit unit, the fourth scan signal line 64 may be located on the side opposite to the second direction Y of the third gate electrode 33, the second power connection line 66 may be located on the side of the fourth scan signal line 64 away from the third gate electrode 33, and the first power connection line 65 may be located on the side of the second power connection line 66 away from the third gate electrode 33. The first scan signal line 61 may be located on the side of the third gate electrode 33 in the second direction Y, the first initial signal line 65 may be located on the side of the first scan signal line 61 away from the third gate electrode 33, the second scan signal line 62 may be located on the side of the first initial signal line 65 away from the third gate electrode 33, the second initial signal line 66 may be located on the side of the second scan signal line 62 away from the third gate electrode 33, and the third scan signal line 63 may be located on the side of the second initial signal line 66 away from the third gate electrode 33.

[0295] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first power connection line 65 on the substrate and the orthographic projection of the first light-emitting signal line 41 on the substrate at least partially overlap. The first power connection line 65 with a constant potential can effectively shield the first light-emitting signal transmitted by the first light-emitting signal line 41 from the pixel driving circuit, thereby improving the working stability of the pixel driving circuit.

[0296] In an exemplary embodiment, the fourth conductive layer in adjacent cell columns (excluding the first power connection block 65-1, the second power connection block 66-1, the first initial connection block 71-1, and the second initial connection block 72-1) can be substantially mirror-symmetrical with respect to the column center line. For example, the fourth conductive layer in the Nth cell column and the N+1th cell column can be substantially mirror-symmetrical with respect to the column center line. Similarly, the fourth conductive layer in the N+1th cell column and the N+2th cell column can be substantially mirror-symmetrical with respect to the column center line.

[0297] (17) Forming a fifth insulating layer and a first planarization layer pattern. In an exemplary embodiment, forming the fifth insulating layer and the first planarization layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, then coating a first planarization film, and patterning the fifth insulating film and the first planarization film using a patterning process to form a fifth insulating layer covering the fourth conductive layer pattern and a first planarization layer disposed on the fifth insulating layer. Multiple vias are provided on the fifth insulating layer and the first planarization layer, such as... Figure 13 As shown.

[0298] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate include at least: a twenty-first via V21 and a twenty-second via V22.

[0299] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the substrate is within the range of the orthographic projection of the fourth connection electrode 54 onto the substrate. The fifth insulating layer and the first planarization layer within the 21st via V21 are removed, exposing the surface of the fourth connection electrode 54. The 21st via V21 is configured to allow subsequently formed data signal lines to be connected to the fourth connection electrode 54 through the via.

[0300] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate is within the range of the orthographic projection of the fifth connecting electrode 55 onto the substrate. The fifth insulating layer and the first planarization layer within the 22nd via V22 are removed, exposing the surface of the fifth connecting electrode 55. The 22nd via V22 is configured to allow a subsequently formed anode connecting electrode to be connected to the fifth connecting electrode 55 through the via.

[0301] In an exemplary embodiment, the plurality of vias may further include a 23rd via V23, a 24th via V24, a 25th via V25, and a 26th via V26.

[0302] In an exemplary embodiment, the orthographic projection of the 23rd via V23 on the substrate is within the range of the orthographic projection of the first power connector 65-1 on the substrate. The fifth insulating layer and the first planarization layer within the 23rd via V23 are removed, exposing the surface of the first power connector 65-1. The 23rd via V23 is configured to allow a subsequently formed first power line to be connected to the first power connector 65-1 through the via.

[0303] In an exemplary embodiment, the twenty-third via V23 can be disposed in the circuit cells of the Nth and N+1th cell columns, respectively.

[0304] In an exemplary embodiment, the orthographic projection of the 24th via V24 on the substrate is within the range of the orthographic projection of the second power connector 66-1 on the substrate. The fifth insulating layer and the first planarization layer within the 24th via V24 are removed, exposing the surface of the second power connector 66-1. The 24th via V24 is configured to allow a subsequently formed second power line to be connected to the second power connector 66-1 through the via.

[0305] In an exemplary embodiment, the twenty-fourth via V24 may be disposed between the N+1th cell column and the N+2th cell column.

[0306] In an exemplary embodiment, the orthographic projection of the 25th via V25 on the substrate is within the range of the orthographic projection of the first initial connecting block 71-1 on the substrate. The fifth insulating layer and the first planarization layer within the 25th via V25 are removed, exposing the surface of the first initial connecting block 71-1. The 25th via V25 is configured to allow the subsequently formed first initial connecting line to be connected to the first initial connecting block 71-1 through the via.

[0307] In an exemplary embodiment, the twenty-fifth via V25 may be disposed in the circuit cell of the N+2th cell column.

[0308] In an exemplary embodiment, the orthographic projection of the 26th via V26 on the substrate is within the range of the orthographic projection of the second initial connecting block 72-1 on the substrate. The fifth insulating layer and the first planarization layer within the 26th via V26 are removed, exposing the surface of the second initial connecting block 72-1. The 26th via V26 is configured to allow the subsequently formed second initial connecting line to be connected to the second initial connecting block 72-1 through the via.

[0309] In an exemplary embodiment, the 26th via V26 may be disposed in the circuit cell of the Nth cell column.

[0310] (18) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first planarization layer, such as... Figure 14A and Figure 14B As shown, Figure 14B for Figure 14A A planar schematic diagram of the fifth conductive layer. In an exemplary embodiment, the fifth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0311] In an exemplary embodiment, the fifth conductive layer of each circuit unit in the display substrate includes at least: a data signal line 83 and an anode connection electrode 84.

[0312] In an exemplary embodiment, the data signal line 83 can be a straight line or a broken line extending along the second direction Y in its main body. The data signal line 83 is connected to the fourth connection electrode 54 through the twenty-first via V21. Since the fourth connection electrode 54 is connected to the first region of the fourth active layer through the via, the data signal line 83 can write data signals to the first electrode of the fourth transistor T4.

[0313] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the data signal line 83 on the substrate does not overlap with the orthographic projection of the first connecting electrode 51 on the substrate, and / or, the orthographic projection of the data signal line 83 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or, the orthographic projection of the data signal line 83 on the substrate does not overlap with the orthographic projection of the electrode connecting strip 38 on the substrate, and / or, the orthographic projection of the data signal line 83 on the substrate does not overlap with the orthographic projection of the sixth connecting electrode 56 on the substrate, and / or, the orthographic projection of the data signal line 83 on the substrate does not overlap with the orthographic projection of the fourth electrode 14 on the substrate. Since the first connecting electrode 51, the third gate electrode 33, the electrode connecting strip 38, the sixth connecting electrode 56, and the fourth electrode 14 have a first node potential, this disclosure can effectively reduce the overlap capacitance between the first node N1 and the data signal line 83 by setting the position of the data signal line 83, thereby reducing the parasitic capacitance of the first node N1.

[0314] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the data signal line 83 on the substrate does not overlap with the orthographic projection of the second connecting electrode 52 on the substrate, and / or, the orthographic projection of the data signal line 83 on the substrate does not overlap with the orthographic projection of the first electrode 11 on the substrate, and / or, the orthographic projection of the data signal line 83 on the substrate does not overlap with the orthographic projection of the third electrode 13 on the substrate. Since the second connecting electrode 52, the first electrode 11, and the third electrode 13 have a second node potential, this disclosure, through the positioning of the data signal line 83, can effectively reduce the overlap capacitance between the second node N2 and the data signal line 83, thereby reducing the parasitic capacitance of the second node N2.

[0315] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the data signal line 83 on the substrate does not overlap with the orthographic projection of the third connection electrode 53 on the substrate. Since the third connection electrode 53 has a third node potential, this disclosure can effectively reduce the overlap capacitance between the third node N3 and the data signal line 83 by setting the position of the data signal line 83, thereby reducing the parasitic capacitance of the third node N3.

[0316] In an exemplary embodiment, the data signal line 83 does not overlap with the multiple connection electrodes, which can also avoid the impact of data voltage jumps on the driving transistor and minimize the crosstalk effect.

[0317] In an exemplary embodiment, the data signal line 83 in the Nth column and the data signal line 83 in the N+1th column can be substantially mirror-symmetrical with respect to the column center line, and the data signal line 83 in the N+1th column and the data signal line 83 in the N+2th column can be substantially mirror-symmetrical with respect to the column center line.

[0318] In an exemplary embodiment, the anode connection electrode 84 can be a strip shape extending along the second direction Y. The anode connection electrode 84 is connected to the fifth connection electrode 55 through the twenty-second via V22, and the anode connection electrode 84 is configured to be connected to the subsequently formed anode. Since the fifth connection electrode 55 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via, the pixel driving circuit can output driving current to the light-emitting device.

[0319] In an exemplary embodiment, the fifth conductive layer may further include a first power line 81, a second power line 82, a first initial connection line 73, and a second initial connection line 74.

[0320] In an exemplary embodiment, the first power line 81 can be shaped as a broken line extending along the second direction Y of the main body. The first power line 81 is connected to the first power connection block 65-1 through the twenty-third via V23. Since the first power connection block 65-1 and the first power connection line 65 achieve mutual connection between the first power connection line 65 extending along the first direction X of the main body and the first power line 81 extending along the second direction Y of the main body, the first power connection line 65 and the first power line 81 form a mesh-like interconnected structure on the display substrate for transmitting the first power signal. This not only effectively reduces the resistance of the first power line and decreases the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0321] In an exemplary embodiment, the first power line 81 can be respectively disposed in the circuit cells of the Nth unit column and the N+1th unit column, and the first power line 81 in the Nth unit column and the first power line 81 in the N+1th unit column can be substantially mirror-symmetrical with respect to the column center line.

[0322] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first power line 81 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or, the orthographic projection of the first power line 81 on the substrate does not overlap with the orthographic projection of the electrode connecting strip 38 on the substrate, and / or, the orthographic projection of the first power line 81 on the substrate does not overlap with the orthographic projection of the sixth connecting electrode 56 on the substrate, and / or, the orthographic projection of the first power line 81 on the substrate does not overlap with the orthographic projection of the fourth electrode 14 on the substrate. Since the third gate electrode 33, the electrode connecting strip 38, the sixth connecting electrode 56, and the fourth electrode 14 have a first node potential, this disclosure can effectively reduce the overlap capacitance between the first node N1 and the first power line 81 by setting the position of the first power line 81 and arranging it in a zigzag pattern, thereby reducing the parasitic capacitance of the first node N1.

[0323] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first power line 81 on the substrate does not overlap with the orthographic projection of the first electrode 11 on the substrate, and / or, the orthographic projection of the first power line 81 on the substrate does not overlap with the orthographic projection of the third electrode 13 on the substrate. Since the first electrode 11 and the third electrode 13 have a second node potential, this disclosure can effectively reduce the overlap capacitance between the second node N2 and the first power line 81 by setting the position of the first power line 81 and setting it in a zigzag pattern, thereby reducing the parasitic capacitance of the second node N2.

[0324] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first power line 81 on the substrate does not overlap with the orthographic projection of the third connection electrode 53 on the substrate. Since the third connection electrode 53 has a third node potential, this disclosure can effectively reduce the overlap capacitance between the third node N3 and the first power line 81 by setting the position of the first power line 81, thereby reducing the parasitic capacitance of the third node N3.

[0325] In an exemplary embodiment, the shape of the second power line 82 can be a straight line or a broken line extending along the second direction Y of the main body. The second power line 82 is connected to the second power connection block 66-1 through the twenty-fourth via V24. Since the second power connection block 66-1 is connected to the second power connection line 66, the interconnection of the second power connection line 66 extending along the first direction X of the main body and the second power line 82 extending along the second direction Y of the main body is realized. The second power connection line 66 and the second power line 82 form a mesh-like interconnected structure on the display substrate for transmitting the second power signal. This not only effectively reduces the resistance of the second power line and the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, thereby improving display uniformity and display quality. In addition, by setting the second power line in the display area, the second power line is located in the pixel (VSS in Pixel, or SIP) structure, which can significantly reduce the width of the bezel power leads, greatly reduce the width of the left and right bezels, increase the screen ratio, and facilitate the realization of full-screen display.

[0326] In an exemplary embodiment, the second power line 82 can be respectively disposed in the circuit units of the N+1 unit column and the N+2 unit column. The second power line 82 in the N+1 unit column and the second power line 82 in the N+2 unit column can be symmetrically disposed with respect to the column center line, and the second power line 82 in the two unit columns can be an integral structure that is interconnected.

[0327] In an exemplary embodiment, the second power line 82 can be a variable width structure, and the width of the second power line is the dimension of the first direction X.

[0328] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second power line 82 on the substrate does not overlap with the orthographic projection of the first connecting electrode 51 on the substrate, and / or, the orthographic projection of the second power line 82 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or, the orthographic projection of the second power line 82 on the substrate does not overlap with the orthographic projection of the electrode connecting strip 38 on the substrate, and / or, the orthographic projection of the second power line 82 on the substrate does not overlap with the orthographic projection of the sixth connecting electrode 56 on the substrate. Since the first connecting electrode 51, the third gate electrode 33, the electrode connecting strip 38, and the sixth connecting electrode 56 all have a first node potential, this disclosure can effectively reduce the overlap capacitance between the first node N1 and the second power line 82 by varying the width of the second power line, thereby reducing the parasitic capacitance of the first node N1.

[0329] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second power line 82 on the substrate at least partially overlaps with the orthographic projections of the fourth electrode plate 14 and the fifth electrode plate 15 on the substrate. The fifth electrode plate 15 is disposed between the fourth electrode plate 14 and the second power line 82 in a direction perpendicular to the substrate. Thus, the fifth electrode plate 15 can effectively shield the overlapping capacitance between the second power line 82 and the first node N1, further reducing the parasitic capacitance of the first node N1.

[0330] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second power line 82 on the substrate does not overlap with the orthographic projection of the second connection electrode 52 on the substrate. Since the second connection electrode 52 has a second node potential, the overlap capacitance between the second node N2 and the second power line 82 can be effectively reduced by varying the width of the second power line, thereby reducing the parasitic capacitance of the second node N2.

[0331] In an exemplary embodiment, the shape of the first initial connection line 73 can be a zigzag line extending along the second direction Y of the main body. The first initial connection line 73 is connected to the first initial connection block 71-1 through the twenty-fifth via V25. Since the first initial connection block 71-1 is connected to the first initial signal line 65, the first initial signal line 65 extending along the first direction X of the main body and the first initial connection line 73 extending along the second direction Y of the main body are interconnected. The first initial signal line 65 and the first initial connection line 73 form a mesh-like interconnected structure on the display substrate for transmitting the first initial signal. This not only effectively reduces the resistance of the first initial connection line and reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0332] In an exemplary embodiment, the first initial connection line 73 may be provided in the circuit cell of the N+2th cell column.

[0333] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first initial connection line 73 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or, the orthographic projection of the first initial connection line 73 on the substrate does not overlap with the orthographic projection of the electrode connecting strip 38 on the substrate, and / or, the orthographic projection of the first initial connection line 73 on the substrate does not overlap with the orthographic projection of the sixth connecting electrode 56 on the substrate, and / or, the orthographic projection of the first initial connection line 73 on the substrate does not overlap with the orthographic projection of the fourth electrode 14 on the substrate. Since the third gate electrode 33, the electrode connecting strip 38, the sixth connecting electrode 56, and the fourth electrode 14 have a first node potential, this disclosure can effectively reduce the overlap capacitance between the first node N1 and the first initial connection line 73 by setting the position of the first initial connection line 73 and setting it in a zigzag shape, thereby reducing the parasitic capacitance of the first node N1.

[0334] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first initial connection line 73 on the substrate does not overlap with the orthographic projection of the first electrode plate 11 on the substrate, and / or, the orthographic projection of the first initial connection line 73 on the substrate does not overlap with the orthographic projection of the third electrode plate 13 on the substrate. Since the first electrode plate 11 and the third electrode plate 13 have a second node potential, this disclosure can effectively reduce the overlap capacitance between the second node N2 and the first initial connection line 73 by setting the position of the first initial connection line 73 and setting it in a zigzag shape, thereby reducing the parasitic capacitance of the second node N2.

[0335] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first initial connection line 73 on the substrate does not overlap with the orthographic projection of the third connection electrode 53 on the substrate. Since the third connection electrode 53 has a third node potential, this disclosure can effectively reduce the overlap capacitance between the third node N3 and the first initial connection line 73 by setting the position of the first initial connection line 73, thereby reducing the parasitic capacitance of the third node N3.

[0336] In an exemplary embodiment, the shape of the second initial connection line 74 can be a straight line or a broken line extending along the second direction Y of the main body. The second initial connection line 74 is connected to the second initial connection block 72-1 through the second sixteenth via V26. Since the second initial connection block 72-1 is connected to the second initial signal line 66, the interconnection between the second initial signal line 66 extending along the first direction X of the main body and the second initial connection line 74 extending along the second direction Y of the main body is realized. The second initial signal line 66 and the second initial connection line 74 form a mesh-like interconnected structure on the display substrate for transmitting the second initial signal. This not only effectively reduces the resistance of the second initial connection line and reduces the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal in the display substrate, effectively improving display uniformity, display quality, and display performance.

[0337] In an exemplary embodiment, the second initial connection line 74 may be disposed in the circuit cell of the Nth cell column, and the position and shape of the second initial connection line 74 in the Nth cell column may be substantially the same as the position and shape of the second power line 82 in the N+2th cell column.

[0338] In an exemplary embodiment, the second initial connecting line 74 can be a variable width structure, and the width of the second initial connecting line is the dimension of the first direction X.

[0339] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second initial connection line 74 on the substrate does not overlap with the orthographic projection of the first connection electrode 51 on the substrate, and / or, the orthographic projection of the second initial connection line 74 on the substrate does not overlap with the orthographic projection of the third gate electrode 33 on the substrate, and / or, the orthographic projection of the second initial connection line 74 on the substrate does not overlap with the orthographic projection of the electrode connecting strip 38 on the substrate, and / or, the orthographic projection of the second initial connection line 74 on the substrate does not overlap with the orthographic projection of the sixth connection electrode 56 on the substrate. Since the first connection electrode 51, the third gate electrode 33, the electrode connecting strip 38, and the sixth connection electrode 56 all have a first node potential, this disclosure can effectively reduce the overlap capacitance between the first node N1 and the second initial connection line 74 by varying the width of the second power line, thereby reducing the parasitic capacitance of the first node N1.

[0340] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second initial connection line 74 onto the substrate at least partially overlaps with the orthographic projections of the fourth electrode plate 14 and the fifth electrode plate 15 onto the substrate. In a direction perpendicular to the substrate, the fifth electrode plate 15 is disposed between the fourth electrode plate 14 and the second initial connection line 74. Thus, the fifth electrode plate 15 can effectively shield the overlapping capacitance between the second initial connection line 74 and the first node N1, further reducing the parasitic capacitance of the first node N1.

[0341] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second initial connection line 74 on the substrate does not overlap with the orthographic projection of the second connection electrode 52 on the substrate. Since the second connection electrode 52 has a second node potential, the overlap capacitance between the second node N2 and the second initial connection line 74 can be effectively reduced by varying the width of the second power line, thereby reducing the parasitic capacitance of the second node N2.

[0342] In an exemplary embodiment, the average width of the second power line 82 can be greater than the average width of the first power line 81, and the width can be the dimension in the first direction X. By setting a wider second power line 82, this disclosure not only effectively reduces the resistance of the second power line 82 and reduces the voltage drop of transmitting the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0343] In an exemplary embodiment, the average width of the first initial connection line 73 may be substantially the same as the average width of the first power line 81, and the average width of the second initial connection line 74 may be substantially the same as the average width of the second power line 82.

[0344] In an exemplary embodiment, a first power connection line 65 may be provided in each cell row, and a first power line 81 may be provided in a portion of cell columns (such as the Nth and N+1th cell columns). A second power connection line 66 may be provided in each cell row, and a second power line 82 may be provided in a portion of cell columns (such as the N+1th and N+2th cell columns). A first initial signal line 65 may be provided in each cell row, and a first initial connection line 73 may be provided in a portion of cell columns (such as the N+2th cell column). A second initial signal line 66 may be provided in each cell row, and a second initial connection line 74 may be provided in a portion of cell columns (such as the Nth cell column).

[0345] Subsequent fabrication processes may include forming a second planarization layer having an anode via exposed on the surface of the anode connection electrode 84, the anode via being configured to allow the subsequent formation of an anode to be connected to the anode connection electrode through the via.

[0346] Thus, the driving structure layer of this embodiment is fabricated on the substrate. In a plane parallel to the display substrate, the driving structure layer may include multiple circuit units. Each circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a first light emission signal line, a second light emission signal line, a first initial signal line, a second initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit.

[0347] In a plane perpendicular to the display substrate, the driving structure layer may include a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a semiconductor layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, a first planarization layer, a fifth conductive layer, and a second planarization layer, sequentially disposed on the substrate. The first conductive layer may include at least the first electrode of a first capacitor and the third electrode of a second capacitor; the second conductive layer may include at least the second electrode of a first capacitor and the fourth electrode of a second capacitor; the semiconductor layer may include at least the fifth electrode and the active layer of the first transistor T1 to the seventh transistor T7; the third conductive layer may include at least the first light-emitting signal line, the second light-emitting signal line, and the gate electrodes of multiple transistors; the fourth conductive layer may include at least the first scan signal line, the second scan signal line, the third scan signal line, the fourth scan signal line, the first power connection line, the second power connection line, the first initial signal line, and the second initial signal line; and the fifth conductive layer may include at least the first power line, the second power line, the data signal line, the first initial connection line, and the second initial connection line.

[0348] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz. The flexible substrate can be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass substrate. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0349] In an exemplary embodiment, the first, second, third, fourth, and fifth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first, second, third, fourth, and fifth conductive layers can be made of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or can be made of alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The first and second planarization layers can be made of organic materials, such as resin or polyimide.

[0350] In an exemplary embodiment, after the driving structure layer is fabricated, a light-emitting structure layer can be fabricated on the driving structure layer, and an encapsulation structure layer can be fabricated on the light-emitting structure layer, which will not be described in detail here.

[0351] With the development of display technology, consumers have increasingly higher requirements for the display effect and quality of display products. Display substrates using oxide transistors have attracted widespread attention due to the low off-state current of oxide transistors, which reduces leakage current, performs well in the low-frequency range, and have relatively simple manufacturing processes and lower costs. However, a display substrate using all-oxide transistors exhibits defects such as brightness changes caused by temperature rise. Research has found that as the temperature gradually increases, the voltage of the light-emitting device decreases, causing a jump in the third node N3, which in turn drives a jump in the first node N1. However, the potential change ΔV of the third node N3... N3 The potential change ΔV greater than that of the first node N1 N1， This causes the gate-source voltage Vgs (=V) of the third transistor T3 (driving transistor) to increase. N1 -V N3 The change in the pixel driving circuit's output current leads to a change in the light emission brightness.

[0352] An exemplary embodiment of this disclosure provides a display substrate in which a top-and-bottom structure is formed by providing a second and a fourth electrode plate located on the upper layer to cover the edges of a first and a third electrode plate located on the lower layer, respectively. This structure can effectively reduce the parasitic capacitance of the second node, effectively improve the jump response of the potential of the first and third nodes, effectively reduce the change in the gate-source voltage Vgs of the third transistor T3, effectively reduce the change in the output current of the pixel driving circuit, effectively reduce the change in the luminous brightness, and improve the display quality and display performance.

[0353] This disclosure achieves the connection between the first and third plates by setting a plate connecting strip with a smaller width. While ensuring the large capacitance values ​​of the first and second capacitors, it can further reduce the parasitic capacitance of the second node, further improve the jump follow-up of the potential of the first and third nodes, and further reduce the change in the gate-source voltage Vgs of the third transistor T3.

[0354] This disclosure improves the jump response of the potentials of the first and third nodes by setting a node coupling capacitor between the first and third nodes. When the potential of the third node changes, the change can be transmitted to the first node through the node coupling capacitor, so that the potential of the first node can change by the same amount. This effectively improves the jump response of the potentials of the first and third nodes, effectively reduces the change of the gate-source voltage Vgs of the third transistor T3, effectively reduces the change of the output current of the pixel driving circuit, effectively reduces the change of the luminous brightness, and improves the display quality.

[0355] This disclosure effectively reduces the parasitic capacitance of the first, second, and third nodes by setting multiple signal lines to avoid the first, second, and third nodes as much as possible. This can further reduce the change in the gate-source voltage Vgs of the third transistor T3, further reduce the change in the output current of the pixel driving circuit, and further reduce the change in the luminous brightness.

[0356] This disclosure provides a more compact arrangement of the pixel driving circuit while meeting design requirements. This effectively improves the layout space utilization, results in a more reasonable structural arrangement, and simplifies the signal line connection structure without complex overlap. This can effectively improve product yield and reduce production costs. By setting a first electrode and a third electrode in a first conductive layer, a second electrode and a fourth electrode in a second conductive layer, and a fifth electrode in a semiconductor layer, the first and second electrodes form a first capacitor, the third and fourth electrodes form a second capacitor, and the fourth and fifth electrodes form a node coupling capacitor.

[0357] This disclosure improves the uniformity and symmetry of the pixel driving circuit by setting the pixel driving circuits of adjacent unit columns in a mirrored manner. This not only enables the design of uniform process and coupling capacitors, but also enables the design of uniform current distribution, effectively improving display stability and uniformity, and effectively enhancing display effect and display quality.

[0358] This disclosure sets up some adjacent cell columns to share the first electrode of the first transistor T1, the first electrode of the fifth transistor T5, and the first electrode of the seventh transistor T7, respectively. The first gate electrode, the second gate electrode, and the fourth gate electrode of some adjacent cell columns are interconnected as an integrated structure. On the one hand, this can effectively reduce the wiring space, the number of vias, and the area occupied by the pixel driving circuit, which is conducive to achieving high resolution. On the other hand, it can effectively increase the size of the capacitor plate and the capacitance value of the capacitor, thereby maximizing the stability of the pixel driving circuit.

[0359] This embodiment of the present disclosure provides a first power connection line and a first power line, which form a mesh-like interconnected structure on the display substrate to transmit the first power signal. This not only effectively reduces the resistance of the first power line and the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, thereby improving display uniformity and display quality.

[0360] This embodiment of the disclosure, by setting a second power connection line and a second power line, and forming a mesh-like interconnected structure on the display substrate to transmit the second power signal, can not only effectively reduce the resistance of the second power line and reduce the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal in the display substrate, thereby improving display uniformity, display quality, and display performance. Moreover, it realizes a SIP structure, which can significantly reduce the width of the bezel power leads, greatly reduce the width of the left and right bezels, increase the screen ratio, and facilitate the realization of full-screen display.

[0361] This embodiment of the present disclosure, by setting a first initial connection line and a second initial connection line, forms a mesh-like interconnected structure on the display substrate to transmit a first initial signal, and the second initial signal line and the second initial connection line form a mesh-like interconnected structure on the display substrate to transmit a second initial signal. This not only effectively reduces the resistance of the initial signal line and the voltage drop of the initial signal, but also effectively improves the uniformity of the initial signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0362] This embodiment of the disclosure avoids signal crosstalk caused by data voltage jumps in the data signal lines by setting the data signal lines to not overlap with multiple connection electrodes, thus avoiding the impact of data voltage jumps on transistors, improving the working stability of the pixel driving circuit, and enhancing the display effect.

[0363] This embodiment of the invention effectively reduces the resistance of the scan signal lines and lowers the voltage drop of the scan signal by setting multiple scan signal lines in the first source-drain metal layer, thereby improving the compensation speed and display quality.

[0364] The preparation process of this disclosure is well compatible with existing preparation processes. The process is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0365] In some possible implementations, the electrode connecting strip connecting the first electrode plate and the third electrode plate can be disposed in other conductive layers. For example, the electrode connecting strip can be disposed in a fourth conductive layer, with one end of the electrode connecting strip connected to the first electrode plate through a via, and the other end of the electrode connecting strip connected to the third electrode plate through a via. This disclosure does not limit the scope of the invention.

[0366] In some possible implementations, the second coupling plate of the node coupling capacitor can be disposed in other conductive layers. For example, the second coupling plate can be disposed in a third conductive layer, with the first coupling plate (fourth plate) in the second conductive layer and the second coupling plate in the third conductive layer forming a node coupling capacitor. Alternatively, the second coupling plate can be disposed in a fourth conductive layer, with the first coupling plate (fourth plate) in the second conductive layer and the second coupling plate in the fourth conductive layer forming a node coupling capacitor. Yet another example is that the second coupling plate can be disposed in both a semiconductor layer and a third conductive layer, with the first coupling plate (fourth plate) in the second conductive layer, the second coupling plate in the semiconductor layer, and the third coupling plate in the third conductive layer forming a sandwich-structured node coupling capacitor. This disclosure does not limit the scope of the invention.

[0367] The structure and its preparation process described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be changed or added or reduced according to actual needs, and this disclosure does not limit them.

[0368] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0369] This disclosure also provides a method for fabricating a display substrate to prepare the display substrate provided in the above embodiments. In an exemplary embodiment, the display substrate includes a plurality of circuit units, and the fabrication method includes:

[0370] A pixel driving circuit is formed in at least one circuit unit. The pixel driving circuit includes at least a first capacitor, a second capacitor, and a third transistor as a driving transistor. The first capacitor includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The second capacitor includes at least a third electrode plate and a fourth electrode plate stacked together. The orthographic projection of the fourth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the third electrode plate on the display substrate plane. The first electrode plate is connected to the third electrode plate, the second electrode plate is connected to the second electrode of the third transistor, and the fourth electrode plate is connected to the gate electrode of the third transistor. Both the first electrode plate and the third electrode plate include multiple edges. The orthographic projection of the second electrode plate on the display substrate plane includes at least one edge of the first electrode plate, and the orthographic projection of the fourth electrode plate on the display substrate plane includes at least one edge of the third electrode plate.

[0371] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0372] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate, characterized in that, The device includes multiple circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes at least a first capacitor, a second capacitor, and a third transistor as a driving transistor. The first capacitor includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The second capacitor includes at least a third electrode plate and a fourth electrode plate stacked together. The orthographic projection of the fourth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the third electrode plate on the display substrate plane. The first electrode plate is connected to the third electrode plate, the second electrode plate is connected to the second electrode of the third transistor, and the fourth electrode plate is connected to the gate electrode of the third transistor; both the first electrode plate and the third electrode plate include multiple edges, the orthographic projection of the second electrode plate on the display substrate plane includes at least one edge of the first electrode plate, and the orthographic projection of the fourth electrode plate on the display substrate plane includes at least one edge of the third electrode plate.

2. The display substrate according to claim 1, characterized in that, The third electrode plate is disposed on one side of the first electrode plate in the second direction and is connected to the first electrode plate by an electrode plate connecting strip. In the first direction, the width of the electrode plate connecting strip is smaller than the width of the first electrode plate and the width of the third electrode plate is smaller than the width of the first electrode plate. The first direction and the second direction intersect.

3. The display substrate according to claim 2, characterized in that, The ratio of the width of the electrode connecting strip to the width of the first electrode plate is 0.1 to 0.2, and the ratio of the width of the electrode connecting strip to the width of the third electrode plate is 0.1 to 0.

2.

4. The display substrate according to claim 2, characterized in that, In the first direction, the edges of the first electrode plate, the third electrode plate, and the electrode plate connecting strip on the same side are flush.

5. The display substrate according to claim 2, characterized in that, The first electrode plate has at least a first edge on the side closer to the third electrode plate in the second direction, a second edge on the side farther from the third electrode plate in the second direction, a third edge on the side closer to the electrode plate connecting strip in the first direction, and a fourth edge on the side farther from the electrode plate connecting strip in the first direction. The orthographic projection of the second electrode plate onto the display substrate plane includes at least the first edge.

6. The display substrate according to claim 5, characterized in that, The orthographic projection of the second electrode plate onto the display substrate plane also includes the second edge, the third edge, and the fourth edge.

7. The display substrate according to claim 2, characterized in that, The third electrode plate has at least a fifth edge on the side closer to the first electrode plate in the second direction, a sixth edge on the side farther from the first electrode plate in the second direction, a seventh edge on the side closer to the electrode plate connecting strip in the first direction, and an eighth edge on the side farther from the electrode plate connecting strip in the first direction. The orthographic projection of the fourth electrode plate onto the display substrate plane includes at least the fifth edge.

8. The display substrate according to claim 7, characterized in that, The orthographic projection of the fourth electrode plate onto the display substrate plane also includes the seventh edge.

9. The display substrate according to claim 2, characterized in that, In a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer disposed on a substrate, a second conductive layer disposed on the side of the first conductive layer away from the substrate, a semiconductor layer disposed on the side of the second conductive layer away from the substrate, a third conductive layer disposed on the side of the semiconductor layer away from the substrate, and a fourth conductive layer disposed on the side of the third conductive layer away from the substrate; the electrode connecting strip is disposed in the first conductive layer, and the orthographic projection of the semiconductor layer on the plane of the display substrate at least partially overlaps with the orthographic projection of the electrode connecting strip on the plane of the display substrate, or the electrode connecting strip is disposed in the fourth conductive layer.

10. The display substrate according to any one of claims 1 to 9, characterized in that, At least one circuit unit further includes a first connection electrode having a first node potential, a second connection electrode having a second node potential, and a third connection electrode having a third node potential. The fourth electrode plate is connected to the gate electrode of the third transistor through the first node electrode, the third electrode plate is connected to the second connection electrode, and the second electrode plate is connected to the second electrode of the third transistor through the third node electrode.

11. The display substrate according to claim 10, characterized in that, At least one circuit unit further includes a gate connection strip connected to the gate electrode of the third transistor, a first end of the first connection electrode being connected to the fourth electrode plate via a via, and a second end of the first connection electrode being connected to the gate connection strip via a via.

12. The display substrate according to claim 10, characterized in that, The pixel driving circuit further includes a second transistor as a second reset transistor. The second transistor includes at least a second active layer. The first end of the second connecting electrode is connected to the second region of the second active layer through a via. The second end of the second connecting electrode is connected to the third electrode plate through a via.

13. The display substrate according to claim 10, characterized in that, The third transistor includes at least a third active layer, the first end of the third node electrode is connected to the second region of the third active layer through a via, and the second end of the third connection electrode is connected to the second electrode plate through a via.

14. The display substrate according to claim 10, characterized in that, In a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer disposed on a substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, a third conductive layer disposed on a side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on a side of the third conductive layer away from the substrate. The first electrode and the third electrode are disposed in the first conductive layer, the second electrode and the fourth electrode are disposed in the second conductive layer, the gate electrode of the third transistor is disposed in the third conductive layer, and the first connection electrode, the second connection electrode and the third connection electrode are disposed in the fourth conductive layer.

15. The display substrate according to any one of claims 1 to 9, characterized in that, The pixel driving circuit further includes a node coupling capacitor, which includes at least a first coupling plate and a second coupling plate stacked together. The first coupling plate is connected to the gate electrode of the third transistor, and the second coupling plate is connected to the second electrode of the third transistor.

16. The display substrate according to claim 15, characterized in that, In a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer disposed on a substrate, a second conductive layer disposed on the side of the first conductive layer away from the substrate, and a semiconductor layer disposed on the side of the second conductive layer away from the substrate. The fourth electrode plate serves as the first coupling electrode plate and is disposed in the second conductive layer, and the second coupling electrode plate is disposed in the semiconductor layer.

17. The display substrate according to claim 16, characterized in that, The third transistor includes at least a third active layer disposed in the semiconductor layer and connected to the second coupling plate.

18. The display substrate according to claim 15, characterized in that, In a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer disposed on a substrate, a second conductive layer disposed on the side of the first conductive layer away from the substrate, a semiconductor layer disposed on the side of the second conductive layer away from the substrate, a third conductive layer disposed on the side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on the side of the third conductive layer away from the substrate. The fourth electrode plate serves as the first coupling electrode plate and is disposed in the second conductive layer. The second coupling electrode plate is disposed in the third conductive layer, or the second coupling electrode plate is disposed in the fourth conductive layer.

19. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 18.

20. A method for preparing a display substrate, characterized in that, The display substrate includes multiple circuit units, and the fabrication method includes: A pixel driving circuit is formed in at least one circuit unit. The pixel driving circuit includes at least a first capacitor, a second capacitor, and a third transistor as a driving transistor. The first capacitor includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The second capacitor includes at least a third electrode plate and a fourth electrode plate stacked together. The orthographic projection of the fourth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the third electrode plate on the display substrate plane. The first electrode plate is connected to the third electrode plate, the second electrode plate is connected to the second electrode of the third transistor, and the fourth electrode plate is connected to the gate electrode of the third transistor. Both the first electrode plate and the third electrode plate include multiple edges. The orthographic projection of the second electrode plate on the display substrate plane includes at least one edge of the first electrode plate, and the orthographic projection of the fourth electrode plate on the display substrate plane includes at least one edge of the third electrode plate.

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