Display device, method of manufacturing display device, and electronic device

Abstract

The present disclosure relates to a display device, a method of manufacturing a display device, and an electronic device. The display device includes a substrate; a first driving voltage supply line in a non-display area; a second driving voltage supply line between a display area and the first driving voltage supply line and spaced apart from the first driving voltage supply line; a bridge electrode electrically connecting the first driving voltage supply line and the second driving voltage supply line; an organic insulating layer on the bridge electrode and including a first portion adjacent to the first driving voltage supply line and a second portion adjacent to the second driving voltage supply line; and an emission layer in the display area and extending to the non-display area such that one end portion of the emission layer in the non-display area overlaps the bridge electrode. An average thickness of the first portion of the organic insulating layer is less than an average thickness of the second portion of the organic insulating layer.

Description

Technical Field

[0001] The embodiments relate to a display device, a method of manufacturing a display device, and an electronic device. More specifically, the embodiments relate to a display device including a demultiplexer circuit, a method of manufacturing a display device, and an electronic device including a display device. Background Technology

[0002] With the development of information technology, the importance of display devices, which provide a connection medium between users and information, is becoming increasingly prominent. For example, the use of display devices such as liquid crystal displays (LCDs), organic light-emitting diode displays (OLEDs), or plasma display panels (PDPs) is increasing.

[0003] The display device includes a display panel for displaying images and a driver for controlling the images displayed on the display panel. The display panel includes data lines, scan lines, and pixels. The driver includes a data driver for providing data signals to the data lines, a scan driver for providing scan signals to the scan lines, and a drive controller for controlling the data driver and the scan driver. The display device may include a time-division demultiplexer for performing time-division demultiplexing on the data signals provided from the data driver. Summary of the Invention

[0004] The embodiments provide a display device with improved reliability.

[0005] The embodiments also provide a method for manufacturing a display device with improved reliability.

[0006] The embodiments also provide electronic devices with improved reliability.

[0007] Additional features of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the invention.

[0008] A display device according to an embodiment includes: a substrate including a display area and a non-display area; a first driving voltage supply line disposed in the non-display area, the first driving voltage supply line extending in a first direction, and a driving voltage applied to the first driving voltage supply line; a second driving voltage supply line disposed in a plan view between the display area and the first driving voltage supply line, the second driving voltage supply line extending in the first direction and spaced apart from the first driving voltage supply line; a bridging electrode disposed on the first driving voltage supply line and the second driving voltage supply line, and the bridging electrode electrically connecting the first driving voltage supply line and the second driving voltage supply line to each other; an organic insulating layer disposed on the bridging electrode, and the organic insulating layer including a first portion adjacent to the first driving voltage supply line and a second portion adjacent to the second driving voltage supply line; and an emitting layer disposed in the display area, and the emitting layer extending from the display area to the non-display area such that an end portion of the emitting layer in the non-display area overlaps with the bridging electrode in a plan view. The average thickness of the first portion of the organic insulating layer is less than the average thickness of the second portion of the organic insulating layer.

[0009] In an embodiment, in a plan view, a first portion of the organic insulating layer may overlap with the bridging electrode and may not overlap with the emitter layer, and a second portion of the organic insulating layer may overlap with both the bridging electrode and the emitter layer.

[0010] In an embodiment, the thickness deviation in the first portion of the organic insulating layer may be greater than the thickness deviation in the second portion of the organic insulating layer.

[0011] In an embodiment, in a plan view, the second driving voltage supply line may be spaced apart from the display area in a second direction intersecting the first direction, and the first driving voltage supply line may be spaced apart from the second driving voltage supply line in the second direction.

[0012] In an embodiment, a first portion of the organic insulating layer may be positioned in a second direction from a second portion of the organic insulating layer.

[0013] In one embodiment, the bridging electrode may define a plurality of holes positioned between the first drive voltage supply line and the second drive voltage supply line and spaced apart from each other in a plan view.

[0014] In an embodiment, the plurality of holes may include a plurality of first holes adjacent to a first drive voltage supply line, the plurality of first holes being arranged along a first direction, and the plurality of first holes being spaced apart from the emitter layer in a plan view. A first-first portion of the first portion of the organic insulating layer that overlaps with the plurality of first holes in a plan view may have a first thickness. A first-second portion of the first portion of the organic insulating layer that overlaps with the first portion of the bridging electrode located between the plurality of first holes in the first direction in a plan view may have a second thickness less than the first thickness.

[0015] In one embodiment, the plurality of holes may include a plurality of second holes adjacent to a second drive voltage supply line, the plurality of second holes being arranged along a first direction, and the plurality of second holes overlapping the emitter layer in a planar view. A second-first portion of the second portion of the organic insulating layer overlapping the plurality of second holes in a planar view may have a first thickness. A second-second portion of the second portion of the organic insulating layer overlapping the second portion of the bridging electrode located between the plurality of second holes in the first direction in a planar view may also have a first thickness.

[0016] In an embodiment, the display device may further include a demultiplexer circuit disposed between the substrate and the bridging electrode and overlapping the bridging electrode in a plan view.

[0017] In one embodiment, the display device may further include pixel electrodes disposed in the display area. The bridging electrode may be made of the same material as the pixel electrode.

[0018] A method of manufacturing a display device according to an embodiment includes: forming a first driving voltage supply line and a second driving voltage supply line in a non-display area on a substrate including a display area and a non-display area; forming a bridging electrode on the first driving voltage supply line and the second driving voltage supply line; forming a preliminary organic insulating layer on the bridging electrode; patterning the preliminary organic insulating layer using a mask to form an organic insulating layer including a first portion adjacent to the first driving voltage supply line and a second portion adjacent to the second driving voltage supply line; and forming an emitter layer extending from the display area to the non-display area such that an end portion of the emitter layer in the non-display area overlaps with the bridging electrode in a plan view. The first driving voltage supply line extends in a first direction. A driving voltage is applied to the first driving voltage supply line. A second driving voltage supply line is disposed in a plan view between the display area and the first driving voltage supply line, the second driving voltage supply line extending in the first direction and spaced apart from the first driving voltage supply line. The bridging electrode electrically connects the first driving voltage supply line and the second driving voltage supply line. The average thickness of the first portion of the organic insulating layer is less than the average thickness of the second portion of the organic insulating layer.

[0019] In an embodiment, in a plan view, a first portion of the organic insulating layer may overlap with the bridging electrode and may not overlap with the emitter layer, and a second portion of the organic insulating layer may overlap with both the bridging electrode and the emitter layer.

[0020] In an embodiment, the thickness deviation in the first portion of the organic insulating layer may be greater than the thickness deviation in the second portion of the organic insulating layer.

[0021] In an embodiment, the mask may be a halftone mask.

[0022] In one embodiment, the bridging electrode may define a plurality of holes positioned between the first drive voltage supply line and the second drive voltage supply line and spaced apart from each other in a plan view.

[0023] In an embodiment, the plurality of holes may include a plurality of first holes adjacent to a first driving voltage supply line, the plurality of first holes being arranged along a first direction, and the plurality of first holes being spaced apart from the emitter layer in a plan view. A first-first portion of the first portion of the organic insulating layer that overlaps with the plurality of first holes in a plan view may have a first thickness. A first-second portion of the first portion of the organic insulating layer that overlaps with the first portion of the bridging electrode located between the plurality of first holes in the first direction in a plan view may have a second thickness less than the first thickness.

[0024] In one embodiment, the plurality of holes may include a plurality of second holes adjacent to a second drive voltage supply line, the plurality of second holes being arranged along a first direction, and the plurality of second holes overlapping the emitter layer in a planar view. A second-first portion of the second portion of the organic insulating layer overlapping the plurality of second holes in a planar view may have a first thickness. A second-second portion of the second portion of the organic insulating layer overlapping the second portion of the bridging electrode located between the plurality of second holes in the first direction in a planar view may also have a first thickness.

[0025] In an embodiment, the method may further include: forming a pixel circuit in the display area and a demultiplexer circuit in the non-display area before forming the first driving voltage supply line and the second driving voltage supply line. The bridging electrode may overlap with the demultiplexer circuit in the planar view.

[0026] In an embodiment, forming a bridging electrode may include: forming a conductive layer in a display area and a non-display area; and patterning the conductive layer to form a pixel electrode in the display area and a bridging electrode in the non-display area.

[0027] An electronic device according to an embodiment includes: a window; a housing coupled to the window to provide an interior space; and a display device housed in the interior space located between the housing and the window. The display device includes: a substrate including a display area and a non-display area; a first driving voltage supply line disposed in the non-display area, the first driving voltage supply line extending in a first direction, and a driving voltage applied to the first driving voltage supply line; a second driving voltage supply line disposed in a plan view between the display area and the first driving voltage supply line, the second driving voltage supply line extending in the first direction and spaced apart from the first driving voltage supply line; a bridging electrode disposed on the first driving voltage supply line and the second driving voltage supply line, and the bridging electrode electrically connecting the first driving voltage supply line and the second driving voltage supply line to each other; an organic insulating layer disposed on the bridging electrode, and the organic insulating layer including a first portion adjacent to the first driving voltage supply line and a second portion adjacent to the second driving voltage supply line; and an emitting layer disposed in the display area, and the emitting layer extending from the display area to the non-display area such that an end portion of the emitting layer in the non-display area overlaps with the bridging electrode in a plan view. The average thickness of the first part of the organic insulating layer is less than the average thickness of the second part of the organic insulating layer.

[0028] The display device according to an embodiment may include bridging electrodes electrically connected to drive voltage supply lines spaced apart from each other in a non-display area. This can prevent or reduce abnormal light emission from the bridging electrodes located in the non-display area, thereby effectively improving the reliability of the display device.

[0029] It will be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0030] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to illustrate the invention.

[0031] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0032] Figure 2 This is a plan view showing a display device according to an embodiment.

[0033] Figure 3 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment.

[0034] Figure 4 This is a cross-sectional view showing a display device according to an embodiment.

[0035] Figure 5 This is a schematic diagram of the equivalent circuit of the demultiplexer according to an embodiment.

[0036] Figure 6 and Figure 7 It is shown Figure 2 An enlarged plan view of an example of region A.

[0037] Figure 8 It is along Figure 7 The cross-sectional view taken from line I-I'.

[0038] Figure 9 It is along Figure 7 The cross-sectional view taken from line II-II'.

[0039] Figures 10 to 13 This is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment.

[0040] Figure 14 This is a block diagram illustrating an electronic device according to an embodiment.

[0041] Figure 15 It is shown that Figure 14 The view shows an example of an electronic device implemented as a smartphone.

[0042] Figure 16 yes Figure 15 An exploded perspective view of an electronic device. Detailed Implementation

[0043] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, in which some exemplary embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity.

[0044] Various modifications and forms may be made in this disclosure, and specific embodiments will be shown in the accompanying drawings and described in detail in the text. However, this is not intended to limit this disclosure to the specific forms disclosed, and it will be understood that all changes, equivalents, or substitutions falling within the spirit and technical scope of this disclosure should be included.

[0045] It will be understood that although the terms “first,” “second,” “first-first,” “second-first,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the invention. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0046] It will be understood that when an element is referred to as “connected” or “coupled” to another element, the element may be directly connected or coupled to the other element, or there may be intermediary elements (multiple intermediary elements). In contrast, when an element is referred to as “directly connected” or “directly coupled” to another element, there are no intermediary elements. Other terms used to describe the relationship between elements should be interpreted in the same way (e.g., “between” vs. “directly between”, “adjacent” vs. “next to”, etc.).

[0047] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0048] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the relative terms are also intended to cover different orientations of the device. For example, if the device is flipped in a drawing, an element described as being “below” the other elements will subsequently be oriented to be “above” the other elements. Thus, depending on the specific orientation of the drawing, the term “below” can cover both “below” and “above” orientations. Similarly, if the device is flipped in a drawing, an element described as being “below” or “under” the other elements will subsequently be oriented to be “above” the other elements. Thus, the terms “below” or “under” can cover both “above” and “below” orientations.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having meanings consistent with their meanings in the context of the relevant field and will not be interpreted in an idealized or overly formalized sense.

[0050] In the following description, embodiments will be illustrated in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0051] Figure 1 This is a block diagram illustrating a display device DD according to an embodiment.

[0052] Reference Figure 1 According to an embodiment, the display device DD may include a display panel DP, a drive controller CON, a scan driver SDV, a data driver DDV, a demultiplexer circuit DMC, and a transmit driver EDV.

[0053] The display panel DP may include multiple pixels PX, multiple scan lines SL, multiple emission control lines EML, and multiple data lines DL. In an embodiment, the pixels PX may be disposed on a first direction DR1 and a second direction DR2 intersecting the first direction DR1.

[0054] Each pixel PX can be electrically connected to one of the scan lines SL, one of the transmit control lines EML, and one of the data lines DL. For example, the first pixel PX1 can be electrically connected to the first data line DL1, and the second pixel PX2 can be electrically connected to the second data line DL2.

[0055] The drive controller CON can receive input image data IDAT and input control signals CTRL from an external device. For example, input image data IDAT may include red, green, and blue image data. For example, input image data IDAT may include white image data. For example, input image data IDAT may include magenta, yellow, and cyan image data. Input control signals CTRL may include a master clock signal and a data enable signal. Input control signals CTRL may also include a vertical synchronization signal and a horizontal synchronization signal.

[0056] The drive controller CON can generate scan control signal SCTRL, data control signal DCTRL, transmit control signal ECTRL, and output image data ODAT based on the input image data IDAT and the input control signal CTRL.

[0057] The drive controller CON can generate a scan control signal SCTRL based on the input control signal CTRL to control the operation of the scan driver SDV. The drive controller CON can output the scan control signal SCTRL to the scan driver SDV. The scan control signal SCTRL may include a vertical start signal and a scan clock signal.

[0058] The drive controller CON can generate a data control signal DCTRL for controlling the operation of the data driver DDV based on the input control signal CTRL. The drive controller CON can output the data control signal DCTRL to the data driver DDV. The data control signal DCTRL can include a horizontal start signal and a load signal.

[0059] The drive controller CON can generate output image data ODAT based on the input image data IDAT. The drive controller CON can then output the output image data ODAT to the data driver DDV.

[0060] The drive controller CON can generate a transmit control signal ECTRL based on the input control signal CTRL to control the operation of the transmit driver EDV. The drive controller CON can then output the transmit control signal ECTRL to the transmit driver EDV.

[0061] The scan driver SDV can generate a scan signal based on the scan control signal SCTRL received from the drive controller CON. The scan driver SDV can then output the scan signal to the scan line SL.

[0062] The data driver DDV can generate a data signal based on the output image data ODAT and the data control signal DCTRL. For example, the data driver DDV can generate a data signal corresponding to the output image data ODAT and can output the data signal based on the data control signal DCTRL. The data driver DDV can output the data signal to the demultiplexer circuit DMC via a data transmission line. For example, the data driver DDV can be implemented using one or more integrated circuits.

[0063] The demultiplexer circuit (DMC) can transmit data signals to data lines DL. For example, the DMC can time-divide data signals and transmit data signals. In an embodiment, the DMC may include multiple demultiplexers (DMs). Each of the demultiplexers (DMs) can time-divide received data signals and transmit data signals to data lines DL. For example, a demultiplexer (DM) can receive data signals from a data driver (DDV) via a first data transmission line (DTL1) and can sequentially transmit the data signals to a first data line DL1 and a second data line DL2. This will be referred to later. Figure 5 Describe in detail.

[0064] The transmit driver EDV can generate a transmit control signal based on the transmit control signal ECTRL received from the drive controller CON. The transmit driver EDV can then output the transmit control signal to the transmit control line EML.

[0065] Figure 2 This is a plan view of the display device DD according to an embodiment. As used herein, "plan view" is a view in the thickness direction (i.e., third direction DR3) of the display device DD (or substrate SUB).

[0066] Reference Figure 2 In this embodiment, the display device DD can display an image on a third direction DR3 via a display surface defined by a first direction DR1 and a second direction DR2. The third direction DR3 can be substantially parallel to the normal direction of the display surface. The display surface can correspond to the upper surface (or front surface) of the display device DD.

[0067] In an embodiment, the display device DD may include a substrate SUB, a pixel PX, a scan driver SDV, a data driver DDV, a transmit driver EDV, a terminal portion TMP, a demultiplexer circuit DMC, a drive voltage supply line DSL, and a common voltage supply line SSL.

[0068] The substrate SUB may include a display area DA and a non-display area NDA. The display area DA can display an image. In an embodiment, in a plan view, the display area DA may have a rectangular shape, and the corners of the display area DA may each have a rounded curved shape, but the invention is not limited thereto. Pixels PX, scan lines SL, data lines DL, transmit control lines EML, and drive voltage lines VDL may be disposed in the display area DA.

[0069] The non-display area NDA can be located outside the display area DA. For example, the non-display area NDA can surround the display area DA in a plan view. In an embodiment, a portion of the non-display area NDA can be bent.

[0070] The scan driver SDV, data driver DDV, and transmit driver EDV can be set in the non-display area NDA. Figure 2 The illustration shows a scan driver (SDV) positioned to the left of the display area (DA) and a transmit driver (EDV) positioned to the right of the display area (DA), but this is an example and the invention is not limited thereto. For example, a first scan driver and a first transmit driver could be positioned to the left of the display area (DA), and a second scan driver and a second transmit driver could be positioned to the right of the display area (DA). The data driver (DDV) could be positioned spaced apart from the display area (DA) in a second direction (DR2).

[0071] The terminal portion TMP can be disposed on one end portion of the base SUB and can include multiple terminals TM1, TM2, TM3, and TM4. The terminal portion TMP can be electrically connected to a protrusion on a circuit board attached to one end portion of the base SUB. For example, signals used to control the operation of the data driver DDV (e.g., Figure 1 The data control signal DCTRL and output image data ODAT can be transmitted to the data driver DDV through the first terminal TM1. For example, the drive voltage can be applied to the drive voltage supply line DSL through the second terminal TM2. For example, signals used to control the operation of the scan driver SDV (e.g., Figure 1 The scan control signal (SCTRL) can be transmitted to the scan driver SDV via the third terminal TM3. For example, a common voltage can be applied to the common voltage supply line SSL via the fourth terminal TM4.

[0072] The demultiplexer circuit (DMC) can be located in the non-display area (NDA). In a plan view, the demultiplexer circuit (DMC) can be positioned between the display area (DA) and the data driver (DDV). The demultiplexer circuit (DMC) receives data signals from the data driver (DDV) via the data transmission line (DTL). The demultiplexer circuit (DMC) can time-divide the data signals and can transmit the data signals to the data line (DL).

[0073] In an embodiment, in a plan view, the demultiplexer circuit DMC can be positioned between the fan-out test circuit and the illumination test circuit in the non-display area NDA. For example, in a plan view, the fan-out test circuit can be positioned between the data driver DDV and the demultiplexer circuit DMC. For example, in a plan view, the illumination test circuit can be positioned between the demultiplexer circuit DMC and the display area DA.

[0074] The driving voltage supply line DSL can be disposed in the non-display area NDA. In an embodiment, in a plan view, the driving voltage supply line DSL can be disposed between the display area DA and the data driver DDV. The driving voltage supply line DSL can provide driving voltage to the pixel PX through the driving voltage line VDL. In an embodiment, the driving voltage lines VDL can each extend in the second direction DR2 and can be disposed in the first direction DR1.

[0075] In an embodiment, in a plan view, the drive voltage supply line DSL may overlap with the demultiplexer circuit DMC. The drive voltage supply line DSL may include a first drive voltage supply line DSL1, a second drive voltage supply line DSL2, and a bridging electrode BRE.

[0076] The first drive voltage supply line DSL1 can extend along the first direction DR1. In the plan view, the first drive voltage supply line DSL1 can be positioned between the display area DA and the data driver DDV. In the plan view, the first drive voltage supply line DSL1 can also be positioned between the demultiplexer circuit DMC and the data driver DDV. The drive voltage can be applied to the first drive voltage supply line DSL1 through the second terminal TM2.

[0077] The second drive voltage supply line DSL2 can extend along the first direction DR1. In the plan view, the second drive voltage supply line DSL2 can be positioned between the display area DA and the first drive voltage supply line DSL1. In the plan view, the second drive voltage supply line DSL2 can be spaced apart from the display area DA along the second direction DR2, and can be spaced apart from the first drive voltage supply line DSL1 in the opposite direction to the second direction DR2. In the plan view, the second drive voltage supply line DSL2 can be positioned between the display area DA and the demultiplexer circuit DMC. The second drive voltage supply line DSL2 can be connected to the drive voltage line VDL extending from the second drive voltage supply line DSL2 to the display area DA.

[0078] In the plan view, the first drive voltage supply line DSL1 and the second drive voltage supply line DSL2 may be spaced apart from each other in the second direction DR2, and the demultiplexer circuit DMC is located between the first drive voltage supply line DSL1 and the second drive voltage supply line DSL2. In the plan view, the first drive voltage supply line DSL1 may be spaced apart from the demultiplexer circuit DMC in the second direction DR2. In the plan view, the second drive voltage supply line DSL2 may be spaced apart from the demultiplexer circuit DMC in the opposite direction to the second direction DR2. That is, in the plan view, each of the first drive voltage supply line DSL1 and the second drive voltage supply line DSL2 may not overlap with the demultiplexer circuit DMC.

[0079] A bridging electrode (BRE) can be disposed on the first drive voltage supply line DSL1, the second drive voltage supply line DSL2, and the demultiplexer circuit DMC. The bridging electrode BRE can overlap with the demultiplexer circuit DMC in a plan view and can electrically connect the first drive voltage supply line DSL1 and the second drive voltage supply line DSL2. For example, a first end portion of the bridging electrode BRE can be connected to the first drive voltage supply line DSL1, a second end portion of the bridging electrode BRE can be connected to the second drive voltage supply line DSL2, and the central portion of the bridging electrode BRE can overlap with the demultiplexer circuit DMC in a plan view. Drive voltage can be applied to the second drive voltage supply line DSL2 through the bridging electrode BRE.

[0080] A common voltage supply line SSL can be located in the non-display area NDA. In an embodiment, the common voltage supply line SSL can be formed as a loop with an open end side and extend along the edge of the substrate SUB except for the edge adjacent to the terminal portion TMP, but the invention is not limited thereto. The common voltage supply line SSL can provide a common voltage to the pixel PX. For example, a light-emitting element LED (see...) Figure 4 The common electrode CE (see) Figure 4 It can be connected to the common voltage supply line SSL in the non-display area NDA.

[0081] Figure 3 This is a schematic diagram of the equivalent circuit of pixel PX according to an embodiment.

[0082] Each pixel PX may include a pixel circuit PC and a light-emitting element LED. The pixel circuit PC may have substantially the same structure. The pixel PX connected to the m-th data line DLm and the i-th scan line SLi will be described below.

[0083] Reference Figure 3 The pixel circuit PC may include a first pixel transistor T1, a second pixel transistor T2, a third pixel transistor T3, a fourth pixel transistor T4, a fifth pixel transistor T5, a sixth pixel transistor T6 and a seventh pixel transistor T7, as well as a storage capacitor CST.

[0084] The first pixel transistor T1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3.

[0085] The second pixel transistor T2 may include a gate electrode connected to the i-th scan line SLi, a first electrode connected to the m-th data line DLm, and a second electrode connected to the second node N2.

[0086] The third pixel transistor T3 may include a gate electrode connected to the i-th scan line SLi, a first electrode connected to the first node N1, and a second electrode connected to the third node N3.

[0087] The fourth pixel transistor T4 may include a gate electrode connected to the (i-1)th scan line SLi-1, a first electrode to which the initialization signal VINT is applied, and a second electrode connected to the first node N1.

[0088] The fifth pixel transistor T5 may include a gate electrode connected to the i-th emitter control line EMLi, a first electrode to which the driving voltage ELVDD is applied, and a second electrode connected to the second node N2. The driving voltage ELVDD may be a high power supply voltage.

[0089] The sixth pixel transistor T6 may include a gate electrode connected to the i-th emission control line EMLi, a first electrode connected to the third node N3, and a pixel electrode (anode) connected to the light-emitting element LED. Figure 4 The second electrode of the pixel electrode (PE).

[0090] The seventh pixel transistor T7 may include a gate electrode connected to the (i-1)th scan line SLi-1, a first electrode to which the initialization signal VINT is applied, and a second electrode connected to the pixel electrode of the light-emitting element LED.

[0091] The storage capacitor CST may include a first electrode to which the drive voltage ELVDD is applied and a second electrode connected to the first node N1.

[0092] The light-emitting element (LED) may include pixel electrodes and a common electrode (cathode) to which the common voltage ELVSS is applied. Figure 4 The common electrode (CE). The common voltage ELVSS can be a low supply voltage. The light-emitting element (LED) can emit light based on the drive current supplied from the pixel circuit PC. For example, the light-emitting element (LED) can include organic light-emitting diodes, inorganic light-emitting diodes, quantum dot light-emitting diodes, or micro light-emitting diodes, etc.

[0093] exist Figure 3 In the diagram, the first pixel transistor T1, the second pixel transistor T2, the third pixel transistor T3, the fourth pixel transistor T4, the fifth pixel transistor T5, the sixth pixel transistor T6, and the seventh pixel transistor T7 are shown as P-channel metal-oxide-semiconductor (“PMOS”) transistors, but the embodiment is not limited thereto. For example, the third pixel transistor T3 and the fourth pixel transistor T4 may be N-channel metal-oxide-semiconductor (“NMOS”) transistors, and the other pixel transistors may be PMOS transistors. As another example, all of the first pixel transistor T1, the second pixel transistor T2, the third pixel transistor T3, the fourth pixel transistor T4, the fifth pixel transistor T5, the sixth pixel transistor T6, and the seventh pixel transistor T7 may be NMOS transistors.

[0094] also, Figure 3 The number of pixel transistors and capacitors shown are merely examples and can be varied according to embodiments.

[0095] Figure 4 This is a cross-sectional view showing the display device DD according to an embodiment.

[0096] Figure 4 This is a cross-sectional view of the display area DA of the display device DD.

[0097] Reference Figure 4The display device DD may include a substrate SUB, a buffer layer BFL, a transistor TR, a storage capacitor CST, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer ILD, a first via insulating layer VIA1, a connection electrode CNE, a second via insulating layer VIA2, a light-emitting element LED, and an organic insulating layer OIL. The transistor TR may include an active layer ACT, a gate electrode GE, a first contact electrode CTE1, and a second contact electrode CTE2. For example, Figure 4 The transistor TR can be Figure 3 The sixth pixel transistor T6. The storage capacitor CST may include a first capacitor electrode CPE1 and a second capacitor electrode CPE2. The light-emitting element LED may include a pixel electrode PE, an emitter layer EL, and a common electrode CE.

[0098] The substrate SUB can form the base of the display device DD. The substrate SUB can be an insulating substrate comprising transparent or opaque materials or formed of transparent or opaque materials. In one embodiment, the substrate SUB can be flexible, and the display device DD can be a flexible display device. In another embodiment, the substrate SUB can be rigid, and the display device DD can be a rigid display device.

[0099] A buffer layer (BFL) can be disposed on the substrate SUB. The buffer layer BFL prevents or reduces the penetration of impurities such as oxygen or moisture through the substrate SUB into the upper portion of the substrate SUB. The buffer layer BFL can comprise inorganic materials such as silicon compounds or metal oxides. For example, the buffer layer BFL can comprise silicon oxide (SiO₂). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x ), tantalum oxide (TaO) x ), hafnium oxide (HfO) x Zirconium oxide (ZrO) x ) or titanium dioxide (TiO) x These materials can be used alone or in combination with each other. The buffer layer BFL can have a single-layer structure or a multi-layer structure including multiple insulating layers.

[0100] The active layer ACT can be disposed on the buffer layer BFL. The active layer ACT can include oxide semiconductors, silicon semiconductors, or organic semiconductors. For example, the oxide semiconductor can include at least one oxide selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The silicon semiconductor can include amorphous silicon or polycrystalline silicon. The active layer ACT can include a first contact region, a second contact region, and a channel region positioned between the first and second contact regions. Each of the first and second contact regions can have a higher conductivity than the channel region.

[0101] A first gate insulating layer GI1 may be disposed on the active layer ACT. The first gate insulating layer GI1 may cover the active layer ACT on the buffer layer BFL. The first gate insulating layer GI1 may include an inorganic insulating material.

[0102] The gate electrode GE can be disposed on the first gate insulating layer GI1. The gate electrode GE can overlap with the channel region of the active layer ACT. The gate electrode GE can be used as the first capacitor electrode CPE1 of the storage capacitor CST. The gate electrode GE can include conductive materials such as metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive materials. For example, the gate electrode GE can include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum-containing alloys, silver-containing alloys, copper-containing alloys, molybdenum-containing alloys, and aluminum nitride (AlN). x ), Tungsten nitride (WN) x Titanium nitride (TiN) x ), Chromium nitride (CrN) x ), Tantalum nitride (TaN) x ), SrRuO x ), zinc oxide (ZnO) x Indium tin oxide (ITO), tin oxide (SnO) x Indium oxide (InO) x Gallium oxide (GaO) x Materials such as indium zinc oxide (IZO) or other similar materials can be used individually or in combination. The gate electrode (GE) can have a single-layer structure or a multilayer structure comprising multiple conductive layers.

[0103] The second gate insulating layer GI2 can be disposed on the gate electrode GE. The second gate insulating layer GI2 can cover the gate electrode GE on the first gate insulating layer GI1. The second gate insulating layer GI2 may include an inorganic insulating material.

[0104] The second capacitor electrode CPE2 can be disposed on the second gate insulating layer GI2. In a plan view, the second capacitor electrode CPE2 can overlap with the first capacitor electrode CPE1. The second capacitor electrode CPE2 can include a conductive material such as a metal, alloy, conductive metal nitride, conductive metal oxide, or transparent conductive material.

[0105] An interlayer insulating layer (ILD) may be disposed on the second capacitor electrode CPE2. The ILD may cover the second capacitor electrode CPE2 on the second gate insulating layer GI2. The ILD may comprise inorganic insulating materials and / or organic insulating materials.

[0106] The first contact electrode CTE1 and the second contact electrode CTE2 can be disposed on the interlayer insulating layer (ILD). The first contact electrode CTE1 and the second contact electrode CTE2 can be respectively connected to the first contact region and the second contact region of the active layer ACT. Each of the first contact electrode CTE1 and the second contact electrode CTE2 may include a conductive material.

[0107] A first via insulating layer VIA1 can be disposed on the first contact electrode CTE1 and the second contact electrode CTE2. The first via insulating layer VIA1 can cover the first contact electrode CTE1 and the second contact electrode CTE2 on the interlayer insulating layer ILD. The first via insulating layer VIA1 can include an organic insulating material. For example, the first via insulating layer VIA1 can include photoresist, polyacrylic resin (such as acrylic resin), polyimide resin, polyamide resin, siloxane resin, or epoxy resin, etc. These materials can be used alone or in combination with each other.

[0108] The connecting electrode CNE can be disposed on the first via insulating layer VIA1. The connecting electrode CNE may include a conductive material. The connecting electrode CNE can be connected to the second contact electrode CTE2 through a contact hole penetrating the first via insulating layer VIA1.

[0109] A second via insulating layer VIA2 can be disposed on the connecting electrode CNE. The second via insulating layer VIA2 can cover the connecting electrode CNE on the first via insulating layer VIA1. The second via insulating layer VIA2 may include an organic insulating material.

[0110] The pixel electrode PE can be disposed on the second via insulating layer VIA2. The pixel electrode PE may include a conductive material. The pixel electrode PE can be connected to the connection electrode CNE through a contact hole penetrating the second via insulating layer VIA2. Therefore, the pixel electrode PE can be electrically connected to the transistor TR. For example, the pixel electrode PE can be the anode of a light-emitting element LED.

[0111] An organic insulating layer (OIL) can be disposed on the pixel electrode (PE). The organic insulating layer (OIL) may include an organic insulating material. In an embodiment, the organic insulating layer (OIL) may further include a light-blocking material with a black color. The organic insulating layer (OIL) may include a first layer (OIL1) and a second layer (OIL2).

[0112] In the display area DA, the first layer OIL1 can cover the peripheral portion of the pixel electrode PE and define a pixel opening that exposes the central portion of the pixel electrode PE. The emission area can be defined by the pixel opening. The first layer OIL1 set in the display area DA can be referred to as the pixel defining layer.

[0113] In the display area DA, a second OIL2 layer can be disposed outside the pixel electrode PE. The second OIL2 layer can be disposed on top of the first OIL1 layer. In an embodiment, in the non-emitting region of the display area DA, multiple second OIL2 layers can be disposed on top of the first OIL1 layer, spaced apart from each other. For example, the second OIL2 layers can be used to support structures used in the manufacturing process of the display device DD (e.g., a fine metal mask (“FMM”) for forming the emitter layer EL, etc.). The second OIL2 layers disposed in the display area DA can be referred to as spacers.

[0114] In an embodiment, the first layer OIL1 and the second layer OIL2 of the organic insulating layer OIL can be formed substantially simultaneously using a halftone mask. That is, the organic insulating layer OIL can have a monolayer structure in which the first layer OIL1 and the second layer OIL2 are integral. The organic insulating layer OIL can have a first thickness TH1 in the region where both the first layer OIL1 and the second layer OIL2 are disposed, and can have a second thickness TH2 less than the first thickness TH1 in the region where only the first layer OIL1 is disposed and the second layer OIL2 is not disposed. In other words, the organic insulating layer OIL can be formed using a halftone mask to include relatively thick portions and relatively thin portions.

[0115] The emitting layer EL can be disposed on the pixel electrode PE and the organic insulating layer OIL. At least a portion of the emitting layer EL can be disposed in the pixel opening of the first layer OIL1 of the organic insulating layer OIL. In embodiments, the emitting layer EL may include at least one of organic light-emitting materials and quantum dots, but the present invention is not limited thereto.

[0116] In the embodiments, the organic light-emitting material may include low-molecular-weight organic compounds or high-molecular-weight organic compounds. Examples of low-molecular-weight organic compounds may include copper phthalocyanine, N,N'-diphenylbiphenyldiamine, or tris(8-hydroxyquinoline)aluminum, etc. Examples of high-molecular-weight organic compounds may include poly(3,4-ethylenedioxythiophene), polyaniline, poly(p-phenylenevinylene), or polyfluorene, etc. These materials may be used alone or in combination.

[0117] In embodiments, the quantum dot may include a core comprising group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, and / or group IV compounds. In embodiments, the quantum dot may have a core-shell structure comprising a core and a shell surrounding the core. The shell may act as a protective layer to prevent the core from being chemically denatured to maintain its semiconductor properties, and may also act as a charging layer to impart electrophoretic properties to the quantum dot.

[0118] A common electrode CE can be disposed on the emitter layer EL. The common electrode CE may include a conductive material. In an embodiment, the common electrode CE can be disposed throughout the entire display area DA and can extend from the display area DA to a portion of the non-display area NDA. As described above, the common electrode CE can be connected to... Figure 2 The common voltage supply line SSL is located in the non-display area NDA. For example, the common electrode CE can be the cathode of the light-emitting element LED.

[0119] In an embodiment, the light-emitting element (LED) may further include a first functional layer disposed between the pixel electrode (PE) and the emitter layer (EL) and / or a second functional layer disposed between the emitter layer (EL) and the common electrode (CE). For example, the first functional layer may include a hole injection layer or a hole transport layer, and the second functional layer may include an electron transport layer or an electron injection layer.

[0120] In embodiments, various layers such as thin-film encapsulation layers, touch sensing layers, color filter layers, or light-collecting layers can be disposed on the common electrode CE.

[0121] Figure 5 This is a schematic diagram of the equivalent circuit of the demultiplexer DM according to an embodiment.

[0122] exist Figure 5 This invention will describe a scenario where a data transmission line DTL is connected to a demultiplexer DM and two data lines DL1 and DL2 are also connected to a demultiplexer DM. For example, the first data line DL2 and the second data line DL2 can be connected to a demultiplexer DM. However, the invention is not limited thereto.

[0123] Reference Figure 5 The demultiplexer DM may include a first allocation transistor TDM1 and a second allocation transistor TDM2.

[0124] The first allocation transistor TDM1 may include a gate electrode connected to a first allocation selection signal line CCL1, a first electrode to which the data signal DATA is applied, and a second electrode connected to a first data line DL1. The first allocation selection signal CL1 can be applied to the gate electrode of the first allocation transistor TDM1 through the first allocation selection signal line CCL1. When the first allocation selection signal CL1 is applied to the gate electrode of the first allocation transistor TDM1, the first allocation transistor TDM1 can be turned on and the data signal DATA can be output to the first data line DL1. That is, the first allocation transistor TDM1 can output the data signal DATA to the first data line DL1 in response to the first allocation selection signal CL1.

[0125] The second allocation transistor TDM2 may include a gate electrode connected to the second allocation selection signal line CCL2, a first electrode to which the data signal DATA is applied, and a second electrode connected to the second data line DL2. The second allocation selection signal CL2 can be applied to the gate electrode of the second allocation transistor TDM2 through the second allocation selection signal line CCL2. When the second allocation selection signal CL2 is applied to the gate electrode of the second allocation transistor TDM2, the second allocation transistor TDM2 can be turned on and the data signal DATA can be output to the second data line DL2. That is, the second allocation transistor TDM2 can output the data signal DATA to the second data line DL2 in response to the second allocation selection signal CL2.

[0126] The first allocation transistor TDM1 and the second allocation transistor TDM2 can be selectively turned on by the first allocation selection signal CL1 and the second allocation selection signal CL2. Therefore, the demultiplexer DM can selectively provide the data signal DATA to the two data lines DL1 and DL2.

[0127] Figure 6 and Figure 7 It is shown Figure 2 An enlarged plan view of an example of region A. Figure 8 It is along Figure 7 The cross-sectional view taken from line I-I'. Figure 9 It is along Figure 7 The cross-sectional view taken from line II-II'.

[0128] Figure 6 and Figure 7 Some components of the display device DD are shown. For example, Figure 6 The first drive voltage supply line DSL1, the second drive voltage supply line DSL2, the bridging electrode BRE, and the drive voltage line VDL can be shown. Figure 7 The organic insulating layer OIL and the emitting layer EL can be further shown in the diagram. Figure 6 On the components shown.

[0129] Reference Figure 2 as well as Figures 6 to 9 In the plan view, the first drive voltage supply line DSL1 can be spaced apart from the demultiplexer circuit DMC in the second direction DR2. In the plan view, the second drive voltage supply line DSL2 can be spaced apart from the demultiplexer circuit DMC in the opposite direction to the second direction DR2.

[0130] The bridging electrode BRE can be disposed on the first drive voltage supply line DSL1, the second drive voltage supply line DSL2, and the demultiplexer circuit DMC. The bridging electrode BRE can overlap with the demultiplexer circuit DMC in the plan view and can electrically connect the first drive voltage supply line DSL1 and the second drive voltage supply line DSL2.

[0131] In an embodiment, the bridging electrode BRE can be in a different layer from the first drive voltage supply line DSL1 and the second drive voltage supply line DSL2. For example, the first drive voltage supply line DSL, the second drive voltage supply line DSL2, and... Figure 4 The connecting electrodes CNE can be in the same layer, and the bridging electrodes BRE and Figure 4 The pixel electrode PE can be in the same layer. The first driving voltage supply line DSL1, the second driving voltage supply line DSL2, and... Figure 4 The connecting electrodes CNE can comprise the same material and can be formed substantially simultaneously with each other. The bridging electrodes BRE and Figure 4 The pixel electrodes PE can comprise the same material and can be formed substantially simultaneously with each other. A first driving voltage supply line DSL1 and a second driving voltage supply line DSL2 can be disposed between a first via insulating layer VIA1 and a second via insulating layer VIA2, and a bridging electrode BRE can be disposed between the second via insulating layer VIA2 and an organic insulating layer OIL. However, this is an example and the invention is not limited thereto.

[0132] In an embodiment, the bridging electrode BRE may include a first end portion that overlaps with the first drive voltage supply line DSL1 in a plan view, a second end portion that overlaps with the second drive voltage supply line DSL2 in a plan view, and a central portion that connects the first end portion and the second end portion.

[0133] For example, the first end portion of the bridging electrode BRE can be connected to the first drive voltage supply line DSL1 via the first contact hole CNT1 penetrating the second via insulating layer VIA2. The second end portion of the bridging electrode BRE can be connected to the second drive voltage supply line DSL2 via the second contact hole CNT2 penetrating the second via insulating layer VIA2. The central portion of the bridging electrode BRE can overlap with the demultiplexer circuit DMC in a plan view. For example, the demultiplexer circuit DMC can be disposed between the substrate SUB and the first via insulating layer VIA1. The demultiplexer circuit DMC can include demultiplexers DM, each containing a first allocation transistor TDM1 and a second allocation transistor TDM2 (see...). Figure 5 ).

[0134] In an embodiment, the central portion of the bridging electrode BRE may define a plurality of holes H for removing gas from the first via insulating layer VIA1 and the second via insulating layer VIA2. In a plan view, the holes H may be positioned between the first drive voltage supply line DSL1 and the second drive voltage supply line DSL2, and may be spaced apart from each other. For example, each of the holes H may have a rectangular planar shape, but the invention is not limited thereto. The holes H may provide pathways through which gas in the first via insulating layer VIA1 and the second via insulating layer VIA2 located below the bridging electrode BRE may be discharged to the outside.

[0135] In an embodiment, the plurality of holes H may include a first hole H1, a second hole H2, a third hole H3, and a fourth hole H4, which are located in different rows. The first hole H1 may be located in one of the rows closest to the first drive voltage supply line DSL1. In a plan view, the first hole H1 may be adjacent to the first drive voltage supply line DSL1 in a direction opposite to the second direction DR2 and may be arranged along the first direction DR1. The second hole H2 may be located in one of the rows closest to the second drive voltage supply line DSL2. In a plan view, the second hole H2 may be adjacent to the second drive voltage supply line DSL2 in the second direction DR2 and may be arranged along the first direction DR1. In a plan view, the third hole H3 and the fourth hole H4 may be located between the first hole H1 and the second hole H2. In a plan view, the third hole H3 may be adjacent to the first hole H1 in a direction opposite to the second direction DR2, and the fourth hole H4 may be adjacent to the second hole H2 in the second direction DR2.

[0136] In this embodiment, the organic insulating layer OIL may also be disposed on the first driving voltage supply line DSL1, the second driving voltage supply line DSL2, and the bridging electrode BRE. Furthermore, the emitter layer EL disposed in the display area DA may extend from the display area DA to the non-display area NDA, such that one end portion of the emitter layer EL in the non-display area NDA is adjacent to a portion of the bridging electrode BRE in a plan view (e.g., Figure 7 The upper portion of the bridging electrode BRE overlaps with the bridging electrode BRE. For example, considering process margins, the emitter layer EL can be formed in the display area DA by a deposition process using a deposition mask (e.g., FMM, etc.), and can also be formed in a portion of the non-display area NDA such that the edge EL-e of the emitter layer EL in the non-display area NDA is positioned on the bridging electrode BRE. That is, in a plan view, one end portion of the emitter layer EL in the non-display area NDA can overlap with the second drive voltage supply line DSL2, a portion of the bridging electrode BRE, and a portion of the demultiplexer circuit DMC.

[0137] In an embodiment, in a plan view, an end portion of the emitter layer EL in the non-display area NDA may overlap with some of the aperture H defined in the bridging electrode BRE. For example, as Figure 7 As shown in the diagram, in the plan view, one end portion of the emitter layer EL in the non-display area NDA may overlap with the second aperture H2, but may not overlap with the first aperture H1. That is, in the plan view, the first aperture H1 may be spaced apart from the emitter layer EL. Furthermore, Figure 7 The diagram shows an end portion of the emitter layer EL in the non-display area NDA that does not overlap with the third hole H3 and the fourth hole H4 in a plan view, but the invention is not limited thereto.

[0138] In an embodiment, the organic insulating layer OIL may include a first portion OILa adjacent to the first driving voltage supply line DSL1 and a second portion OILb adjacent to the second driving voltage supply line DSL2. The first portion OILa may be defined as the portion that overlaps with the bridging electrode BRE in a plan view but does not overlap with the emitter layer EL (i.e., is spaced apart from the emitter layer EL in a plan view), and the second portion OILb may be defined as the portion that overlaps with both the bridging electrode BRE and the emitter layer EL in a plan view. The first portion OILa may be positioned along a second direction DR2 from the second portion OILb. The boundary between the first portion OILa and the second portion OILb may correspond to the edge EL-e of the emitter layer EL.

[0139] In an embodiment, in a plan view, the first portion OILa of the organic insulating layer OIL may overlap with the first hole H1, the third hole H3, and the fourth hole H4, but may not overlap with the second hole H2. In a plan view, the second portion OILb of the organic insulating layer OIL may overlap with the second hole H2, but may not overlap with the first hole H1, the third hole H3, and the fourth hole H4.

[0140] In this embodiment, the average thickness of the first portion OILa of the organic insulating layer OIL can be less than the average thickness of the second portion OILb of the organic insulating layer OIL. Furthermore, the thickness deviation in the first portion OILa of the organic insulating layer OIL can be greater than the thickness deviation in the second portion OILb of the organic insulating layer OIL.

[0141] like Figure 6 , Figure 7 and Figure 8 As shown, in an embodiment, the first portion of the organic insulating layer OIL, OILa, overlapping one of the first holes H1 in a plan view, can have a first thickness TH1. The first portion of OILa can have a structure including a first layer OIL1 and a second layer OIL2. As described above, the first layer OIL1 and the second layer OIL2 can be integrally formed using a halftone mask.

[0142] like Figure 6 , Figure 7 and Figure 9 As shown in the embodiment, the first-second portion of the organic insulating layer OIL, OILa, which overlaps in a plan view with the first portion of the bridging electrode BRE located between two adjacent first holes H1 in the first direction DR1, may have a second thickness TH2 that is less than the first thickness TH1. The first-second portion OILa-2 may have a structure that includes the first layer OIL1 but does not include the second layer OIL2.

[0143] like Figure 6 , Figure 7 and Figure 9 As shown in the embodiment, the second-first portion OILb-1, which overlaps with one of the second holes H2 in the plan view of the second portion OILb of the organic insulating layer OIL, may have a first thickness TH1. The second-first portion OILb-1 may have a structure including a first layer OIL1 and a second layer OIL2.

[0144] like Figure 6 , Figure 7 and Figure 8As shown in the embodiment, the second portion OILb of the organic insulating layer OIL, which overlaps in a plan view with the second portion BREb of the bridging electrode BRE located between two adjacent second holes H2 in the first direction DR1, may have a first thickness TH1. The second portion OILb-2 may have a structure including a first layer OIL1 and a second layer OIL2.

[0145] In other words, according to the embodiment, in the region adjacent to the first drive voltage supply line DSL1 and far from the emitter layer EL (e.g., near the first via H1 arranged along the first direction DR1), the first portion OILa of the organic insulating layer OIL can have a structure in which portions each having a first thickness TH1 (i.e., including the first layer OIL1 and the second layer OIL2) and portions each having a second thickness TH2 less than the first thickness TH1 (i.e., including only the first layer OIL1) alternate with each other. Therefore, the gas release efficiency in the first via insulating layer VIA1 and the second via insulating layer VIA2 located below the bridging electrode BRE can be improved. In contrast, in the region adjacent to the second drive voltage supply line DSL2 and overlapping the emitter layer EL (e.g., near the second via H2 arranged along the first direction DR1), the second portion OILb of the organic insulating layer OIL can be formed to have the first thickness TH1 entirely (i.e., formed to include the first layer OIL1 and the second layer OIL2). In other words, unlike the regions in the planar diagram that do not overlap with the emitter layer EL, the entire organic insulating layer OIL under the emitter layer EL can be formed to be relatively thick in the regions in the planar diagram that overlap with both the emitter layer EL and the bridging electrode BRE.

[0146] For example, when the exposure amount in the exposure process for forming the organic insulating layer OIL is increased to remove residual layers of the first via insulating layer VIA1 and the second via insulating layer VIA2, a relatively thin portion of the organic insulating layer OIL (i.e., including only the first layer OIL1) may be easily lost. If a portion of the organic insulating layer OIL between the bridging electrode BRE to which the driving voltage is applied and the emitting layer EL is lost, abnormal light emission of the emitting layer EL at the bridging electrode BRE located in the non-display area NDA may occur. However, according to the embodiment, since the organic insulating layer OIL under the emitting layer EL is formed to have a relatively thick thickness throughout the region overlapping with the emitting layer EL (i.e., formed to include the first layer OIL1 and the second layer OIL2), the loss of the portion of the organic insulating layer OIL between the bridging electrode BRE to which the driving voltage is applied and the emitting layer EL can be prevented or reduced. Therefore, abnormal light emission of the emitting layer EL at the bridging electrode BRE located in the non-display area NDA can be prevented or reduced, thereby effectively improving the reliability of the display device DD.

[0147] The first portion OILa of the organic insulating layer OIL can be formed with a structure in which portions having a relatively thick first thickness TH1 and portions having a relatively thin second thickness TH2 alternate with each other at least in some regions, and the entire second portion OILb of the organic insulating layer OIL is formed with a relatively thick first thickness TH1 or more, such that the average thickness of the first portion OILa of the organic insulating layer OIL can be less than the average thickness of the second portion OILb of the organic insulating layer OIL. Furthermore, the thickness deviation in the first portion OILa of the organic insulating layer OIL can be greater than the thickness deviation in the second portion OILb of the organic insulating layer OIL.

[0148] In an embodiment, similar to the second portion OILb, a portion of the first portion OILa of the organic insulating layer OIL adjacent to the second portion OILb (i.e., adjacent to the emitting layer EL) can be formed to have a relatively thick first thickness TH1 (i.e., formed to include a first layer OIL1 and a second layer OIL2). For example, as Figures 7 to 9As shown, near the fourth aperture H4 arranged along the first direction DR1, a portion of the first portion OILa of the organic insulating layer OIL can have a general first thickness TH1. For example, near the third aperture H3 arranged along the first direction DR1, another portion of the first portion OILa of the organic insulating layer OIL can have a structure in which portions each having a first thickness TH1 and portions each having a second thickness TH2 less than the first thickness TH1 alternate with each other. For example, the extent of the region in which the organic insulating layer OIL is formed to have a generally thick first thickness TH1 can be determined by considering the tolerances of the deposition mask used to form the emitter layer EL.

[0149] Although not shown in the accompanying drawings, the display device DD may further include a bridging pattern disposed in the non-display area NDA, in the same layer as the pixel electrode PE and the bridging electrode BRE, and to which a common voltage is applied. For example, the bridging pattern disposed in the non-display area NDA can... Figure 2 SSL and public voltage supply lines Figure 4 The common electrode CE is electrically connected. Furthermore, the emitter layer EL can extend from the display area DA to the non-display area NDA, such that a portion of the emitter layer EL overlaps with the bridging pattern in the planar view. Unlike the bridging electrode BRE to which the driving voltage is applied, the emitter layer EL may not emit light on the bridging pattern even if a portion of the organic insulating layer OIL is lost between the bridging pattern and the emitter layer EL where the common voltage is applied. Therefore, to further improve the gas release efficiency in the first via insulating layer VIA1 and the second via insulating layer VIA2, in the region overlapping both the emitter layer EL and the bridging pattern, the organic insulating layer OIL beneath the emitter layer EL can have a structure in which portions each having a first thickness TH1 and portions each having a second thickness TH2 alternate with each other.

[0150] Figures 10 to 13 This is a cross-sectional view illustrating a method for manufacturing a display device DD according to an embodiment.

[0151] For example, in Figures 10 to 13 In each of them, the left cross-sectional view can be compared with Figure 8 Corresponding, and the right cross-sectional view can be compared with Figure 4 Corresponding. In the following text, it will be referred to... Figures 10 to 13 Briefly describe the manufacturing process. Figures 2 to 9 Examples of methods for display devices DD. In the following text, descriptions overlapping with the above description will be omitted or simplified.

[0152] Reference Figure 10A buffer layer BFL, a transistor TR, a storage capacitor CST, a demultiplexer circuit DMC, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer ILD, a first via insulating layer VIA1, a connection electrode CNE, a first drive voltage supply line DSL1, a second drive voltage supply line DSL2, and a second via insulating layer VIA2 can be formed on the substrate SUB. The transistor TR and the storage capacitor CST can be formed on the substrate SUB in the display area DA. The demultiplexer circuit DMC can be formed on the substrate SUB in the non-display area NDA.

[0153] A connection electrode CNE, a first driving voltage supply line DSL1, and a second driving voltage supply line DSL2 can be formed on the first via insulating layer VIA1. The connection electrode CNE can be formed on the first via insulating layer VIA1 in the display area DA, and the first driving voltage supply line DSL1 and the second driving voltage supply line DSL2 can be formed on the first via insulating layer VIA1 in the non-display area NDA. The connection electrode CNE, the first driving voltage supply line DSL1, and the second driving voltage supply line DSL2 can be formed substantially simultaneously. In an embodiment, a first conductive layer can be formed on the first via insulating layer VIA1, and the first conductive layer can be patterned using photolithography and etching processes to form the connection electrode CNE, the first driving voltage supply line DSL1, and the second driving voltage supply line DSL2.

[0154] A second via insulating layer VIA2 can be formed on the connecting electrode CNE, the first driving voltage supply line DSL1, and the second driving voltage supply line DSL2. The second via insulating layer VIA2 can be partially removed to form a contact hole exposing a portion of the connecting electrode CNE, a first contact hole CNT1 exposing a portion of the first driving voltage supply line DSL1, and a second contact hole CNT2 exposing a portion of the second driving voltage supply line DSL2.

[0155] A pixel electrode PE and a bridging electrode BRE can be formed on the second via insulating layer VIA2. The pixel electrode PE can be formed on the second via insulating layer VIA2 in the display area DA, and the bridging electrode BRE can be formed on the second via insulating layer VIA2 in the non-display area NDA. The bridging electrode BRE can be formed to overlap with the demultiplexer circuit DMC in the plan view. The bridging electrode BRE can electrically connect the first drive voltage supply line DSL1 and the second drive voltage supply line DSL2. A first end portion of the bridging electrode BRE can be connected to the first drive voltage supply line DSL1 through a first contact hole CNT1, and a second end portion of the bridging electrode BRE can be connected to the second drive voltage supply line DSL2 through a second contact hole CNT2.

[0156] The bridging electrode BRE is positioned at the central portion between the first end portion and the second end portion, which can define a plurality of holes H for removing gas from the first via insulating layer VIA1 and the second via insulating layer VIA2 (see [link]). Figure 7 In the plan view, hole H can be positioned between the first drive voltage supply line DSL1 and the second drive voltage supply line DSL2, and can be spaced apart from each other.

[0157] The pixel electrode PE and the bridging electrode BRE can be formed essentially simultaneously. In an embodiment, a second conductive layer can be formed on the second via insulating layer VIA2, and the second conductive layer can be patterned by photolithography and etching processes to form the pixel electrode PE and the bridging electrode BRE defining a plurality of vias H.

[0158] Reference Figure 11 and Figure 12 An organic insulating layer (OIL) can be formed on the second via insulating layer (VIA2), the pixel electrode (PE), and the bridging electrode (BRE).

[0159] A preliminary organic insulating layer OIL-p can be formed on the second via insulating layer VIA2, pixel electrode PE, and bridging electrode BRE by applying a photoresist. In an embodiment, the preliminary organic insulating layer OIL-p may have a first thickness TH1. In an embodiment, the preliminary organic insulating layer OIL-p may include a positive photoresist.

[0160] The initial organic insulating layer OIL-p can be patterned using the exposure and development processes of a mask MSK to form an organic insulating layer OIL comprising a first layer OIL1 and a second layer OIL2.

[0161] The mask MSK can be a halftone mask. The mask MSK may include a light-blocking portion (LBP), a light-transmitting portion (TP), and a light-semi-transmitting portion (HTP). The light-blocking portion (LBP) can be the area that blocks incident light incident on the mask MSK. The light-transmitting portion (TP) and the light-semi-transmitting portion (HTP) can be the areas that transmit incident light, and the transmittance of the light-semi-transmitting portion (HTP) can be less than the transmittance of the light-transmitting portion (TP). For example, the light-transmitting portion (TP) can transmit all of the incident light, and the light-semi-transmitting portion (HTP) can transmit only a portion of the incident light.

[0162] The portion of the initial organic insulating layer OIL-p corresponding to the light-blocking portion LBP is not exposed to incident light. The portion of the initial organic insulating layer OIL-p corresponding to the light-transmitting portion TP is fully exposed to incident light. The portion of the initial organic insulating layer OIL-p corresponding to the light-semi-transmitting portion HTP is partially exposed to incident light.

[0163] When the preliminary organic insulating layer OIL-p is developed in the developing process, the portion of the preliminary organic insulating layer OIL-p corresponding to the light-blocking portion LBP can be completely retained, the portion of the preliminary organic insulating layer OIL-p corresponding to the light-transmitting portion TP can be completely removed, and the portion of the preliminary organic insulating layer OIL-p corresponding to the light-semi-transmitting portion HTP can be partially retained. Therefore, as Figure 12 As shown, an organic insulating layer OIL can be formed comprising a portion having a relatively thick first thickness TH1 (i.e., including a first layer OIL1 and a second layer OIL2) and a portion having a relatively thin second thickness TH2 (i.e., including only the first layer OIL1). In other words, the organic insulating layer OIL can be formed as a monolayer structure in which the first layer OIL1 and the second layer OIL2 are integrally formed by a single exposure process.

[0164] Reference Figure 13 An emitter layer (EL) can be formed on the organic insulating layer (OIL). The emitter layer (EL) can also be formed within the display area (DA). For example, considering process margins, the emitter layer (EL) can be formed using a deposition process with a deposition mask, and it can also be formed within a portion of the non-display area (NDA) such that its edges are positioned on the bridging electrode (BRE). A common electrode (CE) can be formed on both the organic insulating layer (OIL) and the emitter layer (EL).

[0165] According to an embodiment, since the organic insulating layer OIL below the emitting layer EL is formed to have a relatively thick thickness throughout the region overlapping with the emitting layer EL (i.e., formed to include a first layer OIL1 and a second layer OIL2), loss of the portion of the organic insulating layer OIL located between the bridging electrode BRE to which the driving voltage is applied and the emitting layer EL can be prevented or reduced. Therefore, abnormal light emission from the emitting layer EL at the bridging electrode BRE located in the non-display area NDA can be prevented or reduced, thereby effectively improving the reliability of the display device DD.

[0166] Figure 14 This is a block diagram illustrating an electronic device 900 according to an embodiment.

[0167] Reference Figure 14 In this embodiment, the electronic device 900 may include a processor 910, a memory device 920, a storage device 930, an input / output (“I / O”) device 940, a power supply 950, and a display device 960. Here, the display device 960 may correspond to the display device DD described above. The electronic device 900 may also include multiple ports for communicating with video cards, sound cards, memory cards, or Universal Serial Bus (“USB”) devices.

[0168] Processor 910 can perform various computing functions or tasks. In embodiments, processor 910 may be a microprocessor, a central processing unit (“CPU”), or an application processor (“AP”), etc. Processor 910 may be coupled to other components via address buses, control buses, or data buses, etc. In embodiments, processor 910 may be coupled to an expansion bus such as a peripheral component interconnect (“PCI”) bus.

[0169] The memory device 920 may store data for the operation of the electronic device 900. In embodiments, the memory device 920 may include at least one non-volatile memory device such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nanofloating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, or a ferroelectric random access memory (“FRAM”) device, and / or at least one volatile memory device such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, or a mobile DRAM device.

[0170] In an embodiment, storage device 930 may include a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, or a read-only optical disc storage (“CD-ROM”) device, etc. In an embodiment, I / O device 940 may include input devices such as a keyboard, keypad, mouse device, touchpad, or touch screen, and output devices such as a printer or speaker.

[0171] Power supply 950 can provide power for the operation of electronic device 900. Display device 960 can be coupled to other components via a bus or other communication link. In an embodiment, display device 960 may be included in I / O device 940.

[0172] Figure 15 It is shown that Figure 14 The electronic device 900 is implemented as an example of a smartphone. Figure 16 yes Figure 15 Exploded perspective view of electronic device 900.

[0173] Reference Figure 15In this embodiment, the electronic device 900 can be implemented as a smartphone. However, the electronic device 900 is not limited to this, and for example, it can be implemented as a television, mobile phone, video phone, smart tablet, smartwatch, tablet PC (“PC”), vehicle navigation, computer monitor, laptop computer, head-mounted display (“HMD”), or self-service kiosk, etc. Referring below... Figure 15 and Figure 16 An embodiment in which the electronic device 900 is implemented as a smartphone is described in more detail.

[0174] Reference Figure 15 and Figure 16 In one embodiment, the electronic device 900 may include a window WU, a display device 960, and a housing HM. The window WU and the housing HM may be coupled to define the appearance of the electronic device 900.

[0175] Display device 960 can display an image. Display device 960 may include a display area DA for displaying the image and a non-display area NDA positioned around the display area DA. A plurality of pixels PX for generating the image may be disposed in the display area DA. A driver (e.g., a data driver DDV) for driving the pixels PX may be disposed in the non-display area NDA. Display device 960 can be associated with the aforementioned display device DD (see [link to display device DD]). Figure 1 , 2 It corresponds to one of the ones in 4).

[0176] The window WU may define the front surface of the electronic device 900. The window WU may be translucent. For example, the window WU may include a resin film such as a polyimide film or an ultra-thin glass film.

[0177] The housing HM can be coupled to the window WU. The housing HM can be coupled to the window WU to provide internal space. The display device 960 can be housed within the internal space provided between the housing HM and the window WU. Various components, such as optical films, pads, heating layers, processors, memory devices, storage devices, I / O devices, or power supplies, can be further housed within the internal space. The housing HM can comprise a material with relatively high rigidity. The housing HM can stably protect the components housed within the internal space from external impacts.

[0178] Although embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the invention is not limited to such embodiments, but rather to the broader scope of the appended claims and the various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A display device, wherein, The display device includes: The substrate includes both the display area and the non-display area; A first driving voltage supply line is disposed in the non-display area, the first driving voltage supply line extends in a first direction, and a driving voltage is applied to the first driving voltage supply line; A second driving voltage supply line is disposed between the display area and the first driving voltage supply line in the plan view. The second driving voltage supply line extends in the first direction and is spaced apart from the first driving voltage supply line. A bridging electrode is disposed on the first driving voltage supply line and the second driving voltage supply line, and the bridging electrode electrically connects the first driving voltage supply line and the second driving voltage supply line to each other. An organic insulating layer is disposed on the bridging electrode, and the organic insulating layer includes a first portion adjacent to the first driving voltage supply line and a second portion adjacent to the second driving voltage supply line; and An emitting layer is disposed in the display area and extends from the display area to the non-display area, such that one end portion of the emitting layer in the non-display area overlaps with the bridging electrode in the plan view. Wherein, the average thickness of the first portion of the organic insulating layer is less than the average thickness of the second portion of the organic insulating layer.

2. The display device according to claim 1, wherein, In the plan view, The first portion of the organic insulating layer overlaps with the bridging electrode but not with the emitter layer, and The second portion of the organic insulating layer overlaps with both the bridging electrode and the emitter layer.

3. The display device according to claim 1, wherein, The thickness deviation in the first portion of the organic insulating layer is greater than the thickness deviation in the second portion of the organic insulating layer.

4. The display device according to claim 1, wherein, In the plan view, The second driving voltage supply line is spaced apart from the display area in a second direction that intersects the first direction, and The first driving voltage supply line is spaced apart from the second driving voltage supply line in the second direction.

5. The display device according to claim 4, wherein, The first portion of the organic insulating layer is positioned in the second direction from the second portion of the organic insulating layer.

6. The display device according to claim 1, wherein, The bridging electrode defines a plurality of holes positioned between the first drive voltage supply line and the second drive voltage supply line and spaced apart from each other in the plan view.

7. The display device according to claim 6, wherein, The plurality of holes includes a plurality of first holes, the plurality of first holes being adjacent to the first driving voltage supply line, the plurality of first holes being arranged along the first direction, and the plurality of first holes being spaced apart from the emitter layer in the plan view. The first portion of the first part of the organic insulating layer, which overlaps with the plurality of first holes in the plan view, has a first thickness, and The first portion of the first part of the organic insulating layer, which overlaps with the first portion of the bridging electrode located between the plurality of first holes in the first direction in the plan view, has a second thickness less than the first thickness.

8. The display device according to claim 7, wherein, The plurality of holes includes a plurality of second holes adjacent to the second drive voltage supply line, the plurality of second holes being arranged along the first direction, and the plurality of second holes overlapping the emitter layer in the plan view. The second portion of the second part of the organic insulating layer, which overlaps with the plurality of second holes in the plan view, has the first thickness, and The second portion of the second portion of the organic insulating layer, which overlaps with the second portion of the bridging electrode located between the plurality of second holes in the first direction in the plan view, has the first thickness.

9. The display device according to claim 1, wherein, The display device further includes: A demultiplexer circuit is disposed between the substrate and the bridging electrode and overlaps with the bridging electrode in the plan view.

10. The display device according to claim 1, wherein, The display device further includes: Pixel electrodes are disposed in the display area, and The bridging electrode and the pixel electrode are made of the same material.

11. A method for manufacturing a display device, wherein, The method includes: A first driving voltage supply line and a second driving voltage supply line are formed in the non-display area on a substrate including a display area and a non-display area, wherein the first driving voltage supply line extends in a first direction, a driving voltage is applied to the first driving voltage supply line, and the second driving voltage supply line is disposed in a plan view between the display area and the first driving voltage supply line, the second driving voltage supply line extends in the first direction, and the second driving voltage supply line is spaced apart from the first driving voltage supply line; A bridging electrode is formed on the first driving voltage supply line and the second driving voltage supply line, wherein the bridging electrode electrically connects the first driving voltage supply line and the second driving voltage supply line. A preliminary organic insulating layer is formed on the bridging electrode; The initial organic insulating layer is patterned using a mask to form an organic insulating layer comprising a first portion adjacent to the first drive voltage supply line and a second portion adjacent to the second drive voltage supply line; and An emitting layer is formed extending from the display area to the non-display area, such that one end portion of the emitting layer in the non-display area overlaps with the bridging electrode in the plan view, and Wherein, the average thickness of the first portion of the organic insulating layer is less than the average thickness of the second portion of the organic insulating layer.

12. The method according to claim 11, wherein, In the plan view, The first portion of the organic insulating layer overlaps with the bridging electrode but not with the emitter layer, and The second portion of the organic insulating layer overlaps with both the bridging electrode and the emitter layer.

13. The method according to claim 11, wherein, The thickness deviation in the first portion of the organic insulating layer is greater than the thickness deviation in the second portion of the organic insulating layer.

14. The method according to claim 11, wherein, The mask is a halftone mask.

15. The method according to claim 11, wherein, The bridging electrode defines a plurality of holes positioned between the first drive voltage supply line and the second drive voltage supply line and spaced apart from each other in the plan view.

16. The method according to claim 15, wherein, The plurality of holes includes a plurality of first holes, the plurality of first holes being adjacent to the first driving voltage supply line, the plurality of first holes being arranged along the first direction, and the plurality of first holes being spaced apart from the emitter layer in the plan view. The first portion of the first part of the organic insulating layer, which overlaps with the plurality of first holes in the plan view, has a first thickness, and The first portion of the first part of the organic insulating layer, which overlaps with the first portion of the bridging electrode located between the plurality of first holes in the first direction in the plan view, has a second thickness less than the first thickness.

17. The method according to claim 16, wherein, The plurality of holes includes a plurality of second holes adjacent to the second drive voltage supply line, the plurality of second holes being arranged along the first direction, and the plurality of second holes overlapping the emitter layer in the plan view. The second portion of the second part of the organic insulating layer, which overlaps with the plurality of second holes in the plan view, has the first thickness, and The second portion of the second portion of the organic insulating layer, which overlaps with the second portion of the bridging electrode located between the plurality of second holes in the first direction in the plan view, has the first thickness.

18. The method according to claim 11, wherein, The method further includes: Before forming the first driving voltage supply line and the second driving voltage supply line, a pixel circuit is formed in the display area and a demultiplexer circuit is formed in the non-display area. The bridging electrode overlaps with the demultiplexer circuit in the plan view.

19. The method according to claim 11, wherein, The formation of the bridging electrode includes: A conductive layer is formed in the display area and the non-display area; and The conductive layer is patterned to form pixel electrodes in the display area and bridging electrodes in the non-display area.

20. An electronic device, wherein, The electronic device includes: window; The outer casing, coupled to the window, provides interior space; and A display device, housed within the internal space located between the housing and the window, the display device comprising: The substrate includes both the display area and the non-display area; A first driving voltage supply line is disposed in the non-display area, the first driving voltage supply line extends in a first direction, and a driving voltage is applied to the first driving voltage supply line; A second driving voltage supply line is disposed between the display area and the first driving voltage supply line in the plan view. The second driving voltage supply line extends in the first direction and is spaced apart from the first driving voltage supply line. A bridging electrode is disposed on the first driving voltage supply line and the second driving voltage supply line, and the bridging electrode electrically connects the first driving voltage supply line and the second driving voltage supply line to each other. An organic insulating layer is disposed on the bridging electrode, and the organic insulating layer includes a first portion adjacent to the first driving voltage supply line and a second portion adjacent to the second driving voltage supply line; and An emitting layer is disposed in the display area and extends from the display area to the non-display area, such that one end portion of the emitting layer in the non-display area overlaps with the bridging electrode in the plan view. Wherein, the average thickness of the first portion of the organic insulating layer is less than the average thickness of the second portion of the organic insulating layer.

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