Display device

By employing a design in the display device that uses transistors sharing a gate electrode or well region, the problem of limited transistor arrangement under high pixel density is solved, and a display device with high resolution and high display quality is realized.

CN122121483APending Publication Date: 2026-05-29SAMSUNG DISPLAY CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SAMSUNG DISPLAY CO LTD
Filing Date
2025-09-08
Publication Date
2026-05-29

AI Technical Summary

Technical Problem

Existing display devices face limitations in transistor placement during the design of pixel circuits to achieve high resolution and low area, making it difficult to meet the requirements for high pixel density.

Method used

By adopting a pixel design approach where transistors share a gate electrode or well region, multiple transistors can be adequately arranged within the pixel region, and the size of the driving transistor can be increased through the shared structure.

Benefits of technology

High display quality of high-resolution display devices is achieved by rationally arranging transistors within the pixel area, ensuring sufficient space and driving capability.

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Abstract

The present application relates to a display device. The display device includes: pixels each including a first sub-pixel, a second sub-pixel, and a third sub-pixel adjacent to each other. The first sub-pixel includes: a first drive transistor including a first well region and a first gate electrode; and a first switch transistor including a second well region and a second gate electrode. The second sub-pixel can include: a second drive transistor including a third well region and a third gate electrode; and a second switch transistor including a fourth well region and a fourth gate electrode connected to the second gate electrode. The third sub-pixel includes: a third drive transistor including a fifth well region and a fifth gate electrode; and a third switch transistor including a sixth well region and a sixth gate electrode connected to the second gate electrode.
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