Three-electrode perovskite x-ray detector and method of manufacturing the same

By introducing a gate and its gate dielectric into a perovskite X-ray detector, programmable control of the carrier channel is achieved, solving the problems of high dark current, high noise, and slow response speed, improving the signal-to-noise ratio and energy spectral resolution, and making it suitable for transparent conductive oxides and metal thin films with various electrode combinations.

CN122121509APending Publication Date: 2026-05-29HUAZHONG UNIV OF SCI & TECH +1

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
HUAZHONG UNIV OF SCI & TECH
Filing Date
2026-01-16
Publication Date
2026-05-29

Smart Images

  • Figure CN122121509A_ABST
    Figure CN122121509A_ABST
Patent Text Reader

Abstract

The application discloses a three-electrode perovskite X-ray detector and a preparation method thereof, and belongs to the technical field of perovskite X-ray detectors. The method comprises the following steps: providing a substrate; preparing a gate electrode on the substrate, wherein the gate electrode comprises a surface gate, a mesh gate and a two-dimensional gate; preparing a gate dielectric on the gate electrode, wherein the gate dielectric comprises polyimide; preparing a perovskite absorption layer on the gate dielectric, wherein the perovskite absorption layer is a thin film or a thin film; preparing a self-assembled layer on the perovskite absorption layer, wherein the self-assembled layer comprises an alkyl mercaptan, a halide salt, an organic ammonium salt and NiOx; preparing a bottom electrode on the left side of the self-assembled layer; and preparing a collecting electrode on the right side of the self-assembled layer. The method introduces a gate electrode and a gate dielectric on the basis of a traditional double electrode, realizes an integrated unit of absorption-electric field regulation-signal reading, thereby obtains built-in gain and noise suppression of the device, and completes signal reading in cooperation with a near-end transimpedance or charge-sensitive amplifier.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] This application belongs to the field of perovskite X-ray detector technology, and particularly relates to a three-electrode perovskite X-ray detector and its fabrication method. Background Technology

[0002] Perovskite direct X-ray detectors have attracted widespread attention due to their potential applications in medical imaging, industrial non-destructive testing, and nuclear radiation monitoring. Perovskite materials possess advantages such as high atomic numbers, excellent carrier mobility-lifetime products, and low-temperature solution fabrication, making them suitable for constructing high-efficiency detection devices with thick absorption layers (0.3–3 mm), thus enabling the achievement of high quantum detection efficiency, high sensitivity, and energy resolution.

[0003] In recent years, with , Perovskite systems, represented by [examples of perovskite materials], have shown promising performance potential in X-ray detection. These materials can have their photoelectric properties optimized through compositional and dimensional manipulation, and possess the potential for integration with flexible substrates and arrayed readout circuits, providing a material basis for realizing low-dose, high-spatial-resolution imaging systems.

[0004] Traditional X-ray detection technology mainly relies on semiconductor materials such as silicon and cadmium selenide. While these materials exhibit stability in some applications, they still have certain limitations: First, the high bias voltage required for high absorption thickness leads to a significant increase in dark current and noise; second, the material itself has limited carrier mobility and lifetime, restricting its charge collection efficiency in thick-layer devices; furthermore, traditional detector structures lack built-in gain and electric field manipulation capabilities, making it difficult to achieve both high count rates and high energy resolution. Existing technologies cannot achieve synergistic optimization between low noise, high sensitivity, and arrayable integration, and still have significant shortcomings in interface manipulation and electric field distribution design. Current perovskite X-ray detectors suffer from problems such as high dark current, insufficient energy spectral resolution, limited response speed, and insufficient stability. Summary of the Invention

[0005] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a three-electrode perovskite X-ray detector and its fabrication method. This method integrates absorption, electric field modulation, and signal readout into a single unit by introducing a gate and its gate dielectric onto a traditional dual-electrode (cathode / anode) architecture. By applying a low-voltage DC or pulsed voltage to the gate, the carrier channels, weighting potential, and effective mobility in the vicinity of the collection end can be programmably controlled, thereby achieving built-in gain and noise suppression. This is then combined with a near-end transimpedance or charge-sensitive amplifier to complete signal readout.

[0006] To address the above problems, according to a first aspect of the present invention, a method for fabricating a three-electrode perovskite X-ray detector is provided, the method comprising: Provide substrate; A gate is fabricated on the substrate, the gate comprising a planar gate, a mesh gate, and a two-dimensional gate; A gate dielectric is fabricated on the gate, the gate dielectric comprising: , , Polyimide; A perovskite absorber layer is prepared on the gate dielectric, wherein the perovskite absorber layer is... thin film or film; A self-assembled layer is prepared on the perovskite absorber layer, the self-assembled layer comprising alkathiol, halide, organic ammonium salt, and NiOx; A bottom electrode is fabricated on the left side of the self-assembled layer; A collection electrode is prepared on the right side of the self-assembled layer.

[0007] According to one embodiment of this application, the preparation of the gate includes surface gate preparation, mesh gate preparation and two-dimensional gate preparation. The surface gate preparation is a sputtering method, in which ITO is sputtered to obtain an ITO thin film with a thickness of 50-150 nm.

[0008] According to one embodiment of this application, the fabrication of the grid includes: A metal thin film is obtained by deposition of metal using a deposition method. The metal thin film is then patterned by photolithography and etching processes to obtain a metal layer with periodic openings as a grid. The size of the openings is 10-200 μm and the duty cycle of the openings is 30%-80%.

[0009] According to one embodiment of this application, the fabrication of the two-dimensional gate includes: Graphene films were deposited using chemical vapor deposition and then patterned to obtain patterned graphene films used as two-dimensional gratings.

[0010] According to one embodiment of this application, the thickness of the gate dielectric is 20-200 mm.

[0011] According to one embodiment of this application, the preparation of the perovskite absorber layer includes: Select a thickness of 0.5-2.0 mm. or Single crystals are subjected to double-sided CMP polishing and low-temperature drying to obtain... thin film or film.

[0012] According to one embodiment of this application, the fabrication of the bottom electrode includes: ITO thin films are obtained by sputtering or vapor deposition. The ITO thin films are then subjected to photolithographic patterning and annealing at 150-200°C to obtain the bottom electrode.

[0013] According to one embodiment of this application, the collecting electrode is prepared by vapor deposition, and the collecting electrode is an Au thin film or a Pt thin film.

[0014] According to a second aspect of the present invention, a three-electrode perovskite X-ray detector is provided, the three-electrode perovskite X-ray detector comprising a substrate, a gate, a gate dielectric, a perovskite absorber layer, a self-assembled layer, a bottom electrode, and a collector electrode.

[0015] According to one embodiment of this application, the operation of the three-electrode perovskite X-ray detector includes: A high voltage bias is applied between the bottom electrode and the collector electrode, and a low voltage is applied between the gate and the bottom electrode or the collector electrode. The gate electric field is coupled to the neighborhood of the collector end through the gate dielectric to change the local carrier density and effective mobility, forming an adjustable equivalent transconductance and realizing device-level built-in gain.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application.

[0017] The present invention provides a method for fabricating a three-electrode perovskite X-ray detector, which has the following advantages over the prior art: (1) This invention integrates amplification and readout within the device by forming a controlled conductive channel and adjustable equivalent transconductance through gate voltage VG coupling with the gate dielectric in the neighborhood of the collection end. Compared with a gateless two-electrode control device, under the same thickness and drift field strength, the output pulse amplitude or equivalent charge corresponding to a single quantum can achieve higher gain, effectively reducing dark current noise and improving the signal-to-noise ratio. By shaping the gate-controlled electric field and introducing equivalent transconductance, device-level amplification is achieved, and only conventional near-end readout is required externally to obtain higher amplitude and a more stable baseline.

[0018] (2) This invention integrates amplification and readout by introducing a gate at the device level, giving the device adjustable gain / threshold / operating point capabilities, reducing the burden on the external front end, and improving the discriminability of single quantum signals. By shaping the electric field and weighted potential through the gate and its dielectric layer, the effective drift path is shortened, pulse tailing and charge sharing are suppressed without sacrificing absorption thickness, and the counting and energy spectrum under high throughput are improved. Dark current and multi-source noise are reduced. Through structured electric field and contact engineering, injection channels and edge leakage are suppressed, and a system optimization framework of material-electrode-morphology is established. It is applicable to various electrode combinations such as transparent conductive oxides / metal thin films / two-dimensional materials, forming a complete design and process window for size, morphology and contact, taking into account transmittance, sheet resistance and interface quality.

[0019] (3) By continuously adjusting the local carrier concentration and effective mobility, the operating point and gain can be programmably set, and the energy spectrum peak shape and linearity can be quickly matched and optimized under different thicknesses / biases. The gate acts as a clamp for injection and edge leakage, significantly suppressing dark current and its low-frequency noise components, and further improving the minimum detectable dose and energy resolution. Attached Figure Description

[0020] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic flowchart of the fabrication method of the three-electrode perovskite X-ray detector provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of the three-electrode perovskite X-ray detector provided in the embodiments of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0022] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0023] The fabrication method of the three-electrode perovskite X-ray detector provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0024] Existing structures based primarily on two electrodes (parallel plates) share the following common problems: (1) High dark current and noise: Contact injection, surface / edge leakage and volume defects together lead to high dark current; low frequency 1 / f and mid frequency GR (generation-recombination) noise are significant, raising the equivalent noise charge (ENC) and limiting the minimum detectable dose and energy resolution.

[0025] (2) Lack of built-in, adjustable gain and threshold control: The two-electrode structure relies solely on external transimpedance / charge amplification, and the device itself does not have adjustable transconductance / threshold. When the pixel capacitance is large or the readout link is limited, the amplitude of the single quantum signal is prone to approach the noise baseline, resulting in peak broadening and energy spectrum degradation.

[0026] (3) Uncontrollable electric field leads to undesirable transport and weighting potential: the electric field distribution in the thick absorption layer is difficult to shape, and the weighting potential gradient near the collection end is too steep or too slow, which will cause problems such as pulse tailing, charge sharing, and ballistic loss. Under high throughput, the above problems are superimposed to form pulse accumulation and counting dead zone.

[0027] (4) Thick devices have long drift time and slow response: When using millimeter-level thickness to ensure absorption efficiency, the drift time increases significantly; existing structures lack engineering means to control the effective mobility / drift path, and pulse shaping is limited, making it difficult to balance energy spectrum and count rate.

[0028] (5) Insufficient interface / contact engineering: Work function mismatch, high interface state density, surface ion migration and local polarization cause injection and non-uniform electric field; the contact morphology / size of transparent conductive oxide (TCO), metal thin film and perovskite lack systematic optimization, which makes it difficult to reduce contact resistance, parasitic capacitance and leakage current.

[0029] Figure 1This is a schematic flowchart illustrating the fabrication method of the three-electrode perovskite X-ray detector provided in the embodiments of this application, as shown below. Figure 1 As shown, the fabrication method of the three-electrode perovskite X-ray detector includes steps 110, 120, 130, 140, 150, 160 and 170.

[0030] Step 110: Provide a substrate; For example, the substrate is a glass support device with a thickness of 1-2 mm for flatness and a light transmittance of >90%.

[0031] Optionally, the substrate may be alumina, glass fiber epoxy, Si, or low thermal expansion ceramic.

[0032] Step 120: Fabricate a gate on the substrate, the gate comprising a planar gate, a mesh gate, and a two-dimensional gate; In some embodiments, the fabrication of the gate includes planar gate fabrication, mesh gate fabrication, and two-dimensional gate fabrication. The planar gate fabrication is performed by sputtering ITO to obtain an ITO thin film with a thickness of 50-150 nm.

[0033] An exemplary process for fabricating a surface grating is as follows: a JCP500 magnetron sputtering device is used for film deposition. The target material is indium-doped tin oxide (ITO) target. The target-to-substrate distance is set to 80 cm. DC sputtering is performed. Argon gas is introduced to make the chamber pressure 0.5 Pa. The sputtering power is set to 100 W and the sputtering time is 10 min, resulting in an ITO surface grating film with a thickness of 100 nm.

[0034] Optionally, the surface grid is a transparent conductive oxide, such as ITO, IZO, or AZO.

[0035] In some embodiments, the fabrication of the mesh includes: A metal thin film is obtained by deposition of metal using a deposition method. The metal thin film is then patterned by photolithography and etching processes to obtain a metal layer with periodic openings as a grid. The size of the openings is 10–200 μm and the duty cycle of the openings is 30%–80%.

[0036] Optionally, the grid can be a thin metal film, such as Au, Al, or Cr.

[0037] For example, the specific process for fabricating the metal mesh is as follows: A 150 nm thick chromium film is deposited on a clean substrate using an electron beam evaporation apparatus. Subsequently, positive photoresist is spin-coated onto the chromium film, and ultraviolet exposure is performed using a photomask with a pre-designed grid pattern. After development, a photoresist pattern is formed. Next, the exposed chromium areas are wet-etched using a chromium etching solution. Finally, residual photoresist is removed with acetone to obtain a metal mesh with an aperture size of 50 μm and a duty cycle of 60%.

[0038] In some embodiments, the fabrication of the two-dimensional grating includes: Graphene films were deposited using chemical vapor deposition and then patterned to obtain patterned graphene films used as two-dimensional gratings.

[0039] An exemplary two-dimensional grating fabrication process is as follows: A monolayer of graphene is grown on a copper foil using chemical vapor deposition at 1000°C in a mixed atmosphere of hydrogen and methane. Subsequently, a PMMA support layer is spin-coated onto the graphene surface. or The copper foil substrate is etched away with solution, and the PMMA / graphene film is transferred onto the target substrate. Finally, the PMMA is removed by dissolving with acetone, and the designed graphene gate pattern is obtained by oxygen plasma etching using photoresist as a mask.

[0040] In this embodiment, by introducing a gate at the device level, amplification and readout are integrated, giving the device adjustable gain / threshold / operating point capabilities, reducing the burden on the external front end, and improving the discriminability of single quantum signals. The electric field and weighting potential are shaped by the gate and its dielectric layer, shortening the effective drift path, suppressing pulse tailing and charge sharing without sacrificing absorption thickness, and improving counting and energy spectrum at high throughput. Dark current and multi-source noise are reduced by suppressing injection channels and edge leakage through structured electric field and contact engineering. A systematic optimization framework of material-electrode-morphology is established, applicable to various electrode combinations such as transparent conductive oxides / metal thin films / two-dimensional materials, forming a complete design and process window for size, morphology, and contact, taking into account transmittance, sheet resistance, and interface quality.

[0041] Step 130: Fabricate a gate dielectric on the gate, the gate dielectric comprising... , , Polyimide; Exemplary The specific process for preparing the gate dielectric is as follows: Using an atomic layer deposition (ALD) system with high-purity nitrogen as both the carrier and purge gas, the substrate temperature was stabilized at 150°C. Trimethylaluminum precursor and deionized water were sequentially pulsed, with each precursor pulse lasting 15 ms and a purge time of 20 s. By controlling 200 deposition cycles, a gate dielectric with a thickness of approximately 20 nm was obtained. film.

[0042] Step 140: Prepare a perovskite absorber layer on the gate dielectric, wherein the perovskite absorber layer is... thin film or film; In some embodiments, the thickness of the gate medium is 20-200 mm.

[0043] Step 150: Prepare a self-assembled layer on the perovskite absorber layer, wherein the self-assembled layer comprises alkathiol, halide, organic ammonium salt, and NiOx; An exemplary self-assembled layer preparation process is as follows: An n-octanethiol / anhydrous ethanol solution is prepared. The prepared perovskite absorber layer wafer is completely immersed in this solution and left to stand in a nitrogen glove box for 12 hours. Afterward, the wafer surface is rinsed with a large amount of anhydrous ethanol to remove physically adsorbed molecules, and then dried at 80°C to obtain a dense n-octanethiol self-assembled monolayer.

[0044] In some embodiments, the preparation of the perovskite absorber layer includes: Select a thickness of 0.5–2.0 mm. or Single crystals are subjected to double-sided CMP polishing and low-temperature drying to obtain... thin film or film.

[0045] The exemplary perovskite absorber layer preparation process is as follows: A layer with a thickness of approximately 3 mm is selected. Bulk single crystals were mechanically ground sequentially using 800-mesh, 2000-mesh, and 5000-mesh diamond abrasive paper to precisely reduce their thickness to 1.0 mm. Subsequently, double-sided chemical mechanical polishing was performed using a 50 nm silica polishing slurry to obtain an atomically smooth surface. Finally, the polished wafers were dried in a nitrogen glove box on a hot table at 80°C for 12 hours to obtain... film.

[0046] Step 160: Prepare a bottom electrode on the left side of the self-assembled layer; In some embodiments, the fabrication of the bottom electrode includes: ITO thin films are obtained by sputtering or vapor deposition. The ITO thin films are then patterned by photolithography and annealed at 150–200°C to obtain the bottom electrode.

[0047] Optionally, the bottom electrode includes Au, Pt, Ti / Au, and ITO.

[0048] Optionally, the bottom electrode is Ti with a thickness of 10 nm or Au with a thickness of 100 nm.

[0049] The exemplary bottom electrode fabrication process is as follows: A JCP500 magnetron sputtering system was used for deposition, with indium-doped tin oxide (ITO) as the target material, purchased from Zhongnuo New Materials Co., Ltd. The target-substrate distance was set to 80 cm, and DC sputtering was employed. Argon and oxygen were introduced to maintain a chamber pressure of 0.5 Pa, with an argon to oxygen flow rate ratio of 28:0. The sputtering power was set to 100 W, and the sputtering time was 15 min, resulting in a 200 nm thick ITO film. Subsequently, photoresist was spin-coated onto the ITO film. After exposure and development, wet etching was performed using a mixture of hydrochloric acid and nitric acid to form the electrode pattern. Finally, the film was annealed at 180°C in air for 1 hour.

[0050] In this embodiment, a controlled conductive channel and adjustable equivalent transconductance are formed by coupling the gate voltage VG with the gate dielectric in the neighborhood of the collection end, enabling amplification and readout to be integrated within the device. Compared with a gateless two-electrode control device, under the same thickness and drift field strength, the output pulse amplitude or equivalent charge corresponding to a single quantum can achieve higher gain, effectively reducing dark current noise and improving the signal-to-noise ratio. By shaping the gate-controlled electric field and introducing equivalent transconductance, device-level amplification is achieved, and only conventional near-end readout is required externally to obtain higher amplitude and a more stable baseline.

[0051] Step 170: Prepare a collection electrode on the right side of the self-assembled layer.

[0052] In some embodiments, the collecting electrode is prepared by vapor deposition, and the collecting electrode is an Au thin film or a Pt thin film.

[0053] The exemplary process for preparing the collecting electrode is as follows: using a high-vacuum thermal evaporation device, the chamber vacuum is evacuated to 5×10⁻⁻⁻⁶. 4 Below Pa. A gold wire was placed in a tantalum boat, and the gold wire was slowly melted and gold atoms were evaporated by controlling the heating current. The deposition rate on the surface of the self-assembled layer was controlled at 0.3-0.5 Å / s and monitored by a quartz crystal film thickness gauge. Finally, a gold film with a thickness of 80 nm was obtained as the collecting electrode.

[0054] Optionally, the thickness of the collecting electrode is 50–150 nm, and the collecting electrode includes Au, Pt, Al, and ITO.

[0055] Optionally, the collecting electrode can be microstructured (e.g., localized windows / steps) to balance the local electric field.

[0056] According to the fabrication method of the three-electrode perovskite X-ray detector provided in this application, an integrated unit for absorption, electric field modulation, and signal readout is achieved by introducing a gate and its gate dielectric on the basis of a conventional dual-electrode (cathode / anode) system. By applying a low-voltage DC or pulsed voltage to the gate, the carrier channels, weighting potential, and effective mobility in the vicinity of the collection end can be programmably controlled, thereby obtaining built-in device gain and noise suppression, and signal readout is completed in conjunction with a near-end transimpedance or charge-sensitive amplifier.

[0057] This application also provides a three-electrode perovskite X-ray detector, such as... Figure 2 As shown, the three-electrode perovskite X-ray detector includes a substrate 101, a gate 106, a gate dielectric, a perovskite absorption layer 103, a self-assembled layer 107, a bottom electrode 102, and a collection electrode 104.

[0058] In some embodiments, the operation of the three-electrode perovskite X-ray detector includes: A high voltage bias is applied between the bottom electrode and the collector electrode, and a low voltage is applied between the gate and the bottom electrode or the collector electrode. The gate electric field is coupled to the neighborhood of the collector end through the gate dielectric to change the local carrier density and effective mobility, forming an adjustable equivalent transconductance and realizing device-level built-in gain.

[0059] In some embodiments, a perovskite absorber layer is mounted onto a substrate using low-shrinkage epoxy or silver paste. Before mounting, the surface is lightly passivated with SAM or halide salts, the device edges are passivated and basically sealed, a desiccant is added to suppress moisture sensitivity, and a barrier or sacrificial layer is provided at the gate dielectric edge to suppress thin-edge leakage.

[0060] In some embodiments, based on ITO planar gratings The fabrication process of the detector includes the following steps: Step 1: Substrate Preparation A glass substrate with a thickness of 1.1 mm and a light transmittance of >92% was selected, and then ultrasonically cleaned (15 minutes each with acetone and isopropanol) and dried with nitrogen.

[0061] Step 2: Fabrication of ITO planar gratings ITO thin films were deposited on glass substrates using magnetron sputtering. Process parameters: Target material was... : (90:10 wt%), substrate temperature 200℃, argon flow rate 30 sccm, oxygen flow rate 1 sccm, sputtering power 150 W, deposition time 12 minutes, to obtain an ITO grating with a thickness of 120 nm.

[0062] Step 3: Gate dielectric deposition Atomic layer deposition (ALD) was used with trimethylaluminum and water as precursors, at a deposition temperature of 150°C, and for 250 cycles, to obtain a layer with a thickness of 25 nm. film.

[0063] Step 4: Preparation of the perovskite absorber layer A thickness of 1.2 mm was selected. The single crystal was subjected to double-sided chemical mechanical polishing to a surface roughness of <0.5 nm, and then dried in a nitrogen atmosphere at 80°C for 6 hours.

[0064] Step 5: Self-assembly layer processing After polishing The wafer was immersed in a 0.01 M n-octanethiol / ethanol solution, left to stand in a nitrogen glove box for 24 hours, then rinsed with ethanol and dried at 80°C.

[0065] Step 6: Bottom Electrode Fabrication An ITO bottom electrode was fabricated on the left side of the self-assembled layer using a photolithographic lift-off process. First, photoresist was spin-coated, exposed, and developed. Then, ITO (150 nm thick) was sputtered. Finally, the electrode pattern was lifted off and annealed at 180°C for 1 hour.

[0066] Step 7: Preparation of collecting electrodes A 100 nm gold electrode was deposited on the right side of the self-assembled layer using electron beam evaporation at an evaporation rate of 0.4 Å / s.

[0067] In some embodiments, based on metal mesh The fabrication process of the detector includes the following steps: Step 1: Substrate Preparation An alumina ceramic substrate with a thickness of 1.0 mm was selected and the surface was polished to Ra < 10 nm.

[0068] Step 2: Preparation of chromium mesh A 150 nm chromium film was deposited by electron beam evaporation, and then formed into a periodic square hole grid with an aperture of 80 μm and a duty cycle of 50% by photolithography and wet etching.

[0069] Step 3: Gate dielectric deposition Atomic layer deposition was employed, with TDMAH and Using a precursor, a deposition temperature of 250°C was achieved, followed by 300 cycles to obtain a thickness of 30 nm. film.

[0070] Step 4: Preparation of the perovskite absorber layer Select a thickness of 0.8 mm. The single crystals, after polishing and cleaning, were treated in a vacuum oven at 100°C for 4 hours.

[0071] Step 5: Self-assembly layer processing Ammonium iodide / isopropanol solution (concentration 5 mg / mL) was spin-coated onto the perovskite surface at 2000 rpm for 30 seconds, followed by annealing at 100°C for 10 minutes.

[0072] Step 6: Fabrication of bottom electrode and collecting electrode The bottom electrode is sputtered ITO (200 nm thick), and the collection electrode is evaporated platinum (80 nm thick), both patterned by photolithography.

[0073] In this embodiment, gate modulation makes the equipotential lines and electric field lines near the collection end more conducive to charge collection, suppresses edge leakage and charge sharing, shortens the effective drift path, improves pulse shaping, weakens the injection channel and surface state participation through gate clamping, reduces dark current and its 1 / f and GR noise components, and reduces baseline drift caused by interface traps and ion migration in conjunction with the self-assembled layer.

[0074] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0075] In the description of this application, "first feature" and "second feature" may include one or more of the features.

[0076] In the description of this application, "multiple" means two or more.

[0077] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

[0078] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0079] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for fabricating a three-electrode perovskite X-ray detector, characterized in that, include Provide substrate; A gate is fabricated on the substrate, the gate comprising a planar gate, a mesh gate, and a two-dimensional gate; A gate dielectric is fabricated on the gate, the gate dielectric comprising: , , Polyimide; A perovskite absorber layer is prepared on the gate dielectric, wherein the perovskite absorber layer is... thin film or film; A self-assembled layer is prepared on the perovskite absorber layer, the self-assembled layer comprising alkathiol, halide, organic ammonium salt, and NiOx; A bottom electrode is fabricated on the left side of the self-assembled layer; A collection electrode is prepared on the right side of the self-assembled layer.

2. The method for fabricating a three-electrode perovskite X-ray detector as described in claim 1, characterized in that, The gate fabrication includes planar gate fabrication, mesh gate fabrication, and two-dimensional gate fabrication. The planar gate fabrication is performed by sputtering ITO to obtain an ITO thin film with a thickness of 50-150 nm.

3. The method for fabricating a three-electrode perovskite X-ray detector as described in claim 2, characterized in that, The fabrication of the grid includes: A metal thin film is obtained by deposition of metal using a deposition method. The metal thin film is then patterned by photolithography and etching processes to obtain a metal layer with periodic openings as a grid. The size of the openings is 10–200 μm and the duty cycle of the openings is 30%–80%.

4. The method for fabricating a three-electrode perovskite X-ray detector as described in claim 3, characterized in that, The fabrication of the two-dimensional gate includes: Graphene films were deposited using chemical vapor deposition and then patterned to obtain patterned graphene films used as two-dimensional gratings.

5. The method for fabricating a three-electrode perovskite X-ray detector as described in claim 4, characterized in that, The thickness of the gate dielectric is 20-200 mm.

6. The method for fabricating a three-electrode perovskite X-ray detector as described in any one of claims 1-5, characterized in that, The preparation of the perovskite absorber layer includes: Select a thickness of 0.5–2.0 mm. or Single crystals are subjected to double-sided CMP polishing and low-temperature drying to obtain... thin film or film.

7. The method for fabricating a three-electrode perovskite X-ray detector as described in claim 6, characterized in that, The fabrication of the bottom electrode includes: ITO thin films are obtained by sputtering or vapor deposition. The ITO thin films are then patterned by photolithography and annealed at 150–200°C to obtain the bottom electrode.

8. The method for fabricating a three-electrode perovskite X-ray detector as described in claim 7, characterized in that, The collecting electrode is prepared by vapor deposition and is an Au thin film or a Pt thin film.

9. A three-electrode perovskite X-ray detector, characterized in that, The three-electrode perovskite X-ray detector includes a substrate, a gate, a gate dielectric, a perovskite absorber layer, a self-assembled layer, a bottom electrode, and a collection electrode.

10. The three-electrode perovskite X-ray detector as described in claim 9, characterized in that, The workflow of the three-electrode perovskite X-ray detector includes: A high voltage bias is applied between the bottom electrode and the collector electrode, and a low voltage is applied between the gate and the bottom electrode or the collector electrode. The gate electric field is coupled to the neighborhood of the collector end through the gate dielectric to change the local carrier density and effective mobility, forming an adjustable equivalent transconductance and realizing device-level built-in gain.