Semiconductor structure and process for producing the same
By using two processes to form through-silicon vias (TSVs) in a semiconductor structure, the problems of large critical size and narrow polishing window of TSVs are solved, resulting in smaller TSV size and larger wiring space, and expanding the polishing window.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MATERIALS INDUSTRY INNOVATION CENTER CO LTD
- Filing Date
- 2024-11-25
- Publication Date
- 2026-05-29
AI Technical Summary
In the prior art, when the depth of through silicon vias is greater than 50 μm, the critical dimension needs to be greater than 3.5 μm due to the limited filling capacity, and the distance between the through silicon via and the device needs to be greater than 4 μm, which restricts the subsequent metal wiring and makes the chemical mechanical polishing process window narrow.
The process employs two steps: first, a first via is etched from the front side of the substrate to form a first via, and then a second via is etched from the back side. The first and second vias are connected to form a through-silicon via (TSV), which is filled with the same conductive material. After each filling, chemical mechanical polishing is performed to remove excess material.
It reduces the critical size of through-silicon vias (TSVs), increases the distance between TSVs and devices, expands the process window for back-end metal wiring, and widens the process window for chemical mechanical polishing (CMP).
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Figure CN122121646A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication process. Background Technology
[0002] The formation process of a logic product includes the following steps:
[0003] like Figure 1 As shown, a contact hole structure 11 is formed in the substrate, which is a substrate that has already undergone the front-end process. Figure 1 In this context, "Cell" refers to a device formed through front-end manufacturing processes.
[0004] like Figure 2 As shown, a through-silicon via (TSV) is formed using a photolithography process, and the TSV is filled to form a TSV structure 12; and,
[0005] like Figures 3-5 As shown, the first back-side metal redistribution (RDL) process, the first wafer bonding process, the BVR (backside via reveal) process, the second back-side metal redistribution process, and the second wafer bonding process are executed sequentially to achieve stacking.
[0006] When the depth of a through-silicon via (TSV) exceeds 50 μm, the critical dimension (CD) of the TSV typically needs to be greater than 3.5 μm due to limitations in fill capacity, and the keep-out zone (KOZ) between the TSV and the device typically needs to be greater than 4 μm, occupying a large area and thus restricting subsequent metal wiring. Furthermore, after filling the TSV, a chemical mechanical polishing (CMP) process is required, which suffers from a narrow polishing process window. Summary of the Invention
[0007] The purpose of this invention is to provide a semiconductor structure and its fabrication process to solve one or more problems in the prior art.
[0008] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure fabrication process, comprising:
[0009] A substrate is provided, and a first interlayer dielectric layer is formed on the front side of the substrate;
[0010] The first interlayer dielectric layer is etched to form a contact hole, and the contact hole is filled with a first conductive material;
[0011] The first interlayer dielectric layer and the substrate are etched to form a first via, and the first conductive material is filled into the first via.
[0012] A first back-end metal redistribution layer is formed on the surface of the first interlayer dielectric layer;
[0013] A second interlayer dielectric layer is formed on the back side of the substrate;
[0014] The second interlayer dielectric layer and the substrate are etched to form a second via, and a second conductive material is filled into the second via. The first via and the second via are connected to form a through-silicon via (TSV).
[0015] A second back-end metal redistribution layer is formed on the surface of the second interlayer dielectric layer.
[0016] Optionally, in the fabrication process of the semiconductor structure, the first conductive material includes tungsten, and the second conductive material includes copper.
[0017] Optionally, in the fabrication process of the semiconductor structure, the critical size of the first via is less than or equal to 3.5 μm, and the depth of the first via is less than 50 μm.
[0018] Optionally, in the fabrication process of the semiconductor structure, the depth of the first via is less than 10 μm.
[0019] Optionally, in the semiconductor structure fabrication process, the depth of the second via is adjusted according to the depth of the first via, so that the sum of the depths of the first via and the second via is greater than 50 μm.
[0020] Optionally, in the fabrication process of the semiconductor structure, the second via and the first via are formed using the same photomask.
[0021] Optionally, in the semiconductor structure fabrication process, after filling the first through-hole with the first conductive material, the fabrication process further includes:
[0022] A chemical mechanical polishing process is performed on the surface of the first interlayer dielectric layer.
[0023] Optionally, in the semiconductor structure fabrication process, after forming a first back-end metal redistribution layer on the surface of the first interlayer dielectric layer, the fabrication process further includes: performing a first wafer bonding process on the surface of the first back-end metal redistribution layer.
[0024] Optionally, in the semiconductor structure fabrication process, after forming a second back-end metal redistribution layer on the surface of the second interlayer dielectric layer, the fabrication process further includes performing a second wafer bonding process on the surface of the second back-end metal redistribution layer.
[0025] The present invention also provides a semiconductor structure formed by the fabrication process described in any of the preceding claims.
[0026] In summary, the semiconductor structure and its fabrication process provided by this invention include: providing a substrate and forming a first interlayer dielectric layer on the front side of the substrate; etching the first interlayer dielectric layer to form a contact hole and filling the contact hole with a first conductive material; etching the interlayer dielectric layer and the substrate to form a first via and filling the first via with the first conductive material; forming a first back-end metal redistribution layer on the surface of the first interlayer dielectric layer; forming a second interlayer dielectric layer on the back side of the substrate; etching the second interlayer dielectric layer and the substrate to form a second via and filling the second via with a second conductive material, wherein the first via and the second via together constitute a through-silicon via (TSV); and forming a second back-end metal redistribution layer on the surface of the second interlayer dielectric layer. Using the fabrication process provided by this invention, the critical size and depth adjustment range of the TSV are large, which can solve the problems of large critical size and narrow TSV process window. Additionally, it can also solve the problem of a narrow polishing process window. Attached Figure Description
[0027] Figures 1-5 This is a schematic diagram of the device structure corresponding to each step in the formation of an existing logic product;
[0028] Figure 6 A flowchart of the semiconductor structure fabrication process provided in the embodiments of the present invention;
[0029] Figures 7-12 for Figure 6 Schematic diagrams of the device structures corresponding to each step in the process;
[0030] The labels in the accompanying drawings are explained as follows:
[0031] 11-Contact hole structure; 12-Through silicon via structure;
[0032] 21-Substrate; 22-First interlayer dielectric layer; 23-Contact hole structure; 241-First through-hole structure; 242-Second through-hole structure; 25-First back-end metal redistribution layer; 26-Second interlayer dielectric layer; 27-Second back-end metal redistribution layer. Detailed Implementation
[0033] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different proportions are sometimes used in different drawings to show different emphases. It should be understood that relative terms such as "above," "below," "top," "bottom," and "upper" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element will now be below that element. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate logical or sequential relationships between the various components, elements, steps, etc.
[0034] Please see Figure 6 This invention provides a semiconductor structure fabrication process, comprising the following steps:
[0035] S1, providing a substrate, and forming a first interlayer dielectric layer on the front side of the substrate;
[0036] S2, the first interlayer dielectric layer is etched to form a contact hole, and the contact hole is filled with a first conductive material;
[0037] S3, the interlayer dielectric layer and the substrate are etched to form a first via, and the first conductive material is filled into the first via;
[0038] S4, a first rear-end metal redistribution layer is formed on the surface of the first interlayer dielectric layer;
[0039] S5, a second interlayer dielectric layer is formed on the back side of the substrate;
[0040] S6, the second interlayer dielectric layer and the substrate are etched to form a second via, and the via is filled with a second conductive material. The first via and the second via are connected to form a through-silicon via.
[0041] S7, a second downstream metal redistribution layer is formed on the surface of the second interlayer dielectric layer.
[0042] The fabrication process provided in this embodiment of the invention involves two processes: a front-side process and a back-side process. First, the front side of the substrate is etched to form a first via, and then the back side is etched to form a second via. The first and second vias are interconnected to form a through-silicon via (TSV). Compared to directly forming TSVs, the depth of the first and second vias is reduced, thus reducing their critical dimensions. This solves the problem of large critical dimensions and narrow process windows for TSV fabrication. The reduced critical dimensions increase the distance (KOZ) between the TSV and other devices within the substrate, thereby increasing the process window for subsequent metal wiring. Furthermore, the conductive material filling the first via is the same as that filling the contact holes, widening the polishing process window of the chemical mechanical polishing (CMP) process after filling the first via with conductive material.
[0043] The following combination Figures 7-12 The preparation process provided by the present invention will be further described.
[0044] First, perform step S1, please refer to [link / reference]. Figure 7 A substrate 21 is provided, and a first interlayer dielectric layer 22 is formed on the front side of the substrate 21.
[0045] The substrate 21 may be a substrate that has completed the front-end process, that is, the substrate 21 includes devices formed by the front-end process. For example, an active region and a drain region are formed in the substrate 21 by ion implantation, a gate is formed on the surface of the substrate 21, and the source region and the drain region are formed on both sides of the gate. Figure 7 The device is referred to as "Cell" in Chinese, and the distance between the through-silicon via and the device is usually greater than 4 μm.
[0046] The substrate 21 can be made of any suitable substrate material known to those skilled in the art. For example, the substrate 21 can be made of silicon, which will not be elaborated here.
[0047] The first interlayer dielectric layer 22 can be made of any suitable insulating material known to those skilled in the art, such as Figure 7 As illustrated in this embodiment, the first interlayer dielectric layer 22 adopts an ONO multilayer structure, that is, the first interlayer dielectric layer 22 includes a silicon oxide layer, a silicon nitride layer and a silicon oxide layer stacked sequentially.
[0048] Next, proceed to step S2. Please see [link / reference] for further instructions. Figure 7 The first interlayer dielectric layer 22 is etched to form a contact hole (CT), and the contact hole is filled with a first conductive material to form a contact hole structure 23. Figure 7The illustration shows an example with two contact holes, but it should be understood that the number of contact holes does not constitute a limitation of this application. When the substrate 21 is formed with the logic device as described above, the gate, source region, and drain region are electrically connected to the subsequent metal layer through different contact hole structures 23.
[0049] The contact hole is formed using a photolithography process well known to those skilled in the art, which generally includes: forming a patterned hard mask layer that defines the location of the contact hole, and then etching the substrate 21 using the patterned hard mask layer as a mask to form the contact hole, the contact hole being formed above the device fabricated using the front-end process.
[0050] When the first conductive material is filled into the contact hole, the first conductive material is also deposited on the surface of the first interlayer dielectric layer 22. Therefore, after the first conductive material is filled into the contact hole, the preparation process provided in this embodiment of the invention further includes the step of performing a chemical mechanical polishing process to remove the first conductive material from the surface of the first interlayer dielectric layer 22.
[0051] Then, proceed to step S3, please refer to [link / reference]. Figure 8 The first interlayer dielectric layer 22 and the substrate 21 are etched to form a first via (TSV1), and the first conductive material is filled into the first via to form a first via structure 241. It can be seen that the conductive material filled in the first via and the contact hole is the same. Since the conductive material filled in the contact hole generally includes tungsten, the conductive material filled in the first via also includes tungsten; that is, the first conductive material includes tungsten.
[0052] Both the first through hole and the second through hole (described below) are formed using photolithography, a process well-known to those skilled in the art. The formation process is similar to that of the contact hole described above, and will not be repeated here.
[0053] Optionally, before filling the first through-hole with conductive material, the preparation process provided in this embodiment of the invention further includes a step of depositing an interlayer buffer layer on the sidewall and bottom wall of the first through-hole. Further optionally, the interlayer buffer layer includes a titanium layer and a titanium nitride layer, wherein the titanium layer is used as an adhesion layer and the titanium nitride layer is used as a barrier layer.
[0054] Similarly, when the first conductive material is filled into the first through hole, the first conductive material will also be deposited on the surface of the first interlayer dielectric layer 22. Therefore, after the first conductive material is filled into the first through hole, the preparation process provided in this embodiment of the invention further includes a chemical mechanical polishing step to remove the first conductive material from the surface of the first interlayer dielectric layer 22 again.
[0055] In the prior art, the contact hole and the first through hole are filled with different conductive materials, resulting in a narrow polishing window during the chemical mechanical polishing process. In this embodiment, the contact hole and the first through hole are filled with the same conductive material, thus widening the polishing window during the chemical mechanical polishing process.
[0056] Next, proceed to step S4, see [link to relevant documentation]. Figure 9 A first rear metal redistribution layer 25 is formed on the surface of the first interlayer dielectric layer 22.
[0057] In this step, the first rear metal redistribution layer 25 includes a dielectric layer and a metal layer formed within the dielectric layer. The contact hole structure 23 and the first through hole structure 241 are electrically connected to different metal layers in the first rear metal redistribution layer 25.
[0058] Next, proceed to step S5, please refer to [link / reference]. Figure 11 A second interlayer dielectric layer 26 is formed on the back side of the substrate 21; and step S6 is performed to etch the second interlayer dielectric layer 26 and the substrate 21 to form a second through-hole (TSV2), and fill the second through-hole with a second conductive material to form a second through-hole structure 242, wherein the first through-hole and the second through-hole are connected to form a silicon through-hole.
[0059] The second through-hole structure 242 and the first through-hole structure 241 are electrically connected. To ensure the conductivity of the silicon through-hole structure, preferably, the second conductive material filling the second through-hole includes the copper material commonly used to fill silicon through-holes.
[0060] The second interlayer dielectric layer 26 can be made of any suitable dielectric material known to those skilled in the art. As an example, in this embodiment, the material of the second interlayer dielectric layer 26 is silicon oxide.
[0061] Combining steps S3 and S6, it can be seen that the fabrication process provided in this embodiment completes the through-silicon via (TSV) through two processes: a front-side process and a back-side process. Compared to directly forming TSVs, the critical dimensions and depths of the first and second TSVs have a larger adjustment range. Therefore, the depths of both the first and second TSVs can be less than 50 μm. Since the depth is less than 50 μm, their respective critical dimensions can also be designed to be smaller. Because the material filled in the first TSV is mainly tungsten or copper, and the material filled in the second TSV is mainly copper or copper, considering the filling process window and conductivity, it is preferable to design the depth of the first TSV to be less than 10 μm, for example, 6 μm. Furthermore, the critical dimension of the first TSV can be designed according to requirements. Since its depth is less than 50 μm, its critical dimension can be designed to be less than or equal to 3.5 μm, for example, 1 μm. Therefore, the fabrication process provided in this embodiment can solve the problems of large critical dimensions and narrow TSV fabrication process windows.
[0062] In this embodiment, optionally, the second through-hole and the first through-hole are formed using the same photomask; that is, the second through-hole and the first through-hole are designed to have the same critical dimensions. This can save on the number of photomasks and achieve cost savings. In other embodiments, the second through-hole may also have a different critical dimension than the first through-hole. The critical dimension and depth of the second through-hole can be adjusted according to requirements. In particular, the depth of the second through-hole is adjusted according to the depth of the first through-hole, ensuring that the sum of the depths of the first and second through-holes is greater than 50 μm.
[0063] Alternatively, before filling the second through-hole with conductive material, the preparation process provided in this embodiment of the invention further includes a step of depositing an interlayer buffer layer on the sidewall and bottom wall of the second through-hole. The interlayer buffer layer may also include a titanium layer and a titanium nitride layer, wherein the titanium layer is used as an adhesion layer and the titanium nitride layer is used as a barrier layer.
[0064] Similarly, when the second conductive material is filled into the second through hole, the second conductive material will also be deposited on the surface of the second interlayer dielectric layer 26. Therefore, after the second conductive material is filled into the second through hole, the preparation process provided in this embodiment of the invention further includes a chemical mechanical polishing step to remove the second conductive material from the surface of the second interlayer dielectric layer 26.
[0065] It is understood that the number of the first through holes and the number of the second through holes are equal, such as... Figures 8-12 As shown in the example, the two first through holes and the two second through holes correspond one-to-one to form two through silicon vias. After filling the two through silicon vias with conductive material, the resulting through silicon via structures are used as signal lines and power lines, respectively.
[0066] Please see Figure 10 After performing step S4 and before performing step S5, the process may further include performing a first wafer bonding process on the surface of the first back-end metal redistribution layer 25. That is, bonding the structure formed by the above steps to other wafers. Wafer bonding processes are well known to those skilled in the art and will not be described in detail here.
[0067] Finally, proceed to step S6, please refer to [link / reference]. Figure 12 A second downstream metal redistribution layer 27 is formed on the surface of the second interlayer dielectric layer 26.
[0068] In this step, the second downstream metal redistribution layer 27 includes a dielectric layer and a metal layer formed within the dielectric layer, and the second via structure 242 is electrically connected to the metal layer within the second downstream metal redistribution layer 27.
[0069] Optional, please continue to see Figure 12 After performing step S6, the fabrication process provided in this embodiment of the invention further includes performing a second wafer bonding process on the surface of the second back-end metal redistribution layer 27. That is, the structure formed by the above steps is bonded to other wafers. Wafer bonding processes are well known to those skilled in the art and will not be described in detail here.
[0070] This invention also provides a semiconductor structure formed by the fabrication process described in this embodiment.
[0071] In summary, the semiconductor structure and its fabrication process provided by the embodiments of the present invention include: providing a substrate and forming a first interlayer dielectric layer on the front side of the substrate; etching the first interlayer dielectric layer to form a contact hole and filling the contact hole with a first conductive material; etching the interlayer dielectric layer and the substrate to form a first via and filling the first via with the first conductive material; forming a first back-end metal redistribution layer on the surface of the first interlayer dielectric layer; forming a second interlayer dielectric layer on the back side of the substrate; etching the second interlayer dielectric layer and the substrate to form a second via and filling the second via with a second conductive material, wherein the first via and the second via together constitute a through-silicon via (TSV); and forming a second back-end metal redistribution layer on the surface of the second interlayer dielectric layer. The semiconductor structure and its fabrication process provided by the embodiments of the present invention have the following advantages compared with the prior art:
[0072] (1) The front side adopts a small TSV1, which occupies a smaller area, allowing the distance (KOZ) between the through silicon via and the device to be increased, thereby increasing the process window for the subsequent metal wiring.
[0073] (2) TSV1 and CT use the same metal filler material, thus the process window is increased when grinding them simultaneously;
[0074] (3) The key dimensions and depth of TSV1 and TSV2 have a large adjustable range. The CD and depth of the front TSV1 can be adjusted according to the design and process capability requirements. Correspondingly, the CD and depth of the back TSV2 can also be adjusted to meet the product specifications while minimizing the resistance.
[0075] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments with equivalent changes, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.
Claims
1. A process for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a first interlayer dielectric layer is formed on the front side of the substrate; The first interlayer dielectric layer is etched to form a contact hole, and the contact hole is filled with a first conductive material; The first interlayer dielectric layer and the substrate are etched to form a first via, and the first conductive material is filled into the first via. A first back-end metal redistribution layer is formed on the surface of the first interlayer dielectric layer; A second interlayer dielectric layer is formed on the back side of the substrate; The second interlayer dielectric layer and the substrate are etched to form a second via, and a second conductive material is filled into the second via. The first via and the second via are connected to form a through-silicon via (TSV). A second back-end metal redistribution layer is formed on the surface of the second interlayer dielectric layer.
2. The semiconductor structure fabrication process as described in claim 1, characterized in that, The first conductive material includes tungsten, and the second conductive material includes copper.
3. The semiconductor structure fabrication process as described in claim 1, characterized in that, The critical dimension of the first through hole is less than or equal to 3.5 μm, and the depth of the first through hole is less than 50 μm.
4. The semiconductor structure fabrication process as described in claim 3, characterized in that, The depth of the first through hole is less than 10 μm.
5. The semiconductor structure fabrication process as described in claim 3, characterized in that, The depth of the second through hole is adjusted according to the depth of the first through hole so that the sum of the depths of the first through hole and the second through hole is greater than 50 μm.
6. The fabrication process of the semiconductor structure as described in claim 1, characterized in that, The second through hole and the first through hole are formed using the same photomask.
7. The semiconductor structure fabrication process according to claim 1, characterized in that, After filling the first through-hole with the first conductive material, the preparation process further includes: A chemical mechanical polishing process is performed on the surface of the first interlayer dielectric layer.
8. The fabrication process of the semiconductor structure as described in claim 1, characterized in that, After forming a first back-end metal redistribution layer on the surface of the first interlayer dielectric layer, the fabrication process further includes performing a first wafer bonding process on the surface of the first back-end metal redistribution layer.
9. The fabrication process of the semiconductor structure as described in claim 1, characterized in that, After forming a second back-end metal redistribution layer on the surface of the second interlayer dielectric layer, the fabrication process further includes performing a second wafer bonding process on the surface of the second back-end metal redistribution layer.
10. A semiconductor structure, characterized in that, The semiconductor structure is formed by the fabrication process described in any one of claims 1 to 9.