A substrate integration method applied to a power module

Abstract

The application relates to the technical field of semiconductor device packaging, in particular to a substrate integration method applied to a power module, which comprises the following steps: step 1, substrate surface pretreatment, providing a ceramic substrate, cleaning and activating the surface of the ceramic substrate to obtain a ceramic substrate with an active surface; step 2, functional gradient layer deposition; step 3, conductive layer patterning; step 4, power device mounting, mounting a power device on the substrate with the conductive layer pattern, adopting a soldering mode to connect the electrode of the power device and the corresponding area of the conductive layer pattern by using solder, and obtaining a substrate with the mounted power device; and step 5, bonding and packaging, carrying out bonding and packaging treatment on the substrate with the mounted power device, and adopting a wire bonding mode for the bonding treatment. Through accurate control of various process parameters, the final power module has excellent thermal stability, electrical performance and long-term working reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device packaging technology, and in particular to a substrate integration method for power modules. Background Technology

[0002] Power modules are core components of power electronic systems, widely used in new energy power generation, electric vehicles, and industrial frequency converters. The substrate integration method of power modules directly affects their heat dissipation performance, electrical insulation reliability, and long-term service life. Existing technologies commonly employ substrate integration methods including direct copper substrate bonding and active metal brazing. The direct copper substrate bonding method involves directly bonding copper foil to a ceramic substrate through high-temperature oxidation treatment to form circuit and insulating layers. However, this method suffers from a mismatch in thermal expansion coefficients. The thermal expansion coefficients of copper and ceramic materials differ significantly. During power module operation, frequent thermal cycling generates substantial thermal stress within the substrate, leading to cracks or delamination between the copper and ceramic layers, reducing the substrate's mechanical strength and thermal conductivity. Furthermore, the direct copper substrate bonding method is prone to generating voids and defects during high-temperature bonding. These defects further exacerbate electric field concentration and increase thermal resistance, impacting the electrical insulation and heat dissipation efficiency of the power module.

[0003] The active metal brazing substrate method uses solder to bond a copper layer to a ceramic substrate. While this alleviates thermal stress to some extent, the solder layer itself has low thermal conductivity and is prone to oxidation and creep at high temperatures, leading to an increase in the substrate's thermal resistance and a decrease in heat dissipation performance over time. Furthermore, the manufacturing process of the active metal brazing substrate method is complex, requiring precise control of the solder composition and bonding temperature; otherwise, incomplete bonding or solder overflow can occur, affecting the accuracy and reliability of the circuit pattern. In high-power-density applications, such as silicon carbide power modules, existing substrate integration methods face even more pronounced thermal management and reliability issues due to higher operating temperatures and faster switching frequencies. Existing methods lack effective stress buffering mechanisms and defect control measures, making it difficult to meet the requirements of high-reliability power modules.

[0004] In summary, existing substrate integration methods have significant shortcomings in terms of thermal stress management, heat dissipation efficiency, and manufacturing reliability. Therefore, there is an urgent need for a new substrate integration method that can effectively alleviate stress problems caused by mismatched coefficients of thermal expansion, improve the thermal conductivity and mechanical reliability of the substrate, and simultaneously simplify the manufacturing process and reduce the defect rate. Summary of the Invention

[0005] To achieve the above objectives, the present invention provides a substrate integration method for power modules, the method comprising the following steps: Step 1: Substrate surface pretreatment. A ceramic substrate is provided, and the surface of the ceramic substrate is cleaned and activated to obtain a ceramic substrate with an active surface. Step 2: Functional graded layer deposition. A functional graded layer is deposited on a ceramic substrate with an active surface. The functional graded layer is composed of metallic and ceramic materials. The composition of the functional graded layer gradually changes from the ceramic substrate side to the outside. In the functional graded layer on the ceramic substrate side, the volume fraction of ceramic material is high and the volume fraction of metallic material is low. In the functional graded layer on the outside, the volume fraction of metallic material is high and the volume fraction of ceramic material is low. The functional graded layer is deposited by magnetron sputtering. By controlling the power of the sputtering target and the deposition time, the compositional gradient and thickness of the functional graded layer are adjusted to obtain a ceramic substrate with a functional graded layer. Step 3: Conductive layer patterning. A conductive layer pattern is formed on a ceramic substrate with a functional gradient layer. The conductive layer material is copper. The conductive layer patterning adopts photolithography and electroplating. A patterned mask is formed by spin-coating photoresist, exposure, and development. Copper material is deposited in the opening area of ​​the patterned mask by electroplating to form a conductive layer pattern, thus obtaining a substrate with a conductive layer pattern. Step 4: Power device mounting. Power devices are mounted on a substrate with a conductive layer pattern. The power devices are mounted by soldering. Solder is used to connect the electrodes of the power devices to the corresponding areas of the conductive layer pattern to obtain a substrate with the power devices mounted. Step 5: Bonding and encapsulation. The substrate with the power devices mounted is bonded and encapsulated. The bonding process uses wire bonding, which uses gold or aluminum wires to connect the other electrodes of the power devices to the external terminals. The encapsulation process uses transfer molding, which uses epoxy resin molding compound to cover the substrate and the power devices to form a protective layer, thus obtaining a complete power module.

[0006] Preferably, in step 1, the cleaning process employs ultrasonic cleaning, using organic solvents to remove contaminants and particles from the surface of the ceramic substrate. The frequency of ultrasonic cleaning is determined based on the size of the ceramic substrate and the degree of surface contamination, and the ultrasonic cleaning time ensures that the surface of the ceramic substrate reaches a preset cleanliness standard. The activation process employs plasma treatment, introducing a mixture of inert and active gases into a vacuum environment. By adjusting the plasma power and treatment time, active groups are formed on the surface of the ceramic substrate. The plasma power and treatment time are determined based on the surface energy requirements of the ceramic substrate material.

[0007] Preferably, in step 2, the thickness of the functionally graded layer is determined based on thermal simulation analysis. The thermal simulation analysis uses finite element software, inputting the operating temperature range and thermal cycle number of the power module, and outputting the minimum and maximum thicknesses of the functionally graded layer. The actual thickness of the functionally graded layer is selected between the minimum and maximum thicknesses. The gradual change in the composition of the functionally graded layer is achieved by controlling the power ratio of multiple sputtering targets, including pure metal targets and pure ceramic targets. By linearly changing the power ratio of the pure metal targets and pure ceramic targets, the volume fraction of metal material in the functionally graded layer is continuously increased from the ceramic substrate side to the outside.

[0008] Preferably, in step 2, the working gas for the magnetron sputtering method is argon, the pressure of the working gas is adjusted based on the compactness requirements of the functionally graded layer, and the flow rate of the working gas is controlled based on the deposition rate requirements; during the magnetron sputtering process, the substrate temperature is controlled within a preset temperature range, which is determined based on the residual stress requirements of the functionally graded layer, and the sputtering parameters are adjusted in real time by monitoring the surface morphology and composition distribution of the functionally graded layer.

[0009] Preferably, in step 3, the thickness of the conductive layer is determined based on electrical simulation. The electrical simulation inputs the rated current and allowable voltage drop of the power module and outputs the minimum thickness of the conductive layer. The actual thickness of the conductive layer is not less than the minimum thickness. During the electroplating process, the thickness and uniformity of the conductive layer are controlled by monitoring the electroplating current density and electroplating time. The electroplating current density is selected based on the crystal quality requirements of the conductive layer, and the electroplating time is calculated based on the target thickness of the conductive layer.

[0010] Preferably, in step 3, the photolithography and electroplating method includes seed layer deposition before electroplating. The seed layer material is titanium or chromium. The seed layer deposition adopts physical vapor deposition. The thickness of the seed layer is determined based on the adhesion requirements of the conductive layer. The mask pattern used in the exposure process is based on the circuit layout design of the power module. The exposure energy and focal length are adjusted based on the sensitivity of the photoresist.

[0011] Preferably, in step 4, during the brazing process, the integrity and uniformity of the solder layer are ensured by controlling the brazing temperature curve and applying pressure. The brazing temperature curve is determined based on the melting point of the solder, and the brazing temperature is not lower than the melting point of the solder and does not exceed the maximum withstand temperature of the power device. The magnitude of the applied pressure is determined based on the flow characteristics of the solder, and the direction of the applied pressure is perpendicular to the substrate surface.

[0012] Preferably, in step 5, the bonding parameters in the wire bonding method include bonding pressure, ultrasonic power, and bonding time, and the bonding parameters are determined based on the surface characteristics of the wire material and the bonding area; in the transfer molding method, the molding temperature is determined based on the glass transition temperature of the molding compound, and the molding temperature is not lower than the glass transition temperature of the molding compound, and the molding pressure is adjusted based on the viscosity characteristics of the molding compound.

[0013] Preferably, step 5 is followed by step 6: reliability testing, which involves thermal cycling testing and electrical performance testing of the complete power module. The temperature range of the thermal cycling test is determined based on the application environment of the power module, and the number of thermal cycles is set based on the design life requirements of the power module. The electrical performance test includes insulation withstand voltage testing and conduction resistance testing. The test results are used to verify the reliability of the power module.

[0014] Preferably, in step 2, after the functionally graded layer is deposited, an annealing treatment is performed. The annealing temperature is determined based on the crystallization state of the functionally graded layer, the annealing time is set based on the stress release requirements of the functionally graded layer, and the annealing atmosphere is a vacuum or inert gas protective atmosphere. After the annealing treatment, the surface of the functionally graded layer is smoothed using a chemical mechanical polishing method. The composition of the polishing fluid is selected based on the material composition of the functionally graded layer, and the polishing pressure and time are controlled based on the surface roughness requirements of the functionally graded layer.

[0015] The beneficial effects of this invention are: 1. This invention involves depositing a functionally graded layer on a ceramic substrate. The composition of the functionally graded layer gradually transitions from the ceramic substrate side to the outside, and the ratio of metal materials to ceramic materials is adjusted according to actual needs. This effectively mitigates the difference in thermal expansion coefficients between ceramic and metal materials, reduces cracking or delamination caused by thermal stress, and significantly improves the mechanical strength and thermal conductivity of the substrate.

[0016] 2. By employing a functionally graded layer (FJT) design, the composition of the FJT gradually transitions with positional changes, thereby optimizing the thermal conductivity of the substrate. Precise control of the magnetron sputtering method and gas flow rate allows for optimal configuration of the FJT's thickness and composition. The substrate's thermal conductivity is significantly improved, thus enhancing heat dissipation efficiency.

[0017] 3. The substrate integration method of the present invention achieves a more precise and controllable manufacturing process by optimizing processes such as magnetron sputtering, photolithography, and brazing. The patterning of the conductive layer employs a combination of photolithography and electroplating, using seed layer deposition to improve adhesion, thereby ensuring the accuracy and reliability of the circuit pattern. Furthermore, during the brazing process, by controlling the temperature profile and applying pressure, the uniformity and integrity of the solder layer are ensured, avoiding defects caused by temperature inhomogeneity.

[0018] 4. This invention ensures the uniformity and integrity of the brazing filler metal layer by precisely controlling the brazing temperature and pressure during the brazing process, thereby avoiding the problem of thermal resistance increasing over time. This invention effectively solves the problems of brazing filler metal oxidation and creep in active metal brazing methods, reduces the decline in heat dissipation performance caused by increased thermal resistance during long-term operation, and helps to improve the long-term service life of power modules.

[0019] 5. This invention ensures the reliability of the substrate integration method in high power density applications. By optimizing the design and manufacturing process of the functional gradient layer, the stability and reliability of the power module under complex operating conditions are improved. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of the steps of the method of the present invention; Figure 2 This is a flowchart illustrating the steps of photolithography and electroplating in the method of the present invention. Detailed Implementation

[0022] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. It should also be noted that, to make the embodiments more comprehensive, the following embodiments are the best and preferred embodiments, and those skilled in the art can use other alternative methods to implement some well-known technologies; moreover, the accompanying drawings are only for more specific description of the embodiments and are not intended to specifically limit the present invention.

[0023] Please see Figures 1-2 This invention provides a substrate integration method for power modules. In step 1, a ceramic substrate suitable for the power module is first selected, and its surface is cleaned and activated. The purpose of this process is to remove contaminants from the surface of the ceramic substrate, increase its surface chemical activity, and enable it to better bond with the subsequently deposited functionally graded layers. The cleaned and activated ceramic substrate has a high surface energy, which helps the functionally graded layers to adhere well and ensures the smooth progress of subsequent processes.

[0024] In step 2, a functionally graded layer (FJG) is deposited on the cleaned and activated ceramic substrate surface using magnetron sputtering. The FJG is composed of both metallic and ceramic materials, with its composition gradually varying along the substrate thickness. On the substrate side, the volume fraction of ceramic material is higher than that of metallic material; conversely, on the outer side, the volume fraction of metallic material is higher than that of ceramic material. This FJG design effectively mitigates the mismatch in thermal expansion coefficients between the ceramic substrate and the metallic material, reducing cracking or delamination caused by thermal stress and improving the substrate's thermal conductivity and mechanical reliability. By precisely controlling the sputtering target power and deposition time, the compositional gradient and thickness of the FJG can be adjusted, thereby optimizing thermal management performance.

[0025] In step 3, photolithography and electroplating techniques are used to form a copper conductive layer pattern on the functionally graded layer. First, photoresist is spin-coated, and a mask is formed through exposure and development steps. Then, copper material is deposited at the openings of the mask through an electroplating process to form the circuit pattern. This process can precisely control the shape and position of the copper conductive layer, ensuring high precision and stability of the circuit and avoiding the problems of unclear patterns or errors that may occur with traditional soldering methods.

[0026] In step 4, after the conductive layer is patterned, the power devices are then mounted onto the substrate. The power devices are connected to the conductive layer via brazing. The selection and control of the solder are crucial, ensuring excellent electrical and mechanical connection performance at high temperatures. Brazing effectively reduces problems such as poor contact or excessive contact resistance that may occur in traditional soldering methods, ensuring stable operation of the power module in high-power-density applications.

[0027] In step 5, the substrate on which the power devices are mounted is bonded and encapsulated. Bonding uses gold or aluminum wire to connect the other electrodes of the power devices to external terminals. Encapsulation employs a transfer molding process, covering the substrate and power devices with epoxy molding compound to form a protective layer. This encapsulation layer not only provides excellent electrical insulation but also effectively improves the environmental resistance of the power module, preventing interference and damage to the internal circuitry from the external environment.

[0028] The functionally graded layer design effectively solves the problem of thermal expansion coefficient mismatch between ceramic substrate and metal material, reduces structural damage caused by thermal stress, improves the thermal conductivity of the substrate, and significantly enhances heat dissipation performance.

[0029] In one possible implementation, the ceramic substrate is first cleaned using ultrasonic cleaning. Ultrasonic cleaning is a highly efficient surface cleaning technology that disperses and removes contaminants, oil, and microparticles from the surface of the ceramic substrate through high-frequency ultrasonic vibrations. To ensure cleaning effectiveness, the organic solvent used needs to have strong dissolving power and be able to effectively remove grease, dust, and other organic contaminants.

[0030] The frequency of ultrasonic cleaning is adjusted according to the size and surface contamination level of the ceramic substrate. Larger substrates may require lower frequencies, while smaller or less contaminated substrates use higher frequency ultrasonic waves. In this embodiment of the invention, the frequency range is 20-50 kHz. The ultrasonic cleaning time also needs to be precisely controlled to ensure that the ceramic substrate surface reaches the required cleanliness standard, thereby guaranteeing good adhesion between the functionally graded layer and the substrate in subsequent processes.

[0031] After cleaning, the ceramic substrate needs to undergo activation treatment, typically using plasma treatment. Plasma treatment is carried out in a vacuum environment, during which a mixture of inert and active gases (such as oxygen, argon, etc.) is introduced. By exciting the gases, plasma is generated, forming active groups on the surface of the ceramic substrate.

[0032] The power and time of plasma treatment are adjusted according to the surface energy requirements of the ceramic substrate material. Specifically, higher plasma power or longer treatment time can more effectively stimulate surface activity, generating more active groups, thereby increasing the chemical reactivity and adhesion of the ceramic substrate surface. This process significantly improves the hydrophilicity or oleophilicity of the ceramic substrate surface, providing a better substrate for the subsequent deposition of functionally graded layers.

[0033] This invention employs a process combining ultrasonic cleaning and plasma treatment during the cleaning and activation process. This not only improves the cleanliness and activity of the ceramic substrate surface but also enhances the adhesion of subsequent materials, laying a solid foundation for the long-term stability and high-efficiency performance of the power module.

[0034] In one possible implementation, the thickness of the functionally graded layer is determined through thermal simulation analysis. First, the operating environment of the power module is simulated using finite element method (FEM) software, inputting the module's operating temperature range and the number of thermal cycles. These parameters help simulate the thermal stress and temperature changes experienced by the power module during actual operation. Based on these input conditions, the software performs thermal analysis to calculate the minimum and maximum thickness of the functionally graded layer.

[0035] Minimum thickness is typically based on the minimum thermal protection standards required by the power module, ensuring that the functional graded layer can function effectively in the most demanding operating environments; while maximum thickness takes into account the limits of thermal stress, ensuring that the material will not be damaged due to excessive expansion or contraction under long-term thermal cycling.

[0036] The actual thickness of the functional graded layer is selected between the minimum and maximum thickness, and is usually optimized according to the specific application and performance requirements of the power module, so as to take into account both thermal management and the difficulty of material processing.

[0037] The compositional variation of the functionally graded layer is achieved by controlling the power ratio of multiple sputtering targets during the sputtering process. This process utilizes multiple sputtering targets, including pure metal targets and pure ceramic targets. The power ratio of the sputtering targets determines the relative proportions of metal and ceramic materials in the functionally graded layer.

[0038] Specifically, by linearly adjusting the power ratio of the metal target to the ceramic target, the volume fraction of metal material in the functionally graded layer can gradually increase from the ceramic substrate side to the outer side. Ceramic materials typically have high thermal stability, while metal materials exhibit better thermal conductivity and mechanical strength. Through this compositional gradient design, a good bond between the ceramic substrate and the functionally graded layer can be maintained while improving the thermal conductivity and strength of the outer layer, ensuring the thermal stability and reliability of the power module under long-term operation.

[0039] The thickness of the functionally graded layer is determined based on thermal simulation analysis, and the gradual change in material composition is achieved by controlling the power ratio of the sputtering target. This optimizes the thermal performance and structural stability of the power module, while improving its long-term operational reliability. This integrated approach not only enhances the thermal management of the power module but also provides an effective solution for power module design in various application environments.

[0040] In one possible implementation, argon is selected as the working gas during magnetron sputtering. As an inert gas, argon possesses good stability, effectively preventing material reactions or chemical contamination and ensuring the purity of the deposition process. The pressure of the argon gas plays a crucial role in the magnetron sputtering process, primarily by controlling the compactness of the functionally graded layer through pressure regulation.

[0041] Higher working gas pressure helps improve film density because gas molecules collide more frequently at higher pressures, promoting sputtered particle aggregation and tighter interlayer bonding. However, excessively high gas pressure can also reduce the deposition rate of sputtered particles, so adjustments need to be made based on specific requirements.

[0042] The flow rate of the working gas also needs to be precisely controlled according to the required deposition rate. The deposition rate typically affects the thickness and quality of the functionally graded layer; therefore, the argon flow rate needs to be adjusted based on the target deposition rate. Appropriate flow rate control not only ensures uniform material deposition but also guarantees stability during the deposition process, avoiding film inhomogeneity or defects caused by excessive or insufficient flow.

[0043] During magnetron sputtering, the substrate temperature must be strictly controlled within a preset temperature range. This temperature range is selected based on the residual stress requirements of the functionally graded layer. Substrate temperature directly affects the microstructure and properties of the thin film; excessively high temperatures may lead to excessive thermal stress within the film, causing cracks or peeling; excessively low temperatures may affect the film's adhesion or density. To ensure that the functionally graded layer possesses suitable mechanical and thermal properties during deposition, the substrate temperature must be monitored in real time to ensure it remains within a reasonable temperature range.

[0044] To ensure the quality of functionally graded layers (FJTs), it is essential to monitor the surface morphology and composition distribution during the deposition process. By using surface morphology analysis instruments and composition detection techniques (such as X-ray diffraction and scanning electron microscopy), the surface quality and material distribution of the FJT can be obtained in real time. Based on the monitoring results, magnetron sputtering parameters, such as sputtering power, gas flow rate, and substrate temperature, can be adjusted to ensure that the performance indicators of the FJT meet design requirements.

[0045] In one possible implementation, the thickness of the conductive layer is determined through electrical simulation. First, the electrical simulation inputs two key parameters: the rated current of the power module and the allowable voltage drop. The rated current is the maximum current that the power module needs to pass through the conductive layer during normal operation, while the allowable voltage drop is the maximum voltage loss that the power module can tolerate during operation. Through electrical simulation calculations, the minimum thickness of the conductive layer required under specific conditions can be determined, ensuring stable current flow without causing excessive voltage drops that could affect the performance of the power module. The actual thickness of the conductive layer will not be less than the minimum thickness, thus ensuring that the module will not experience excessive resistance and voltage drop due to an excessively thin conductive layer during actual operation.

[0046] During the electroplating process, the thickness and uniformity of the conductive layer are controlled by monitoring the electroplating current density and electroplating time.

[0047] It is understandable that current density is a crucial factor affecting the crystal quality of the conductive layer. By selecting an appropriate electroplating current density, the crystal structure of the conductive layer can be controlled, ensuring that the grains are fine and uniform, thereby improving the conductivity and mechanical strength of the conductive layer. A conductive layer with high crystal quality can effectively reduce resistance and voltage loss, thus improving the operating efficiency and reliability of the power module.

[0048] The electroplating time is calculated based on the target thickness of the conductive layer. The thickness of the conductive layer is directly proportional to the electroplating time; therefore, by calculating the electroplating time appropriately, it can be ensured that the layer thickness reaches the predetermined value during the electroplating process. If the electroplating time is too long, the conductive layer may be too thick, increasing costs and potentially affecting subsequent processes; if the electroplating time is too short, the conductive layer may not meet the minimum thickness requirement, affecting module performance.

[0049] By determining the conductive layer thickness through electrical simulation and precisely controlling the current density and plating time during the electroplating process, the performance of the conductive layer can be effectively optimized, ensuring the stability of the power module's electrical and mechanical properties. This method not only improves the overall performance of the power module but also provides reliable technical support for subsequent integration and applications.

[0050] In one possible implementation, a seed layer needs to be deposited before electroplating. The seed layer provides a good adhesion base for subsequent electroplating, and its material can be titanium or chromium. Titanium and chromium, as seed layer materials, have excellent adhesion, which can ensure the stability and reliability of the conductive layer on the substrate.

[0051] The deposition process employs physical vapor deposition (PVD), a method that uniformly deposits a seed layer on the substrate surface. The PVD process involves heating and evaporating titanium or chromium, then physically depositing it onto the substrate surface to form a thin seed layer. The thickness of the seed layer is determined based on the adhesion requirements of the conductive layer. If higher adhesion is required, the seed layer thickness needs to be increased to ensure a firm bond between the conductive layer and the substrate surface. The thickness of the seed layer is crucial for subsequent electroplating processes, as it directly affects the quality, stability, and electrical properties of the conductive layer.

[0052] Photolithography transfers circuit design patterns onto a substrate. The mask pattern used in the exposure process is customized based on the circuit layout design of the power module. This process determines the precise position and shape of the circuit pattern on the substrate; therefore, the mask design must strictly adhere to the circuit layout requirements to ensure the correctness and functionality of the circuit.

[0053] During the exposure process, exposure energy and focal length are two key parameters that need to be adjusted according to the sensitivity of the photoresist used. The sensitivity of the photoresist determines its responsiveness to exposed light; therefore, adjusting the exposure energy and focal length helps achieve optimal exposure results. Higher exposure energy helps improve pattern resolution and edge sharpness, but may also lead to overexposure of the photoresist; conversely, lower exposure energy may cause pattern blurring, affecting circuit accuracy. Adjusting the focal length affects the focusing accuracy of the exposure, ensuring that the photoresist surface is uniformly exposed and avoiding pattern distortion.

[0054] By depositing a seed layer and precisely adjusting photolithography exposure, the precision of the power module circuitry, the adhesion of the conductive layer, and the overall process stability can be effectively improved. This method provides a strong guarantee for the high performance and high reliability of the power module.

[0055] In one possible implementation, temperature is a critical factor affecting the melting and solidification of the solder during brazing. The brazing temperature profile needs to be precisely controlled based on the melting point of the solder. The melting point of the solder is the lowest temperature at which it begins to melt and flow; therefore, the brazing temperature must not be lower than this melting point to ensure that the solder melts smoothly and fills the joint. During brazing, excessively low temperatures will cause the solder to fail to melt completely, affecting the bonding effect; while excessively high temperatures may damage power devices or degrade the performance of other heat-sensitive components. Therefore, the brazing temperature needs to be strictly controlled between the solder melting point and the maximum withstand temperature of the power device. The maximum withstand temperature refers to the highest temperature that the power module or power device can withstand; exceeding this temperature range may cause component failure. Through reasonable temperature control, it is possible to ensure that the solder flows sufficiently and evenly covers the welding area, while avoiding damage to the components from excessively high temperatures.

[0056] Applying pressure is another crucial factor affecting brazing quality. The flow characteristics of the brazing filler metal determine the appropriate pressure. During brazing, the applied pressure promotes filler metal flow and fills voids in the joint, thereby improving the quality and strength of the bond. The flow characteristics of the brazing filler metal typically depend on its viscosity and melting point. Lower viscosity filler metals flow at lower pressures, while higher viscosity filler metals may require higher pressures to ensure proper flow and filling. Therefore, the applied pressure needs to be adjusted according to the flow characteristics of the filler metal to ensure complete coverage of the joint surface, forming a uniform and robust weld layer.

[0057] The pressure applied should be perpendicular to the substrate surface. This is because vertical pressure ensures even distribution of the solder layer, guaranteeing a uniform joint surface. Horizontal or inclined pressure may result in uneven solder distribution, affecting solder quality.

[0058] By precisely controlling the brazing temperature profile and applying pressure, the integrity, uniformity, and welding quality of the solder layer can be effectively guaranteed. Appropriate temperature control protects heat-sensitive components in the power module, preventing damage caused by excessively high or low temperatures; while the applied pressure promotes the fluidity and uniform distribution of the solder, thereby improving the bonding quality.

[0059] In one possible implementation, wire bonding is the process of electrically connecting leads in a power module to a substrate, typically using ultrasonic bonding or thermo-press bonding. Key parameters for wire bonding include bonding pressure, ultrasonic power, and bonding time, which must be adjusted according to the lead material and the surface characteristics of the bonding area.

[0060] The bonding pressure determines the tightness of the contact between the lead and the substrate surface. Appropriate pressure helps ensure good electrical contact and mechanical connection. Insufficient pressure may lead to a weak connection, affecting electrical performance; excessive pressure may damage the lead or the substrate surface. Therefore, the bonding pressure needs to be precisely adjusted according to the material properties.

[0061] Ultrasonic power affects the transmission of ultrasonic waves in the bonding area. During bonding, ultrasonic waves generate localized heating and vibration, thereby promoting the metal connection between the lead and the substrate. Adjusting the ultrasonic power helps control the vibration intensity, ensuring uniform heating of the bonding area and avoiding poor soldering caused by overheating or undercooling.

[0062] Bonding time determines the duration of ultrasonic or thermo-pressing action, directly affecting the heating and pressure effects in the bonding area. Too short a time may result in insufficient bonding, while too long a time may cause damage to the lead or substrate surface. Therefore, bonding time needs to be optimized based on the specific lead and substrate materials to ensure optimal bonding quality.

[0063] Transfer molding is used to uniformly coat the surface of a power module with molding compound, forming a protective layer. Molding temperature and molding pressure are key parameters for controlling this process.

[0064] The molding temperature needs to be determined based on the glass transition temperature of the molding compound. The glass transition temperature is the temperature range within which a material transitions from a hard and brittle state to a more flexible state. Therefore, the molding temperature must not be lower than this temperature to ensure that the molding compound can flow effectively and uniformly cover the substrate surface. If the molding temperature is lower than the glass transition temperature, the molding compound may not be able to flow, resulting in poor molding performance and affecting the formation of the protective layer.

[0065] The molding pressure is adjusted according to the viscosity characteristics of the molding compound. Molding compounds with lower viscosity can flow uniformly at lower pressures, while those with higher viscosity require higher pressures to propel the flow. Appropriate molding pressure ensures that the molding compound fills the mold evenly, forming a smooth, bubble-free protective layer and avoiding defects or uneven areas.

[0066] By precisely controlling the pressure, ultrasonic power, and bonding time during wire bonding, as well as the temperature and pressure during transfer molding, the connection stability, material flowability, and surface protection of the power module can be ensured. Optimizing these technical steps not only improves the reliability and durability of the power module but also enhances the stability and efficiency of the manufacturing process, thus guaranteeing the high performance and long-term use of the power module.

[0067] In one possible implementation, thermal cycling testing simulates the temperature changes of the power module under actual operating conditions by exposing it to different temperature environments. This process is crucial for testing the stability of the power module under the thermal expansion and contraction effects caused by temperature changes.

[0068] The temperature range is determined based on the specific application environment of the power module. For example, different environments have different temperature requirements in fields such as automotive electronics, industrial control, or aerospace. Therefore, the temperature range during testing needs to cover the extreme temperature range that may occur in actual applications, thereby ensuring that the module can still operate stably under extreme conditions.

[0069] The number of thermal cycles is set according to the design life requirements of the power module. These design life requirements typically take into account factors such as long-term use of the module, changes in the operating environment, and potential temperature fluctuations. By setting the number of thermal cycles, the thermal fatigue and aging of the power module during long-term use are tested to ensure that the module will not fail due to thermal stress within its intended lifespan.

[0070] Electrical performance testing aims to verify whether the electrical performance of the power module meets the design standards, to ensure its normal operation and avoid electrical failures during use.

[0071] Insulation withstand voltage testing is used to check the insulation performance of power modules, ensuring they maintain good electrical insulation even under high-voltage conditions. Insulation failure can lead to electrical leakage, short circuits, or even serious electrical faults. Therefore, the test applies a certain voltage to check whether the module can withstand the high voltage without breakdown or leakage.

[0072] On-resistance testing verifies whether the resistance value of the internal conductive path of the power module meets design requirements. Excessive on-resistance may cause the power module to generate excessive heat during operation, affecting its efficiency and even causing damage. By measuring the module's conductivity, the test ensures stable and low-impedance electrical connections, guaranteeing normal operation.

[0073] Reliability testing, as a verification method, ensures the stability and safety of power modules under different operating environments and long-term use through thermal cycling and electrical performance testing. In particular, thermal cycling and electrical performance testing effectively evaluate the module's resistance to temperature changes, electrical insulation, and conductivity stability, preventing failures caused by environmental changes or electrical problems. Such testing not only guarantees the high reliability of power modules but also improves product lifespan and safety, providing customers with more reliable products.

[0074] In one possible implementation, annealing is used to improve the material properties of the functionally graded layer. The main purpose is to optimize its crystallization state and reduce stress by controlling temperature and time, thereby improving its mechanical properties and thermal stability.

[0075] Annealing temperature setting: The annealing temperature is typically determined based on the crystallization state of the functionally graded layer. The crystallization process of different materials is temperature-sensitive; therefore, adjusting the annealing temperature helps the crystal structure of the functionally graded layer reach its optimal state. Too low an annealing temperature may result in an incomplete crystal structure, while too high a temperature may induce lattice defects or material degradation. Therefore, the temperature selection should be precisely controlled according to the material's characteristics.

[0076] Annealing time setting: The length of the annealing time directly affects the stress release effect of the material and is usually set based on the stress release requirements of the functional graded layer. The stress release process requires a certain amount of time for the internal stress to gradually distribute evenly. Therefore, the annealing time must be sufficient to ensure that the stress of the entire functional graded layer is effectively released. An annealing time that is too short may not be able to fully release the stress, resulting in excessive stress remaining inside the material, which will affect the long-term stability of the power module.

[0077] Annealing Atmosphere: The atmosphere used during annealing is crucial. Vacuum or inert gas protective atmospheres are widely used in annealing processes. A vacuum environment prevents oxidation reactions, thus maintaining the purity and properties of the material. Inert gases (such as nitrogen or argon) serve a similar purpose, preventing unwanted reactions between the material and oxygen or other elements in the air at high temperatures, ensuring material quality.

[0078] Planarization is used to improve the surface quality of functionally graded layers, ensuring that subsequent processing (such as encapsulation or conductivity) can proceed smoothly.

[0079] The surface smoothing process employs chemical mechanical polishing (CMP), which combines chemical reactions and mechanical friction to remove surface irregularities and achieve a smooth, flat finish. CMP is suitable for most functionally graded layer materials, especially for applications requiring high surface smoothness, such as power module integration.

[0080] The composition of the polishing slurry needs to be selected based on the material composition of the functional graded layer. Different materials may require different chemical agents during the polishing process. The function of the polishing slurry is to remove tiny particles from the surface through a chemical reaction and achieve a polishing effect through mechanical friction. If the formula of the polishing slurry is unsuitable, it may affect the polishing quality or even damage the functional graded layer.

[0081] Polishing pressure and time directly affect surface roughness. Excessive polishing pressure may cause surface damage or unevenness, while insufficient polishing time may leave uneven areas on the surface. Therefore, polishing pressure and time need to be precisely controlled to ensure that the surface achieves the required smoothness and roughness.

[0082] By precisely controlling the annealing temperature, time, and atmosphere, the crystalline structure of the material can be optimized and stress can be effectively released; while the surface leveling process removes surface inhomogeneities through CMP, improves surface quality, and ensures the performance and stability of the module.

[0083] The following detailed description is provided through examples: This embodiment focuses on silicon carbide power modules in electric vehicle drive systems, which have a wide operating temperature range (-40℃ to 175℃) and a high switching frequency (up to 100kHz), placing extremely high demands on the thermal management, electrical insulation, and mechanical reliability of the substrate.

[0084] Step 1: Substrate surface pretreatment: A ceramic substrate is provided, made of aluminum nitride (AlN) with high thermal conductivity (approximately 170 W / m·K), suitable for high power density applications. The surface of the ceramic substrate is cleaned and activated to obtain a ceramic substrate with an active surface.

[0085] Cleaning Process: Ultrasonic cleaning was employed using an organic solvent (such as a 1:1 volume ratio of acetone and isopropanol) to remove contaminants and particles from the ceramic substrate surface. The ultrasonic cleaning frequency was determined based on the size of the ceramic substrate and the degree of surface contamination: the substrate size was 50mm × 50mm × 0.5mm, and the surface contamination level was determined using an optical microscope, showing a contaminant coverage area of ​​less than 5%; therefore, an ultrasonic frequency of 40kHz was selected. The ultrasonic cleaning time ensured that the ceramic substrate surface reached a preset cleanliness standard: the cleanliness standard was defined as a surface contact angle of less than 10°, verified by measuring the water contact angle of the cleaned surface; the ultrasonic cleaning time was set to 15 minutes. After cleaning, the surface was dried with nitrogen gas.

[0086] Activation Treatment: A plasma treatment method was used, in which a mixture of inert gas (argon) and active gas (oxygen) was introduced into a vacuum environment (vacuum degree ≤ 1×10⁻³ Pa), with a volume ratio of argon to oxygen of 4:1. By adjusting the plasma power and treatment time, active groups (such as hydroxyl and carboxyl groups) were formed on the surface of the ceramic substrate. The plasma power and treatment time were determined based on the surface energy requirements of the ceramic substrate material: the target surface energy of aluminum nitride ceramic was ≥60 mN / m. By testing the surface energy under different powers and treatment times, a plasma power of 300 W and a treatment time of 5 minutes were determined. After treatment, the surface energy of the ceramic substrate increased to 65 mN / m, which is beneficial for the subsequent deposition of functionally graded layers.

[0087] Step 2: Functional graded layer deposition: A functionally graded layer (FGR) is deposited on the ceramic substrate with an active surface output in step 1. The FGR consists of a metallic material (copper) and a ceramic material (aluminum nitride), and the composition of the FGR gradually changes from the ceramic substrate side to the outside: the volume fraction of aluminum nitride in the FGR on the ceramic substrate side is 80%, and the volume fraction of copper is 20%; the volume fraction of aluminum nitride in the external FGR is 20%, and the volume fraction of copper is 80%. The FGR is deposited using magnetron sputtering.

[0088] The thickness of the functionally graded layer (FJT) was determined based on thermal simulation analysis. The thermal simulation analysis used finite element software (such as ANSYS), inputting the power module's operating temperature range (-40℃ to 175℃) and the number of thermal cycles (set to 10,000 cycles according to the electric vehicle lifespan requirements). The simulation model included the ceramic substrate, the FJT, and the conductive layer. By simulating the thermal stress distribution, the minimum (10 μm) and maximum (50 μm) thickness of the FJT were output. The actual thickness of the FJT was chosen to be 30 μm to balance thermal stress and thermal conductivity.

[0089] Composition gradient control: This is achieved by controlling the power ratio of multiple sputtering targets. The sputtering targets include pure copper targets (purity ≥99.99%) and pure aluminum nitride targets (purity ≥99.9%). By linearly changing the power ratio of the pure copper and pure aluminum nitride targets, a continuous increase in the copper volume fraction in the functionally graded layer is achieved from the ceramic substrate side to the outside. Specifically, starting from the ceramic substrate side, the power ratio linearly changes from 100% power for the pure aluminum nitride target (0% power for the pure copper target) to 20% power for the pure aluminum nitride target (80% power for the pure copper target), with a deposition time of 120 minutes.

[0090] Magnetron sputtering parameters: The working gas is argon, and its pressure is adjusted based on the compactness requirements of the functionally graded layer (FJT): the porosity requirement is ≤1%, and the working gas pressure was determined to be 0.5 Pa using scanning electron microscopy. The working gas flow rate is controlled based on the deposition rate requirement: the target deposition rate is 0.25 μm / min, therefore the argon flow rate is set to 50 sccm. During magnetron sputtering, the substrate temperature is controlled within a preset temperature range (200℃ to 300℃), which is determined based on the residual stress requirements of the FJT: the residual stress target is ≤100 MPa, and the substrate temperature was determined to be 250℃ using X-ray diffraction. Sputtering parameters, such as power and gas flow rate, are adjusted in real time by monitoring the surface morphology (using atomic force microscopy) and compositional distribution (using energy dispersive spectroscopy) of the FJT.

[0091] Annealing and leveling: After deposition, annealing is performed. The annealing temperature is determined based on the crystallization state of the functionally graded layer: the target crystallization state is uniform grain size (0.5 μm to 1 μm), and the annealing temperature is determined to be 500℃ by transmission electron microscopy. The annealing time is set based on the stress release requirements of the functionally graded layer: the stress release target is a 50% reduction in residual stress, and the annealing time is set to 60 minutes. The annealing atmosphere is vacuum (vacuum degree ≤ 1 × 10⁻⁻⁻⁴). 4 After annealing, the surface of the functionally graded layer (FJT) is planarized using chemical mechanical polishing (CMP). The polishing slurry composition is selected based on the material composition of the FJT: since the FJT contains copper and aluminum nitride, the polishing slurry is a silica-based slurry (pH 10.5). Polishing pressure and time are controlled based on the surface roughness requirements of the FJT: the target surface roughness Ra ≤ 0.1 μm, the polishing pressure is set at 5 psi, and the polishing time is 10 minutes.

[0092] Step 3: Conductive layer patterning: A conductive layer pattern is formed on the ceramic substrate with a functionally graded layer output in step 2. The conductive layer material is copper (purity ≥ 99.99%). The conductive layer patterning is performed using photolithography and electroplating.

[0093] The thickness of the conductive layer was determined based on electrical simulation. The electrical simulation used finite element software (such as COMSOL), with the input power module's rated current (100A) and allowable voltage drop (≤0.1V), outputting a minimum conductive layer thickness of 100μm. The actual thickness of the conductive layer was set to 120μm to provide a margin.

[0094] Photolithography and electroplating details: First, photoresist (positive photoresist, model AZ-4620) is spin-coated onto the functionally graded layer surface at a spin speed of 3000 rpm to a thickness of 5 μm. Then, a patterned mask is formed through exposure and development. The mask pattern used during exposure is based on the circuit layout design of the power module (including source, gate, and drain regions), and the exposure energy is adjusted based on the photoresist's sensitivity: the photoresist's sensitivity is 200 mJ / cm², therefore the exposure energy is set to 250 mJ / cm². The focus is controlled by an autofocus system to ensure pattern sharpness. Development uses an alkaline developer (e.g., 0.5% NaOH solution) for 60 seconds.

[0095] Seed layer deposition: A seed layer is deposited before electroplating. The seed layer material is titanium (50 nm thick), and a physical vapor deposition method is used. The thickness of the seed layer is determined based on the adhesion requirements of the conductive layer: the adhesion target is ≥10 MPa, which is verified through scratch testing.

[0096] Electroplating Process: Copper material is deposited in the opening areas of a patterned mask using electroplating. The electroplating solution is a copper sulfate-based solution (containing 200 g / L copper sulfate and 50 g / L sulfuric acid). The thickness and uniformity of the conductive layer are controlled by monitoring the electroplating current density and electroplating time. The electroplating current density is selected based on the crystal quality requirements of the conductive layer: the target crystal quality is a grain size ≤ 5 μm, and the current density is determined to be 2 A / dm² by metallographic microscopy. The electroplating time is calculated based on the target thickness of the conductive layer: a thickness of 120 μm and a deposition rate of 10 μm / min, therefore the electroplating time is 12 minutes. After electroplating, excess photoresist and seed layer are removed, and wet etching (hydrofluoric acid-based etching solution) is used.

[0097] Step 4: Power Device Installation Power devices are mounted on the substrate with the conductive layer pattern output in step 3. The power devices are silicon carbide metal-oxide-semiconductor field-effect transistors (SiCMOSFETs, rated voltage 1200V). The power devices are mounted by soldering.

[0098] Brazing Process: A solder filler metal (tin-silver-copper alloy, melting point 217℃) is used to connect the electrodes (source and gate) of the power device to the corresponding areas of the conductive layer pattern. The integrity and uniformity of the solder layer are ensured by controlling the brazing temperature profile and applied pressure. The brazing temperature profile is determined based on the solder melting point: the brazing temperature is not lower than the solder melting point and does not exceed the maximum withstand temperature of the power device (the maximum withstand temperature of SiCMOSFET is 250℃), therefore the peak brazing temperature is set at 240℃. The temperature profile includes a heating phase (rate 3℃ / s), a holding phase (60 seconds), and a cooling phase (rate 2℃ / s). The applied pressure is determined based on the solder flow characteristics: the solder flow target is a coverage area ≥95%, and an applied pressure of 0.1MPa is set through X-ray detection. The direction of the applied pressure is perpendicular to the substrate surface, and a fixture is used to ensure uniformity.

[0099] Step 5: Bonding and Packaging The substrate with power devices mounted on it, output from step 4, is then bonded and packaged.

[0100] Bonding process: Wire bonding is used, employing aluminum wire (300μm in diameter) to connect other electrodes of the power device (such as the source auxiliary terminal) to external terminals (copper terminals). Bonding parameters, including bonding pressure, ultrasonic power, and bonding time, are determined based on the wire material and the surface characteristics of the bonding area: for bonding the aluminum wire to the copper terminal, the bonding pressure is 0.5N, the ultrasonic power is 1.5W, and the bonding time is 100ms. After bonding, a pull test (target value ≥0.5N) is performed to verify reliability.

[0101] Encapsulation Process: Transfer molding is used, employing epoxy molding compound (glass transition temperature ≥150℃) to cover the substrate and power devices, forming a protective layer. The molding temperature is determined based on the glass transition temperature of the molding compound: the molding temperature is not lower than the glass transition temperature of the molding compound, therefore, the molding temperature is set to 160℃. The molding pressure is adjusted based on the viscosity characteristics of the molding compound: the viscosity is 500 cP at 160℃, so the molding pressure is set to 10 MPa. After molding, it is cured at 150℃ for 60 minutes.

[0102] Step 6: Reliability Testing The complete power module undergoes reliability testing, including thermal cycling and electrical performance testing.

[0103] Thermal cycling test: The temperature range is determined based on the application environment of the power module: the operating temperature range of the electric vehicle drive system is -40℃ to 125℃, but during testing, it is extended to -55℃ to 150℃ to accelerate aging. The number of thermal cycles is set based on the design life requirements of the power module: the design life is 10 years, equivalent to 10,000 cycles, and the test is performed for 5,000 cycles (30 minutes per cycle). After the test, substrate delamination and cracks are inspected.

[0104] Electrical performance testing includes insulation withstand voltage testing and continuity resistance testing. The insulation withstand voltage test applies a voltage of 1.5 times the rated voltage (1800V) for 60 seconds, with a leakage current requirement of ≤1μA. The continuity resistance test is performed at the rated current, requiring a resistance of ≤10mΩ. The test results are used to verify the reliability of the power module.

[0105] This method effectively solves the problems of thermal stress, heat dissipation and reliability through functionally graded layer deposition and precise process control, and is suitable for high power density applications.

[0106] This invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of this invention. To provide the public with a thorough understanding of this invention, specific details are described in detail in the following preferred embodiments; however, those skilled in the art will fully understand the invention even without these details. Furthermore, to avoid unnecessary misunderstanding of the essence of this invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0107] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A substrate integration method for power modules, characterized in that, The method includes the following steps: Step 1: Substrate surface pretreatment. A ceramic substrate is provided, and the surface of the ceramic substrate is cleaned and activated to obtain a ceramic substrate with an active surface. Step 2: Functional graded layer deposition. A functional graded layer is deposited on a ceramic substrate with an active surface. The functional graded layer is composed of metallic and ceramic materials. The composition of the functional graded layer gradually changes from the ceramic substrate side to the outside. In the functional graded layer on the ceramic substrate side, the volume fraction of ceramic material is high and the volume fraction of metallic material is low. In the functional graded layer on the outside, the volume fraction of metallic material is high and the volume fraction of ceramic material is low. The functional graded layer is deposited by magnetron sputtering. By controlling the power of the sputtering target and the deposition time, the compositional gradient and thickness of the functional graded layer are adjusted to obtain a ceramic substrate with a functional graded layer. Step 3: Conductive layer patterning. A conductive layer pattern is formed on a ceramic substrate with a functional gradient layer. The conductive layer material is copper. The conductive layer patterning adopts photolithography and electroplating. A patterned mask is formed by spin-coating photoresist, exposure, and development. Copper material is deposited in the opening area of ​​the patterned mask by electroplating to form a conductive layer pattern, thus obtaining a substrate with a conductive layer pattern. Step 4: Power device mounting. Power devices are mounted on a substrate with a conductive layer pattern. The power devices are mounted by soldering. Solder is used to connect the electrodes of the power devices to the corresponding areas of the conductive layer pattern to obtain a substrate with the power devices mounted. Step 5: Bonding and encapsulation. The substrate with the power devices mounted is bonded and encapsulated. The bonding process uses wire bonding, which uses gold or aluminum wires to connect the other electrodes of the power devices to the external terminals. The encapsulation process uses transfer molding, which uses epoxy resin molding compound to cover the substrate and the power devices to form a protective layer, thus obtaining a complete power module.

2. The substrate integration method for a power module according to claim 1, characterized in that, In step 1, the cleaning process adopts ultrasonic cleaning, using organic solvents to remove contaminants and particles from the surface of the ceramic substrate. The frequency of ultrasonic cleaning is determined based on the size of the ceramic substrate and the degree of surface contamination. The ultrasonic cleaning time ensures that the surface of the ceramic substrate reaches the preset cleanliness standard. The activation process employs plasma treatment, in which a mixture of inert and active gases is introduced into a vacuum environment. By adjusting the plasma power and treatment time, active groups are formed on the surface of the ceramic substrate. The plasma power and treatment time are determined based on the surface energy requirements of the ceramic substrate material.

3. The substrate integration method for a power module according to claim 1, characterized in that, In step 2, the thickness of the functional gradient layer is determined based on thermal simulation analysis. The thermal simulation analysis uses finite element software, inputs the operating temperature range and thermal cycle number of the power module, and outputs the minimum and maximum thickness of the functional gradient layer. The actual thickness of the functional gradient layer is selected between the minimum and maximum thickness. The compositional gradient of the functionally graded layer is achieved by controlling the power ratio of multiple sputtering targets, including pure metal targets and pure ceramic targets. By linearly changing the power ratio of the pure metal targets and pure ceramic targets, the volume fraction of metal material in the functionally graded layer is continuously increased from the ceramic substrate side to the outside.

4. The substrate integration method for a power module according to claim 1, characterized in that, In step 2, the working gas for the magnetron sputtering method is argon. The pressure of the working gas is adjusted based on the compactness requirements of the functionally graded layer, and the flow rate of the working gas is controlled based on the deposition rate requirements. During the magnetron sputtering process, the substrate temperature is controlled within a preset temperature range, which is determined based on the residual stress requirements of the functionally graded layer. The sputtering parameters are adjusted in real time by monitoring the surface morphology and composition distribution of the functionally graded layer.

5. The substrate integration method for a power module according to claim 1, characterized in that, In step 3, the thickness of the conductive layer is determined based on electrical simulation. The electrical simulation inputs the rated current and allowable voltage drop of the power module and outputs the minimum thickness of the conductive layer. The actual thickness of the conductive layer is not less than the minimum thickness. During the electroplating process, the thickness and uniformity of the conductive layer are controlled by monitoring the electroplating current density and electroplating time. The electroplating current density is selected based on the crystal quality requirements of the conductive layer, and the electroplating time is calculated based on the target thickness of the conductive layer.

6. The substrate integration method for a power module according to claim 1, characterized in that, In step 3, the photolithography and electroplating methods include: A seed layer is deposited before electroplating. The seed layer material is titanium or chromium. The seed layer is deposited using physical vapor deposition. The thickness of the seed layer is determined based on the adhesion requirements of the conductive layer. The mask pattern used in the exposure process is based on the circuit layout design of the power module, and the exposure energy and focal length are adjusted based on the sensitivity of the photoresist.

7. The substrate integration method for a power module according to claim 1, characterized in that, In step 4, during the brazing process, the integrity and uniformity of the brazing filler layer are ensured by controlling the brazing temperature profile and applying pressure. The brazing temperature profile is determined based on the melting point of the brazing filler, and the brazing temperature is not lower than the melting point of the brazing filler and does not exceed the maximum withstand temperature of the power device. The magnitude of the applied pressure is determined based on the solder flow characteristics, and the direction of the applied pressure is perpendicular to the substrate surface.

8. The substrate integration method for a power module according to claim 1, characterized in that, In step 5, the bonding parameters in the wire bonding method include bonding pressure, ultrasonic power, and bonding time. The bonding parameters are determined based on the wire material and the surface characteristics of the bonding area. In the aforementioned transfer molding method, the molding temperature is determined based on the glass transition temperature of the molding compound, and the molding temperature is not lower than the glass transition temperature of the molding compound. The molding pressure is adjusted based on the viscosity characteristics of the molding compound.

9. A substrate integration method for a power module according to claim 1, characterized in that, Step 5 is followed by step 6: Reliability testing involves thermal cycling and electrical performance testing of the complete power module. The temperature range for thermal cycling is determined based on the application environment of the power module, and the number of thermal cycles is set based on the design life requirements of the power module. Electrical performance testing includes insulation withstand voltage testing and continuity resistance testing. The test results are used to verify the reliability of the power module.

10. A substrate integration method for a power module according to claim 1, characterized in that, In step 2, after the functionally graded layer is deposited, it is annealed. The annealing temperature is determined based on the crystallization state of the functionally graded layer, the annealing time is set based on the stress release requirements of the functionally graded layer, and the annealing atmosphere is a vacuum or inert gas protective atmosphere. After the annealing process, the surface of the functionally graded layer is smoothed using a chemical mechanical polishing method. The composition of the polishing slurry is selected based on the material composition of the functionally graded layer, and the polishing pressure and time are controlled based on the surface roughness requirements of the functionally graded layer.

Images