Pixel circuit and display device

Abstract

A pixel circuit and a display device. The pixel circuit comprises a pixel driving circuit (100), N light emitting elements and N current control circuits; N is an integer greater than 1; a first electrode of a first light emitting element (E1) is electrically connected with the driving current output terminal (OT); a second electrode of an n-th light emitting element (En) and a first electrode of an (n+1)-th light emitting element (En+1) are both electrically connected with an n-th display node (NXn), and the second electrode of the N-th light emitting element (En) is electrically connected with a first voltage terminal (V1); n is a positive integer less than N; and an n-th current control circuit (1n) controls an n-th control current provided to the n-th display node (NXn) under the control of a display control signal. By driving N light emitting elements in series through one pixel driving circuit, the driving transistor and the light emitting control transistor in the pixel driving circuit on the driving current path are shared, and the power consumption is reduced.

Description

Pixel circuit and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit and a display device. BACKGROUND

[0002] The display market is currently booming, and more new display products will emerge in the future as consumers' demand for various display products such as notebook computers, smart phones, televisions, tablets, smart watches and fitness wristbands continues to rise. The power consumption of related pixel circuits is high.

[0003] SUMMARY

[0004] In one aspect, the pixel circuit comprises a pixel driving circuit, N light emitting elements and N current control circuits; N is an integer greater than 1.

[0005] The pixel driving circuit is electrically connected to a display control terminal, configured to generate a driving current and output the driving current through a driving current output terminal under the control of a display control signal provided by the display control terminal.

[0006] The first electrode of the first light emitting element is electrically connected to the driving current output terminal.

[0007] The second electrode of the Nth light emitting element and the first electrode of the N+1th light emitting element are both electrically connected to an Nth display node, and the second electrode of the Nth light emitting element is electrically connected to a first voltage terminal; n is a positive integer less than N.

[0008] The Nth current control circuit is electrically connected to the display control terminal and the Nth display node, respectively, and configured to control the provision of an Nth control current to the Nth display node under the control of the display control signal.

[0009] In at least one embodiment of the present disclosure, the display period of the pixel circuit comprises a light emitting phase.

[0010] The display control terminal is configured to provide a display control signal with gradually decreasing potential during at least part of the light emitting phase, or to provide a display control signal with gradually increasing potential during at least part of the light emitting phase.

[0011] In at least one embodiment of the present disclosure, the light emitting phase comprises a plurality of light emitting time periods.

[0012] The display control terminal is configured to provide a display control signal with gradually decreasing potential during the light emitting time periods; or,

[0013] The display control terminal is configured to provide a display control signal with gradually increasing potential during the light emitting time periods.

[0014] In at least one embodiment of the present disclosure, the nth current control circuit includes an nth display driving circuit and an nth display control circuit;

[0015] The nth display driving circuit is electrically connected with an nth display data voltage terminal and an nth display driving control node respectively, and is configured to control whether to provide an nth control current according to an nth display data voltage provided by the nth display data voltage terminal.

[0016] The nth display control circuit is electrically connected with the nth display driving control node, an nth control data voltage terminal, the display control terminal and the nth display node respectively, and is configured to control the nth display node and the nth display driving control node to be connected or disconnected according to a display control signal and an nth control data voltage provided by the nth control data voltage terminal.

[0017] In at least one embodiment of the present disclosure, the nth control current includes an nth first driving current and / or an nth second driving current.

[0018] The nth display driving circuit includes an nth first display driving circuit and / or an nth second display driving circuit.

[0019] The nth first display driving circuit is electrically connected with an nth display data voltage terminal, an nth display driving control node, an nth display power voltage terminal and a light emitting control terminal respectively, and is configured to control whether to provide an nth first driving current flowing from the nth display power voltage terminal to the nth display driving control node according to an nth display data voltage provided by the nth display data voltage terminal under control of a light emitting control signal provided by the light emitting control terminal.

[0020] The nth second display driving circuit is electrically connected with an nth display data voltage terminal, an nth display driving control node, an nth display low voltage terminal and a light emitting control terminal respectively, and is configured to control whether to provide an nth second driving current flowing from the nth display driving control node to the nth display low voltage terminal according to the nth display data voltage under control of the light emitting control signal.

[0021] In at least one embodiment of the present disclosure, the nth display control circuit includes an nth on-off control circuit, an nth writing circuit and an nth control energy storage circuit.

[0022] The nth on-off control circuit is electrically connected with an nth on-off control node, the nth display node and the nth display driving control node respectively, and is configured to control the nth display node and the nth display driving control node to be connected or disconnected under control of an electric potential of the nth on-off control node.

[0023] The nth write circuit is electrically connected with the nth control reset end, the nth control data voltage end and the nth on-off control node respectively, and is used for writing the nth control data voltage provided by the nth control data voltage end into the nth on-off control node under the control of the nth control reset signal provided by the nth control reset end.

[0024] The nth control energy storage circuit is electrically connected with the display control end and the nth on-off control node respectively, and is used for controlling the potential of the nth on-off control node under the control of the display control signal.

[0025] In at least one embodiment of the present disclosure, the nth display control circuit comprises an nth control circuit and an nth display driving control circuit.

[0026] The nth control circuit is electrically connected with the light emitting control end, the nth intermediate node and the nth display node respectively, and is used for controlling the communication or disconnection between the nth intermediate node and the nth display node under the control of the light emitting control signal provided by the light emitting control end.

[0027] The nth display control circuit comprises an nth on-off control circuit, an nth control energy storage circuit, an nth setting circuit, an nth control compensation circuit, an nth initialization circuit, an nth first voltage providing circuit and an nth second voltage providing circuit.

[0028] The nth on-off control circuit is electrically connected with the nth on-off control node, the nth display driving control node and the nth intermediate node respectively, and is used for controlling the communication or disconnection between the nth display driving control node and the nth intermediate node under the control of the potential of the nth on-off control node.

[0029] The first end of the nth control energy storage circuit is electrically connected with the nth on-off control node, and the second end of the nth control energy storage circuit is electrically connected with the nth write node, and the nth control energy storage circuit is used for storing electric energy.

[0030] The nth setting circuit is electrically connected with the nth control reset end, the nth control initial voltage end, the nth on-off control node and the nth write node respectively, and is used for writing the nth control initial voltage provided by the nth control initial voltage end into the nth on-off control node and the nth write node under the control of the nth control reset signal provided by the nth control reset end.

[0031] The nth control compensation circuit is electrically connected with the nth compensation control end, the nth display driving control node and the nth on-off control node respectively, and is used for controlling the communication or disconnection between the nth display driving control node and the nth on-off control node under the control of the nth compensation control signal provided by the nth compensation control end.

[0032] The nth initialization circuit is electrically connected with the nth write control end, the reference voltage end and the nth intermediate node, for writing the reference voltage provided by the reference voltage end into the nth intermediate node under the control of the nth write control signal provided by the nth write control end;

[0033] The nth first voltage providing circuit is electrically connected with the nth write control end, the nth control data voltage end and the nth write node, for writing the nth control data voltage provided by the nth control data voltage end into the nth write node under the control of the nth write control signal;

[0034] The nth second voltage providing circuit is electrically connected with the light emitting control end, the display control end and the nth write node, for writing the display control signal provided by the display control end into the nth write node under the control of the light emitting control signal provided by the light emitting control end.

[0035] In at least one embodiment of the present disclosure, the nth current control circuit comprises an nth display control circuit;

[0036] The nth display control circuit is electrically connected with the light emitting control end, the nth display node and the nth display driving control node, for controlling the communication or disconnection between the nth display node and the nth display driving control node under the control of the light emitting control signal provided by the light emitting control end;

[0037] The nth display control circuit further comprises an nth first display driving circuit and / or an nth second display driving circuit, and the display control end comprises a first display control end and / or a second display control end; the nth control current comprises an nth first driving current and / or an nth second driving current;

[0038] The nth first display driving circuit is electrically connected with the nth display data voltage end, the nth display driving control node, the nth display power voltage end, the light emitting control end and the first display control end, for controlling whether to provide the nth first driving current flowing from the nth display power voltage end to the nth display driving control node according to the first display control signal provided by the first display control end and the nth display data voltage provided by the nth display data voltage end under the control of the light emitting control signal provided by the light emitting control end;

[0039] The nth second display driving circuit is electrically connected with an nth display data voltage terminal, an nth display driving control node, an nth display low voltage terminal, a light emitting control terminal and a second display control terminal respectively, and is configured to control whether to provide an nth second driving current flowing from the nth display driving control node to the nth display low voltage terminal according to a second display control signal provided by the second display control terminal and the nth display data voltage under control of a light emitting control signal.

[0040] In at least one embodiment of the present disclosure, the display period of the pixel circuit includes a light emitting stage.

[0041] The first display control terminal is configured to provide a first display control signal with gradually decreasing potential during at least part of the time period included in the light emitting stage.

[0042] The second display control terminal is configured to provide a second display control signal with gradually increasing potential during at least part of the time period included in the light emitting stage. In at least one embodiment of the present disclosure, the nth first display driving circuit includes an nth first driving circuit, an nth first light emitting control circuit, an nth first compensation circuit, an nth first reset circuit, an nth first data writing circuit and an nth first energy storage circuit.

[0043] The control terminal of the nth first driving circuit is electrically connected with an nth control node, and the nth first driving circuit is configured to generate an nth first driving current under control of the potential of the nth control node.

[0044] The nth first light emitting control circuit is electrically connected with a light emitting control terminal, an nth display power voltage terminal and a first terminal of the nth first driving circuit respectively, and is configured to control the communication or disconnection between the nth display power voltage terminal and the first terminal of the nth first driving circuit under control of a light emitting control signal provided by the light emitting control terminal.

[0045] The nth first compensation circuit is electrically connected with an nth compensation control terminal, the nth control node and a second terminal of the nth first driving circuit respectively, and is configured to control the communication or disconnection between the nth control node and the second terminal of the nth first driving circuit under control of an nth compensation control signal provided by the nth compensation control terminal.

[0046] The nth first reset circuit is electrically connected with an nth control reset terminal, an nth control initial voltage terminal and the nth control node respectively, and is configured to write an nth control initial voltage provided by the nth control initial voltage terminal into the nth control node under control of an nth control reset signal.

[0047] The nth first data write circuit is electrically connected with the nth write control end, the nth display data voltage end and the first end of the nth first drive circuit respectively, and is used for writing the nth display data voltage provided by the nth display data voltage end into the first end of the nth first drive circuit under the control of the nth write control signal provided by the nth write control end;

[0048] The nth first energy storage circuit is electrically connected with the nth control node, and is used for maintaining the potential of the nth control node.

[0049] In at least one embodiment of the present disclosure, the nth second display drive circuit comprises an nth second drive circuit, an nth second light-emitting control circuit, an nth second compensation circuit, an nth second reset circuit, an nth second data write circuit and an nth second energy storage circuit.

[0050] The control end of the nth second drive circuit is electrically connected with the nth inverted control node, and the nth second drive circuit is used for generating an nth second drive current under the control of the potential of the nth inverted control node.

[0051] The nth second light-emitting control circuit is electrically connected with the light-emitting control end, the nth display low-voltage end and the first end of the nth second drive circuit respectively, and is used for controlling the communication or disconnection between the nth display low-voltage end and the first end of the nth second drive circuit under the control of the light-emitting control signal provided by the light-emitting control end.

[0052] The nth second compensation circuit is electrically connected with the nth inverted compensation control end, the nth inverted control node and the second end of the nth second drive circuit respectively, and is used for controlling the communication or disconnection between the nth inverted control node and the second end of the nth second drive circuit under the control of the nth inverted compensation control signal provided by the nth inverted compensation control end.

[0053] The nth second reset circuit is electrically connected with the nth control reset end, the nth inverted control initial voltage end and the nth inverted control node respectively, and is used for writing the nth inverted control initial voltage provided by the nth inverted control initial voltage end into the nth inverted control node under the control of the nth control reset signal.

[0054] The nth second data write circuit is electrically connected with the nth inverted write control end, the nth display data voltage end and the first end of the nth second drive circuit respectively, and is used for writing the nth display data voltage provided by the nth display data voltage end into the first end of the nth second drive circuit under the control of the nth inverted write control signal provided by the nth inverted write control end.

[0055] The nth second energy storage circuit is electrically connected with the nth opposite control node, and is used for maintaining the electric potential of the nth opposite control node.

[0056] In at least one embodiment of the present disclosure, the nth first display driving circuit comprises an nth first driving circuit, an nth first light emitting control circuit, an nth first compensation circuit, an nth first reset circuit, an nth first energy storage circuit, an nth first data writing circuit and an nth first driving control circuit.

[0057] The control end of the nth first driving circuit is electrically connected with the nth control node, and the nth first driving circuit is used for generating an nth first driving current under the control of the electric potential of the nth control node.

[0058] The nth first light emitting control circuit is electrically connected with a light emitting control end, an nth display power voltage end and the first end of the nth first driving circuit respectively, and is used for controlling the communication or disconnection between the nth display power voltage end and the first end of the nth first driving circuit under the control of a light emitting control signal provided by the light emitting control end.

[0059] The nth first compensation circuit is electrically connected with an nth compensation control end, the nth control node and the second end of the nth first driving circuit respectively, and is used for controlling the communication or disconnection between the nth control node and the second end of the nth first driving circuit under the control of an nth compensation control signal provided by the nth compensation control end.

[0060] The nth first reset circuit is electrically connected with an nth control reset end, an nth control initial voltage end and the nth control node respectively, and is used for writing an nth control initial voltage provided by the nth control initial voltage end into the nth control node under the control of the nth control reset signal.

[0061] The nth first energy storage circuit is electrically connected with the nth control node, and is used for maintaining the electric potential of the nth control node.

[0062] The nth first data writing circuit is electrically connected with an nth writing control end, an nth display data voltage end and the first end of the nth first driving circuit respectively, and is used for writing an nth display data voltage provided by the nth display data voltage end into the first end of the nth first driving circuit under the control of an nth writing control signal provided by the nth writing control end.

[0063] The nth first driving control circuit comprises an nth first driving energy storage circuit, an nth first control driving circuit, an nth third light emitting control circuit, an nth first writing circuit, an nth first control compensation circuit and an nth first setting circuit.

[0064] a first end of the nth first drive storage circuit is electrically connected with the first display control terminal, and a second end of the nth first drive storage circuit is electrically connected with the nth first drive control node, the nth first drive storage circuit being configured to store electric energy;

[0065] a control terminal of the nth first control drive circuit is electrically connected with the nth first drive control node, a first end of the nth first control drive circuit is electrically connected with the nth first drive node, and a second end of the nth first control drive circuit is electrically connected with the nth control node, the nth first control drive circuit being configured to control the nth first drive node and the nth control node to be connected or disconnected under the control of the electric potential of the nth first drive control node;

[0066] the nth third light emitting control circuit is electrically connected with the light emitting control terminal, the nth display power voltage terminal and the nth first drive node respectively, and is configured to control the nth display power voltage terminal and the nth first drive node to be connected or disconnected under the control of a light emitting control signal provided by the light emitting control terminal;

[0067] the nth first write-in circuit is electrically connected with the nth control scanning terminal, the nth control data voltage terminal and the nth first drive node respectively, and is configured to write an nth control data voltage provided by the nth control data voltage terminal into the nth first drive node under the control of an nth control scanning signal provided by the nth control scanning terminal;

[0068] the nth first control compensation circuit is electrically connected with the nth control scanning terminal, the nth first drive control node and the nth control node respectively, and is configured to control the nth first drive control node and the nth control node to be connected or disconnected under the control of the nth control scanning signal;

[0069] the nth first setting circuit is electrically connected with the nth control reset terminal, the nth control initial voltage terminal and the nth first drive control node respectively, and is configured to write an nth control initial voltage provided by the nth control initial voltage terminal into the nth first drive control node under the control of an nth control reset signal provided by the nth control reset terminal.

[0070] In at least one embodiment of the present disclosure, the nth second display drive circuit comprises an nth second drive circuit, an nth second light emitting control circuit, an nth second compensation circuit, an nth second reset circuit, an nth second storage circuit, an nth second data write-in circuit and an nth second drive control circuit.

[0071] The control end of the nth second driving circuit is electrically connected with the nth opposite control node, and the nth second driving circuit is used for generating an nth second driving current under the control of the potential of the nth opposite control node;

[0072] The nth second light emitting control circuit is electrically connected with the light emitting control end, the nth display low voltage end and the first end of the nth second driving circuit respectively, and is used for controlling the communication or disconnection between the nth display low voltage end and the first end of the nth second driving circuit under the control of the light emitting control signal provided by the light emitting control end;

[0073] The nth second compensation circuit is electrically connected with the nth opposite compensation control end, the nth opposite control node and the second end of the nth second driving circuit respectively, and is used for controlling the communication or disconnection between the nth opposite control node and the second end of the nth second driving circuit under the control of the nth opposite compensation control signal provided by the nth opposite compensation control end;

[0074] The nth second reset circuit is electrically connected with the nth control reset end, the nth opposite control initial voltage end and the nth opposite control node respectively, and is used for writing the nth opposite control initial voltage provided by the nth opposite control initial voltage end into the nth opposite control node under the control of the nth control reset signal;

[0075] The nth second energy storage circuit is electrically connected with the nth opposite control node, and is used for maintaining the potential of the nth opposite control node;

[0076] The nth second data writing circuit is electrically connected with the nth opposite writing control end, the nth display data voltage end and the first end of the nth second driving circuit respectively, and is used for writing the nth display data voltage provided by the nth display data voltage end into the first end of the nth second driving circuit under the control of the nth opposite writing control signal provided by the nth opposite writing control end;

[0077] The nth second driving control circuit comprises an nth second driving energy storage circuit, an nth second control driving circuit, an nth fourth light emitting control circuit, an nth second data writing circuit, an nth second control compensation circuit and an nth second setting circuit;

[0078] The first end of the nth second driving energy storage circuit is electrically connected with the second display control end, the second end of the nth second driving energy storage circuit is electrically connected with the nth second driving control node, and the nth second driving energy storage circuit is used for storing electric energy;

[0079] The control end of the nth second control drive circuit is electrically connected with the nth second drive control node, the first end of the nth second control drive circuit is electrically connected with the nth second drive node, the second end of the nth second control drive circuit is electrically connected with the nth inverted control node, and the nth second control drive circuit is used for controlling the communication or disconnection between the nth second drive node and the nth inverted control node under the control of the potential of the nth second drive control node;

[0080] The nth fourth light-emitting control circuit is electrically connected with the light-emitting control end, the nth display low-voltage end and the nth second drive node respectively, and is used for controlling the communication or disconnection between the nth display low-voltage end and the nth second drive node under the control of the light-emitting control signal provided by the light-emitting control end;

[0081] The nth second data write-in circuit is electrically connected with the nth inverted control scanning end, the nth control data voltage end and the nth second drive node respectively, and is used for writing the nth control data voltage provided by the nth control data voltage end into the nth second drive node under the control of the nth inverted control scanning signal provided by the nth inverted control scanning end;

[0082] The nth second control compensation circuit is electrically connected with the nth inverted control scanning end, the nth second drive control node and the nth inverted control node respectively, and is used for controlling the communication or disconnection between the nth second drive control node and the nth inverted control node under the control of the nth inverted control scanning signal;

[0083] The nth second setting circuit is electrically connected with the nth control reset end, the nth inverted control initial voltage end and the nth second drive control node respectively, and is used for writing the nth inverted control initial voltage provided by the nth inverted control initial voltage end into the nth second drive control node under the control of the nth control reset signal provided by the nth control reset end.

[0084] In at least one embodiment of the present disclosure, the pixel drive circuit comprises a drive circuit, a data write-in circuit, a display energy storage circuit, a compensation control circuit, a first reset circuit, a display light-emitting control circuit, a display control circuit and a node control circuit.

[0085] The drive circuit is electrically connected with a drive node, and is used for generating the drive current under the control of the potential of the drive node;

[0086] The data writing circuit is electrically connected with a display scanning end, a data voltage end and a first end of the driving circuit respectively, and is configured to write data voltage provided by the data voltage end into the first end of the driving circuit under control of a display scanning signal provided by the display scanning end;

[0087] The display energy storage circuit is electrically connected with the driving node, and is configured to maintain the potential of the driving node;

[0088] The compensation control circuit is electrically connected with a compensation control end, the driving node and a second end of the driving circuit respectively, and is configured to control the driving node and the second end of the driving circuit to be in communication or disconnected under control of a compensation control signal provided by the compensation control end;

[0089] The first reset circuit is electrically connected with a reset control end, a display initial voltage end and the driving node respectively, and is configured to write display initial voltage provided by the display initial voltage end into the driving node under control of a reset control signal provided by the reset control end;

[0090] The display light emitting control circuit is electrically connected with a light emitting control end, a power voltage end and the first end of the driving circuit respectively, and is configured to control the power voltage end and the first end of the driving circuit to be in communication or disconnected under control of a light emitting control signal provided by the light emitting control end;

[0091] The display control circuit is electrically connected with a display control node, the second end of the driving circuit and the driving current output end respectively, and is configured to control the second end of the driving circuit and the driving current output end to be in communication or disconnected under control of the potential of the display control node;

[0092] The node control circuit is electrically connected with the display control node, the reset control end, a display control data voltage end and the display control end respectively, and is configured to write display control data voltage provided by the display control data voltage end into the display control node under control of the reset control signal, and to control the potential of the display control node according to the display control signal.

[0093] In at least one embodiment of the present disclosure, the pixel driving circuit comprises a driving circuit, a data writing circuit, a display energy storage circuit, a compensation control circuit, a first reset circuit, a first display light emitting control circuit, a second display light emitting control circuit, a display control circuit, a control reset circuit and a node control circuit;

[0094] The driving circuit is electrically connected with a driving node, and is configured to generate the driving current under control of the potential of the driving node;

[0095] The data writing circuit is electrically connected with a display scanning end, a data voltage end and a first end of the driving circuit respectively, and is used for writing data voltage provided by the data voltage end into the first end of the driving circuit under control of a display scanning signal provided by the display scanning end;

[0096] The display energy storage circuit is electrically connected with the driving node, and is used for maintaining the potential of the driving node;

[0097] The compensation control circuit is electrically connected with a compensation control end, the driving node and a second end of the driving circuit respectively, and is used for controlling the driving node and the second end of the driving circuit to be connected or disconnected under control of a compensation control signal provided by the compensation control end;

[0098] The first reset circuit is electrically connected with a reset control end, a display initial voltage end and the driving node respectively, and is used for writing display initial voltage provided by the display initial voltage end into the driving node under control of a reset control signal provided by the reset control end;

[0099] The first display light emitting control circuit is electrically connected with a light emitting control end, a power voltage end and the first end of the driving circuit respectively, and is used for controlling the power voltage end and the first end of the driving circuit to be connected or disconnected under control of a light emitting control signal provided by the light emitting control end;

[0100] The second display light emitting control circuit is electrically connected with a light emitting control end, a second end of the driving circuit and a light emitting control node respectively, and is used for controlling the second end of the driving circuit and the light emitting control node to be connected or disconnected under control of the light emitting control signal;

[0101] The display control circuit is electrically connected with a display control node, the light emitting control node and the driving current output end respectively, and is used for controlling the light emitting control node and the driving current output end to be connected or disconnected under control of the potential of the display control node;

[0102] The control reset circuit is electrically connected with a display scanning end, a reference voltage end and the light emitting control node respectively, and is used for writing reference voltage provided by the reference voltage end into the light emitting control node under control of the display scanning signal;

[0103] The node control circuit is electrically connected with the display control node, a display control data voltage end and the display control end respectively, and is used for controlling the potential of the display control node according to display control data voltage provided by the display control data voltage end and the display control signal.

[0104] In at least one embodiment of the present disclosure, the node control circuit includes a display control storage circuit, a first write control circuit, a second write control circuit, a control set circuit, and a control compensation control circuit.

[0105] A first end of the display control storage circuit is electrically connected to the display control node, and a second end of the display control storage circuit is electrically connected to a display write node.

[0106] The first write control circuit is electrically connected to a display scanning end, a display control data voltage end, and the display write node, respectively, for writing the display control data voltage into the display write node under the control of the display scanning signal.

[0107] The second write control circuit is electrically connected to a light-emitting control end, the display control end, and the display write node, respectively, for writing the display control signal into the display write node under the control of the light-emitting control signal provided by the light-emitting control end.

[0108] The control set circuit is electrically connected to a reset control end, a display initial voltage end, the display control node, and the display write node, respectively, for writing the display initial voltage provided by the display initial voltage end into the display control node and the display write node under the control of the reset control signal provided by the reset control end.

[0109] The control compensation control circuit is electrically connected to a compensation control end, the drive current output end, and the display control node, respectively, for controlling the drive current output end and the display control node to be connected or disconnected under the control of the compensation control signal provided by the compensation control end.

[0110] The pixel circuit in at least one embodiment of the present disclosure further includes a third display light-emitting control circuit.

[0111] The third display light-emitting control circuit is electrically connected to a light-emitting control end, the display control circuit, and the drive current output end, respectively, for controlling the display control circuit and the drive current output end to be connected or disconnected under the control of the light-emitting control signal.

[0112] In at least one embodiment of the present disclosure, the pixel driving circuit includes a driving circuit, a display storage circuit, a data write circuit, a compensation control circuit, a first reset circuit, a first display light-emitting control circuit, a second display light-emitting control circuit, and a driving node control circuit.

[0113] The driving circuit is electrically connected to a driving node for generating the drive current under the control of the potential of the driving node.

[0114] The display energy storage circuit is electrically connected with the driving node, and is used for maintaining the potential of the driving node;

[0115] The data writing circuit is electrically connected with the display scanning end, the data voltage end and the first end of the driving circuit respectively, and is used for writing the data voltage provided by the data voltage end into the first end of the driving circuit under the control of the display scanning signal provided by the display scanning end;

[0116] The compensation control circuit is electrically connected with the compensation control end, the driving node and the second end of the driving circuit respectively, and is used for controlling the communication or disconnection between the driving node and the second end of the driving circuit under the control of the compensation control signal provided by the compensation control end;

[0117] The first reset circuit is electrically connected with the reset control end, the display initial voltage end and the driving node respectively, and is used for writing the display initial voltage provided by the display initial voltage end into the driving node under the control of the reset control signal provided by the reset control end;

[0118] The first display light emitting control circuit is electrically connected with the light emitting control end, the power supply voltage end and the first end of the driving circuit respectively, and is used for controlling the communication or disconnection between the power supply voltage end and the first end of the driving circuit under the control of the light emitting control signal provided by the light emitting control end;

[0119] The second display light emitting control circuit is electrically connected with the light emitting control end, the second end of the driving circuit and the driving current output end respectively, and is used for controlling the communication or disconnection between the second end of the driving circuit and the driving current output end under the control of the light emitting control signal;

[0120] The driving node control circuit comprises a third light emitting control circuit, a control driving circuit, a data writing control circuit, a control energy storage circuit, a control reset circuit and a control compensation circuit;

[0121] The control end of the control driving circuit is electrically connected with a control driving node, the first end of the control driving circuit is electrically connected with a light emitting node, the second end of the control driving circuit is electrically connected with a driving node, and the control driving circuit is used for controlling the communication or disconnection between the light emitting node and the driving node under the control of the potential of the control driving node;

[0122] The third light emitting control circuit is electrically connected with the light emitting control end, the power supply voltage end and the light emitting node respectively, and is used for controlling the communication or disconnection between the power supply voltage end and the light emitting node under the control of the light emitting control signal provided by the light emitting control end;

[0123] The data write control circuit is electrically connected with a display control scanning end, a display control data voltage end and the light-emitting node respectively, and is used for writing display control data voltage provided by the display control data voltage end into the light-emitting node under the control of a display control scanning signal provided by the display control scanning end.

[0124] The first end of the control energy storage circuit is electrically connected with the first display control end, and the second end of the control energy storage circuit is electrically connected with the control driving node.

[0125] The control reset circuit is electrically connected with a reset control end, a display initial voltage end and the control driving node respectively, and is used for writing display initial voltage provided by the display initial voltage end into the control driving node under the control of a reset control signal provided by the reset control end.

[0126] The control compensation circuit is electrically connected with the display control scanning end, the control driving node and the driving node respectively, and is used for controlling the control driving node and the driving node to be connected or disconnected under the control of the display control scanning signal.

[0127] In at least one embodiment of the present disclosure, the nth on-off control circuit includes an nth first transistor, the nth write circuit includes an nth second transistor, and the nth control energy storage circuit includes an nth first capacitor.

[0128] The gate of the nth first transistor is electrically connected with the nth on-off control node, the first pole of the nth first transistor is electrically connected with the nth display driving control node, and the second pole of the nth first transistor is electrically connected with the nth display node.

[0129] The gate of the nth second transistor is electrically connected with the nth control reset end, the first pole of the nth second transistor is electrically connected with the nth control data voltage end, and the second pole of the nth second transistor is electrically connected with the nth on-off control node.

[0130] The first end of the nth first capacitor is electrically connected with the display control end, and the second end of the nth first capacitor is electrically connected with the nth on-off control node.

[0131] In at least one embodiment of the present disclosure, the nth first driving circuit includes an nth first driving transistor, the nth first light-emitting control circuit includes an nth third transistor, the nth first compensation circuit includes an nth fourth transistor, the nth first reset circuit includes an nth fifth transistor, the nth first data write circuit includes an nth sixth transistor, and the nth first energy storage circuit includes an nth second capacitor.

[0132] a gate of the nth first driving transistor is electrically connected with the nth control node;

[0133] a gate of the nth third transistor is electrically connected with the light emitting control end, a first pole of the nth third transistor is electrically connected with the nth display power voltage end, and a second pole of the nth third transistor is electrically connected with a first pole of the nth first driving transistor;

[0134] a gate of the nth fourth transistor is electrically connected with the nth compensation control end, a first pole of the nth fourth transistor is electrically connected with the nth control node, and a second pole of the nth fourth transistor is electrically connected with a second pole of the nth first driving transistor;

[0135] a gate of the nth fifth transistor is electrically connected with the nth control reset end, a first pole of the nth fifth transistor is electrically connected with the nth control initial voltage end, and a second pole of the nth fifth transistor is electrically connected with the nth control node;

[0136] a gate of the nth sixth transistor is electrically connected with the nth write control end, a first pole of the nth sixth transistor is electrically connected with the nth display data voltage end, and a second pole of the nth sixth transistor is electrically connected with a first pole of the nth first driving transistor;

[0137] a first end of the nth second capacitor is electrically connected with the nth control node, and a second end of the nth second capacitor is electrically connected with the direct current voltage end.

[0138] In at least one embodiment of the present disclosure, the nth second driving circuit includes a nth second driving transistor, the nth second light emitting control circuit includes a nth seventh transistor, the nth second compensation circuit includes a nth eighth transistor, the nth second reset circuit includes a nth ninth transistor, the nth second data write circuit includes a nth tenth transistor, and the nth second energy storage circuit includes a nth third capacitor.

[0139] a gate of the nth second driving transistor is electrically connected with the nth inverted control node;

[0140] a gate of the nth seventh transistor is electrically connected with the light emitting control end, a first pole of the nth seventh transistor is electrically connected with the nth display low voltage end, and a second pole of the nth seventh transistor is electrically connected with a first pole of the nth second driving transistor;

[0141] The gate of the nth eighth transistor is electrically connected with an nth inverse compensation control end, the first pole of the nth eighth transistor is electrically connected with the nth inverse control node, and the second pole of the nth eighth transistor is electrically connected with the second pole of the nth second driving transistor;

[0142] The gate of the nth ninth transistor is electrically connected with an nth control reset end, the first pole of the nth ninth transistor is electrically connected with the nth inverse control initial voltage end, and the second pole of the nth ninth transistor is electrically connected with the nth inverse control node;

[0143] The gate of the nth tenth transistor is electrically connected with an nth inverse write control end, the first pole of the nth tenth transistor is electrically connected with the nth display data voltage end, and the second pole of the nth tenth transistor is electrically connected with the first pole of the nth second driving transistor;

[0144] The first end of the nth third capacitor is electrically connected with the nth inverse control node, and the second end of the nth third capacitor is electrically connected with a direct current voltage end.

[0145] In at least one embodiment of the present disclosure, the driving circuit includes a display driving transistor, the data write circuit includes a first control transistor, the display energy storage circuit includes a storage capacitor, the compensation control circuit includes a second control transistor, the first reset circuit includes a third control transistor, the display light-emitting control circuit includes a fourth control transistor, and the display control circuit includes a fifth control transistor.

[0146] The gate of the display driving transistor is electrically connected with the driving node;

[0147] The gate of the first control transistor is electrically connected with the display scanning end, the first pole of the first control transistor is electrically connected with the data voltage end, and the second pole of the first control transistor is electrically connected with the first pole of the display driving transistor;

[0148] The first end of the storage capacitor is electrically connected with the driving node, and the second end of the storage capacitor is electrically connected with a direct current voltage end;

[0149] The gate of the second control transistor is electrically connected with the compensation control end, the first pole of the second control transistor is electrically connected with the driving node, and the second pole of the second control transistor is electrically connected with the second pole of the display driving transistor;

[0150] The gate of the third control transistor is electrically connected with the reset control end, the first pole of the third control transistor is electrically connected with the display initial voltage end, and the second pole of the third control transistor is electrically connected with the driving node;

[0151] a gate of the fourth control transistor is electrically connected with the light-emitting control end, a first electrode of the fourth control transistor is electrically connected with the power voltage end, and a second electrode of the fourth control transistor is electrically connected with the first electrode of the display driving transistor;

[0152] a gate of the fifth control transistor is electrically connected with the display control node, a first electrode of the fifth control transistor is electrically connected with the first electrode of the display driving transistor, and a second electrode of the fifth control transistor is electrically connected with the driving current output end.

[0153] In at least one embodiment of the present disclosure, the node control circuit comprises a sixth control transistor and a first control capacitor.

[0154] a gate of the sixth control transistor is electrically connected with the reset control end, a first electrode of the sixth control transistor is electrically connected with the display control data voltage end, and a second electrode of the sixth control transistor is electrically connected with the display control node.

[0155] a first end of the first control capacitor is electrically connected with the display control end, and a second end of the first control capacitor is electrically connected with the display control node.

[0156] In at least one embodiment of the present disclosure, the nth on-off control circuit comprises an nth eleventh transistor, the nth control energy storage circuit comprises an nth fourth capacitor, the nth setting circuit comprises an nth twelfth transistor and an nth thirteenth transistor, the nth control compensation circuit comprises an nth fourteenth transistor, the nth initialization circuit comprises an nth fifteenth transistor, the nth first voltage providing circuit comprises an nth sixteenth transistor, and the nth second voltage providing circuit comprises an nth seventeenth transistor.

[0157] a gate of the nth eleventh transistor is electrically connected with the nth on-off control node, a first electrode of the nth eleventh transistor is electrically connected with the nth display driving control node, and a second electrode of the nth eleventh transistor is electrically connected with the nth intermediate node.

[0158] a first end of the nth fourth capacitor is electrically connected with the nth on-off control node, and a second end of the nth fourth capacitor is electrically connected with the nth write node.

[0159] a gate of the nth twelfth transistor is electrically connected with the nth control reset end, a first electrode of the nth twelfth transistor is electrically connected with the nth control initial voltage end, and a second electrode of the nth twelfth transistor is electrically connected with the nth on-off control node.

[0160] The gate of the nth thirteenth transistor is electrically connected with the nth control reset end, the first electrode of the nth thirteenth transistor is electrically connected with the nth control initial voltage end, and the second electrode of the nth thirteenth transistor is electrically connected with the nth write-in node;

[0161] The gate of the nth fourteenth transistor is electrically connected with the nth compensation control end, the first electrode of the nth fourteenth transistor is electrically connected with the nth display driving control node, and the second electrode of the nth fourteenth transistor is electrically connected with the nth on-off control node;

[0162] The gate of the nth fifteenth transistor is electrically connected with the nth write-in control end, the first electrode of the nth fifteenth transistor is electrically connected with the reference voltage end, and the second electrode of the nth fifteenth transistor is electrically connected with the nth intermediate node;

[0163] The gate of the nth sixteenth transistor is electrically connected with the nth write-in control end, the first electrode of the nth sixteenth transistor is electrically connected with the nth control data voltage end, and the second electrode of the nth sixteenth transistor is electrically connected with the nth write-in node;

[0164] The gate of the nth seventeenth transistor is electrically connected with the light-emitting control end, the first electrode of the nth seventeenth transistor is electrically connected with the display control end, and the second electrode of the nth seventeenth transistor is electrically connected with the nth write-in node.

[0165] In at least one embodiment of the present disclosure, the control reset circuit includes a sixth control transistor; the display control energy storage circuit includes a first control capacitor, the first write-in control circuit includes a seventh control transistor; the second write-in control circuit includes an eighth control transistor; the control set circuit includes a ninth control transistor and a tenth control transistor, and the control compensation control circuit includes an eleventh control transistor;

[0166] The gate of the sixth control transistor is electrically connected with a display scanning end, the first electrode of the sixth control transistor is electrically connected with a reference voltage end, and the second electrode of the sixth control transistor is electrically connected with the light-emitting control node;

[0167] The first end of the first control capacitor is electrically connected with the display control node, and the second end of the first control capacitor is electrically connected with a display write-in node;

[0168] The gate of the seventh control transistor is electrically connected with the display scanning end, the first electrode of the seventh control transistor is electrically connected with a display control data voltage end, and the second electrode of the seventh control transistor is electrically connected with the display write-in node;

[0169] A gate of the eighth control transistor is electrically connected with the light-emitting control end, a first pole of the eighth control transistor is electrically connected with the display control end, and a second pole of the eighth control transistor is electrically connected with the display write-in node;

[0170] A gate of the ninth control transistor is electrically connected with the reset control end, a first pole of the ninth control transistor is electrically connected with the display initial voltage end, and a second pole of the ninth control transistor is electrically connected with the display control node;

[0171] A gate of the tenth control transistor is electrically connected with the reset control end, a first pole of the tenth control transistor is electrically connected with the display initial voltage end, and a second pole of the tenth control transistor is electrically connected with the display write-in node;

[0172] A gate of the eleventh control transistor is electrically connected with the compensation control end, a first pole of the eleventh control transistor is electrically connected with the driving current output end, and a second pole of the eleventh control transistor is electrically connected with the display control node.

[0173] In at least one embodiment of the present disclosure, the third display light-emitting control circuit comprises a twelfth control transistor;

[0174] A gate of the twelfth control transistor is electrically connected with the light-emitting control end, a first pole of the twelfth control transistor is electrically connected with the display control circuit, and a second pole of the twelfth control transistor is electrically connected with the driving current output end.

[0175] In at least one embodiment of the present disclosure, the nth first driving circuit comprises an nth first driving transistor, the nth first light-emitting control circuit comprises an nth first transistor, the nth first compensation circuit comprises an nth second transistor, the nth first reset circuit comprises an nth third transistor, the nth first energy storage circuit comprises an nth first capacitor, and the nth first write-in circuit comprises an nth fourth transistor;

[0176] A gate of the nth first driving transistor is electrically connected with the nth control node;

[0177] A gate of the nth first transistor is electrically connected with the light-emitting control end, a first pole of the nth first transistor is electrically connected with the nth display power voltage end, and a second pole of the nth first transistor is electrically connected with a first pole of the nth first driving transistor;

[0178] A gate of the nth second transistor is electrically connected with the nth compensation control end, a first pole of the nth second transistor is electrically connected with the nth control node, and a second pole of the nth second transistor is electrically connected with a second pole of the nth first driving transistor;

[0179] a gate of the nth third transistor is electrically connected with an nth control reset end, a first pole of the nth third transistor is electrically connected with an nth control initial voltage end, and a second pole of the nth third transistor is electrically connected with the nth control node;

[0180] a first end of the nth first capacitor is electrically connected with the nth control node, and a second end of the nth first capacitor is electrically connected with a direct current voltage end;

[0181] a gate of the nth fourth transistor is electrically connected with an nth write control end, a first pole of the nth fourth transistor is electrically connected with an nth display data voltage end, and a second pole of the nth fourth transistor is electrically connected with the first pole of the nth first driving transistor.

[0182] In at least one embodiment of the present disclosure, the nth first driving energy storage circuit includes an nth second capacitor, the nth first control driving circuit includes an nth fifth transistor, the nth third light-emitting control circuit includes an nth sixth transistor, the nth first data write circuit includes an nth seventh transistor, the nth first setting circuit includes an nth eighth transistor, and the nth first control compensation circuit includes an nth ninth transistor.

[0183] a first end of the nth second capacitor is electrically connected with a first display control end, and a second end of the nth second capacitor is electrically connected with an nth first driving control node;

[0184] a gate of the nth fifth transistor is electrically connected with the nth first driving control node, a first pole of the nth fifth transistor is electrically connected with an nth first driving node, and a second pole of the nth fifth transistor is electrically connected with the nth control node;

[0185] a gate of the nth sixth transistor is electrically connected with a light-emitting control end, a first pole of the nth sixth transistor is electrically connected with an nth display power voltage end, and a second pole of the nth sixth transistor is electrically connected with the nth first driving node;

[0186] a gate of the nth seventh transistor is electrically connected with an nth control scanning end, a first pole of the nth seventh transistor is electrically connected with an nth control data voltage end, and a second pole of the nth seventh transistor is electrically connected with the nth first driving node;

[0187] a gate of the nth eighth transistor is electrically connected with an nth control reset end, a first pole of the nth eighth transistor is electrically connected with an nth control initial voltage end, and a second pole of the nth eighth transistor is electrically connected with the nth first driving control node;

[0188] The gate of the nth ninth transistor is electrically connected with the nth control scanning end, the first pole of the nth ninth transistor is electrically connected with the nth first driving control node, and the second pole of the nth ninth transistor is electrically connected with the nth control node.

[0189] In at least one embodiment of the present disclosure, the nth second driving circuit includes an nth second driving transistor, the nth second light-emitting control circuit includes an nth tenth transistor, the nth second compensation circuit includes an nth eleventh transistor, the nth second reset circuit includes an nth twelfth transistor, the nth second energy storage circuit includes an nth third capacitor, and the nth second data writing circuit includes an nth thirteenth transistor.

[0190] The gate of the nth second driving transistor is electrically connected with the nth inverted control node.

[0191] The gate of the nth tenth transistor is electrically connected with a light-emitting control end, the first pole of the nth tenth transistor is electrically connected with the nth display low-voltage end, and the second pole of the nth tenth transistor is electrically connected with the first pole of the nth second driving transistor.

[0192] The gate of the nth eleventh transistor is electrically connected with an nth inverted compensation control end, the first pole of the nth eleventh transistor is electrically connected with the nth inverted control node, and the second pole of the nth eleventh transistor is electrically connected with the second pole of the nth second driving transistor.

[0193] The gate of the nth twelfth transistor is electrically connected with an nth control reset end, the first pole of the nth twelfth transistor is electrically connected with an nth inverted control initial voltage end, and the second pole of the nth twelfth transistor is electrically connected with the nth inverted control node.

[0194] The first end of the nth third capacitor is electrically connected with the nth inverted control node, and the second end of the nth third capacitor is electrically connected with a direct-current voltage end.

[0195] The gate of the nth thirteenth transistor is electrically connected with an nth inverted writing control end, the first pole of the nth thirteenth transistor is electrically connected with an nth display data voltage end, and the second pole of the nth thirteenth transistor is electrically connected with the first pole of the nth second driving transistor.

[0196] In at least one embodiment of the present disclosure, the nth second drive energy storage circuit includes an nth fourth capacitor, the nth second control drive circuit includes an nth fourteenth transistor, the nth fourth light emitting control circuit includes an nth fifteenth transistor, the nth second data write circuit includes an nth sixteenth transistor, the nth second control compensation circuit includes an nth seventeenth transistor, and the nth second set circuit includes an nth eighteenth transistor.

[0197] A first end of the nth fourth capacitor is electrically connected to the second display control end, and a second end of the nth fourth capacitor is electrically connected to the nth second drive control node.

[0198] A gate of the nth fourteenth transistor is electrically connected to the nth second drive control node, a first pole of the nth fourteenth transistor is electrically connected to the nth second drive node, and a second pole of the nth fourteenth transistor is electrically connected to the nth inverted control node.

[0199] A gate of the nth fifteenth transistor is electrically connected to the light emitting control end, a first pole of the nth fifteenth transistor is electrically connected to the nth display low voltage end, and a second pole of the nth fifteenth transistor is electrically connected to the nth second drive node.

[0200] A gate of the nth sixteenth transistor is electrically connected to the nth inverted control scan end, a first pole of the nth sixteenth transistor is electrically connected to the nth control data voltage end, and a second pole of the nth sixteenth transistor is electrically connected to the nth second drive node.

[0201] A gate of the nth seventeenth transistor is electrically connected to the nth inverted control scan end, a first pole of the nth seventeenth transistor is electrically connected to the nth second drive control node, and a second pole of the nth seventeenth transistor is electrically connected to the nth inverted control node.

[0202] A gate of the nth eighteenth transistor is electrically connected to the nth control reset end, a first pole of the nth eighteenth transistor is electrically connected to the nth inverted control initial voltage end, and a second pole of the nth eighteenth transistor is electrically connected to the nth second drive control node.

[0203] In at least one embodiment of the present disclosure, the nth display control circuit includes an nth nineteenth transistor.

[0204] A gate of the nth nineteenth transistor is electrically connected to the light emitting control end, a first pole of the nth nineteenth transistor is electrically connected to the nth display node, and a second pole of the nth nineteenth transistor is electrically connected to the nth display drive control node.

[0205] In at least one embodiment of the present disclosure, the driving circuit includes a display driving transistor, the data writing circuit includes a first control transistor, the display energy storage circuit includes a storage capacitor, the compensation control circuit includes a second control transistor, the first reset circuit includes a third control transistor, the first display light emitting control circuit includes a first light emitting control transistor, and the second display light emitting control circuit includes a second light emitting control transistor.

[0206] The gate of the display driving transistor is electrically connected with the driving node.

[0207] The first end of the storage capacitor is electrically connected with the driving node, and the second end of the storage capacitor is electrically connected with a direct current voltage end.

[0208] The gate of the first control transistor is electrically connected with the display scanning end, the first pole of the first control transistor is electrically connected with the data voltage end, and the second pole of the first control transistor is electrically connected with the first pole of the display driving transistor.

[0209] The gate of the second control transistor is electrically connected with the compensation control end, the first pole of the second control transistor is electrically connected with the driving node, and the second pole of the second control transistor is electrically connected with the second pole of the display driving transistor.

[0210] The gate of the third control transistor is electrically connected with the reset control end, the first pole of the third control transistor is electrically connected with the display initial voltage end, and the second pole of the third control transistor is electrically connected with the driving node.

[0211] The gate of the first light emitting control transistor is electrically connected with the light emitting control end, the first pole of the first light emitting control transistor is electrically connected with the power voltage end, and the second pole of the first light emitting control transistor is electrically connected with the first pole of the display driving transistor.

[0212] The gate of the second light emitting control transistor is electrically connected with the light emitting control end, the first pole of the second light emitting control transistor is electrically connected with the first pole of the display driving transistor, and the second pole of the second light emitting control transistor is electrically connected with the driving current output end.

[0213] In at least one embodiment of the present disclosure, the third light emitting control circuit includes a sixth control transistor, the control driving circuit includes a seventh control transistor, the data writing control circuit includes an eighth control transistor, the control energy storage circuit includes a control capacitor, the control reset circuit includes a ninth control transistor, and the control compensation circuit includes a tenth control transistor.

[0214] A gate of the sixth control transistor is electrically connected with the light-emitting control end, a first pole of the sixth control transistor is electrically connected with the power voltage end, and a second pole of the sixth control transistor is electrically connected with the light-emitting node;

[0215] A gate of the seventh control transistor is electrically connected with the control driving node, a first pole of the seventh control transistor is electrically connected with the light-emitting node, and a second pole of the seventh control transistor is electrically connected with the driving node;

[0216] A gate of the eighth control transistor is electrically connected with the display control scanning end, a first pole of the eighth control transistor is electrically connected with the display control data voltage end, and a second pole of the eighth control transistor is electrically connected with the light-emitting node;

[0217] A first end of the control capacitor is electrically connected with the first display control end, and a second end of the control capacitor is electrically connected with the control driving node;

[0218] A gate of the ninth control transistor is electrically connected with the reset control end, a first pole of the ninth control transistor is electrically connected with the display initial voltage end, and a second pole of the ninth control transistor is electrically connected with the control driving node;

[0219] A gate of the tenth control transistor is electrically connected with the display control scanning end, a first pole of the tenth control transistor is electrically connected with the control driving node, and a second pole of the tenth control transistor is electrically connected with the driving node.

[0220] In a second aspect, the embodiments of the present disclosure provide a display device, comprising the pixel circuit. BRIEF DESCRIPTION OF DRAWINGS

[0221] FIG. 1 is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0222] FIG. 2A is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0223] FIG. 2B is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0224] FIG. 3 is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0225] FIG. 4 is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0226] FIG. 5 is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0227] FIG. 6A is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0228] Figure 6B is a structural diagram of the first first display driving circuit, the first second display driving circuit, and the first display control circuit in Figure 6A;

[0229] Figure 6C is a structural diagram of the second first display driving circuit, the second second display driving circuit, and the second display control circuit in Figure 6A;

[0230] Figure 6D is a structural diagram of the third first display driving circuit, the third second display driving circuit, and the third display control circuit in Figure 6A.

[0231] Figure 7A is a structural diagram of at least one embodiment of the first display driving circuit and at least one embodiment of the first second display driving circuit;

[0232] Figure 7B is a structural diagram of at least one embodiment of the second first display driving circuit and at least one embodiment of the second second display driving circuit;

[0233] Figure 7C is a structural diagram of at least one embodiment of the third first display driving circuit and at least one embodiment of the third second display driving circuit;

[0234] Figure 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0235] Figure 9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0236] Figure 10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0237] Figure 11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0238] Figure 12A is a structural diagram of at least one embodiment of the first display driving circuit;

[0239] Figure 12B is a structural diagram of at least one embodiment of the first second display driving circuit;

[0240] Figure 12C is a structural diagram of at least one embodiment of the second first display driving circuit;

[0241] Figure 12D is a structural diagram of at least one embodiment of the second display driving circuit;

[0242] Figure 12E is a structural diagram of at least one embodiment of the third first display driving circuit;

[0243] Figure 12F is a structural diagram of at least one embodiment of the third second display driving circuit;

[0244] Figure 13 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0245] FIG. 14 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0246] FIG. 15A is a timing chart of operation of at least one embodiment of the pixel circuit shown in FIG. 14;

[0247] FIG. 15B is a first timing chart of signals provided by EM1 and signals provided by SWP during operation of at least one embodiment of the pixel circuit shown in FIG. 14;

[0248] FIG. 15C is a second timing chart of signals provided by EM1, signals provided by SWP, and the potential of SX during operation of at least one embodiment of the pixel circuit shown in FIG. 14;

[0249] FIG. 16A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0250] FIG. 16B is a circuit diagram of a pixel drive circuit in FIG. 16A;

[0251] FIG. 16C is a circuit diagram of a first current control circuit in FIG. 16A;

[0252] FIG. 16D is a circuit diagram of a second current control circuit in FIG. 16A;

[0253] FIG. 16E is a circuit diagram of a third current control circuit in FIG. 16A;

[0254] FIG. 17 is a timing chart of operation of at least one embodiment of the pixel circuit shown in FIG. 16A;

[0255] FIG. 18A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0256] FIG. 18B is a circuit diagram of a pixel drive circuit in FIG. 18A;

[0257] FIG. 18C is a circuit diagram of a first current control circuit in FIG. 18A;

[0258] FIG. 18D is a circuit diagram of a second current control circuit in FIG. 18A;

[0259] FIG. 18E is a circuit diagram of a third current control circuit in FIG. 18A;

[0260] FIG. 19 is a timing chart of operation of at least one embodiment of the pixel circuit shown in FIG. 18A;

[0261] FIG. 20 is a circuit diagram of a pixel drive circuit according to at least one embodiment;

[0262] FIG. 21 is a circuit diagram of a pixel drive circuit according to at least one embodiment; and

[0263] FIG. 22 is a circuit diagram of at least one embodiment of a pixel driving circuit. DETAILED DESCRIPTION

[0264] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0265] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is referred to as the first pole and the other pole is referred to as the second pole.

[0266] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0267] The pixel circuit described in the embodiments of the present disclosure includes a pixel driving circuit, N light emitting elements and N current control circuits; N is an integer greater than 1.

[0268] The pixel driving circuit is electrically connected to a display control end, for generating a driving current and outputting the driving current through a driving current output end under the control of a display control signal provided by the display control end.

[0269] The first pole of the first light emitting element is electrically connected to the driving current output end.

[0270] The second pole of the nth light emitting element and the first pole of the (n+1)th light emitting element are both electrically connected to an nth display node, and the second pole of the Nth light emitting element is electrically connected to a first voltage end; n is a positive integer less than N.

[0271] The nth current control circuit is electrically connected to the display control end and the nth display node, for controlling an nth control current provided to the nth display node under the control of the display control signal.

[0272] The pixel circuit described in the embodiments of the present disclosure drives N light emitting elements in series through one pixel driving circuit, realizes that the driving transistor and the light emitting control transistor in the pixel driving circuit on the driving current path are shared, only one group of driving transistors has power consumption loss, so as to achieve the purpose of reducing power consumption.

[0273] In at least one embodiment of the present disclosure, the display period of the pixel circuit can include a light emitting phase.

[0274] The display control terminal is configured to provide a display control signal with gradually decreasing potential during at least part of the light-emitting stage, or configured to provide a display control signal with gradually increasing potential during at least part of the light-emitting stage.

[0275] In at least one embodiment of the present disclosure, N is taken as an example of 3, but not limited thereto; in actual operation, N can be an integer greater than 1.

[0276] In at least one embodiment of the present disclosure, the light-emitting element can be a Micro LED (micro light-emitting diode), a Mini LED (mini light-emitting diode), or an OLED (organic light-emitting diode), the first electrode of the light-emitting element can be an anode, and the second electrode of the light-emitting element can be a cathode, but not limited thereto.

[0277] Optionally, the first voltage terminal can be a low voltage terminal, but not limited thereto.

[0278] In at least one embodiment of the present disclosure, the light-emitting element is a current-driven device, and to achieve the required brightness, the required current is input to the device brightness. The pixel circuit in at least one embodiment of the present disclosure drives N light-emitting elements through a driving transistor in a pixel driving circuit, so as to reduce power consumption.

[0279] For example, when the required brightness (L255) needs to be achieved, each light-emitting element needs to drive current Id to achieve the required brightness, and only the driving transistor needs to provide driving current Id. Compared with the power consumption of the related pixel driving circuit, the original power consumption can be reduced by 25%-50%, and the purpose of reducing the power consumption of the backplane is achieved.

[0280] As shown in FIG. 1, the pixel circuit in at least one embodiment of the present disclosure can include a pixel driving circuit 10, a first light-emitting element E1, a second light-emitting element E2, a third light-emitting element E3, a fourth light-emitting element E4, a first current control circuit 11, a second current control circuit 12, and a third current control circuit 13.

[0281] The pixel driving circuit 10 is electrically connected with the display control terminal SWP, configured to generate a driving current, and output the driving current through a driving current output terminal OT under the control of a display control signal provided by the display control terminal SWP.

[0282] The first electrode of the first light-emitting element E1 is electrically connected with the driving current output terminal OT.

[0283] The second electrode of the first light-emitting element E1 and the first electrode of the second light-emitting element E2 are both electrically connected with a first display node NX1.

[0284] The second electrode of the second light emitting element E2 and the first electrode of the third light emitting element E3 are electrically connected with the second display node NX2;

[0285] The second electrode of the third light emitting element E3 and the first electrode of the fourth light emitting element E4 are electrically connected with the third display node NX3;

[0286] The second electrode of the fourth light emitting element E4 is electrically connected with the first voltage terminal V1;

[0287] The first current control circuit 11 is electrically connected with the display control terminal SWP and the first display node NX1 respectively, and is configured to control the first control current provided to the first display node NX1 under the control of the display control signal.

[0288] The second current control circuit 12 is electrically connected with the display control terminal SWP and the second display node NX2 respectively, and is configured to control the second control current provided to the second display node NX2 under the control of the display control signal.

[0289] The third current control circuit 13 is electrically connected with the display control terminal SWP and the third display node NX3 respectively, and is configured to control the third control current provided to the third display node NX3 under the control of the display control signal.

[0290] In at least one embodiment of the present disclosure, the nth current control circuit can include an nth display driving circuit and an nth display control circuit.

[0291] The nth display driving circuit is electrically connected with an nth display data voltage terminal and an nth display driving control node respectively, and is configured to control whether to provide an nth control current according to an nth display data voltage provided by the nth display data voltage terminal.

[0292] The nth display control circuit is electrically connected with the nth display driving control node, an nth control data voltage terminal, the display control terminal and the nth display node respectively, and is configured to control the communication or disconnection between the nth display node and the nth display driving control node according to the display control signal and an nth control data voltage provided by the nth control data voltage terminal.

[0293] In specific implementation, the nth current control circuit can include an nth display driving circuit and an nth display control circuit, the nth display control circuit controls the communication or disconnection between the nth display node and the nth display driving control node according to the display control signal and an nth control data voltage, and the nth display driving circuit controls whether to provide an nth control current according to an nth display data voltage.

[0294] As shown in FIG. 2A, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the first current control circuit comprises a first display driving circuit 21 and a first display control circuit 210;

[0295] The first display driving circuit 21 is electrically connected with a first display data voltage terminal DL1 and a first display driving control node NQ1 respectively, for controlling whether to provide a first control current according to a first display data voltage provided by the first display data voltage terminal DL1;

[0296] The first display control circuit 210 is electrically connected with a first control data voltage terminal DTC1, the display control terminal SWP, the first display node NX1 and the first display driving control node NQ1 respectively, for controlling the first display node NX1 and the first display driving control node NQ1 to be connected or disconnected according to a display control signal and a first control data voltage provided by the first control data voltage terminal DTC1;

[0297] The second current control circuit comprises a second display driving circuit 22 and a second display control circuit 220;

[0298] The second display driving circuit 22 is electrically connected with a second display data voltage terminal DL2 and a second display driving control node NQ2 respectively, for controlling whether to provide a second control current according to a second display data voltage provided by the second display data voltage terminal DL2;

[0299] The second display control circuit 220 is electrically connected with a second control data voltage terminal DTC2, the display control terminal SWP, the second display node NX2 and the second display driving control node NQ2 respectively, for controlling the second display node NX2 and the second display driving control node NQ2 to be connected or disconnected according to a display control signal and a second control data voltage provided by the second control data voltage terminal DTC2;

[0300] The third current control circuit comprises a third display driving circuit 23 and a third display control circuit 230;

[0301] The third display driving circuit 23 is electrically connected with a third display data voltage terminal DL3 and a third display driving control node NQ3 respectively, for controlling whether to provide a third control current according to a third display data voltage provided by the third display data voltage terminal DL3;

[0302] The third display control circuit 230 is electrically connected with a third control data voltage terminal DTC3, the display control terminal SWP, the third display node NX3 and a third display driving control node NQ3 respectively, and is configured to control the third display node NX3 to be connected or disconnected with the third display driving control node NQ3 according to the display control signal and a third control data voltage provided by the third control data voltage terminal DTC3.

[0303] In at least one embodiment of the present disclosure, the nth control current includes an nth first driving current and / or an nth second driving current.

[0304] The nth display driving circuit includes an nth first display driving circuit and / or an nth second display driving circuit.

[0305] The nth first display driving circuit is electrically connected with an nth display data voltage terminal, an nth display driving control node, an nth display power voltage terminal and a light-emitting control terminal respectively, and is configured to control whether to provide an nth first driving current flowing from the nth display power voltage terminal to the nth display driving control node according to an nth display data voltage provided by the nth display data voltage terminal under the control of a light-emitting control signal provided by the light-emitting control terminal.

[0306] The nth second display driving circuit is electrically connected with an nth display data voltage terminal, an nth display driving control node, an nth display low voltage terminal and a light-emitting control terminal respectively, and is configured to control whether to provide an nth second driving current flowing from the nth display driving control node to the nth display low voltage terminal according to the nth display data voltage under the control of the light-emitting control signal.

[0307] In specific implementation, the nth control current can include an nth first driving current and / or an nth second driving current; the nth display driving circuit can include an nth first display driving circuit and / or an nth second display driving circuit; the nth first display driving circuit provides the nth first driving current, and the nth second display driving circuit provides the nth second driving current; the nth first driving current flows from the nth display power voltage terminal to the nth display driving control node, and the nth second driving current flows from the nth display driving control node to the nth display low voltage terminal; when a light-emitting current flowing through the nth+1 light-emitting element is greater than a light-emitting current flowing through the nth light-emitting element, the nth first display driving circuit provides the nth first driving current to increase the light-emitting current; and when the light-emitting current flowing through the nth+1 light-emitting element is less than the light-emitting current flowing through the nth light-emitting element, the nth second display driving circuit provides the nth second driving current to decrease the light-emitting current.

[0308] In at least one embodiment of the present disclosure, the nth display driving circuit can only include the nth first display driving circuit, at this time, the light emitting current flowing through the (n+1)th light emitting element is greater than or equal to the light emitting current flowing through the nth light emitting element; or,

[0309] The nth display driving circuit can only include the nth second display driving circuit, at this time, the light emitting current flowing through the (n+1)th light emitting element is less than or equal to the light emitting current flowing through the nth light emitting element; or,

[0310] The nth display driving circuit can include the nth first display driving circuit and the nth second display driving circuit, at this time, the light emitting current flowing through the (n+1)th light emitting element can be less than, greater than or equal to the light emitting current flowing through the nth light emitting element.

[0311] In a specific implementation, when the light emitting current flowing through the (n+1)th light emitting element is equal to the light emitting current flowing through the nth light emitting element, the nth display driving circuit can not provide the nth control current.

[0312] As shown in FIG. 2B, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the first current control circuit includes a first first display driving circuit 211, a first second display driving circuit 212 and a first display control circuit 210;

[0313] The first first display driving circuit 211 is electrically connected with a first display data voltage terminal DL1, a first display driving control node NQ1, a first display power voltage terminal VD1 and a light emitting control terminal EM1 respectively, for controlling whether to provide a first first driving current flowing from the first display power voltage terminal VD1 to the first display driving control node NQ1 under the control of a light emitting control signal provided by the light emitting control terminal EM1 according to a first display data voltage provided by the first display data voltage terminal DL1;

[0314] The first second display driving circuit 212 is electrically connected with the first display data voltage terminal DL1, the first display driving control node NQ1, a first display low voltage terminal VS1 and the light emitting control terminal EM1 respectively, for controlling whether to provide a first second driving current flowing from the first display driving control node NQ1 to the first display low voltage terminal VS1 under the control of the light emitting control signal according to the first display data voltage;

[0315] The first display control circuit 210 is electrically connected with the first control data voltage terminal DTC1, the display control terminal SWP, the first control reset terminal RSTC1, the first display node NX1 and the first display drive control node NQ1, and is configured to control the first display node NX1 and the first display drive control node NQ1 to be connected or disconnected under the control of a first control reset signal provided by the first control reset terminal RSTC1, according to the display control signal and a first control data voltage provided by the first control data voltage terminal DTC1;

[0316] The second current control circuit includes a second first display drive circuit 221, a second second display drive circuit 222 and a second display control circuit 220.

[0317] The second first display drive circuit 221 is electrically connected with the second display data voltage terminal DL2, the second display drive control node NQ2, the second display power voltage terminal VD2 and the light-emitting control terminal EM1, and is configured to control whether to provide a second first drive current flowing from the second display power voltage terminal VD2 to the second display drive control node NQ2 under the control of a light-emitting control signal provided by the light-emitting control terminal EM1, according to a second display data voltage provided by the second display data voltage terminal DL2.

[0318] The second second display drive circuit 222 is electrically connected with the second display data voltage terminal DL2, the second display drive control node NQ2, the second display low voltage terminal VS2 and the light-emitting control terminal EM1, and is configured to control whether to provide a second second drive current flowing from the second display drive control node NQ2 to the second display low voltage terminal VS2 under the control of the light-emitting control signal, according to the second display data voltage.

[0319] The second display control circuit 220 is electrically connected with the second control data voltage terminal DTC2, the display control terminal SWP, the second control reset terminal RSTC2, the second display node NX2 and the second display drive control node NQ2, and is configured to control the second display node NX2 and the second display drive control node NQ2 to be connected or disconnected under the control of a second control reset signal provided by the second control reset terminal RSTC2, according to the display control signal and a second control data voltage provided by the second control data voltage terminal DTC2.

[0320] The third current control circuit includes a third first display drive circuit 231, a third second display drive circuit 232 and a third display control circuit 230.

[0321] The third first display driving circuit 231 is electrically connected with the third display data voltage terminal DL3, the third display driving control node NQ3, the third display power voltage terminal VD3 and the light emitting control terminal EM1, and is configured to control whether to provide a third first driving current flowing from the third display power voltage terminal VD3 to the third display driving control node NQ3 according to a third display data voltage provided by the third display data voltage terminal DL3 under control of a light emitting control signal provided by the light emitting control terminal EM1;

[0322] The third second display driving circuit 232 is electrically connected with the third display data voltage terminal DL3, the third display driving control node NQ3, the third display low voltage terminal VS3 and the light emitting control terminal EM1, and is configured to control whether to provide a third second driving current flowing from the third display driving control node NQ3 to the third display low voltage terminal VS3 according to the third display data voltage under control of the light emitting control signal;

[0323] The third display control circuit 230 is electrically connected with the third control data voltage terminal DTC3, the display control terminal SWP, the third control reset terminal RSTC3, the third display node NX3 and the third display driving control node NQ3, and is configured to control the third display node NX3 and the third display driving control node NQ3 to be connected or disconnected according to a third control data voltage provided by the third control data voltage terminal DTC3 under control of a second control reset signal provided by the third control reset terminal RSTC3.

[0324] In at least one embodiment of the present disclosure, the nth display control circuit includes an nth on-off control circuit, an nth writing circuit and an nth control energy storage circuit.

[0325] The nth on-off control circuit is electrically connected with an nth on-off control node, the nth display node and the nth display driving control node, and is configured to control the nth display node and the nth display driving control node to be connected or disconnected under control of a potential of the nth on-off control node.

[0326] The nth writing circuit is electrically connected with an nth control reset terminal, the nth control data voltage terminal and the nth on-off control node, and is configured to write an nth control data voltage provided by the nth control data voltage terminal into the nth on-off control node under control of an nth control reset signal provided by the nth control reset terminal.

[0327] The nth control energy storage circuit is electrically connected with the display control terminal and the nth on-off control node, and is configured to control the potential of the nth on-off control node under control of the display control signal.

[0328] In a specific implementation, the nth display control circuit can include an nth on-off control circuit, an nth write-in circuit and an nth control energy storage circuit; the nth on-off control circuit controls the communication or disconnection between the nth display node and the nth display drive control node under the control of the potential of the nth on-off control node; the nth write-in circuit writes the nth control data voltage into the nth on-off control node under the control of the nth control reset signal; and the nth control energy storage circuit controls the potential of the nth on-off control node under the control of the display control signal.

[0329] As shown in FIG. 3, based on at least one embodiment of the pixel circuit shown in FIG. 2, the first display control circuit includes a first on-off control circuit 311, a first write-in circuit 312 and a first control energy storage circuit 313;

[0330] The first on-off control circuit 311 is electrically connected with a first on-off control node NT1, the first display node NX1 and the first display drive control node NQ1 respectively, and is configured to control the communication or disconnection between the first display node NX1 and the first display drive control node NQ1 under the control of the potential of the first on-off control node NT1;

[0331] The first write-in circuit 312 is electrically connected with a first control reset end RSTC1, a first control data voltage end DTC1 and the first on-off control node NT1 respectively, and is configured to write the first control data voltage provided by the first control data voltage end DTC1 into the first on-off control node NT1 under the control of the first control reset signal provided by the first control reset end RSTC1;

[0332] The first control energy storage circuit 313 is electrically connected with the display control end SWP and the first on-off control node NT1 respectively, and is configured to control the potential of the first on-off control node NT1 under the control of the display control signal;

[0333] The second display control circuit includes a second on-off control circuit 321, a second write-in circuit 322 and a second control energy storage circuit 323;

[0334] The second on-off control circuit 321 is electrically connected with a second on-off control node NT2, the second display node NX2 and the second display drive control node NQ2 respectively, and is configured to control the communication or disconnection between the second display node NX2 and the second display drive control node NQ2 under the control of the potential of the second on-off control node NT2;

[0335] The second write circuit 322 is electrically connected with the second control reset end RSTC2, the second control data voltage end DTC2 and the second on-off control node NT2 respectively, and is used for writing the second control data voltage provided by the second control data voltage end DTC2 into the second on-off control node NT2 under the control of the second control reset signal provided by the second control reset end RSTC2;

[0336] The second control energy storage circuit 323 is electrically connected with the display control end SWP and the second on-off control node NT2 respectively, and is used for controlling the potential of the second on-off control node NT2 under the control of the display control signal;

[0337] The third display control circuit includes a third on-off control circuit 331, a third write circuit 332 and a second control energy storage circuit 333.

[0338] The third on-off control circuit 331 is electrically connected with the third on-off control node NT3, the third display node NX3 and the third display drive control node NQ3 respectively, and is used for controlling the communication or disconnection between the third display node NX3 and the third display drive control node NQ3 under the control of the potential of the third on-off control node NT3.

[0339] The third write circuit 332 is electrically connected with the third control reset end RSTC3, the third control data voltage end DTC3 and the third on-off control node NT3 respectively, and is used for writing the third control data voltage provided by the third control data voltage end DTC3 into the third on-off control node NT3 under the control of the third control reset signal provided by the third control reset end RSTC3.

[0340] The third control energy storage circuit 333 is electrically connected with the display control end SWP and the third on-off control node NT3 respectively, and is used for controlling the potential of the third on-off control node NT3 under the control of the display control signal.

[0341] In at least one embodiment of the present disclosure, the pixel driving circuit includes a driving circuit, a data write circuit, a display energy storage circuit, a compensation control circuit, a first reset circuit, a display light-emitting control circuit, a display control circuit and a node control circuit.

[0342] The driving circuit is electrically connected with the driving node, and is used for generating the driving current under the control of the potential of the driving node.

[0343] The data writing circuit is electrically connected with a display scanning end, a data voltage end and a first end of the driving circuit respectively, for writing data voltage provided by the data voltage end into the first end of the driving circuit under the control of a display scanning signal provided by the display scanning end;

[0344] The display energy storage circuit is electrically connected with the driving node, for maintaining the potential of the driving node;

[0345] The compensation control circuit is electrically connected with a compensation control end, the driving node and a second end of the driving circuit respectively, for controlling the communication or disconnection between the driving node and the second end of the driving circuit under the control of a compensation control signal provided by the compensation control end;

[0346] The first reset circuit is electrically connected with a reset control end, a display initial voltage end and the driving node respectively, for writing display initial voltage provided by the display initial voltage end into the driving node under the control of a reset control signal provided by the reset control end;

[0347] The display light emitting control circuit is electrically connected with a light emitting control end, a power voltage end and the first end of the driving circuit respectively, for controlling the communication or disconnection between the power voltage end and the first end of the driving circuit under the control of a light emitting control signal provided by the light emitting control end;

[0348] The display control circuit is electrically connected with a display control node, a second end of the driving circuit and the driving current output end respectively, for controlling the communication or disconnection between the second end of the driving circuit and the driving current output end under the control of the potential of the display control node;

[0349] The node control circuit is electrically connected with the display control node, the reset control end, a display control data voltage end and the display control end respectively, for writing display control data voltage provided by the display control data voltage end into the display control node under the control of the reset control signal, and controlling the potential of the display control node according to the display control signal.

[0350] In a specific implementation, the pixel driving circuit can include a driving circuit, a data writing circuit, a display energy storage circuit, a compensation control circuit, a first reset circuit, a display light emitting control circuit, a display control circuit, and a node control circuit; the data writing circuit writes a data voltage into a first end of the driving circuit under control of a display scanning signal; the display energy storage circuit maintains a potential of the driving node; the compensation control circuit controls communication or disconnection between the driving node and a second end of the driving circuit under control of a compensation control signal; the first reset circuit writes a display initial voltage into the driving node under control of a reset control signal; the display light emitting control circuit controls communication or disconnection between the power supply voltage end and the first end of the driving circuit under control of a light emitting control signal; the display control circuit controls communication or disconnection between the second end of the driving circuit and the driving current output end under control of a potential of the display control node; and the node control circuit writes a display control data voltage into the display control node under control of the reset control signal, and controls the potential of the display control node according to the display control signal.

[0351] As shown in FIG. 4, on the basis of at least one embodiment of the pixel circuit shown in FIG. 3, the pixel driving circuit includes a driving circuit 40, a data writing circuit 41, a display energy storage circuit 42, a compensation control circuit 43, a first reset circuit 44, a display light emitting control circuit 45, a display control circuit 46, and a node control circuit 47.

[0352] The driving circuit 40 is electrically connected with a driving node N1, and is configured to generate a driving current under control of a potential of the driving node N1.

[0353] The data writing circuit 41 is electrically connected with a display scanning end Gat, a data voltage end DA1, and a first end of the driving circuit 40, respectively, and is configured to write a data voltage provided by the data voltage end DA1 into the first end of the driving circuit 40 under control of a display scanning signal provided by the display scanning end Gat.

[0354] The display energy storage circuit 42 is electrically connected with the driving node N1, and is configured to maintain the potential of the driving node N1.

[0355] The compensation control circuit 43 is electrically connected with a compensation control end Gat1N, the driving node N1, and a second end of the driving circuit 40, respectively, and is configured to control communication or disconnection between the driving node N1 and the second end of the driving circuit 40 under control of a compensation control signal provided by the compensation control end Gat1N.

[0356] The first reset circuit 44 is electrically connected with a reset control end RST1, a display initial voltage end I1 and the driving node N1 respectively, for writing the display initial voltage Vinit1 provided by the display initial voltage end I1 into the driving node N1 under the control of a reset control signal provided by the reset control end RST1.

[0357] The display light emitting control circuit 45 is electrically connected with a light emitting control end EM1, a power voltage end VDD1 and the first end of the driving circuit 41 respectively, for controlling the communication or disconnection between the power voltage end VDD1 and the first end of the driving circuit 41 under the control of a light emitting control signal provided by the light emitting control end EM1.

[0358] The display control circuit 46 is electrically connected with a display control node SX, the second end of the driving circuit 40 and the driving current output end OT respectively, for controlling the communication or disconnection between the second end of the driving circuit 40 and the driving current output end OT under the control of the potential of the display control node SX.

[0359] The node control circuit 47 is electrically connected with the display control node SX, the reset control end RST1, a display control data voltage end DAT and the display control end SWP respectively, for writing the display control data voltage provided by the display control data voltage end DAT into the display control node SX under the control of the reset control signal, and controlling the potential of the display control node SX according to the reset control signal.

[0360] In at least one embodiment of the present disclosure, the nth current control circuit comprises an nth display control circuit.

[0361] The nth display control circuit is electrically connected with a light emitting control end, an nth display node and an nth display driving control node respectively, for controlling the communication or disconnection between the nth display node and the nth display driving control node under the control of a light emitting control signal provided by the light emitting control end.

[0362] The nth display control circuit further comprises an nth first display driving circuit and / or an nth second display driving circuit, the display control end comprises a first display control end and / or a second display control end, and the nth control current comprises an nth first driving current and / or an nth second driving current.

[0363] The nth first display driving circuit is electrically connected with the nth display data voltage terminal, the nth display driving control node, the nth display power voltage terminal, the light-emitting control terminal and the first display control terminal respectively, and is configured to control whether to provide the nth first driving current flowing from the nth display power voltage terminal to the nth display driving control node under the control of the light-emitting control signal provided by the light-emitting control terminal, according to the first display control signal provided by the first display control terminal and the nth display data voltage provided by the nth display data voltage terminal.

[0364] The nth second display driving circuit is electrically connected with the nth display data voltage terminal, the nth display driving control node, the nth display low voltage terminal, the light-emitting control terminal and the second display control terminal respectively, and is configured to control whether to provide the nth second driving current flowing from the nth display driving control node to the nth display low voltage terminal under the control of the light-emitting control signal, according to the second display control signal provided by the second display control terminal and the nth display data voltage.

[0365] In a specific implementation, the nth current control circuit can include an nth display control circuit, and the nth display control circuit is configured to control the on-off between the nth display node and the nth display driving control node under the control of the light-emitting control signal.

[0366] Further, the nth display control circuit further includes an nth first display driving circuit and / or an nth second display driving circuit, the nth first display driving circuit is configured to control whether to provide the nth first driving current flowing from the nth display power voltage terminal to the nth display driving control node, and the nth second display driving circuit is configured to control whether to provide the nth second driving current flowing from the nth display driving control node to the nth display low voltage terminal.

[0367] In a specific implementation, the nth current control circuit can include an nth first driving current and / or an nth second driving current, the nth display driving circuit can include an nth first display driving circuit and / or an nth second display driving circuit, the nth first display driving circuit provides the nth first driving current, the nth second display driving circuit provides the nth second driving current, the nth first driving current flows from the nth display power voltage terminal to the nth display driving control node, and the nth second driving current flows from the nth display driving control node to the nth display low voltage terminal; when the light-emitting current flowing through the nth+1 light-emitting element is greater than the light-emitting current flowing through the nth light-emitting element, the nth first display driving circuit provides the nth first driving current to increase the current; and when the light-emitting current flowing through the nth+1 light-emitting element is less than the light-emitting current flowing through the nth light-emitting element, the nth second display driving circuit provides the nth second driving current to decrease the current.

[0368] In at least one embodiment of the present disclosure, the nth display driving circuit can only include the nth first display driving circuit, at this time, the light emitting current flowing through the (n+1)th light emitting element is greater than or equal to the light emitting current flowing through the nth light emitting element; or,

[0369] The nth display driving circuit can only include the nth second display driving circuit, at this time, the light emitting current flowing through the (n+1)th light emitting element is less than or equal to the light emitting current flowing through the nth light emitting element; or,

[0370] The nth display driving circuit can include the nth first display driving circuit and the nth second display driving circuit, at this time, the light emitting current flowing through the (n+1)th light emitting element can be less than, greater than or equal to the light emitting current flowing through the nth light emitting element.

[0371] In specific implementation, when the light emitting current flowing through the (n+1)th light emitting element is equal to the light emitting current flowing through the nth light emitting element, the nth display driving circuit can not provide the nth control current.

[0372] In at least one embodiment of the present disclosure, the display period of the pixel circuit can include a light emitting stage;

[0373] The first display control terminal is used to provide a first display control signal with gradually decreasing potential during at least part of the time period included in the light emitting stage;

[0374] The second display control terminal is used to provide a second display control signal with gradually increasing potential during at least part of the time period included in the light emitting stage.

[0375] In at least one embodiment of the present disclosure, the nth current control circuit includes the nth first display driving circuit, the nth second display driving circuit, the nth display control circuit and the nth control circuit;

[0376] The nth first display driving circuit is electrically connected with the nth display data voltage terminal, the nth display driving control node, the nth display power voltage terminal and the light emitting control terminal respectively, and is used to control whether to provide the nth first driving current flowing from the nth display power voltage terminal to the nth display driving control node under the control of the light emitting control signal provided by the light emitting control terminal according to the nth display data voltage provided by the nth display data voltage terminal;

[0377] The nth second display driving circuit is electrically connected with the nth display data voltage terminal, the nth display driving control node, the nth display low voltage terminal and the light emitting control terminal respectively, and is configured to control whether to provide the nth second driving current flowing from the nth display driving control node to the nth display low voltage terminal according to the nth display data voltage under control of the light emitting control signal;

[0378] The nth control circuit is electrically connected with the light emitting control terminal, the nth intermediate node and the nth display node respectively, and is configured to control the nth intermediate node and the nth display node to be connected or disconnected under control of the light emitting control signal;

[0379] The nth display control circuit comprises an nth on-off control circuit, an nth control energy storage circuit, an nth setting circuit, an nth control compensation circuit, an nth initialization circuit, an nth first voltage providing circuit and an nth second voltage providing circuit.

[0380] The nth on-off control circuit is electrically connected with the nth on-off control node, the nth display driving control node and the nth intermediate node respectively, and is configured to control the nth display driving control node and the nth intermediate node to be connected or disconnected under control of the potential of the nth on-off control node.

[0381] The first end of the nth control energy storage circuit is electrically connected with the nth on-off control node, and the second end of the nth control energy storage circuit is electrically connected with the nth write-in node, and the nth control energy storage circuit is configured to store electric energy.

[0382] The nth setting circuit is electrically connected with the nth control reset terminal, the nth control initial voltage terminal, the nth on-off control node and the nth write-in node respectively, and is configured to write the nth control initial voltage provided by the nth control initial voltage terminal into the nth on-off control node and the nth write-in node under control of the nth control reset signal provided by the nth control reset terminal.

[0383] The nth control compensation circuit is electrically connected with the nth compensation control terminal, the nth display driving control node and the nth on-off control node respectively, and is configured to control the nth display driving control node and the nth on-off control node to be connected or disconnected under control of the nth compensation control signal provided by the nth compensation control terminal.

[0384] The nth initialization circuit is electrically connected with the nth write-in control terminal, the reference voltage terminal and the nth intermediate node respectively, and is configured to write the reference voltage provided by the reference voltage terminal into the nth intermediate node under control of the nth write-in control signal provided by the nth write-in control terminal.

[0385] The nth first voltage providing circuit is electrically connected with the nth write control terminal, the nth control data voltage terminal and the nth write node respectively, and is configured to write the nth control data voltage provided by the nth control data voltage terminal into the nth write node under the control of the nth write control signal.

[0386] The nth second voltage providing circuit is electrically connected with the light emitting control terminal, the display control terminal and the nth write node respectively, and is configured to write the display control signal provided by the display control terminal into the nth write node under the control of the light emitting control signal provided by the light emitting control terminal.

[0387] In a specific implementation, the nth current control circuit includes an nth first display driving circuit, an nth second display driving circuit, an nth display control circuit and an nth control circuit; the nth first display driving circuit is configured to control whether to provide an nth first driving current according to an nth display data voltage under the control of a light emitting control signal; the nth second display driving circuit is configured to control whether to provide an nth second driving current according to the nth display data voltage under the control of the light emitting control signal; and the nth control circuit is configured to control the nth intermediate node and the nth display node to be connected or disconnected under the control of the light emitting control signal.

[0388] The nth display control circuit includes an nth on-off control circuit, an nth control energy storage circuit, an nth setting circuit, an nth control compensation circuit, an nth initialization circuit, an nth first voltage providing circuit and an nth second voltage providing circuit; the nth on-off control circuit is configured to control the nth display driving control node and the nth intermediate node to be connected or disconnected under the control of the potential of the nth on-off control node; the nth setting circuit is configured to write an nth control initial voltage into the nth on-off control node and the nth write node under the control of an nth control reset signal; the nth control compensation circuit is configured to control the nth display driving control node and the nth on-off control node to be connected or disconnected under the control of an nth compensation control signal; the nth initialization circuit is configured to write a reference voltage into the nth intermediate node under the control of an nth write control signal; the nth first voltage providing circuit is configured to write an nth control data voltage into the nth write node under the control of the nth write control signal; and the nth second voltage providing circuit is configured to write a display control signal into the nth write node under the control of a light emitting control signal.

[0389] As shown in FIG. 5, based on at least one embodiment of the pixel circuit shown in FIG. 1, the first current control circuit includes a first first display driving circuit 211, a first second display driving circuit 212, a first display control circuit and a first display light emitting control circuit 213.

[0390] The first first display driving circuit 211 is electrically connected with the first display data voltage terminal DL1, the first display driving control node NQ1, the first display power voltage terminal VD1 and the light emitting control terminal EM1 respectively, and is configured to control whether to provide a first first driving current flowing from the first display power voltage terminal VD1 to the first display driving control node NQ1 according to a first display data voltage provided by the first display data voltage terminal DL1 under control of a light emitting control signal provided by the light emitting control terminal EM1;

[0391] The first second display driving circuit 212 is electrically connected with the first display data voltage terminal DL1, the first display driving control node NQ1, the first display low voltage terminal VS1 and the light emitting control terminal EM1 respectively, and is configured to control whether to provide a first second driving current flowing from the first display driving control node NQ1 to the first display low voltage terminal VS1 according to the first display data voltage under control of the light emitting control signal;

[0392] The first display light emitting control circuit 213 is electrically connected with the light emitting control terminal EM1, the first intermediate node NZ1 and the first display node NX1 respectively, and is configured to control the first intermediate node NZ1 and the first display node NX1 to be connected or disconnected under control of the light emitting control signal;

[0393] The first display control circuit includes a first on-off control circuit 311, a first control energy storage circuit 313, a first set circuit 314, a first control compensation circuit 315, a first initialization circuit 316, a first first voltage providing circuit 317 and a first second voltage providing circuit 318;

[0394] The first on-off control circuit 311 is electrically connected with the first on-off control node NT1, the first display driving control node NQ1 and the first intermediate node NZ1 respectively, and is configured to control the first display driving control node NQ1 and the first intermediate node NZ1 to be connected or disconnected under control of a potential of the first on-off control node NT1;

[0395] The first end of the first control energy storage circuit 313 is electrically connected with the first on-off control node NT1, the second end of the first control energy storage circuit 313 is electrically connected with the first write node N01, and the first control energy storage circuit 313 is configured to store electric energy;

[0396] The first setting circuit 314 is electrically connected with the first control reset end RSTC1, the first control initial voltage end CI1, the first on-off control node NT1 and the first write node N01 respectively, and is used for writing the first control initial voltage provided by the first control initial voltage end CI1 into the first on-off control node NT1 and the first write node N01 under the control of the first control reset signal provided by the first control reset end RSTC1;

[0397] The first control compensation circuit 315 is electrically connected with the first compensation control end GT1N, the first display drive control node NQ1 and the first on-off control node NT1 respectively, and is used for controlling the first display drive control node NQ1 and the first on-off control node NT1 to be connected or disconnected under the control of the first compensation control signal provided by the first compensation control end GT1N;

[0398] The first initialization circuit 316 is electrically connected with the first write control end Gat1, the reference voltage end REF and the first intermediate node NZ1 respectively, and is used for writing the reference voltage Vref provided by the reference voltage end REF into the first intermediate node NZ1 under the control of the first write control signal provided by the first write control end Gat1;

[0399] The first voltage providing circuit 317 is electrically connected with the first write control end Gat1, the first control data voltage end DTC1 and the first write node N01 respectively, and is used for writing the first control data voltage provided by the first control data voltage end DTC1 into the first write node N01 under the control of the first write control signal;

[0400] The second voltage providing circuit 318 is electrically connected with the light-emitting control end EM1, the display control end SWP and the first write node N01 respectively, and is used for writing the display control signal provided by the display control end SWP into the first write node N01 under the control of the light-emitting control signal provided by the light-emitting control end EM1;

[0401] The second current control circuit includes a second first display drive circuit 221, a second second display drive circuit 222, a second display control circuit and a second display light-emitting control circuit 223;

[0402] The second first display driving circuit 221 is electrically connected with the second display data voltage terminal DL2, the second display driving control node NQ2, the second display power voltage terminal VD2 and the light emitting control terminal EM1 respectively, and is configured to control whether to provide a second first driving current flowing from the second display power voltage terminal VD2 to the second display driving control node NQ2 according to a second display data voltage provided by the second display data voltage terminal DL2 under control of a light emitting control signal provided by the light emitting control terminal EM1;

[0403] The second second display driving circuit 222 is electrically connected with the second display data voltage terminal DL2, the second display driving control node NQ2, the second display low voltage terminal VS2 and the light emitting control terminal EM1 respectively, and is configured to control whether to provide a second second driving current flowing from the second display driving control node NQ2 to the second display low voltage terminal VS2 according to the second display data voltage under control of the light emitting control signal;

[0404] The second display light emitting control circuit 223 is electrically connected with the light emitting control terminal EM1, the second intermediate node NZ2 and the second display node NX2 respectively, and is configured to control the second intermediate node NZ2 and the second display node NX2 to be connected or disconnected under control of the light emitting control signal;

[0405] The second display control circuit includes a second on-off control circuit 321, a second control energy storage circuit 323, a second set circuit 324, a second control compensation circuit 325, a second initialization circuit 326, a second first voltage providing circuit 327 and a second second voltage providing circuit 328;

[0406] The second on-off control circuit 321 is electrically connected with the second on-off control node NT2, the second display driving control node NQ2 and the second intermediate node NZ2 respectively, and is configured to control the second display driving control node NQ2 and the second intermediate node NZ2 to be connected or disconnected under control of a potential of the second on-off control node NT2;

[0407] The first end of the second control energy storage circuit 323 is electrically connected with the second on-off control node NT2, and the second end of the second control energy storage circuit 323 is electrically connected with the second write node N02, and the second control energy storage circuit 323 is configured to store electric energy;

[0408] The second setting circuit 324 is electrically connected with the second control reset end RSTC2, the second control initial voltage end CI2, the second on-off control node NT2 and the second write node N02 respectively, for writing the second control initial voltage provided by the second control initial voltage end CI2 into the second on-off control node NT2 and the second write node N02 under the control of the second control reset signal provided by the second control reset end RSTC2;

[0409] The second control compensation circuit 325 is electrically connected with the second compensation control end GT2N, the second display drive control node NQ2 and the second on-off control node NT2 respectively, for controlling the communication or disconnection between the second display drive control node NQ2 and the second on-off control node NT2 under the control of the second compensation control signal provided by the second compensation control end GT2N;

[0410] The second initialization circuit 326 is electrically connected with the second write control end Gat2, the reference voltage end REF and the second intermediate node NZ2 respectively, for writing the reference voltage Vref provided by the reference voltage end REF into the second intermediate node NZ2 under the control of the second write control signal provided by the second write control end Gat2;

[0411] The second first voltage providing circuit 327 is electrically connected with the second write control end Gat2, the second control data voltage end DTC2 and the second write node N02 respectively, for writing the second control data voltage provided by the second control data voltage end DTC2 into the second write node N02 under the control of the second write control signal;

[0412] The second second voltage providing circuit 328 is electrically connected with the light-emitting control end EM1, the display control end SWP and the second write node N02 respectively, for writing the display control signal provided by the display control end SWP into the second write node N02 under the control of the light-emitting control signal provided by the light-emitting control end EM1;

[0413] The third current control circuit includes a third first display drive circuit 231, a third second display drive circuit 232, a third display control circuit and a third display light-emitting control circuit 233;

[0414] The third first display driving circuit 231 is electrically connected with the third display data voltage terminal DL3, the third display driving control node NQ3, the third display power voltage terminal VD3 and the light emitting control terminal EM1 respectively, and is configured to control whether to provide a third first driving current flowing from the third display power voltage terminal VD3 to the third display driving control node NQ3 according to a third display data voltage provided by the third display data voltage terminal DL3 under control of a light emitting control signal provided by the light emitting control terminal EM1;

[0415] The third second display driving circuit 232 is electrically connected with the third display data voltage terminal DL3, the third display driving control node NQ3, the third display low voltage terminal VS3 and the light emitting control terminal EM1 respectively, and is configured to control whether to provide a third second driving current flowing from the third display driving control node NQ3 to the third display low voltage terminal VS3 according to the third display data voltage under control of the light emitting control signal;

[0416] The third display light emitting control circuit 233 is electrically connected with the light emitting control terminal EM1, the third intermediate node NZ3 and the third display node NX3 respectively, and is configured to control the third intermediate node NZ3 and the third display node NX3 to be connected or disconnected under control of the light emitting control signal;

[0417] The third display control circuit includes a third on-off control circuit 331, a third control energy storage circuit 333, a third set circuit 334, a third control compensation circuit 335, a third initialization circuit 336, a third first voltage providing circuit 337 and a third second voltage providing circuit 338;

[0418] The third on-off control circuit 331 is electrically connected with the third on-off control node NT3, the third display driving control node NQ3 and the third intermediate node NZ3 respectively, and is configured to control the third display driving control node NQ3 and the third intermediate node NZ3 to be connected or disconnected under control of a potential of the third on-off control node NT3;

[0419] The first end of the third control energy storage circuit 333 is electrically connected with the third on-off control node NT3, the second end of the third control energy storage circuit 333 is electrically connected with the third write node N03, and the third control energy storage circuit 333 is configured to store electric energy;

[0420] The third setting circuit 334 is electrically connected with the third control reset end RSTC3, the third control initial voltage end CI3, the third on-off control node NT3 and the third write node N03 respectively, and is used for writing the third control initial voltage provided by the third control initial voltage end CI3 into the third on-off control node NT3 and the third write node N03 under the control of the third control reset signal provided by the third control reset end RSTC3;

[0421] The third compensation control circuit 335 is electrically connected with the third compensation control end GT3N, the third display drive control node NQ3 and the third on-off control node NT3 respectively, and is used for controlling the third display drive control node NQ3 and the third on-off control node NT3 to be connected or disconnected under the control of the third compensation control signal provided by the third compensation control end GT3N;

[0422] The third initialization circuit 336 is electrically connected with the third write control end Gat3, the reference voltage end REF and the third intermediate node NZ3 respectively, and is used for writing the reference voltage Vref provided by the reference voltage end REF into the third intermediate node NZ3 under the control of the third write control signal provided by the third write control end Gat3;

[0423] The third first voltage providing circuit 337 is electrically connected with the third write control end Gat3, the third control data voltage end DTC3 and the third write node N03 respectively, and is used for writing the third control data voltage provided by the third control data voltage end DTC3 into the third write node N03 under the control of the third write control signal;

[0424] The third second voltage providing circuit 338 is electrically connected with the light-emitting control end EM1, the display control end SWP and the third write node N03 respectively, and is used for writing the display control signal provided by the display control end SWP into the third write node N03 under the control of the light-emitting control signal provided by the light-emitting control end EM1.

[0425] In at least one embodiment of the present disclosure, the nth first display drive circuit includes an nth first drive circuit, an nth first light-emitting control circuit, an nth first compensation circuit, an nth first reset circuit, an nth first data write circuit and an nth first energy storage circuit.

[0426] The control end of the nth first drive circuit is electrically connected with the nth control node, and the nth first drive circuit is used for generating an nth first drive current under the control of the potential of the nth control node.

[0427] The nth first light-emitting control circuit is electrically connected with the light-emitting control terminal, the nth display power supply voltage terminal and the first terminal of the nth first driving circuit respectively, and is used for controlling the communication or disconnection between the nth display power supply voltage terminal and the first terminal of the nth first driving circuit under the control of the light-emitting control signal provided by the light-emitting control terminal;

[0428] The nth first compensation circuit is electrically connected with the nth compensation control terminal, the nth control node and the second terminal of the nth first driving circuit respectively, and is used for controlling the communication or disconnection between the nth control node and the second terminal of the nth first driving circuit under the control of the nth compensation control signal provided by the nth compensation control terminal;

[0429] The nth first reset circuit is electrically connected with the nth control reset terminal, the nth control initial voltage terminal and the nth control node respectively, and is used for writing the nth control initial voltage provided by the nth control initial voltage terminal into the nth control node under the control of the nth control reset signal;

[0430] The nth first data writing circuit is electrically connected with the nth writing control terminal, the nth display data voltage terminal and the first terminal of the nth first driving circuit respectively, and is used for writing the nth display data voltage provided by the nth display data voltage terminal into the first terminal of the nth first driving circuit under the control of the nth writing control signal provided by the nth writing control terminal;

[0431] The nth first energy storage circuit is electrically connected with the nth control node, and is used for maintaining the potential of the nth control node.

[0432] In a specific implementation, the nth first display driving circuit can include the nth first driving circuit, the nth first light-emitting control circuit, the nth first compensation circuit, the nth first reset circuit, the nth first data writing circuit and the nth first energy storage circuit; the nth first driving circuit generates the nth first driving current under the control of the potential of the nth control node; the nth first light-emitting control circuit controls the communication or disconnection between the nth display power supply voltage terminal and the first terminal of the nth first driving circuit under the control of the light-emitting control signal; the nth first compensation circuit controls the communication or disconnection between the nth control node and the second terminal of the nth first driving circuit under the control of the nth compensation control signal; the nth first reset circuit writes the nth control initial voltage into the nth control node under the control of the nth control reset signal; the nth first data writing circuit writes the nth display data voltage into the first terminal of the nth first driving circuit under the control of the nth writing control signal; and the nth first energy storage circuit maintains the potential of the nth control node.

[0433] In at least one embodiment of the present disclosure, the nth second display driving circuit comprises an nth second driving circuit, an nth second light emitting control circuit, an nth second compensation circuit, an nth second reset circuit, an nth second data writing circuit and an nth second energy storage circuit;

[0434] The control end of the nth second driving circuit is electrically connected with the nth inverted control node, and the nth second driving circuit is used for generating an nth second driving current under the control of the potential of the nth inverted control node;

[0435] The nth second light emitting control circuit is electrically connected with the light emitting control end, the nth display low voltage end and the first end of the nth second driving circuit respectively, and is used for controlling the communication or disconnection between the nth display low voltage end and the first end of the nth second driving circuit under the control of the light emitting control signal provided by the light emitting control end;

[0436] The nth second compensation circuit is electrically connected with the nth inverted compensation control end, the nth inverted control node and the second end of the nth second driving circuit respectively, and is used for controlling the communication or disconnection between the nth inverted control node and the second end of the nth second driving circuit under the control of the nth inverted compensation control signal provided by the nth inverted compensation control end;

[0437] The nth second reset circuit is electrically connected with the nth control reset end, the nth inverted control initial voltage end and the nth inverted control node respectively, and is used for writing the nth inverted control initial voltage provided by the nth inverted control initial voltage end into the nth inverted control node under the control of the nth control reset signal;

[0438] The nth second data writing circuit is electrically connected with the nth inverted writing control end, the nth display data voltage end and the first end of the nth second driving circuit respectively, and is used for writing the nth display data voltage provided by the nth display data voltage end into the first end of the nth second driving circuit under the control of the nth inverted writing control signal provided by the nth inverted writing control end;

[0439] The nth second energy storage circuit is electrically connected with the nth inverted control node, and is used for maintaining the potential of the nth inverted control node.

[0440] In a specific implementation, the nth second display driving circuit can include an nth second driving circuit, an nth second light emitting control circuit, an nth second compensation circuit, an nth second reset circuit, an nth second data writing circuit, and an nth second energy storage circuit; the nth second driving circuit generates an nth second driving current under the control of the potential of the nth inversion control node; the nth second light emitting control circuit controls the communication or disconnection between the nth display low voltage end and the first end of the nth second driving circuit under the control of a light emitting control signal; the nth second compensation circuit controls the communication or disconnection between the nth inversion control node and the second end of the nth second driving circuit under the control of an nth inversion compensation control signal; the nth second reset circuit writes an nth inversion control initial voltage to the nth inversion control node under the control of the nth control reset signal; the nth second data writing circuit writes an nth display data voltage to the first end of the nth second driving circuit under the control of an nth inversion writing control signal; and the nth second energy storage circuit maintains the potential of the nth inversion control node.

[0441] Optionally, the nth inversion compensation control end and the nth inversion writing control end can be the same control end.

[0442] As shown in FIG. 6A, based on at least one embodiment of the pixel circuit shown in FIG. 4, the first first display driving circuit includes a first first driving circuit 410, a first first light emitting control circuit 411, a first first compensation circuit 412, a first first reset circuit 413, a first first data writing circuit 414, and a first first energy storage circuit 415.

[0443] The control end of the first first driving circuit 410 is electrically connected with the first control node NC1, and the first first driving circuit 410 is configured to generate a first first driving current under the control of the potential of the first control node NC1.

[0444] The first first light emitting control circuit 411 is electrically connected with a light emitting control end EM1, a first display power voltage end VD1, and the first end of the first first driving circuit 410, respectively, and is configured to control the communication or disconnection between the first display power voltage end VD1 and the first end of the first first driving circuit 410 under the control of a light emitting control signal provided by the light emitting control end EM1.

[0445] The first first compensation circuit 412 is electrically connected with the first compensation control end GT1N, the first control node NC1 and the second end of the first first driving circuit 410 respectively, for controlling the first control node NC1 and the second end of the first first driving circuit 410 to be connected or disconnected under the control of the first compensation control signal provided by the first compensation control end GT1N;

[0446] The first first reset circuit 413 is electrically connected with the first control reset end RSTC1, the first control initial voltage end CI1 and the first control node NC1 respectively, for writing the first control initial voltage provided by the first control initial voltage end CI1 into the first control node NC1 under the control of the first control reset signal;

[0447] The first first data write-in circuit 414 is electrically connected with the first write-in control end Gat1, the first display data voltage end DL1 and the first end of the first first driving circuit 410 respectively, for writing the first display data voltage provided by the first display data voltage end DL1 into the first end of the first first driving circuit 410 under the control of the first write-in control signal provided by the first write-in control end Gat1;

[0448] The first first energy storage circuit 415 is electrically connected with the first control node NC1, for maintaining the potential of the first control node NC1;

[0449] The first second display driving circuit comprises a first second driving circuit 510, a first second light-emitting control circuit 511, a first second compensation circuit 512, a first second reset circuit 513, a first second data write-in circuit 514 and a first second energy storage circuit 515;

[0450] The control end of the first second driving circuit 510 is electrically connected with the first inverting control node NF1, and the first second driving circuit 510 is used for generating a first second driving current under the control of the potential of the first inverting control node NF1;

[0451] The first second light-emitting control circuit 511 is electrically connected with the light-emitting control end EM1, the first display low voltage end VS1 and the first end of the first second driving circuit 510 respectively, for controlling the first display low voltage end VS1 and the first end of the first second driving circuit 510 to be connected or disconnected under the control of the light-emitting control signal provided by the light-emitting control end EM1;

[0452] The first second compensation circuit 512 is electrically connected with the first inverting compensation control end GT1B, the first inverting control node NF1 and the second end of the first second driving circuit 510 respectively, for controlling the first inverting control node NF1 and the second end of the first second driving circuit 510 to be connected or disconnected under the control of the first inverting compensation control signal provided by the first inverting compensation control end GT1B;

[0453] The first second reset circuit 513 is electrically connected with the first control reset end RSTC1, the first inverting control initial voltage end CIN1 and the first inverting control node NF1 respectively, for writing the first inverting control initial voltage provided by the first inverting control initial voltage end CIN1 into the first inverting control node NF1 under the control of the first control reset signal;

[0454] The first second data write-in circuit 514 is electrically connected with the first inverting write-in control end Gat1B, the first display data voltage end DL1 and the first end of the first second driving circuit 510 respectively, for writing the first display data voltage provided by the first display data voltage end DL1 into the first end of the first second driving circuit 510 under the control of the first inverting write-in control signal provided by the first inverting write-in control end Gat1B;

[0455] The first second energy storage circuit 515 is electrically connected with the first inverting control node NF1, for maintaining the potential of the first inverting control node NF1;

[0456] The second first display driving circuit comprises a second first driving circuit 420, a second first light-emitting control circuit 421, a second first compensation circuit 422, a second first reset circuit 423, a second first data write-in circuit 424 and a second first energy storage circuit 425.

[0457] The control end of the second first driving circuit 420 is electrically connected with the second control node NC2, and the second first driving circuit 420 is used for generating a second first driving current under the control of the potential of the second control node NC2.

[0458] The second first light-emitting control circuit 421 is electrically connected with the light-emitting control end EM1, the second display power supply voltage end VD2 and the first end of the second first driving circuit 420 respectively, for controlling the second display power supply voltage end VD2 and the first end of the second first driving circuit 420 to be connected or disconnected under the control of the light-emitting control signal provided by the light-emitting control end EM1.

[0459] The second first compensation circuit 422 is electrically connected with the second compensation control end GT2N, the second control node NC2 and the second end of the second first driving circuit 420 respectively, and is used for controlling the second control node NC2 and the second end of the second first driving circuit 420 to be connected or disconnected under the control of the second compensation control signal provided by the second compensation control end GT2N;

[0460] The second first reset circuit 423 is electrically connected with the second control reset end RSTC2, the second control initial voltage end CI2 and the second control node NC2 respectively, and is used for writing the second control initial voltage provided by the second control initial voltage end CI2 into the second control node NC2 under the control of the second control reset signal;

[0461] The second first data write-in circuit 424 is electrically connected with the second write-in control end Gat2, the second display data voltage end DL2 and the first end of the second first driving circuit 420 respectively, and is used for writing the second display data voltage provided by the second display data voltage end DL2 into the first end of the second first driving circuit 420 under the control of the second write-in control signal provided by the second write-in control end Gat2;

[0462] The second first energy storage circuit 425 is electrically connected with the second control node NC2, and is used for maintaining the potential of the second control node NC2;

[0463] The second second display driving circuit comprises a second second driving circuit 520, a second second light-emitting control circuit 521, a second second compensation circuit 522, a second second reset circuit 523, a second second data write-in circuit 524 and a second second energy storage circuit 525;

[0464] The control end of the second second driving circuit 520 is electrically connected with the second inverting control node NF2, and the second second driving circuit 520 is used for generating a second second driving current under the control of the potential of the second inverting control node NF2;

[0465] The second second light-emitting control circuit 521 is electrically connected with the light-emitting control end EM1, the second display low voltage end VS2 and the first end of the second second driving circuit 520 respectively, and is used for controlling the second display low voltage end VS2 and the first end of the second second driving circuit 520 to be connected or disconnected under the control of the light-emitting control signal provided by the light-emitting control end EM1;

[0466] The second second compensation circuit 522 is electrically connected with the second inverting compensation control end GT2B, the second inverting control node NF2 and the second end of the second second driving circuit 520 respectively, for controlling the second inverting control node NF2 and the second end of the second second driving circuit 520 to be connected or disconnected under the control of the second inverting compensation control signal provided by the second inverting compensation control end GT2B;

[0467] The second second reset circuit 523 is electrically connected with the second control reset end RSTC2, the second inverting control initial voltage end CIN2 and the second inverting control node NF2 respectively, for writing the second inverting control initial voltage provided by the second inverting control initial voltage end CIN2 into the second inverting control node NF2 under the control of the second control reset signal;

[0468] The second second data write-in circuit 524 is electrically connected with the second inverting write-in control end Gat2B, the second display data voltage end DL2 and the first end of the second second driving circuit 520 respectively, for writing the second display data voltage provided by the second display data voltage end DL2 into the first end of the second second driving circuit 520 under the control of the second inverting write-in control signal provided by the second inverting write-in control end Gat2B;

[0469] The second second energy storage circuit 525 is electrically connected with the second inverting control node NF2, for maintaining the potential of the second inverting control node NF2;

[0470] The third first display driving circuit comprises a third first driving circuit 430, a third first light emitting control circuit 431, a third first compensation circuit 432, a third first reset circuit 433, a third first data write-in circuit 434 and a third first energy storage circuit 435;

[0471] The control end of the third first driving circuit 430 is electrically connected with the third control node NC3, and the third first driving circuit 430 is used for generating a third first driving current under the control of the potential of the third control node NC3;

[0472] The third first light emitting control circuit 431 is electrically connected with the light emitting control end EM1, the third display power supply voltage end VD3 and the first end of the third first driving circuit 430 respectively, for controlling the third display power supply voltage end VD3 and the first end of the third first driving circuit 430 to be connected or disconnected under the control of the light emitting control signal provided by the light emitting control end EM1;

[0473] The third first compensation circuit 432 is electrically connected with the third compensation control end GT3N, the third control node NC3 and the second end of the third first driving circuit 430 respectively, for controlling the third control node NC3 and the second end of the third first driving circuit 430 to be connected or disconnected under the control of the third compensation control signal provided by the third compensation control end GT3N;

[0474] The third first reset circuit 433 is electrically connected with the third control reset end RSTC3, the third control initial voltage end CI3 and the third control node NC3 respectively, for writing the third control initial voltage provided by the third control initial voltage end CI3 into the third control node NC3 under the control of the third control reset signal;

[0475] The third first data write-in circuit 434 is electrically connected with the third write-in control end Gat3, the third display data voltage end DL3 and the first end of the third first driving circuit 430 respectively, for writing the third display data voltage provided by the third display data voltage end DL3 into the first end of the third first driving circuit 430 under the control of the third write-in control signal provided by the third write-in control end Gat3;

[0476] The third first energy storage circuit 435 is electrically connected with the third control node NC3, for maintaining the potential of the third control node NC3;

[0477] The third second display driving circuit comprises a third second driving circuit 530, a third second light-emitting control circuit 531, a third second compensation circuit 532, a third second reset circuit 533, a third second data write-in circuit 534 and a third second energy storage circuit 535;

[0478] The control end of the third second driving circuit 530 is electrically connected with the third inverting control node NF3, and the third second driving circuit 530 is used for generating a third second driving current under the control of the potential of the third inverting control node NF3;

[0479] The third second light-emitting control circuit 531 is electrically connected with the light-emitting control end EM1, the third display low voltage end VS3 and the first end of the third second driving circuit 530 respectively, for controlling the third display low voltage end VS3 and the first end of the third second driving circuit 530 to be connected or disconnected under the control of the light-emitting control signal provided by the light-emitting control end EM1;

[0480] The third second compensation circuit 532 is electrically connected with the third inverting compensation control end GT3B, the third inverting control node NF3 and the second end of the third second driving circuit 530 respectively, for controlling the third inverting control node NF3 and the second end of the third second driving circuit 530 to be connected or disconnected under the control of the third inverting compensation control signal provided by the third inverting compensation control end GT3B;

[0481] The third second reset circuit 533 is electrically connected with the third control reset end RSTC3, the third inverting control initial voltage end CIN3 and the third inverting control node NF3 respectively, for writing the third inverting control initial voltage provided by the third inverting control initial voltage end CIN3 into the third inverting control node NF3 under the control of the third control reset signal;

[0482] The third second data writing circuit 534 is electrically connected with the third inverting writing control end Gat3B, the third display data voltage end DL3 and the first end of the third second driving circuit 530 respectively, for writing the third display data voltage provided by the third display data voltage end DL3 into the first end of the third second driving circuit 530 under the control of the third inverting writing control signal provided by the third inverting writing control end Gat3B;

[0483] The third second energy storage circuit 535 is electrically connected with the third inverting control node NF3, for maintaining the potential of the third inverting control node NF3.

[0484] FIG. 6B is a structural diagram of the first first display driving circuit, the first second display driving circuit and the first display control circuit in FIG. 6A;

[0485] FIG. 6C is a structural diagram of the second first display driving circuit, the second second display driving circuit and the second display control circuit in FIG. 6A;

[0486] FIG. 6D is a structural diagram of the third first display driving circuit, the third second display driving circuit and the third display control circuit in FIG. 6A.

[0487] On the basis of at least one embodiment of the pixel circuit shown in FIG. 5,

[0488] As shown in FIG. 7A, the first first display driving circuit includes the first first driving circuit 410, the first first light-emitting control circuit 411, the first first compensation circuit 412, the first first reset circuit 413, the first first data writing circuit 414 and the first first energy storage circuit 415.

[0489] A first control end of the first driving circuit 410 is electrically connected with a first control node NC1, and the first driving circuit 410 is configured to generate a first driving current under the control of a potential of the first control node NC1; a second end of the first driving circuit 410 is electrically connected with NQ1;

[0490] The first light emitting control circuit 411 is electrically connected with a first display power voltage end VD1, a first end of the first driving circuit 410, and a light emitting control end EM1, respectively, and is configured to control the first display power voltage end VD1 and the first end of the first driving circuit 410 to be connected or disconnected under the control of a light emitting control signal provided by the light emitting control end EM1;

[0491] The first compensation circuit 412 is electrically connected with the first control node NC1, a second end of the first driving circuit 410, and a first compensation control end GT1N, respectively, and is configured to control the first control node NC1 and the second end of the first driving circuit 410 to be connected or disconnected under the control of a first compensation control signal provided by the first compensation control end GT1N;

[0492] The first reset circuit 413 is electrically connected with the first control node NC1, a first control initial voltage end CI1, and a first control reset end RSTC1, respectively, and is configured to write a first control initial voltage provided by the first control initial voltage end CI1 into the first control node NC1 under the control of a first control reset signal;

[0493] The first data writing circuit 414 is electrically connected with the first driving circuit 410, a first display data voltage end DL1, and a first writing control end Gat1, respectively, and is configured to write a first display data voltage provided by the first display data voltage end DL1 into the first end of the first driving circuit 410 under the control of a first writing control signal provided by the first writing control end Gat1;

[0494] The first energy storage circuit 415 is electrically connected with the first control node NC1, and is configured to maintain the potential of the first control node NC1;

[0495] The first second display driving circuit includes a first second driving circuit 510, a first second light emitting control circuit 511, a first second compensation circuit 512, a first second reset circuit 513, a first second data writing circuit 514, and a first second energy storage circuit 515;

[0496] A control terminal of the first second driving circuit 510 is electrically connected with the first inverting control node NF1, and the first second driving circuit 510 is used for generating a first second driving current under the control of the potential of the first inverting control node NF1.

[0497] The first second light emitting control circuit 511 is electrically connected with the light emitting control terminal EM1, the first display low voltage terminal VS1 and the first terminal of the first second driving circuit 510 respectively, and is used for controlling the communication or disconnection between the first display low voltage terminal VS1 and the first terminal of the first second driving circuit 510 under the control of the light emitting control signal provided by the light emitting control terminal EM1.

[0498] The first second compensation circuit 512 is electrically connected with the first inverting compensation control terminal GT1B, the first inverting control node NF1 and the second terminal of the first second driving circuit 510 respectively, and is used for controlling the communication or disconnection between the first inverting control node NF1 and the second terminal of the first second driving circuit 510 under the control of the first inverting compensation control signal provided by the first inverting compensation control terminal GT1B.

[0499] The first second reset circuit 513 is electrically connected with the first control reset terminal RSTC1, the first inverting control initial voltage terminal CIN1 and the first inverting control node NF1 respectively, and is used for writing the first inverting control initial voltage provided by the first inverting control initial voltage terminal CIN1 into the first inverting control node NF1 under the control of the first control reset signal.

[0500] The first second data writing circuit 514 is electrically connected with the first inverting writing control terminal Gat1B, the first display data voltage terminal DL1 and the first terminal of the first second driving circuit 510 respectively, and is used for writing the first display data voltage provided by the first display data voltage terminal DL1 into the first terminal of the first second driving circuit 510 under the control of the first inverting writing control signal provided by the first inverting writing control terminal Gat1B.

[0501] The first second energy storage circuit 515 is electrically connected with the first inverting control node NF1, and is used for maintaining the potential of the first inverting control node NF1.

[0502] On the basis of at least one embodiment of the pixel circuit shown in FIG. 5,

[0503] As shown in FIG. 7B, the second first display driving circuit includes a second first driving circuit 420, a second first light emitting control circuit 421, a second first compensation circuit 422, a second first reset circuit 423, a second first data writing circuit 424 and a second first energy storage circuit 425.

[0504] A control terminal of the second first driving circuit 420 is electrically connected with the second control node NC2, and the second first driving circuit 420 is configured to generate a second first driving current under the control of a potential of the second control node NC2;

[0505] The second first light emitting control circuit 421 is electrically connected with the light emitting control terminal EM1, the second display power voltage terminal VD2 and the first terminal of the second first driving circuit 420 respectively, and is configured to control the second display power voltage terminal VD2 and the first terminal of the second first driving circuit 420 to be connected or disconnected under the control of a light emitting control signal provided by the light emitting control terminal EM1;

[0506] The second first compensation circuit 422 is electrically connected with the second compensation control terminal GT2N, the second control node NC2 and the second terminal of the second first driving circuit 420 respectively, and is configured to control the second control node NC2 and the second terminal of the second first driving circuit 420 to be connected or disconnected under the control of a second compensation control signal provided by the second compensation control terminal GT2N;

[0507] The second first reset circuit 423 is electrically connected with the second control reset terminal RSTC2, the second control initial voltage terminal CI2 and the second control node NC2 respectively, and is configured to write a second control initial voltage provided by the second control initial voltage terminal CI2 into the second control node NC2 under the control of the second control reset signal;

[0508] The second first data writing circuit 424 is electrically connected with the second writing control terminal Gat2, the second display data voltage terminal DL2 and the first terminal of the second first driving circuit 420 respectively, and is configured to write a second display data voltage provided by the second display data voltage terminal DL2 into the first terminal of the second first driving circuit 420 under the control of a second writing control signal provided by the second writing control terminal Gat2;

[0509] The second first energy storage circuit 425 is electrically connected with the second control node NC2, and is configured to maintain the potential of the second control node NC2;

[0510] The second second display driving circuit includes a second second driving circuit 520, a second second light emitting control circuit 521, a second second compensation circuit 522, a second second reset circuit 523, a second second data writing circuit 524 and a second second energy storage circuit 525;

[0511] A control terminal of the second second driving circuit 520 is electrically connected with the second inverting control node NF2, and the second second driving circuit 520 is used for generating a second second driving current under the control of the potential of the second inverting control node NF2.

[0512] The second second light emitting control circuit 521 is electrically connected with the light emitting control terminal EM1, the second display low voltage terminal VS2 and the first terminal of the second second driving circuit 520 respectively, and is used for controlling the communication or disconnection between the second display low voltage terminal VS2 and the first terminal of the second second driving circuit 520 under the control of the light emitting control signal provided by the light emitting control terminal EM1.

[0513] The second second compensation circuit 522 is electrically connected with the second inverting compensation control terminal GT2B, the second inverting control node NF2 and the second terminal of the second second driving circuit 520 respectively, and is used for controlling the communication or disconnection between the second inverting control node NF2 and the second terminal of the second second driving circuit 520 under the control of the second inverting compensation control signal provided by the second inverting compensation control terminal GT2B.

[0514] The second second reset circuit 523 is electrically connected with the second control reset terminal RSTC2, the second inverting control initial voltage terminal CIN2 and the second inverting control node NF2 respectively, and is used for writing the second inverting control initial voltage provided by the second inverting control initial voltage terminal CIN2 into the second inverting control node NF2 under the control of the second control reset signal.

[0515] The second second data writing circuit 524 is electrically connected with the second inverting writing control terminal Gat2B, the second display data voltage terminal DL2 and the first terminal of the second second driving circuit 520 respectively, and is used for writing the second display data voltage provided by the second display data voltage terminal DL2 into the first terminal of the second second driving circuit 520 under the control of the second inverting writing control signal provided by the second inverting writing control terminal Gat2B.

[0516] The second second energy storage circuit 525 is electrically connected with the second inverting control node NF2, and is used for maintaining the potential of the second inverting control node NF2.

[0517] On the basis of at least one embodiment of the pixel circuit shown in FIG. 5,

[0518] As shown in FIG. 7C, the third first display driving circuit includes a third first driving circuit 430, a third first light emitting control circuit 431, a third first compensation circuit 432, a third first reset circuit 433, a third first data writing circuit 434 and a third first energy storage circuit 435.

[0519] A control terminal of the third first driving circuit 430 is electrically connected with a third control node NC3, and the third first driving circuit 430 is configured to generate a third first driving current under the control of a potential of the third control node NC3;

[0520] The third first light emitting control circuit 431 is electrically connected with the light emitting control terminal EM1, a third display power voltage terminal VD3 and a first terminal of the third first driving circuit 430 respectively, and is configured to control the third display power voltage terminal VD3 and the first terminal of the third first driving circuit 430 to be connected or disconnected under the control of a light emitting control signal provided by the light emitting control terminal EM1;

[0521] The third first compensation circuit 432 is electrically connected with a third compensation control terminal GT3N, the third control node NC3 and a second terminal of the third first driving circuit 430 respectively, and is configured to control the third control node NC3 and the second terminal of the third first driving circuit 430 to be connected or disconnected under the control of a third compensation control signal provided by the third compensation control terminal GT3N;

[0522] The third first reset circuit 433 is electrically connected with a third control reset terminal RSTC3, a third control initial voltage terminal CI3 and the third control node NC3 respectively, and is configured to write a third control initial voltage provided by the third control initial voltage terminal CI3 into the third control node NC3 under the control of a third control reset signal;

[0523] The third first data writing circuit 434 is electrically connected with a third writing control terminal Gat3, a third display data voltage terminal DL3 and the first terminal of the third first driving circuit 430 respectively, and is configured to write a third display data voltage provided by the third display data voltage terminal DL3 into the first terminal of the third first driving circuit 430 under the control of a third writing control signal provided by the third writing control terminal Gat3;

[0524] The third first energy storage circuit 435 is electrically connected with the third control node NC3, and is configured to maintain the potential of the third control node NC3;

[0525] The third second display driving circuit includes a third second driving circuit 530, a third second light emitting control circuit 531, a third second compensation circuit 532, a third second reset circuit 533, a third second data writing circuit 534 and a third second energy storage circuit 535;

[0526] A third second driving circuit 530 has a control terminal electrically connected to the third inverting control node NF3, and is configured to generate a third second driving current under the control of the potential of the third inverting control node NF3.

[0527] A third second light emitting control circuit 531 is electrically connected to the light emitting control terminal EM1, the third display low voltage terminal VS3 and the first terminal of the third second driving circuit 530, and is configured to control the communication or disconnection between the third display low voltage terminal VS3 and the first terminal of the third second driving circuit 530 under the control of a light emitting control signal provided by the light emitting control terminal EM1.

[0528] The third second compensation circuit 532 is electrically connected to the third inverting compensation control terminal GT3B, the third inverting control node NF3 and the second terminal of the third second driving circuit 530, and is configured to control the communication or disconnection between the third inverting control node NF3 and the second terminal of the third second driving circuit 530 under the control of a third inverting compensation control signal provided by the third inverting compensation control terminal GT3B.

[0529] The third second reset circuit 533 is electrically connected to the third control reset terminal RSTC3, the third inverting control initial voltage terminal CIN3 and the third inverting control node NF3, and is configured to write a third inverting control initial voltage provided by the third inverting control initial voltage terminal CIN3 into the third inverting control node NF3 under the control of the third control reset signal.

[0530] The third second data writing circuit 534 is electrically connected to the third inverting writing control terminal Gat3B, the third display data voltage terminal DL3 and the first terminal of the third second driving circuit 530, and is configured to write a third display data voltage provided by the third display data voltage terminal DL3 into the first terminal of the third second driving circuit 530 under the control of a third inverting writing control signal provided by the third inverting writing control terminal Gat3B.

[0531] The third second energy storage circuit 535 is electrically connected to the third inverting control node NF3, and is configured to maintain the potential of the third inverting control node NF3.

[0532] In at least one embodiment of the present disclosure, the pixel driving circuit includes a driving circuit, a data writing circuit, a display energy storage circuit, a compensation control circuit, a first reset circuit, a first display light emitting control circuit, a second display light emitting control circuit, a display control circuit, a control reset circuit and a node control circuit.

[0533] The driving circuit is electrically connected with the driving node, and is configured to generate the driving current under control of a potential of the driving node.

[0534] The data writing circuit is electrically connected with the display scanning end, the data voltage end and the first end of the driving circuit respectively, and is configured to write a data voltage provided by the data voltage end into the first end of the driving circuit under control of a display scanning signal provided by the display scanning end.

[0535] The display energy storage circuit is electrically connected with the driving node, and is configured to maintain the potential of the driving node.

[0536] The compensation control circuit is electrically connected with the compensation control end, the driving node and the second end of the driving circuit respectively, and is configured to control the driving node and the second end of the driving circuit to be connected or disconnected under control of a compensation control signal provided by the compensation control end.

[0537] The first reset circuit is electrically connected with the reset control end, the display initial voltage end and the driving node respectively, and is configured to write a display initial voltage provided by the display initial voltage end into the driving node under control of a reset control signal provided by the reset control end.

[0538] The first display light emitting control circuit is electrically connected with the light emitting control end, the power voltage end and the first end of the driving circuit respectively, and is configured to control the power voltage end and the first end of the driving circuit to be connected or disconnected under control of a light emitting control signal provided by the light emitting control end.

[0539] The second display light emitting control circuit is electrically connected with the light emitting control end, the second end of the driving circuit and the light emitting control node respectively, and is configured to control the second end of the driving circuit and the light emitting control node to be connected or disconnected under control of the light emitting control signal.

[0540] The display control circuit is electrically connected with the display control node, the light emitting control node and the driving current output end respectively, and is configured to control the light emitting control node and the driving current output end to be connected or disconnected under control of a potential of the display control node.

[0541] The control reset circuit is electrically connected with the display scanning end, the reference voltage end and the light emitting control node respectively, and is configured to write a reference voltage provided by the reference voltage end into the light emitting control node under control of the display scanning signal.

[0542] The node control circuit is electrically connected with the display control node, the display control data voltage end and the display control end respectively, and is configured to control a potential of the display control node according to a display control data voltage provided by the display control data voltage end and the display control signal.

[0543] In a specific implementation, the pixel driving circuit can include a driving circuit, a data writing circuit, a display energy storage circuit, a compensation control circuit, a first reset circuit, a first display light emitting control circuit, a second display light emitting control circuit, a display control circuit, a control reset circuit and a node control circuit. The driving circuit generates the driving current under the control of the potential of the driving node. The data writing circuit writes the data voltage into the first end of the driving circuit under the control of a display scanning signal. The display energy storage circuit maintains the potential of the driving node. The compensation control circuit controls the communication or disconnection between the driving node and the second end of the driving circuit under the control of a compensation control signal. The first reset circuit writes a display initial voltage into the driving node under the control of a reset control signal. The first display light emitting control circuit controls the communication or disconnection between the power voltage end and the first end of the driving circuit under the control of a light emitting control signal. The second display light emitting control circuit controls the communication or disconnection between the second end of the driving circuit and the light emitting control node under the control of the light emitting control signal. The display control circuit controls the communication or disconnection between the light emitting control node and the driving current output end under the control of the potential of the display control node. The control reset circuit writes a reference voltage into the light emitting control node under the control of the display scanning signal. The node control circuit controls the potential of the display control node according to the display control data voltage and the display control signal.

[0544] As shown in FIG. 8, on the basis of at least one embodiment of the pixel circuit shown in FIG. 5, the pixel driving circuit includes a driving circuit 40, a data writing circuit 41, a display energy storage circuit 42, a compensation control circuit 43, a first reset circuit 44, a first display light emitting control circuit 451, a second display light emitting control circuit 452, a display control circuit 46, a control reset circuit 48 and a node control circuit 47.

[0545] The driving circuit 40 is electrically connected with the driving node N1, and is configured to generate the driving current under the control of the potential of the driving node N1.

[0546] The data writing circuit 41 is electrically connected with a display scanning end Gat, a data voltage end DA1 and the first end of the driving circuit 40 respectively, and is configured to write the data voltage provided by the data voltage end DA1 into the first end of the driving circuit 40 under the control of a display scanning signal provided by the display scanning end Gat.

[0547] The display energy storage circuit 42 is electrically connected with the driving node N1, for maintaining the potential of the driving node N1;

[0548] The compensation control circuit 43 is electrically connected with the compensation control end Gat1N, the driving node N1 and the second end of the driving circuit 40 respectively, for controlling the communication or disconnection between the driving node N1 and the second end of the driving circuit 40 under the control of the compensation control signal provided by the compensation control end Gat1N;

[0549] The first reset circuit 44 is electrically connected with the reset control end RST1, the display initial voltage end I1 and the driving node N1 respectively, for writing the display initial voltage provided by the display initial voltage end I1 into the driving node N1 under the control of the reset control signal provided by the reset control end RST1;

[0550] The first display light emitting control circuit 451 is electrically connected with the light emitting control end EM1, the power voltage end VDD1 and the first end of the driving circuit 40 respectively, for controlling the communication or disconnection between the power voltage end VDD1 and the first end of the driving circuit 40 under the control of the light emitting control signal provided by the light emitting control end EM1;

[0551] The second display light emitting control circuit 452 is electrically connected with the light emitting control end EM1, the second end of the driving circuit 40 and the light emitting control node NE respectively, for controlling the communication or disconnection between the second end of the driving circuit 40 and the light emitting control node NE under the control of the light emitting control signal;

[0552] The display control circuit 46 is electrically connected with the display control node SX, the light emitting control node NE and the driving current output end OT respectively, for controlling the communication or disconnection between the light emitting control node NE and the driving current output end OT under the control of the potential of the display control node SX;

[0553] The control reset circuit 48 is electrically connected with the display scanning end Gat, the reference voltage end REF and the light emitting control node NE respectively, for writing the reference voltage Vref provided by the reference voltage end REF into the light emitting control node NE under the control of the display scanning signal;

[0554] The node control circuit 47 is electrically connected with the display control node SX, the display control data voltage end DAT and the display control end SWP respectively, for controlling the potential of the display control node SX according to the display control data voltage provided by the display control data voltage end DAT and the display control signal.

[0555] In at least one embodiment of the present disclosure, the node control circuit comprises a display control storage circuit, a first write control circuit, a second write control circuit, a control set circuit and a control compensation control circuit;

[0556] A first end of the display control storage circuit is electrically connected to the display control node, and a second end of the display control storage circuit is electrically connected to a display write node;

[0557] The first write control circuit is electrically connected to a display scanning end, a display control data voltage end and the display write node respectively, and is used for writing the display control data voltage into the display write node under the control of the display scanning signal;

[0558] The second write control circuit is electrically connected to a light-emitting control end, the display control end and the display write node respectively, and is used for writing the display control signal into the display write node under the control of the light-emitting control signal provided by the light-emitting control end;

[0559] The control set circuit is electrically connected to a reset control end, a display initial voltage end, the display control node and the display write node respectively, and is used for writing the display initial voltage provided by the display initial voltage end into the display control node and the display write node under the control of the reset control signal provided by the reset control end;

[0560] The control compensation control circuit is electrically connected to a compensation control end, the driving current output end and the display control node respectively, and is used for controlling the driving current output end and the display control node to be connected or disconnected under the control of the compensation control signal provided by the compensation control end.

[0561] As shown in FIG. 9, on the basis of at least one embodiment of the pixel circuit shown in FIG. 8, the node control circuit comprises a display control storage circuit 61, a first write control circuit 62, a second write control circuit 62, a control set circuit 64 and a control compensation control circuit 65;

[0562] A first end of the display control storage circuit 61 is electrically connected to the display control node SX, and a second end of the display control storage circuit 61 is electrically connected to a display write node ND;

[0563] The first write control circuit 62 is electrically connected to a display scanning end Gat, a display control data voltage end DAT and the display write node ND respectively, and is used for writing the display control data voltage provided by the display control data voltage end DAT into the display write node ND under the control of the display scanning signal;

[0564] The second write control circuit 63 is electrically connected with the light emitting control end EM1, the display control end SWP and the display write node ND respectively, and is configured to write the display control signal into the display write node ND under the control of the light emitting control signal provided by the light emitting control end EM1.

[0565] The control setting circuit 64 is electrically connected with the reset control end RST1, the display initial voltage end I1, the display control node SX and the display write node ND respectively, and is configured to write the display initial voltage Vinit1 provided by the display initial voltage end I1 into the display control node SX and the display write node ND under the control of the reset control signal provided by the reset control end RST1.

[0566] The control compensation control circuit 65 is electrically connected with the compensation control end Gat1N, the driving current output end OT and the display control node SX respectively, and is configured to control the driving current output end OT and the display control node SX to be connected or disconnected under the control of the compensation control signal provided by the compensation control end Gat1N.

[0567] The pixel circuit in at least one embodiment of the present disclosure further comprises a third display light emitting control circuit.

[0568] The third display light emitting control circuit is electrically connected with the light emitting control end, the display control circuit and the driving current output end respectively, and is configured to control the display control circuit and the driving current output end to be connected or disconnected under the control of the light emitting control signal.

[0569] In specific implementation, the pixel circuit can further comprise a third display light emitting control circuit, which controls the display control circuit and the driving current output end to be connected or disconnected under the control of the light emitting control signal.

[0570] As shown in FIG. 10, on the basis of at least one embodiment of the pixel circuit shown in FIG. 9, the pixel circuit in at least one embodiment of the present disclosure further comprises a third display light emitting control circuit 66.

[0571] The third display light emitting control circuit 66 is electrically connected with the light emitting control end EM1, the display control circuit 46 and the driving current output end OT respectively, and is configured to control the display control circuit 46 and the driving current output end OT to be connected or disconnected under the control of the light emitting control signal.

[0572] In at least one embodiment of the present disclosure, the nth current control circuit comprises an nth first display driving circuit, an nth first display driving circuit and an nth display control circuit; the display control end comprises a first display control end and a second display control end;

[0573] The nth first display driving circuit is electrically connected with the nth display data voltage terminal, the nth display driving control node, the nth display power voltage terminal, the light emitting control terminal and the first display control terminal respectively, and is configured to control whether to provide the nth first driving current flowing from the nth display power voltage terminal to the nth display driving control node under control of a light emitting control signal provided by the light emitting control terminal, according to a first display control signal provided by the first display control terminal and the nth display data voltage provided by the nth display data voltage terminal.

[0574] The nth second display driving circuit is electrically connected with the nth display data voltage terminal, the nth display driving control node, the nth display low voltage terminal, the light emitting control terminal and the second display control terminal respectively, and is configured to control whether to provide the nth second driving current flowing from the nth display driving control node to the nth display low voltage terminal under control of the light emitting control signal, according to a second display control signal provided by the second display control terminal and the nth display data voltage.

[0575] The nth display control circuit is electrically connected with the light emitting control terminal, the nth display node and the nth display driving control node respectively, and is configured to control the communication or disconnection between the nth display node and the nth display driving control node under control of the light emitting control signal.

[0576] In a specific implementation, the nth current control circuit can include the nth first display driving circuit, the nth first display driving circuit and the nth display control circuit; the display control terminal can include the first display control terminal and the second display control terminal; the nth first display driving circuit controls whether to provide the nth first driving current under control of the light emitting control signal, according to the first display control signal and the nth display data voltage; the nth second display driving circuit controls whether to provide the nth second driving current under control of the light emitting control signal, according to the second display control signal and the nth display data voltage; and the nth display control circuit controls the communication or disconnection between the nth display node and the nth display driving control node under control of the light emitting control signal.

[0577] As shown in FIG. 11, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the first current control circuit includes the first first display driving circuit 211, the first first display driving circuit 212 and the first display control circuit 210; and the display control terminal includes the first display control terminal SWP1 and the second display control terminal SWP2.

[0578] The first first display driving circuit 211 is electrically connected with the first display data voltage terminal DL1, the first display driving control node NQ1, the first display power voltage terminal VD1, the light emitting control terminal EM1 and the first display control terminal SWP1 respectively, and is configured to control whether to provide a first first driving current flowing from the first display power voltage terminal VD1 to the first display driving control node NQ1 under control of a light emitting control signal provided by the light emitting control terminal EM1 according to a first display control signal provided by the first display control terminal SWP1 and a first display data voltage provided by the first display data voltage terminal DL1;

[0579] The first second display driving circuit 212 is electrically connected with the first display data voltage terminal DL1, the first display driving control node NQ1, the first display low voltage terminal VS1, the light emitting control terminal EM1 and the second display control terminal SWP2 respectively, and is configured to control whether to provide a first second driving current flowing from the first display driving control node NQ1 to the first display low voltage terminal VS1 under control of the light emitting control signal according to a second display control signal provided by the second display control terminal SWP2 and the first display data voltage;

[0580] The first display control circuit 210 is electrically connected with the light emitting control terminal EM1, the first display node NX1 and the first display driving control node NQ1 respectively, and is configured to control the first display node NX1 and the first display driving control node NQ1 to be connected or disconnected under control of the light emitting control signal;

[0581] The second current control circuit includes a second first display driving circuit 221, a second first display driving circuit 222 and a second display control circuit 220.

[0582] The second first display driving circuit 221 is electrically connected with the second display data voltage terminal DL2, the second display driving control node NQ2, the second display power voltage terminal VD2, the light emitting control terminal EM1 and the first display control terminal SWP1 respectively, and is configured to control whether to provide a second first driving current flowing from the second display power voltage terminal VD2 to the second display driving control node NQ2 under control of a light emitting control signal provided by the light emitting control terminal EM1 according to a first display control signal provided by the first display control terminal SWP1 and a second display data voltage provided by the second display data voltage terminal DL2;

[0583] The second second display driving circuit 222 is electrically connected with the second display data voltage terminal DL2, the second display driving control node NQ2, the second display low voltage terminal VS2, the light emitting control terminal EM1 and the second display control terminal SWP2 respectively, and is configured to control whether to provide a second second driving current flowing from the second display driving control node NQ2 to the second display low voltage terminal VS2 under the control of the light emitting control signal according to the second display control signal provided by the second display control terminal SWP2 and the second display data voltage;

[0584] The second display control circuit 220 is electrically connected with the light emitting control terminal EM, the second display node NX2 and the second display driving control node NQ2 respectively, and is configured to control the second display node NX2 and the second display driving control node NQ2 to be connected or disconnected under the control of the light emitting control signal;

[0585] The third current control circuit includes a third first display driving circuit 231, a third first display driving circuit 232 and a third display control circuit 230.

[0586] The third first display driving circuit 231 is electrically connected with the third display data voltage terminal DL3, the third display driving control node NQ3, the third display power voltage terminal VD3, the light emitting control terminal EM1 and the first display control terminal SWP1 respectively, and is configured to control whether to provide a third first driving current flowing from the third display power voltage terminal VD3 to the third display driving control node NQ3 under the control of the light emitting control signal provided by the light emitting control terminal EM1 according to the first display control signal provided by the first display control terminal SWP1 and the third display data voltage provided by the third display data voltage terminal DL3;

[0587] The third second display driving circuit 232 is electrically connected with the third display data voltage terminal DL3, the third display driving control node NQ3, the third display low voltage terminal VS3, the light emitting control terminal EM1 and the second display control terminal SWP2 respectively, and is configured to control whether to provide a third second driving current flowing from the third display driving control node NQ3 to the third display low voltage terminal VS3 under the control of the light emitting control signal according to the second display control signal provided by the second display control terminal SWP2 and the third display data voltage;

[0588] The third display control circuit 230 is electrically connected with the light emitting control terminal EM, the third display node NX3 and the third display driving control node NQ3 respectively, and is configured to control the third display node NX3 and the third display driving control node NC3 to be connected or disconnected under the control of the light emitting control signal;

[0589] In at least one embodiment of the present disclosure, the nth first display driving circuit comprises an nth first driving circuit, an nth first light emitting control circuit, an nth first compensation circuit, an nth first reset circuit, an nth first energy storage circuit, an nth first data writing circuit and an nth first driving control circuit;

[0590] The control end of the nth first driving circuit is electrically connected with the nth control node, and the nth first driving circuit is used for generating an nth first driving current under the control of the potential of the nth control node;

[0591] The nth first light emitting control circuit is electrically connected with a light emitting control end, an nth display power voltage end and the first end of the nth first driving circuit respectively, and is used for controlling the communication or disconnection between the nth display power voltage end and the first end of the nth first driving circuit under the control of a light emitting control signal provided by the light emitting control end;

[0592] The nth first compensation circuit is electrically connected with an nth compensation control end, the nth control node and the second end of the nth first driving circuit respectively, and is used for controlling the communication or disconnection between the nth control node and the second end of the nth first driving circuit under the control of an nth compensation control signal provided by the nth compensation control end;

[0593] The nth first reset circuit is electrically connected with an nth control reset end, an nth control initial voltage end and the nth control node respectively, and is used for writing an nth control initial voltage provided by the nth control initial voltage end into the nth control node under the control of the nth control reset signal;

[0594] The nth first energy storage circuit is electrically connected with the nth control node, and is used for maintaining the potential of the nth control node;

[0595] The nth first data writing circuit is electrically connected with an nth writing control end, an nth display data voltage end and the first end of the nth first driving circuit respectively, and is used for writing an nth display data voltage provided by the nth display data voltage end into the first end of the nth first driving circuit under the control of an nth writing control signal provided by the nth writing control end;

[0596] The nth first driving control circuit comprises an nth first driving energy storage circuit, an nth first control driving circuit, an nth third light emitting control circuit, an nth first writing circuit, an nth first control compensation circuit and an nth first set circuit;

[0597] The first end of the nth first driving energy storage circuit is electrically connected with the first display control end, the second end of the nth first driving energy storage circuit is electrically connected with the nth first driving control node, and the nth first driving energy storage circuit is used for storing electric energy;

[0598] The control end of the nth first control driving circuit is electrically connected with the nth first driving control node, the first end of the nth first control driving circuit is electrically connected with the nth first driving node, the second end of the nth first control driving circuit is electrically connected with the nth control node, and the nth first control driving circuit is used for controlling the communication or disconnection between the nth first driving node and the nth control node under the control of the potential of the nth first driving control node;

[0599] The nth third light emitting control circuit is electrically connected with the light emitting control end, the nth display power voltage end and the nth first driving node respectively, and is used for controlling the communication or disconnection between the nth display power voltage end and the nth first driving node under the control of a light emitting control signal provided by the light emitting control end;

[0600] The nth first writing circuit is electrically connected with the nth control scanning end, the nth control data voltage end and the nth first driving node respectively, and is used for writing an nth control data voltage provided by the nth control data voltage end into the nth first driving node under the control of an nth control scanning signal provided by the nth control scanning end;

[0601] The nth first control compensation circuit is electrically connected with the nth control scanning end, the nth first driving control node and the nth control node respectively, and is used for controlling the communication or disconnection between the nth first driving control node and the nth control node under the control of the nth control scanning signal;

[0602] The nth first setting circuit is electrically connected with the nth control reset end, the nth control initial voltage end and the nth first driving control node respectively, and is used for writing an nth control initial voltage provided by the nth control initial voltage end into the nth first driving control node under the control of an nth control reset signal provided by the nth control reset end.

[0603] In at least one embodiment of the present disclosure, the nth second display driving circuit includes an nth second driving circuit, an nth second light emitting control circuit, an nth second compensation circuit, an nth second reset circuit, an nth second energy storage circuit, an nth second data writing circuit and an nth second driving control circuit;

[0604] The control end of the nth second driving circuit is electrically connected with the nth opposite control node, and the nth second driving circuit is used for generating an nth second driving current under the control of the potential of the nth opposite control node;

[0605] The nth second light emitting control circuit is electrically connected with the light emitting control end, the nth display low voltage end and the first end of the nth second driving circuit respectively, and is used for controlling the communication or disconnection between the nth display low voltage end and the first end of the nth second driving circuit under the control of the light emitting control signal provided by the light emitting control end;

[0606] The nth second compensation circuit is electrically connected with the nth opposite compensation control end, the nth opposite control node and the second end of the nth second driving circuit respectively, and is used for controlling the communication or disconnection between the nth opposite control node and the second end of the nth second driving circuit under the control of the nth opposite compensation control signal provided by the nth opposite compensation control end;

[0607] The nth second reset circuit is electrically connected with the nth control reset end, the nth opposite control initial voltage end and the nth opposite control node respectively, and is used for writing the nth opposite control initial voltage provided by the nth opposite control initial voltage end into the nth opposite control node under the control of the nth control reset signal;

[0608] The nth second energy storage circuit is electrically connected with the nth opposite control node, and is used for maintaining the potential of the nth opposite control node;

[0609] The nth second data writing circuit is electrically connected with the nth opposite writing control end, the nth display data voltage end and the first end of the nth second driving circuit respectively, and is used for writing the nth display data voltage provided by the nth display data voltage end into the first end of the nth second driving circuit under the control of the nth opposite writing control signal provided by the nth opposite writing control end;

[0610] The nth second driving control circuit comprises an nth second driving energy storage circuit, an nth second control driving circuit, an nth fourth light emitting control circuit, an nth second data writing circuit, an nth second control compensation circuit and an nth second setting circuit;

[0611] The first end of the nth second driving energy storage circuit is electrically connected with the second display control end, the second end of the nth second driving energy storage circuit is electrically connected with the nth second driving control node, and the nth second driving energy storage circuit is used for storing electric energy;

[0612] The control end of the nth second control drive circuit is electrically connected with the nth second drive control node, the first end of the nth second control drive circuit is electrically connected with the nth second drive node, the second end of the nth second control drive circuit is electrically connected with the nth inverted control node, and the nth second control drive circuit is used for controlling the communication or disconnection between the nth second drive node and the nth inverted control node under the control of the potential of the nth second drive control node;

[0613] The nth fourth light-emitting control circuit is electrically connected with the light-emitting control end, the nth display low-voltage end and the nth second drive node respectively, and is used for controlling the communication or disconnection between the nth display low-voltage end and the nth second drive node under the control of the light-emitting control signal provided by the light-emitting control end;

[0614] The nth second data write circuit is electrically connected with the nth inverted control scanning end, the nth control data voltage end and the nth second drive node respectively, and is used for writing the nth control data voltage provided by the nth control data voltage end into the nth second drive node under the control of the nth inverted control scanning signal provided by the nth inverted control scanning end;

[0615] The nth second control compensation circuit is electrically connected with the nth inverted control scanning end, the nth second drive control node and the nth inverted control node respectively, and is used for controlling the communication or disconnection between the nth second drive control node and the nth inverted control node under the control of the nth inverted control scanning signal;

[0616] The nth second setting circuit is electrically connected with the nth control reset end, the nth inverted control initial voltage end and the nth second drive control node respectively, and is used for writing the nth inverted control initial voltage provided by the nth inverted control initial voltage end into the nth second drive control node under the control of the nth control reset signal provided by the nth control reset end.

[0617] On the basis of at least one embodiment of the pixel circuit shown in FIG. 11, as shown in FIG. 12A, the first first display drive circuit includes a first first drive circuit 410, a first first light-emitting control circuit 411, a first first compensation circuit 412, a first first reset circuit 413, a first first energy storage circuit 415, a first first data write circuit 414 and a first first drive control circuit;

[0618] A first control end of the first driving circuit 410 is electrically connected with a first control node NC1, and the first driving circuit 410 is configured to generate a first driving current under the control of a potential of the first control node NC1; and a second end of the first driving circuit 410 is electrically connected with NQ1.

[0619] The first light emitting control circuit 411 is electrically connected with a light emitting control end EM1, a first display power voltage end VD1 and the first end of the first driving circuit 410, respectively, and is configured to control the first display power voltage end VD1 to be connected or disconnected with the first end of the first driving circuit 410 under the control of a light emitting control signal provided by the light emitting control end EM1.

[0620] The first compensation circuit 412 is electrically connected with a first compensation control end GT1N, the first control node NC1 and the second end of the first driving circuit 410, respectively, and is configured to control the first control node NC1 to be connected or disconnected with the second end of the first driving circuit 410 under the control of a first compensation control signal provided by the first compensation control end GT1N.

[0621] The first reset circuit 413 is electrically connected with a first control reset end RSTC1, a first control initial voltage end CI1 and the first control node NC1, respectively, and is configured to write a first control initial voltage provided by the first control initial voltage end CI1 into the first control node NC1 under the control of a first control reset signal.

[0622] The first energy storage circuit 415 is electrically connected with the first control node NC1, and is configured to maintain a potential of the first control node NC1.

[0623] The first data write-in circuit 414 is electrically connected with a first write-in control end Gat1, a first display data voltage end DL1 and the first end of the first driving circuit 410, respectively, and is configured to write a first display data voltage provided by the first display data voltage end DL1 into the first end of the first driving circuit 410 under the control of a first write-in control signal provided by the first write-in control end Gat1.

[0624] The first driving control circuit includes a first driving energy storage circuit 710, a first control driving circuit 711, a first third light emitting control circuit 712, a first first write-in circuit 713, a first control compensation circuit 714 and a first set circuit 715.

[0625] The first end of the first driving energy storage circuit 710 is electrically connected with a first display control terminal SWP1, the second end of the first driving energy storage circuit 710 is electrically connected with a first driving control node N11, and the first driving energy storage circuit 710 is used for storing electric energy;

[0626] The control terminal of the first first control driving circuit 711 is electrically connected with the first driving control node N11, the first end of the first first control driving circuit 711 is electrically connected with a first driving node ND11, and the second end of the first first control driving circuit 711 is electrically connected with the first control node NC1, and the first first control driving circuit 711 is used for controlling the first driving node ND11 and the first control node NC1 to be connected or disconnected under the control of the potential of the first driving control node N11.

[0627] The first third light emitting control circuit 712 is electrically connected with a light emitting control terminal EM1, a first display power voltage terminal VD1 and the first driving node ND11 respectively, and is used for controlling the first display power voltage terminal VD1 and the first driving node ND11 to be connected or disconnected under the control of a light emitting control signal provided by the light emitting control terminal EM1.

[0628] The first first writing circuit 713 is electrically connected with a first control scanning terminal GTC1, a first control data voltage terminal DTC1 and the first driving node ND11 respectively, and is used for writing a first control data voltage provided by the first control data voltage terminal DTC1 into the first driving node ND11 under the control of a first control scanning signal provided by the first control scanning terminal GTC1.

[0629] The first first control compensation circuit 714 is electrically connected with the first control scanning terminal GTC1, the first driving control node N11 and the first control node NC1 respectively, and is used for controlling the first driving control node N11 and the first control node NC1 to be connected or disconnected under the control of the first control scanning signal.

[0630] The first first setting circuit 715 is electrically connected with a first control reset terminal RSTC1, a first control initial voltage terminal CI1 and the first driving control node N11 respectively, and is used for writing a first control initial voltage provided by the first control initial voltage terminal CI1 into the first driving control node N11 under the control of a first control reset signal provided by the first control reset terminal RSTC1.

[0631] On the basis of at least one embodiment of the pixel circuit shown in FIG. 11, as shown in FIG. 12B,

[0632] The first second display driving circuit includes a first second driving circuit 510, a first second light emitting control circuit 511, a first second compensation circuit 512, a first second reset circuit 513, a first second energy storage circuit 515, a first second data writing circuit 514, and a first second driving control circuit;

[0633] The control end of the first second driving circuit 510 is electrically connected with the first inverting control node NF1, and the first second driving circuit 510 is configured to generate a first second driving current under the control of the potential of the first inverting control node NF1.

[0634] The first second light emitting control circuit 511 is electrically connected with the light emitting control end EM1, the first display low voltage end VS1, and the first end of the first second driving circuit 510 respectively, and is configured to control the communication or disconnection between the first display low voltage end VS1 and the first end of the first second driving circuit 510 under the control of the light emitting control signal provided by the light emitting control end EM1.

[0635] The first second compensation circuit 512 is electrically connected with the first inverting compensation control end GT1B, the first inverting control node NF1, and the second end of the first second driving circuit 510 respectively, and is configured to control the communication or disconnection between the first inverting control node NF1 and the second end of the first second driving circuit 510 under the control of the first inverting compensation control signal provided by the first inverting compensation control end GT1B.

[0636] The first second reset circuit 513 is electrically connected with the first control reset end RSTC1, the first inverting control initial voltage end CIN1, and the first inverting control node NF1 respectively, and is configured to write the first inverting control initial voltage provided by the first inverting control initial voltage end CIN1 into the first inverting control node NF1 under the control of the first control reset signal.

[0637] The first second energy storage circuit 515 is electrically connected with the first inverting control node NF1, and is configured to maintain the potential of the first inverting control node NF1.

[0638] The first second data writing circuit 514 is electrically connected with the first inverse writing control end Gat1B, the first display data voltage end DL1 and the first end of the first second driving circuit 510 respectively, and is used for writing the first display data voltage provided by the first display data voltage end DL1 into the first end of the first second driving circuit 510 under the control of the first inverse writing control signal provided by the first inverse writing control end Gat1B;

[0639] The first second driving control circuit comprises a first second driving energy storage circuit 810, a first second control driving circuit 811, a first fourth light emitting control circuit 812, a first second writing circuit 813, a first second control compensation circuit 814 and a first second setting circuit 815;

[0640] The first end of the first second driving energy storage circuit 810 is electrically connected with the second display control end SWP2, the second end of the first second driving energy storage circuit 810 is electrically connected with the first second driving control node N12, and the first second driving energy storage circuit 810 is used for storing electric energy;

[0641] The control end of the first second control driving circuit 811 is electrically connected with the first second driving control node N12, the first end of the first second control driving circuit 811 is electrically connected with the first second driving node ND12, the second end of the first second control driving circuit 811 is electrically connected with the first inverse control node NF1, and the first second control driving circuit 811 is used for controlling the first second driving node ND12 and the first inverse control node NF1 to be connected or disconnected under the control of the electric potential of the first second driving control node N12;

[0642] The first fourth light emitting control circuit 812 is electrically connected with the light emitting control end EM1, the first display low voltage end VS1 and the first second driving node ND12 respectively, and is used for controlling the first display low voltage end VS1 and the first second driving node ND12 to be connected or disconnected under the control of the light emitting control signal provided by the light emitting control end EM1;

[0643] The first second writing circuit 813 is electrically connected with the first inverse control scanning end GTCB1, the first control data voltage end DTC1 and the first second driving node ND12 respectively, and is used for writing the first control data voltage provided by the first control data voltage end DTC1 into the first second driving node ND12 under the control of the first inverse control scanning signal provided by the first inverse control scanning end GTCB1;

[0644] The first second control compensation circuit 814 is electrically connected with the first inverting control scanning end GTCB1, the first second drive control node N12 and the first inverting control node NF1 respectively, for controlling the communication or disconnection between the first second drive control node N12 and the first inverting control node NF1 under the control of the first inverting control scanning signal;

[0645] The first second setting circuit 815 is electrically connected with the first control reset end RSTC1, the first inverting control initial voltage end CIN1 and the first second drive control node N12 respectively, for writing the first inverting control initial voltage provided by the first inverting control initial voltage end CIN1 into the first second drive control node N12 under the control of the first control reset signal provided by the first control reset end RSTC1.

[0646] On the basis of at least one embodiment of the pixel circuit shown in FIG. 11, as shown in FIG. 12C,

[0647] The second first display drive circuit includes a second first drive circuit 420, a second first light emitting control circuit 421, a second first compensation circuit 422, a second first reset circuit 423, a second first energy storage circuit 425, a second first data writing circuit 424 and a second first drive control circuit.

[0648] The control end of the second first drive circuit 420 is electrically connected with the second control node NC2, and the second first drive circuit 420 is used for generating a second first drive current under the control of the potential of the second control node NC2.

[0649] The second first light emitting control circuit 421 is electrically connected with the light emitting control end EM1, the second display power supply voltage end VD2 and the first end of the second first drive circuit 420 respectively, for controlling the communication or disconnection between the second display power supply voltage end VD2 and the first end of the second first drive circuit 420 under the control of the light emitting control signal provided by the light emitting control end EM1.

[0650] The second first compensation circuit 422 is electrically connected with the second compensation control end GT2N, the second control node NC2 and the second end of the second first drive circuit 420 respectively, for controlling the communication or disconnection between the second control node NC2 and the second end of the second first drive circuit 420 under the control of the second compensation control signal provided by the second compensation control end GT2N.

[0651] The second first reset circuit 423 is electrically connected with the second control reset end RSTC2, the second control initial voltage end CI2 and the second control node NC2 respectively, and is used for writing the second control initial voltage provided by the second control initial voltage end CI2 into the second control node NC2 under the control of the second control reset signal;

[0652] The second first energy storage circuit 425 is electrically connected with the second control node NC2, and is used for maintaining the potential of the second control node NC2;

[0653] The second first data write-in circuit 424 is electrically connected with the second write-in control end Gat2, the second display data voltage end DL2 and the first end of the second first drive circuit 420 respectively, and is used for writing the second display data voltage provided by the second display data voltage end DL2 into the first end of the second first drive circuit 420 under the control of the second write-in control signal provided by the second write-in control end Gat2;

[0654] The second first drive control circuit comprises a second first drive energy storage circuit 720, a second first control drive circuit 721, a second third light emitting control circuit 722, a second first data write-in circuit 723, a second first control compensation circuit 724 and a second first set circuit 725.

[0655] On the basis of at least one embodiment of the pixel circuit shown in FIG. 11, as shown in FIG. 12D,

[0656] The first end of the second first drive energy storage circuit 720 is electrically connected with the first display control end SWP1, the second end of the second first drive energy storage circuit 720 is electrically connected with the second first drive control node N21, and the second first drive energy storage circuit 720 is used for storing electric energy;

[0657] The control end of the second first control drive circuit 721 is electrically connected with the second first drive control node N21, the first end of the second first control drive circuit 721 is electrically connected with the second first drive node ND21, the second end of the second first control drive circuit 721 is electrically connected with the second control node NC2, and the second first control drive circuit 721 is used for controlling the second first drive node ND21 and the second control node NC2 to be connected or disconnected under the control of the potential of the second first drive control node N21;

[0658] The second third light emitting control circuit 722 is electrically connected with the light emitting control end EM1, the second display power voltage end VD2 and the second first driving node ND21 respectively, and is configured to control the second display power voltage end VD2 to be connected or disconnected with the second first driving node ND21 under the control of the light emitting control signal provided by the light emitting control end EM1;

[0659] The second first data writing circuit 723 is electrically connected with the second control scanning end GTC2, the second control data voltage end DTC2 and the second first driving node ND21 respectively, and is configured to write the second control data voltage provided by the second control data voltage end DTC2 into the second first driving node ND21 under the control of the second control scanning signal provided by the second control scanning end GTC2;

[0660] The second first control compensation circuit 724 is electrically connected with the second control scanning end GTC2, the second first driving control node N21 and the second control node NC2 respectively, and is configured to control the second first driving control node N21 to be connected or disconnected with the second control node NC2 under the control of the second control scanning signal;

[0661] The second first setting circuit 725 is electrically connected with the second control reset end RSTC2, the second control initial voltage end CI2 and the second first driving control node N21 respectively, and is configured to write the second control initial voltage provided by the second control initial voltage end CI2 into the second first driving control node N21 under the control of the second control reset signal provided by the second control reset end RSTC2;

[0662] The second second display driving circuit includes a second second driving circuit 520, a second second light emitting control circuit 521, a second second compensation circuit 522, a second second reset circuit 523, a second second energy storage circuit 525, a second second data writing circuit 524 and a second second driving control circuit.

[0663] The control end of the second second driving circuit 520 is electrically connected with the second inverting control node NF2, and the second second driving circuit 520 is configured to generate a second second driving current under the control of the potential of the second inverting control node NF2.

[0664] The second second light emitting control circuit 521 is electrically connected with the light emitting control end EM1, the second display low voltage end VS2 and the first end of the second second driving circuit 520 respectively, for controlling the second display low voltage end VS2 and the first end of the second second driving circuit 520 to be connected or disconnected under the control of the light emitting control signal provided by the light emitting control end EM1;

[0665] The second second compensation circuit 522 is electrically connected with the second inverse compensation control end GT2B, the second inverse control node NF2 and the second end of the second second driving circuit 520 respectively, for controlling the second inverse control node NF2 and the second end of the second second driving circuit 520 to be connected or disconnected under the control of the second inverse compensation control signal provided by the second inverse compensation control end GT2B;

[0666] The second second reset circuit 523 is electrically connected with the second control reset end RSTC2, the second inverse control initial voltage end CIN2 and the second inverse control node NF2 respectively, for writing the second inverse control initial voltage provided by the second inverse control initial voltage end CIN2 into the second inverse control node NF2 under the control of the second control reset signal;

[0667] The second second energy storage circuit 525 is electrically connected with the second inverse control node NF2, for maintaining the potential of the second inverse control node NF2;

[0668] The second second data write-in circuit 524 is electrically connected with the second inverse write-in control end Gat2B, the second display data voltage end DL2 and the first end of the second second driving circuit 520 respectively, for writing the second display data voltage provided by the second display data voltage end DL2 into the first end of the second second driving circuit 520 under the control of the second inverse write-in control signal provided by the second inverse write-in control end Gat2B;

[0669] The second second driving control circuit comprises a second second driving energy storage circuit 820, a second second control driving circuit 821, a second fourth light emitting control circuit 822, a second second data write-in circuit 823, a second second control compensation circuit 824 and a second second set circuit 825;

[0670] The first end of the second second driving energy storage circuit 820 is electrically connected with the second display control end SWP2, the second end of the second second driving energy storage circuit 820 is electrically connected with the second second driving control node N22, and the second second driving energy storage circuit 820 is used for storing electric energy;

[0671] The control end of the second second control drive circuit 821 is electrically connected with the second second drive control node N22, the first end of the second second control drive circuit 821 is electrically connected with the second second drive node ND22, the second end of the first second control drive circuit 811 is electrically connected with the second inverting control node NF2, and the second second control drive circuit 821 is used for controlling the second second drive node ND22 and the second inverting control node NF2 to be in communication or disconnected under the control of the potential of the second second drive control node N22.

[0672] The second fourth light emitting control circuit 822 is electrically connected with the light emitting control end EM1, the second display low voltage end VS2 and the second second drive node ND22 respectively, and is used for controlling the second display low voltage end VS2 and the second second drive node ND22 to be in communication or disconnected under the control of the light emitting control signal provided by the light emitting control end EM1.

[0673] The second second data writing circuit 823 is electrically connected with the second inverting control scanning end GTCB2, the second control data voltage end DTC2 and the second second drive node ND22 respectively, and is used for writing the second control data voltage provided by the second control data voltage end DTC2 into the second second drive node ND22 under the control of the second inverting control scanning signal provided by the second inverting control scanning end GTCB2.

[0674] The second second control compensation circuit 824 is electrically connected with the second inverting control scanning end GTCB2, the second second drive control node N22 and the second inverting control node NF2 respectively, and is used for controlling the second second drive control node N22 and the second inverting control node NF2 to be in communication or disconnected under the control of the second inverting control scanning signal.

[0675] The second second setting circuit 825 is electrically connected with the second control reset end RSTC2, the second inverting control initial voltage end CIN2 and the second second drive control node N22 respectively, and is used for writing the second inverting control initial voltage provided by the second inverting control initial voltage end CIN2 into the second second drive control node N22 under the control of the second control reset signal provided by the second control reset end RSTC2.

[0676] On the basis of at least one embodiment of the pixel circuit shown in FIG. 11, as shown in FIG. 12E,

[0677] The third first display driving circuit comprises a third first driving circuit 430, a third first light emitting control circuit 431, a third first compensation circuit 432, a third first reset circuit 433, a third first energy storage circuit 435, a third first data writing circuit 434 and a third first driving control circuit;

[0678] The control end of the third first driving circuit 430 is electrically connected with a third control node NC3, and the third first driving circuit 430 is used for generating a third first driving current under the control of the potential of the third control node NC3;

[0679] The third first light emitting control circuit 431 is electrically connected with a light emitting control end EM1, a third display power supply voltage end VD3 and the first end of the third first driving circuit 430 respectively, and is used for controlling the communication or disconnection between the third display power supply voltage end VD3 and the first end of the third first driving circuit 430 under the control of a light emitting control signal provided by the light emitting control end EM1;

[0680] The third first compensation circuit 432 is electrically connected with a third compensation control end GT3N, the third control node NC3 and the second end of the third first driving circuit 430 respectively, and is used for controlling the communication or disconnection between the third control node NC3 and the second end of the third first driving circuit 430 under the control of a third compensation control signal provided by the third compensation control end GT3N;

[0681] The third first reset circuit 433 is electrically connected with a third control reset end RSTC3, a third control initial voltage end CI3 and the third control node NC3 respectively, and is used for writing a third control initial voltage provided by the third control initial voltage end CI3 into the third control node NC3 under the control of a third control reset signal;

[0682] The third first energy storage circuit 435 is electrically connected with the third control node NC3, and is used for maintaining the potential of the third control node NC3;

[0683] The third first data writing circuit 434 is electrically connected with a third writing control end Gat3, a third display data voltage end DL3 and the first end of the third first driving circuit 430 respectively, and is used for writing a third display data voltage provided by the third display data voltage end DL3 into the first end of the third first driving circuit 430 under the control of a third writing control signal provided by the third writing control end Gat3;

[0684] The third first driving control circuit comprises a third first driving energy storage circuit 730, a third first control driving circuit 731, a third third light emitting control circuit 732, a third first data writing circuit 733, a third first control compensation circuit 734 and a third first setting circuit 735;

[0685] The first end of the third first driving energy storage circuit 730 is electrically connected with a first display control end SWP1, and the second end of the third first driving energy storage circuit 730 is electrically connected with a third first driving control node N31, and the third first driving energy storage circuit 730 is used for storing electric energy;

[0686] The control end of the third first control driving circuit 731 is electrically connected with the third first driving control node N31, the first end of the third first control driving circuit 731 is electrically connected with a third first driving node ND31, and the second end of the third first control driving circuit 731 is electrically connected with the third control node NC3, and the third first control driving circuit 731 is used for controlling the third first driving node ND31 and the third control node NC3 to be connected or disconnected under the control of the potential of the third first driving control node N31;

[0687] The third third light emitting control circuit 732 is electrically connected with a light emitting control end EM1, a third display power voltage end VD3 and the third first driving node ND31 respectively, and is used for controlling the third display power voltage end VD3 and the third first driving node ND31 to be connected or disconnected under the control of a light emitting control signal provided by the light emitting control end EM1;

[0688] The third first data writing circuit 733 is electrically connected with a third control scanning end GTC, a third control data voltage end DTC3 and the third first driving node ND31 respectively, and is used for writing a third control data voltage provided by the third control data voltage end DTC3 into the third first driving node ND31 under the control of a third control scanning signal provided by the third control scanning end GTC3;

[0689] The third first control compensation circuit 734 is electrically connected with the third control scanning end GTC3, the third first driving control node N31 and the third control node NC3 respectively, and is used for controlling the third first driving control node N31 and the third control node NC3 to be connected or disconnected under the control of the third control scanning signal;

[0690] The third first setting circuit 735 is electrically connected with a third control reset end RSTC3, a third control initial voltage end CI3 and the third first driving control node N31 respectively, and is used for writing a third control initial voltage provided by the third control initial voltage end CI3 into the third first driving control node N31 under the control of a third control reset signal provided by the third control reset end RSTC3.

[0691] On the basis of at least one embodiment of the pixel circuit shown in FIG. 11, as shown in FIG. 12F,

[0692] The third second display driving circuit includes a third second driving circuit 530, a third second light emitting control circuit 531, a third second compensation circuit 532, a third second reset circuit 533, a third second energy storage circuit 535, a third second data writing circuit 534 and a third second driving control circuit;

[0693] The control end of the third second driving circuit 530 is electrically connected with a third inverting control node NF3, and the third second driving circuit 530 is used for generating a third second driving current under the control of the potential of the third inverting control node NF3.

[0694] The third second light emitting control circuit 531 is electrically connected with a light emitting control end EM1, a third display low voltage end VS3 and the first end of the third second driving circuit 530 respectively, and is used for controlling the communication or disconnection between the third display low voltage end VS3 and the first end of the third second driving circuit 530 under the control of a light emitting control signal provided by the light emitting control end EM1.

[0695] The third second compensation circuit 532 is electrically connected with a third inverting compensation control end GT3B, the third inverting control node NF3 and the second end of the third second driving circuit 530 respectively, and is used for controlling the communication or disconnection between the third inverting control node NF3 and the second end of the third second driving circuit 530 under the control of a third inverting compensation control signal provided by the third inverting compensation control end GT3B.

[0696] The third second reset circuit 533 is electrically connected with a third control reset end RSTC3, a third inverting control initial voltage end CIN3 and the third inverting control node NF3 respectively, and is used for writing a third inverting control initial voltage provided by the third inverting control initial voltage end CIN3 into the third inverting control node NF3 under the control of the third control reset signal.

[0697] The third second energy storage circuit 535 is electrically connected with the third inverting control node NF3, and is used for maintaining the potential of the third inverting control node NF3.

[0698] The third second data write circuit 534 is electrically connected with the third inverse write control end Gat3B, the third display data voltage end DL3 and the first end of the third second drive circuit 530 respectively, for writing the third display data voltage provided by the third display data voltage end DL3 into the first end of the third second drive circuit 530 under the control of the third inverse write control signal provided by the third inverse write control end Gat3B;

[0699] The third second drive control circuit comprises a third second drive energy storage circuit 830, a third second control drive circuit 831, a third fourth light emitting control circuit 832, a third second data write circuit 833, a third second control compensation circuit 834 and a third second set circuit 835;

[0700] The first end of the third second drive energy storage circuit 830 is electrically connected with the second display control end SWP2, the second end of the third second drive energy storage circuit 830 is electrically connected with the third second drive control node N32, and the third second drive energy storage circuit 830 is used for storing electric energy;

[0701] The control end of the third second control drive circuit 831 is electrically connected with the third second drive control node N32, the first end of the third second control drive circuit 831 is electrically connected with the third second drive node ND32, the second end of the third second control drive circuit 831 is electrically connected with the third inverse control node NF3, and the third second control drive circuit 831 is used for controlling the third second drive node ND32 and the third inverse control node NF3 to be connected or disconnected under the control of the potential of the third second drive control node N32;

[0702] The third fourth light emitting control circuit 832 is electrically connected with the light emitting control end EM1, the third display low voltage end VS3 and the third second drive node N32 respectively, for controlling the third display low voltage end VS3 and the third second drive node ND32 to be connected or disconnected under the control of the light emitting control signal provided by the light emitting control end EM1;

[0703] The third second data write circuit 833 is electrically connected with the third inverse control scanning end GTCB3, the third control data voltage end DTC3 and the third second drive node ND32 respectively, for writing the third control data voltage provided by the third control data voltage end DTC3 into the third second drive node ND32 under the control of the third inverse control scanning signal provided by the third inverse control scanning end GTCB3;

[0704] The third second control compensation circuit 834 is electrically connected with the third inverting control scan end GTCB3, the third second drive control node N32 and the third inverting control node NF3 respectively, and is configured to control the third second drive control node N32 to be connected or disconnected with the third inverting control node NF3 under the control of the third inverting control scan signal;

[0705] The third second setting circuit 835 is electrically connected with the third control reset end RSTC3, the third inverting control initial voltage end CIN3 and the third second drive control node N32 respectively, and is configured to write the third inverting control initial voltage provided by the third inverting control initial voltage end CIN3 into the third second drive control node N32 under the control of the third control reset signal provided by the third control reset end RSTC3.

[0706] In at least one embodiment of the present disclosure, the pixel driving circuit comprises a driving circuit, a display energy storage circuit, a data writing circuit, a compensation control circuit, a first reset circuit, a first display light emitting control circuit, a second display light emitting control circuit, a drive node control circuit;

[0707] The driving circuit is electrically connected with the drive node, and is configured to generate the driving current under the control of the potential of the drive node.

[0708] The display energy storage circuit is electrically connected with the drive node, and is configured to maintain the potential of the drive node.

[0709] The data writing circuit is electrically connected with a display scan end, a data voltage end and a first end of the driving circuit respectively, and is configured to write the data voltage provided by the data voltage end into the first end of the driving circuit under the control of the display scan signal provided by the display scan end.

[0710] The compensation control circuit is electrically connected with a compensation control end, the drive node and a second end of the driving circuit respectively, and is configured to control the drive node to be connected or disconnected with the second end of the driving circuit under the control of the compensation control signal provided by the compensation control end.

[0711] The first reset circuit is electrically connected with a reset control end, a display initial voltage end and the drive node respectively, and is configured to write the display initial voltage provided by the display initial voltage end into the drive node under the control of the reset control signal provided by the reset control end.

[0712] The first display light emitting control circuit is electrically connected with a light emitting control end, a power voltage end and a first end of the driving circuit respectively, and is used for controlling the communication or disconnection between the power voltage end and the first end of the driving circuit under the control of a light emitting control signal provided by the light emitting control end;

[0713] The second display light emitting control circuit is electrically connected with a light emitting control end, a second end of the driving circuit and the driving current output end respectively, and is used for controlling the communication or disconnection between the second end of the driving circuit and the driving current output end under the control of the light emitting control signal;

[0714] The driving node control circuit comprises a third light emitting control circuit, a control driving circuit, a data writing control circuit, a control energy storage circuit, a control reset circuit and a control compensation circuit;

[0715] The control end of the control driving circuit is electrically connected with a control driving node, the first end of the control driving circuit is electrically connected with a light emitting node, the second end of the control driving circuit is electrically connected with a driving node, and the control driving circuit is used for controlling the communication or disconnection between the light emitting node and the driving node under the control of the potential of the control driving node;

[0716] The third light emitting control circuit is electrically connected with a light emitting control end, a power voltage end and the light emitting node respectively, and is used for controlling the communication or disconnection between the power voltage end and the light emitting node under the control of a light emitting control signal provided by the light emitting control end;

[0717] The data writing control circuit is electrically connected with a display control scanning end, a display control data voltage end and the light emitting node respectively, and is used for writing a display control data voltage provided by the display control data voltage end into the light emitting node under the control of a display control scanning signal provided by the display control scanning end;

[0718] The first end of the control energy storage circuit is electrically connected with a first display control end, the second end of the control energy storage circuit is electrically connected with the control driving node, and the control energy storage circuit is used for storing electric energy;

[0719] The control reset circuit is electrically connected with a reset control end, a display initial voltage end and the control driving node respectively, and is used for writing a display initial voltage provided by the display initial voltage end into the control driving node under the control of a reset control signal provided by the reset control end;

[0720] The control compensation circuit is electrically connected with a display control scanning end, the control driving node and a driving node respectively, and is used for controlling the communication or disconnection between the control driving node and the driving node under the control of the display control scanning signal.

[0721] As shown in FIG. 13, on the basis of at least one embodiment of the pixel circuit shown in FIG. 11, the pixel driving circuit comprises a driving circuit 40, a display energy storage circuit 42, a data writing circuit 41, a compensation control circuit 43, a first reset circuit 44, a first display light emitting control circuit 451, a second display light emitting control circuit 452 and a driving node control circuit;

[0722] The driving circuit 40 is electrically connected with the driving node N1, and is used for generating the driving current under the control of the potential of the driving node N1;

[0723] The display energy storage circuit 42 is electrically connected with the driving node N1, and is used for maintaining the potential of the driving node N1;

[0724] The data writing circuit 41 is electrically connected with a display scanning end Gat, a data voltage end DA1 and a first end of the driving circuit 40 respectively, and is used for writing the data voltage provided by the data voltage end DA1 into the first end of the driving circuit 40 under the control of a display scanning signal provided by the display scanning end Gat;

[0725] The compensation control circuit 43 is electrically connected with a compensation control end Gat1N, the driving node N1 and a second end of the driving circuit 40 respectively, and is used for controlling the communication or disconnection between the driving node N1 and the second end of the driving circuit 40 under the control of a compensation control signal provided by the compensation control end Gat1N;

[0726] The first reset circuit 44 is electrically connected with a reset control end RST1, a display initial voltage end I1 and the driving node N1 respectively, and is used for writing a display initial voltage provided by the display initial voltage end I1 into the driving node N1 under the control of a reset control signal provided by the reset control end RST1;

[0727] The first display light emitting control circuit 451 is electrically connected with a light emitting control end EM1, a power voltage end VDD1 and the first end of the driving circuit 40 respectively, and is used for controlling the communication or disconnection between the power voltage end VDD1 and the first end of the driving circuit 40 under the control of a light emitting control signal provided by the light emitting control end EM1;

[0728] The second display light emitting control circuit 452 is electrically connected with the light emitting control end EM1, a second end of the driving circuit 40 and the driving current output end OT respectively, and is used for controlling the communication or disconnection between the second end of the driving circuit 40 and the driving current output end OT under the control of the light emitting control signal;

[0729] The driving node control circuit comprises a third display light emitting control circuit 91, a control driving circuit 92, a data writing control circuit 93, a control energy storage circuit 94, a control reset circuit 95 and a control compensation circuit 96;

[0730] The control end of the control driving circuit 92 is electrically connected with a control driving node NCD, the first end of the control driving circuit 92 is electrically connected with a light emitting node NE, the second end of the control driving circuit 92 is electrically connected with a driving node N1, and the control driving circuit 92 is configured to control the communication or disconnection between the light emitting node NE and the driving node N1 under the control of the potential of the control driving node NCD;

[0731] The third display light emitting control circuit 91 is electrically connected with a light emitting control end EM1, a power supply voltage end VDD1 and the light emitting node NE respectively, and is configured to control the communication or disconnection between the power supply voltage end VDD1 and the light emitting node NE under the control of a light emitting control signal provided by the light emitting control end EM1;

[0732] The data writing control circuit 93 is electrically connected with a display control scanning end GTDC, a display control data voltage end DAT and the light emitting node NE respectively, and is configured to write a display control data voltage provided by the display control data voltage end DAT into the light emitting node NE under the control of a display control scanning signal provided by the display control scanning end DTDC;

[0733] The first end of the control energy storage circuit 94 is electrically connected with a first display control end SWP1, and the second end of the control energy storage circuit 94 is electrically connected with the control driving node NCD, and the control energy storage circuit 94 is configured to store electric energy;

[0734] The control reset circuit 95 is electrically connected with a reset control end RST1, a display initial voltage end I1 and the control driving node NCD respectively, and is configured to write a display initial voltage provided by the display initial voltage end I1 into the control driving node NCD under the control of a reset control signal provided by the reset control end RST1;

[0735] The control compensation circuit 96 is electrically connected with the display control scanning end GTDC, the control driving node NCD and the driving node N1 respectively, and is configured to control the communication or disconnection between the control driving node NCD and the driving node N1 under the control of the display control scanning signal.

[0736] In at least one embodiment of the present disclosure, the nth on-off control circuit comprises an nth first transistor, the nth writing circuit comprises an nth second transistor, and the nth control energy storage circuit comprises an nth first capacitor.

[0737] The gate of the nth first transistor is electrically connected with the nth on-off control node, the first pole of the nth first transistor is electrically connected with the nth display driving control node, and the second pole of the nth first transistor is electrically connected with the nth display node.

[0738] The gate of the nth second transistor is electrically connected with the nth control reset end, the first pole of the nth second transistor is electrically connected with the nth control data voltage end, and the second pole of the nth second transistor is electrically connected with the nth on-off control node.

[0739] The first end of the nth first capacitor is electrically connected with the display control end, and the second end of the nth first capacitor is electrically connected with the nth on-off control node.

[0740] In at least one embodiment of the present disclosure, the nth first driving circuit includes an nth first driving transistor, the nth first light-emitting control circuit includes an nth third transistor, the nth first compensation circuit includes an nth fourth transistor, the nth first reset circuit includes an nth fifth transistor, the nth first data writing circuit includes an nth sixth transistor, and the nth first energy storage circuit includes an nth second capacitor.

[0741] The gate of the nth first driving transistor is electrically connected with the nth control node.

[0742] The gate of the nth third transistor is electrically connected with the light-emitting control end, the first pole of the nth third transistor is electrically connected with the nth display power voltage end, and the second pole of the nth third transistor is electrically connected with the first pole of the nth first driving transistor.

[0743] The gate of the nth fourth transistor is electrically connected with the nth compensation control end, the first pole of the nth fourth transistor is electrically connected with the nth control node, and the second pole of the nth fourth transistor is electrically connected with the second pole of the nth first driving transistor.

[0744] The gate of the nth fifth transistor is electrically connected with the nth control reset end, the first pole of the nth fifth transistor is electrically connected with the nth control initial voltage end, and the second pole of the nth fifth transistor is electrically connected with the nth control node.

[0745] The gate of the nth sixth transistor is electrically connected with the nth writing control end, the first pole of the nth sixth transistor is electrically connected with the nth display data voltage end, and the second pole of the nth sixth transistor is electrically connected with the first pole of the nth first driving transistor.

[0746] A first end of the nth second capacitor is electrically connected with the nth control node, and a second end of the nth second capacitor is electrically connected with the direct current voltage end.

[0747] In at least one embodiment of the present disclosure, the nth second driving circuit includes an nth second driving transistor, the nth second light-emitting control circuit includes an nth seventh transistor, the nth second compensation circuit includes an nth eighth transistor, the nth second reset circuit includes an nth ninth transistor, the nth second data writing circuit includes an nth tenth transistor, and the nth second energy storage circuit includes an nth third capacitor.

[0748] A gate of the nth second driving transistor is electrically connected with the nth inverted control node.

[0749] A gate of the nth seventh transistor is electrically connected with the light-emitting control end, a first pole of the nth seventh transistor is electrically connected with the nth display low voltage end, and a second pole of the nth seventh transistor is electrically connected with a first pole of the nth second driving transistor.

[0750] A gate of the nth eighth transistor is electrically connected with the nth inverted compensation control end, a first pole of the nth eighth transistor is electrically connected with the nth inverted control node, and a second pole of the nth eighth transistor is electrically connected with a second pole of the nth second driving transistor.

[0751] A gate of the nth ninth transistor is electrically connected with the nth control reset end, a first pole of the nth ninth transistor is electrically connected with the nth inverted control initial voltage end, and a second pole of the nth ninth transistor is electrically connected with the nth inverted control node.

[0752] A gate of the nth tenth transistor is electrically connected with the nth inverted writing control end, a first pole of the nth tenth transistor is electrically connected with the nth display data voltage end, and a second pole of the nth tenth transistor is electrically connected with a first pole of the nth second driving transistor.

[0753] A first end of the nth third capacitor is electrically connected with the nth inverted control node, and a second end of the nth third capacitor is electrically connected with the direct current voltage end.

[0754] In at least one embodiment of the present disclosure, the driving circuit includes a display driving transistor, the data writing circuit includes a first control transistor, the display energy storage circuit includes a storage capacitor, the compensation control circuit includes a second control transistor, the first reset circuit includes a third control transistor, the display light-emitting control circuit includes a fourth control transistor, and the display control circuit includes a fifth control transistor.

[0755] A gate of the display driving transistor is electrically connected with the driving node;

[0756] A gate of the first control transistor is electrically connected with the display scanning end, a first pole of the first control transistor is electrically connected with the data voltage end, and a second pole of the first control transistor is electrically connected with a first pole of the display driving transistor;

[0757] A first end of the storage capacitor is electrically connected with the driving node, and a second end of the storage capacitor is electrically connected with the direct current voltage end;

[0758] A gate of the second control transistor is electrically connected with the compensation control end, a first pole of the second control transistor is electrically connected with the driving node, and a second pole of the second control transistor is electrically connected with a second pole of the display driving transistor;

[0759] A gate of the third control transistor is electrically connected with the reset control end, a first pole of the third control transistor is electrically connected with the display initial voltage end, and a second pole of the third control transistor is electrically connected with the driving node;

[0760] A gate of the fourth control transistor is electrically connected with the light emitting control end, a first pole of the fourth control transistor is electrically connected with the power voltage end, and a second pole of the fourth control transistor is electrically connected with a first pole of the display driving transistor;

[0761] A gate of the fifth control transistor is electrically connected with the display control node, a first pole of the fifth control transistor is electrically connected with a first pole of the display driving transistor, and a second pole of the fifth control transistor is electrically connected with the driving current output end.

[0762] In at least one embodiment of the present disclosure, the node control circuit comprises a sixth control transistor and a first control capacitor;

[0763] A gate of the sixth control transistor is electrically connected with the reset control end, a first pole of the sixth control transistor is electrically connected with the display control data voltage end, and a second pole of the sixth control transistor is electrically connected with the display control node;

[0764] A first end of the first control capacitor is electrically connected with the display control end, and a second end of the first control capacitor is electrically connected with the display control node.

[0765] As shown in FIG. 14, on the basis of at least one embodiment of the pixel circuit shown in FIG. 6A,

[0766] The first on-off control circuit comprises a first transistor M11, the first write circuit comprises a second transistor M12, and the first control energy storage circuit comprises a first capacitor C11;

[0767] The gate of the first transistor M11 is electrically connected with the first on-off control node NT1, the source of the first transistor M11 is electrically connected with the first display driving control node NQ1, and the drain of the first transistor M11 is electrically connected with the first display node NX1;

[0768] The gate of the second transistor M12 is electrically connected with the first control reset end RSTC1, the source of the second transistor M12 is electrically connected with the first control data voltage end DTC1, and the drain of the second transistor M12 is electrically connected with the first on-off control node NT1;

[0769] The first end of the first capacitor C11 is electrically connected with the display control end SWP, and the second end of the first capacitor C11 is electrically connected with the first on-off control node NT1;

[0770] The first first drive circuit comprises a first first drive transistor DT11, the first first light-emitting control circuit comprises a first third transistor M13, the first first compensation circuit comprises a first fourth transistor M14, the first first reset circuit comprises a first fifth transistor M15, the first first data write circuit comprises a first sixth transistor M16, and the first first energy storage circuit comprises a first second capacitor C12;

[0771] The gate of the first first drive transistor DT11 is electrically connected with the first control node NC1;

[0772] The gate of the first third transistor M13 is electrically connected with the light-emitting control end EM1, the source of the first third transistor M13 is electrically connected with the first display power voltage end VD1, and the drain of the first third transistor M13 is electrically connected with the source of the first first drive transistor DT11;

[0773] The gate of the first fourth transistor M14 is electrically connected with the first compensation control end GT1N, the source of the first fourth transistor M14 is electrically connected with the first control node NC1, and the drain of the first fourth transistor M14 is electrically connected with the drain of the first first drive transistor DT11;

[0774] A gate of the first fifth transistor M15 is electrically connected with a first control reset end RSTC1, a source of the first fifth transistor M15 is electrically connected with a first control initial voltage end CI1, and a drain of the first fifth transistor M15 is electrically connected with the first control node NC1;

[0775] A gate of the first sixth transistor M16 is electrically connected with a first write control end Gat1, a source of the first sixth transistor M16 is electrically connected with a first display data voltage end DL1, and a drain of the first sixth transistor M16 is electrically connected with a source of the first first driving transistor DT11;

[0776] A first end of the first second capacitor C12 is electrically connected with the first control node NC1, and a second end of the first second capacitor C12 is electrically connected with VD1;

[0777] The first second driving circuit includes a first second driving transistor DT12, the first second light-emitting control circuit includes a first seventh transistor M17, the first second compensation circuit includes a first eighth transistor M18, the first second reset circuit includes a first ninth transistor M19, the first second data write circuit includes a first tenth transistor M110, and the first second energy storage circuit includes a first third capacitor C13;

[0778] A gate of the first second driving transistor DT12 is electrically connected with the first inverted control node NF1;

[0779] A gate of the first seventh transistor M17 is electrically connected with the light-emitting control end EM1, a source of the first seventh transistor M17 is electrically connected with the first display low voltage end VS1, and a drain of the first seventh transistor M17 is electrically connected with a source of the first second driving transistor DT12;

[0780] A gate of the first eighth transistor M18 is electrically connected with a first inverted compensation control end GT1B, a source of the first eighth transistor M18 is electrically connected with the first inverted control node NF1, and a drain of the first eighth transistor M18 is electrically connected with a drain of the first second driving transistor DT12;

[0781] A gate of the first ninth transistor M19 is electrically connected with the first control reset end RSTC1, a source of the first ninth transistor M19 is electrically connected with the first inverted control initial voltage end CIN1, and a drain of the first ninth transistor M19 is electrically connected with the first inverted control node NF1;

[0782] The gate of the first tenth transistor M110 is electrically connected with the first inverse compensation control end GT1B, the source of the first tenth transistor M110 is electrically connected with the first display data voltage end DL1, and the drain of the first tenth transistor M110 is electrically connected with the source of the first second driving transistor DT12;

[0783] The first end of the first third capacitor C13 is electrically connected with the first inverse control node NF1, and the second end of the first third capacitor C13 is electrically connected with VS1;

[0784] The second on-off control circuit comprises a second first transistor M21, the second write circuit comprises a second second transistor M22, and the second control energy storage circuit comprises a second first capacitor C21;

[0785] The gate of the second first transistor M21 is electrically connected with the second on-off control node NT2, the source of the second first transistor M21 is electrically connected with the second display driving control node NQ2, and the drain of the second first transistor M21 is electrically connected with the second display node NX2;

[0786] The gate of the second second transistor M22 is electrically connected with the second control reset end RSTC2, the source of the second second transistor M22 is electrically connected with the second control data voltage end DTC2, and the drain of the second second transistor M22 is electrically connected with the second on-off control node NT2;

[0787] The first end of the second first capacitor C21 is electrically connected with the display control end SWP, and the second end of the second first capacitor C21 is electrically connected with the second on-off control node NT2;

[0788] The second first driving circuit comprises a second first driving transistor DT21, the second first light-emitting control circuit comprises a second third transistor M23, the second first compensation circuit comprises a second fourth transistor M24, the second first reset circuit comprises a second fifth transistor M25, the second first data write circuit comprises a second sixth transistor M26, and the second first energy storage circuit comprises a second second capacitor C22;

[0789] The gate of the second first driving transistor DT21 is electrically connected with the second control node NC2;

[0790] The gate of the second third transistor M23 is electrically connected with the light emitting control end EM1, the source of the second third transistor M23 is electrically connected with the second display power voltage end VD2, and the drain of the second third transistor M23 is electrically connected with the source of the second first driving transistor DT21;

[0791] The gate of the second fourth transistor M24 is electrically connected with the second compensation control end GT2N, the source of the second fourth transistor M24 is electrically connected with the second control node NC2, and the drain of the second fourth transistor M24 is electrically connected with the drain of the second first driving transistor DT21;

[0792] The gate of the second fifth transistor M25 is electrically connected with the second control reset end RSTC2, the source of the second fifth transistor M25 is electrically connected with the second control initial voltage end CI2, and the drain of the second fifth transistor M25 is electrically connected with the second control node NC2;

[0793] The gate of the second sixth transistor M26 is electrically connected with the second write control end Gat2, the source of the second sixth transistor M26 is electrically connected with the second display data voltage end DL2, and the drain of the second sixth transistor M26 is electrically connected with the source of the second first driving transistor DT21;

[0794] The first end of the second second capacitor C22 is electrically connected with the second control node NC2, and the second end of the second second capacitor C22 is electrically connected with VD2;

[0795] The second second driving circuit includes a second second driving transistor DT22, the second second light emitting control circuit includes a second seventh transistor M27, the second second compensation circuit includes a second eighth transistor M28, the second second reset circuit includes a second ninth transistor M29, the second second data write circuit includes a second tenth transistor M210, and the second second energy storage circuit includes a second third capacitor C23;

[0796] The gate of the second second driving transistor DT22 is electrically connected with the second non-inverted control node NF2;

[0797] The gate of the second seventh transistor M27 is electrically connected with the light emitting control end EM1, the source of the second seventh transistor M27 is electrically connected with the second display low voltage end VS2, and the drain of the second seventh transistor M27 is electrically connected with the source of the second second driving transistor DT22;

[0798] The gate of the second eighth transistor M28 is electrically connected with the second inverse compensation control end GT2B, the source of the second eighth transistor M28 is electrically connected with the second inverse control node NF2, and the drain of the second eighth transistor M28 is electrically connected with the drain of the second second driving transistor DT22;

[0799] The gate of the second ninth transistor M29 is electrically connected with the second control reset end RSTC2, the source of the second ninth transistor M29 is electrically connected with the second inverse control initial voltage end CIN2, and the drain of the second ninth transistor M29 is electrically connected with the second inverse control node NF2;

[0800] The gate of the second tenth transistor M210 is electrically connected with the second inverse compensation control end GT2B, the source of the second tenth transistor M210 is electrically connected with the second display data voltage end DL2, and the drain of the second tenth transistor M210 is electrically connected with the source of the second second driving transistor DT22;

[0801] The first end of the second third capacitor C23 is electrically connected with the second inverse control node NF2, and the second end of the second third capacitor C23 is electrically connected with VS1;

[0802] The third write circuit comprises a third second transistor M32, and the third control energy storage circuit comprises a third first capacitor C31;

[0803] The gate of the third first transistor M31 is electrically connected with the third on-off control node NT3, the source of the third first transistor M31 is electrically connected with the third display driving control node NQ3, and the drain of the third first transistor M31 is electrically connected with the third display node NX3;

[0804] The gate of the third second transistor M32 is electrically connected with the third control reset end RSTC3, the source of the third second transistor M32 is electrically connected with the third control data voltage end DTC3, and the drain of the third second transistor M32 is electrically connected with the third on-off control node NT3;

[0805] The first end of the third first capacitor C31 is electrically connected with the display control end SWP, and the second end of the third first capacitor C31 is electrically connected with the third on-off control node NT3;

[0806] The third first driving transistor DT31, the third third transistor M33, the third fourth transistor M34, the third fifth transistor M35, the third sixth transistor M36 and the third second capacitor C32 are arranged in the third first driving circuit.

[0807] The gate of the third first driving transistor DT31 is electrically connected with the third control node NC3.

[0808] The gate of the third third transistor M33 is electrically connected with the light-emitting control end EM1, the source of the third third transistor M33 is electrically connected with the third display power voltage end VD3, and the drain of the third third transistor M33 is electrically connected with the source of the third first driving transistor DT31.

[0809] The gate of the third fourth transistor M34 is electrically connected with the third compensation control end GT3N, the source of the third fourth transistor M34 is electrically connected with the third control node NC3, and the drain of the third fourth transistor M34 is electrically connected with the drain of the third first driving transistor DT31.

[0810] The gate of the third fifth transistor M35 is electrically connected with the third control reset end RSTC3, the source of the third fifth transistor M35 is electrically connected with the third control initial voltage end CI3, and the drain of the third fifth transistor M35 is electrically connected with the third control node NC3.

[0811] The gate of the third sixth transistor M36 is electrically connected with the third write control end Gat3, the source of the third sixth transistor M36 is electrically connected with the third display data voltage end DL3, and the drain of the third sixth transistor M36 is electrically connected with the source of the third first driving transistor DT31.

[0812] The first end of the third second capacitor C32 is electrically connected with the third control node NC3, and the second end of the third second capacitor C32 is electrically connected with VD3.

[0813] The third second driving transistor DT32, the third seventh transistor M37, the third eighth transistor M38, the third ninth transistor M39, the third tenth transistor M310 and the third third capacitor C33 are arranged in the third second driving circuit.

[0814] The third second drive transistor DT32 has a gate electrically connected to the third non-inverted control node NF3;

[0815] The third seventh transistor M37 has a gate electrically connected to the light-emitting control end EM1, a source electrically connected to the third display low voltage end VS3, and a drain electrically connected to the source of the third second drive transistor DT32;

[0816] The third eighth transistor M38 has a gate electrically connected to the third non-inverted compensation control end GT3B, a source electrically connected to the third non-inverted control node NF3, and a drain electrically connected to the drain of the third second drive transistor DT32;

[0817] The third ninth transistor M39 has a gate electrically connected to the third control reset end RSTC3, a source electrically connected to the third non-inverted control initial voltage end CIN3, and a drain electrically connected to the third non-inverted control node NF3;

[0818] The third tenth transistor M310 has a gate electrically connected to the third non-inverted compensation control end GT3B, a source electrically connected to the third display data voltage end DL3, and a drain electrically connected to the source of the third second drive transistor DT32;

[0819] The third third capacitor C33 has a first end electrically connected to the third non-inverted control node NF3 and a second end electrically connected to VS3;

[0820] The driving circuit includes a display drive transistor DT, the data writing circuit includes a first control transistor T1, the display energy storage circuit includes a storage capacitor Cst, the compensation control circuit includes a second control transistor T2, the first reset circuit includes a third control transistor T3, the display light-emitting control circuit includes a fourth control transistor T4, and the display control circuit includes a fifth control transistor T5;

[0821] The display drive transistor DT has a gate electrically connected to the driving node N1;

[0822] The gate of the first control transistor T1 is electrically connected with the display scanning end Gat, the source of the first control transistor T1 is electrically connected with the data voltage end DA1, and the drain of the first control transistor T1 is electrically connected with the source of the display driving transistor DT;

[0823] The first end of the storage capacitor Cst is electrically connected with the driving node N1, and the second end of the storage capacitor Cst is electrically connected with VDD1;

[0824] The gate of the second control transistor T2 is electrically connected with the compensation control end Gat1N, the source of the second control transistor T2 is electrically connected with the driving node N1, and the drain of the second control transistor T2 is electrically connected with the drain of the display driving transistor DT;

[0825] The gate of the third control transistor T3 is electrically connected with the reset control end RST1, the source of the third control transistor T3 is electrically connected with the display initial voltage end I1, and the drain of the third control transistor T3 is electrically connected with the driving node N1;

[0826] The gate of the fourth control transistor T4 is electrically connected with the light-emitting control end EM1, the source of the fourth control transistor T4 is electrically connected with the power voltage end VDD1, and the drain of the fourth control transistor T4 is electrically connected with the source of the display driving transistor DT;

[0827] The gate of the fifth control transistor T5 is electrically connected with the display control node SX, the source of the fifth control transistor T5 is electrically connected with the source of the display driving transistor DT, and the drain of the fifth control transistor T5 is electrically connected with the driving current output end OT;

[0828] The node control circuit comprises a sixth control transistor T6 and a first control capacitor C1;

[0829] The gate of the sixth control transistor T6 is electrically connected with the reset control end RST1, the source of the sixth control transistor T6 is electrically connected with the display control data voltage end DAT, and the drain of the sixth control transistor T6 is electrically connected with the display control node SX;

[0830] The first end of the first control capacitor C1 is electrically connected with the display control end SWP, and the second end of the first control capacitor C1 is electrically connected with the display control node SX;

[0831] The pixel driving circuit further comprises a reset transistor TR, the gate of the reset transistor TR is electrically connected with RST1, the source of the reset transistor TR is electrically connected with I1, and the drain of the reset transistor TR is electrically connected with the anode of O1.

[0832] In at least one embodiment of FIG. 14, the first light emitting element is a first organic light emitting diode O1, the second light emitting element is a second organic light emitting diode O2, the third light emitting element is a third organic light emitting diode O3, the fourth light emitting element is a fourth organic light emitting diode O4, and the first voltage terminal is a low voltage terminal VSS1.

[0833] In at least one embodiment of the present disclosure, the first pole of the first light emitting element is an anode of O1, the second pole of the first light emitting element is a cathode of O1, the first pole of the second light emitting element is an anode of O2, the second pole of the second light emitting element is a cathode of O2, the first pole of the third light emitting element is an anode of O3, the second pole of the third light emitting element is a cathode of O3, the first pole of the fourth light emitting element is an anode of O4, and the second pole of the fourth light emitting element is a cathode of O4; the cathode of O4 is electrically connected to VSS1.

[0834] In at least one embodiment of the pixel circuit shown in FIG. 14, T4, T1, DT and T5 are p-type transistors, T2, T3, TR and T6 are n-type transistors;

[0835] M13, DT11, M17 and M11 are p-type transistors, M14, M15, M110, M18, DT12, M19 and M12 are n-type transistors;

[0836] M23, DT21, M27 and M21 are p-type transistors, M24, M25, M210, M28, DT22, M29 and M22 are n-type transistors;

[0837] M33, DT31, M37 and M31 are p-type transistors, M34, M35, M310, M38, DT32, M39 and M32 are n-type transistors.

[0838] In at least one embodiment of the pixel circuit shown in FIG. 14,

[0839] The first first display driving circuit includes DT11, M13, M14, M15, M16 and C12, and the first first display driving circuit can control whether to provide a first first driving current flowing from VD1 to NQ1 according to a data voltage provided by DL1;

[0840] The first second display driving circuit includes DT12, M17, M18, M19, M110 and C13; the first second display driving circuit can control whether to provide a first second driving current flowing from NQ1 to VS1 according to a data voltage provided by DL1;

[0841] The first display control circuit includes M11, M12 and C11, under the control of the data voltage provided by DTC1 and the display control signal provided by SWP, M12 and C11 control the potential of NT1, and under the control of the potential of NT1, M11 controls the communication or disconnection between NQ1 and NX1;

[0842] The second first display driving circuit includes DT21, M23, M24, M25, M26 and C22, and can control whether to provide the second first driving current flowing from NQ2 to VS2 according to the data voltage provided by DL2;

[0843] The second second display driving circuit includes DT22, M27, M28, M29, M210 and C23, and can control whether to provide the second second driving current flowing from NQ2 to VS2 according to the data voltage provided by DL2;

[0844] The second display control circuit includes M21, M22 and C21, under the control of the data voltage provided by DTC2 and the display control signal provided by SWP, M22 and C21 control the potential of NT2, and under the control of the potential of NT2, M21 controls the communication or disconnection between NQ2 and NX2;

[0845] The third first display driving circuit includes DT31, M33, M34, M35, M36 and C32, and can control whether to provide the third first driving current flowing from NQ3 to VS3 according to the data voltage provided by DL3;

[0846] The third second display driving circuit includes DT32, M37, M38, M39, M310 and C33, and can control whether to provide the third second driving current flowing from NQ3 to VS3 according to the data voltage provided by DL3;

[0847] The third display control circuit includes M31, M32 and C31, under the control of the data voltage provided by DTC3 and the display control signal provided by SWP, M32 and C31 control the potential of NT3, and under the control of the potential of NT3, M31 controls the communication or disconnection between NQ3 and NX3.

[0848] At least one embodiment of the pixel circuit shown in FIG. 14 works as follows in the light-emitting stage,

[0849] When the light-emitting current flowing through O1 is equal to the light-emitting current flowing through O2, the first first display driving circuit and the first second display driving circuit do not provide current;

[0850] When the light emitting current flowing through O1 is less than the light emitting current flowing through O2, the first first display driving circuit provides a first first driving current flowing from VD1 to NQ1;

[0851] When the light emitting current flowing through O1 is greater than the light emitting current flowing through O2, th...

Claims

1. A pixel circuit, comprising a pixel driving circuit, N light emitting elements, and N current control circuits; N is an integer greater than 1; the pixel driving circuit is electrically connected with a display control terminal, for generating a driving current, and outputting the driving current through a driving current output terminal under the control of a display control signal provided by the display control terminal; a first electrode of a first light emitting element is electrically connected with the driving current output terminal; a second electrode of an Nth light emitting element and a first electrode of an N+1th light emitting element are both electrically connected with an Nth display node, and the second electrode of the Nth light emitting element is electrically connected with a first voltage terminal; n is a positive integer less than N; an Nth current control circuit is electrically connected with the display control terminal and the Nth display node, for controlling an Nth control current provided to the Nth display node under the control of the display control signal.

2. The pixel circuit of claim 1, wherein, a display period of the pixel circuit comprises a light emitting phase; the display control terminal is configured to provide a display control signal with gradually decreasing potential during at least part of the light emitting phase, or to provide a display control signal with gradually increasing potential during at least part of the light emitting phase.

3. The pixel circuit of claim 2, wherein, the light emitting phase comprises a plurality of light emitting time periods; the display control terminal is configured to provide a display control signal with gradually decreasing potential during the light emitting time periods; or the display control terminal is configured to provide a display control signal with gradually increasing potential during the light emitting time periods.

4. The pixel circuit of claim 1, wherein, the Nth current control circuit comprises an Nth display driving circuit and an Nth display control circuit; the Nth display driving circuit is electrically connected with an Nth display data voltage terminal and an Nth display driving control node, for controlling whether to provide an Nth control current according to an Nth display data voltage provided by the Nth display data voltage terminal; the Nth display control circuit is electrically connected with the Nth display driving control node, an Nth control data voltage terminal, the display control terminal, and the Nth display node, for controlling the Nth display node to be connected or disconnected with the Nth display driving control node according to the display control signal and an Nth control data voltage provided by the Nth control data voltage terminal.

5. The pixel circuit of claim 4, wherein, the Nth control current comprises an Nth first driving current and / or an Nth second driving current; the Nth display driving circuit comprises an Nth first display driving circuit and / or an Nth second display driving circuit; the Nth first display driving circuit is electrically connected with the Nth display data voltage terminal, the Nth display driving control node, an Nth display power voltage terminal, and a light emitting control terminal, for controlling whether to provide an Nth first driving current flowing from the Nth display power voltage terminal to the Nth display driving control node according to an Nth display data voltage provided by the Nth display data voltage terminal under the control of a light emitting control signal provided by the light emitting control terminal. The nth second display driving circuit is electrically connected with the nth display data voltage terminal, the nth display driving control node, the nth display low voltage terminal and the light emitting control terminal respectively, and is configured to control whether to provide the nth second driving current flowing from the nth display driving control node to the nth display low voltage terminal according to the nth display data voltage under control of the light emitting control signal.

6. The pixel circuit of claim 4, wherein, The nth display control circuit comprises an nth on-off control circuit, an nth writing circuit and an nth control energy storage circuit. The nth on-off control circuit is electrically connected with the nth on-off control node, the nth display node and the nth display driving control node respectively, and is configured to control the nth display node and the nth display driving control node to be connected or disconnected under control of the potential of the nth on-off control node. The nth writing circuit is electrically connected with the nth control reset terminal, the nth control data voltage terminal and the nth on-off control node respectively, and is configured to write the nth control data voltage provided by the nth control data voltage terminal into the nth on-off control node under control of the nth control reset signal provided by the nth control reset terminal. The nth control energy storage circuit is electrically connected with the display control terminal and the nth on-off control node respectively, and is configured to control the potential of the nth on-off control node under control of the display control signal.

7. The pixel circuit of claim 4, wherein, The nth display control circuit comprises an nth control circuit and an nth display driving control circuit. The nth control circuit is electrically connected with the light emitting control terminal, the nth intermediate node and the nth display node respectively, and is configured to control the nth intermediate node and the nth display node to be connected or disconnected under control of the light emitting control signal provided by the light emitting control terminal. The nth display control circuit comprises an nth on-off control circuit, an nth control energy storage circuit, an nth setting circuit, an nth control compensation circuit, an nth initialization circuit, an nth first voltage providing circuit and an nth second voltage providing circuit. The nth on-off control circuit is electrically connected with the nth on-off control node, the nth display driving control node and the nth intermediate node respectively, and is configured to control the nth display driving control node and the nth intermediate node to be connected or disconnected under control of the potential of the nth on-off control node. The first end of the nth control energy storage circuit is electrically connected with the nth on-off control node, and the second end of the nth control energy storage circuit is electrically connected with the nth writing node, and the nth control energy storage circuit is configured to store electric energy. The nth setting circuit is electrically connected with the nth control reset terminal, the nth control initial voltage terminal, the nth on-off control node and the nth writing node respectively, and is configured to write the nth control initial voltage provided by the nth control initial voltage terminal into the nth on-off control node and the nth writing node under control of the nth control reset signal provided by the nth control reset terminal. The nth control compensation circuit is electrically connected with the nth compensation control end, the nth display driving control node and the nth on-off control node, and is used for controlling the communication or disconnection between the nth display driving control node and the nth on-off control node under the control of the nth compensation control signal provided by the nth compensation control end; The nth initialization circuit is electrically connected with the nth write control end, the reference voltage end and the nth intermediate node, and is used for writing the reference voltage provided by the reference voltage end into the nth intermediate node under the control of the nth write control signal provided by the nth write control end; The nth first voltage providing circuit is electrically connected with the nth write control end, the nth control data voltage end and the nth write node, and is used for writing the nth control data voltage provided by the nth control data voltage end into the nth write node under the control of the nth write control signal. The nth current control circuit comprises a nth display control circuit; 8. The pixel circuit of claim 1, wherein, The nth display control circuit is electrically connected with the light emitting control end, the nth display node and the nth display driving control node, and is used for controlling the communication or disconnection between the nth display node and the nth display driving control node under the control of the light emitting control signal provided by the light emitting control end; The nth display control circuit further comprises a nth first display driving circuit and / or a nth second display driving circuit, the display control end comprises a first display control end and / or a second display control end, and the nth control current comprises a nth first driving current and / or a nth second driving current; The nth first display driving circuit is electrically connected with the nth display data voltage end, the nth display driving control node, the nth display power voltage end, the light emitting control end and the first display control end, and is used for controlling whether to provide the nth first driving current flowing from the nth display power voltage end to the nth display driving control node according to the first display control signal provided by the first display control end and the nth display data voltage provided by the nth display data voltage end under the control of the light emitting control signal provided by the light emitting control end; The nth second display driving circuit is electrically connected with the nth display data voltage end, the nth display driving control node, the nth display low voltage end, the light emitting control end and the second display control end, and is used for controlling whether to provide the nth second driving current flowing from the nth display driving control node to the nth display low voltage end according to the second display control signal provided by the second display control end and the nth display data voltage under the control of the light emitting control signal. The display period of the pixel circuit comprises a light emitting stage.

9. The pixel circuit of claim 8, wherein, ​ The first display control terminal is configured to provide a first display control signal with gradually decreasing potential during at least part of the light emitting stage. The second display control terminal is configured to provide a second display control signal with gradually increasing potential during at least part of the light emitting stage.

10. The pixel circuit of claim 5, wherein, The nth first display driving circuit comprises an nth first driving circuit, an nth first light emitting control circuit, an nth first compensation circuit, an nth first reset circuit, an nth first data writing circuit and an nth first energy storage circuit. The control terminal of the nth first driving circuit is electrically connected with the nth control node, and the nth first driving circuit is configured to generate an nth first driving current under the control of the potential of the nth control node. The nth first light emitting control circuit is electrically connected with the light emitting control terminal, the nth display power voltage terminal and the first terminal of the nth first driving circuit respectively, and is configured to control the communication or disconnection between the nth display power voltage terminal and the first terminal of the nth first driving circuit under the control of the light emitting control signal provided by the light emitting control terminal. The nth first compensation circuit is electrically connected with the nth compensation control terminal, the nth control node and the second terminal of the nth first driving circuit respectively, and is configured to control the communication or disconnection between the nth control node and the second terminal of the nth first driving circuit under the control of the nth compensation control signal provided by the nth compensation control terminal. The nth first reset circuit is electrically connected with the nth control reset terminal, the nth control initial voltage terminal and the nth control node respectively, and is configured to write the nth control initial voltage provided by the nth control initial voltage terminal into the nth control node under the control of the nth control reset signal. The nth first data writing circuit is electrically connected with the nth writing control terminal, the nth display data voltage terminal and the first terminal of the nth first driving circuit respectively, and is configured to write the nth display data voltage provided by the nth display data voltage terminal into the first terminal of the nth first driving circuit under the control of the nth writing control signal provided by the nth writing control terminal. The nth first energy storage circuit is electrically connected with the nth control node, and is configured to maintain the potential of the nth control node.

11. The pixel circuit of claim 5, wherein, The nth second display driving circuit comprises an nth second driving circuit, an nth second light emitting control circuit, an nth second compensation circuit, an nth second reset circuit, an nth second data writing circuit and an nth second energy storage circuit. The control terminal of the nth second driving circuit is electrically connected with the nth inverted control node, and the nth second driving circuit is configured to generate an nth second driving current under the control of the potential of the nth inverted control node. The nth second light emitting control circuit is electrically connected with the light emitting control terminal, the nth display low voltage terminal and the first terminal of the nth second driving circuit respectively, and is configured to control the communication or disconnection between the nth display low voltage terminal and the first terminal of the nth second driving circuit under the control of the light emitting control signal provided by the light emitting control terminal. The nth second compensation circuit is electrically connected with the nth opposite compensation control end, the nth opposite control node and the second end of the nth second driving circuit respectively, and is used for controlling the communication or disconnection between the nth opposite control node and the second end of the nth second driving circuit under the control of the nth opposite compensation control signal provided by the nth opposite compensation control end. The nth second reset circuit is electrically connected with the nth control reset end, the nth opposite control initial voltage end and the nth opposite control node respectively, and is used for writing the nth opposite control initial voltage provided by the nth opposite control initial voltage end into the nth opposite control node under the control of the nth control reset signal. The nth second data writing circuit is electrically connected with the nth opposite writing control end, the nth display data voltage end and the first end of the nth second driving circuit respectively, and is used for writing the nth display data voltage provided by the nth display data voltage end into the first end of the nth second driving circuit under the control of the nth opposite writing control signal provided by the nth opposite writing control end. The nth second energy storage circuit is electrically connected with the nth opposite control node, and is used for maintaining the potential of the nth opposite control node.

12. The pixel circuit of claim 8, wherein, The nth first display driving circuit comprises a nth first driving circuit, a nth first light emitting control circuit, a nth first compensation circuit, a nth first reset circuit, a nth first energy storage circuit, a nth first data writing circuit and a nth first driving control circuit. The control end of the nth first driving circuit is electrically connected with the nth control node, and the nth first driving circuit is used for generating the nth first driving current under the control of the potential of the nth control node. The nth first light emitting control circuit is electrically connected with the light emitting control end, the nth display power voltage end and the first end of the nth first driving circuit respectively, and is used for controlling the communication or disconnection between the nth display power voltage end and the first end of the nth first driving circuit under the control of the light emitting control signal provided by the light emitting control end. The nth first compensation circuit is electrically connected with the nth compensation control end, the nth control node and the second end of the nth first driving circuit respectively, and is used for controlling the communication or disconnection between the nth control node and the second end of the nth first driving circuit under the control of the nth compensation control signal provided by the nth compensation control end. The nth first reset circuit is electrically connected with the nth control reset end, the nth control initial voltage end and the nth control node respectively, and is used for writing the nth control initial voltage provided by the nth control initial voltage end into the nth control node under the control of the nth control reset signal. The nth first energy storage circuit is electrically connected with the nth control node, and is used for maintaining the potential of the nth control node. The nth first data write circuit is electrically connected with the nth write control end, the nth display data voltage end and the first end of the nth first drive circuit respectively, and is used for writing the nth display data voltage provided by the nth display data voltage end into the first end of the nth first drive circuit under the control of the nth write control signal provided by the nth write control end; The nth first drive control circuit comprises an nth first drive energy storage circuit, an nth first control drive circuit, an nth third light emitting control circuit, an nth first write circuit, an nth first control compensation circuit and an nth first setting circuit; The first end of the nth first drive energy storage circuit is electrically connected with the first display control end, and the second end of the nth first drive energy storage circuit is electrically connected with the nth first drive control node, and the nth first drive energy storage circuit is used for storing electric energy; The control end of the nth first control drive circuit is electrically connected with the nth first drive control node, the first end of the nth first control drive circuit is electrically connected with the nth first drive node, and the second end of the nth first control drive circuit is electrically connected with the nth control node, and the nth first control drive circuit is used for controlling the communication or disconnection between the nth first drive node and the nth control node under the control of the potential of the nth first drive control node; The nth third light emitting control circuit is electrically connected with the light emitting control end, the nth display power voltage end and the nth first drive node respectively, and is used for controlling the communication or disconnection between the nth display power voltage end and the nth first drive node under the control of the light emitting control signal provided by the light emitting control end; The nth first write circuit is electrically connected with the nth control scanning end, the nth control data voltage end and the nth first drive node respectively, and is used for writing the nth control data voltage provided by the nth control data voltage end into the nth first drive node under the control of the nth control scanning signal provided by the nth control scanning end; The nth first control compensation circuit is electrically connected with the nth control scanning end, the nth first drive control node and the nth control node respectively, and is used for controlling the communication or disconnection between the nth first drive control node and the nth control node under the control of the nth control scanning signal; The nth first setting circuit is electrically connected with the nth control reset end, the nth control initial voltage end and the nth first drive control node respectively, and is used for writing the nth control initial voltage provided by the nth control initial voltage end into the nth first drive control node under the control of the nth control reset signal provided by the nth control reset end.

13. The pixel circuit of claim 8, wherein, The nth second display drive circuit comprises an nth second drive circuit, an nth second light emitting control circuit, an nth second compensation circuit, an nth second reset circuit, an nth second energy storage circuit, an nth second data write circuit and an nth second drive control circuit; The control end of the nth second driving circuit is electrically connected with the nth opposite control node, and the nth second driving circuit is used for generating an nth second driving current under the control of the potential of the nth opposite control node; The nth second light-emitting control circuit is electrically connected with the light-emitting control end, the nth display low-voltage end and the first end of the nth second driving circuit respectively, and is used for controlling the communication or disconnection between the nth display low-voltage end and the first end of the nth second driving circuit under the control of the light-emitting control signal provided by the light-emitting control end; The nth second compensation circuit is electrically connected with the nth opposite compensation control end, the nth opposite control node and the second end of the nth second driving circuit respectively, and is used for controlling the communication or disconnection between the nth opposite control node and the second end of the nth second driving circuit under the control of the nth opposite compensation control signal provided by the nth opposite compensation control end; The nth second reset circuit is electrically connected with the nth control reset end, the nth opposite control initial voltage end and the nth opposite control node respectively, and is used for writing the nth opposite control initial voltage provided by the nth opposite control initial voltage end into the nth opposite control node under the control of the nth control reset signal; The nth second energy storage circuit is electrically connected with the nth opposite control node, and is used for maintaining the potential of the nth opposite control node; The nth second data writing circuit is electrically connected with the nth opposite writing control end, the nth display data voltage end and the first end of the nth second driving circuit respectively, and is used for writing the nth display data voltage provided by the nth display data voltage end into the first end of the nth second driving circuit under the control of the nth opposite writing control signal provided by the nth opposite writing control end; The nth second driving control circuit comprises an nth second driving energy storage circuit, an nth second control driving circuit, an nth fourth light-emitting control circuit, an nth second data writing circuit, an nth second control compensation circuit and an nth second setting circuit; The first end of the nth second driving energy storage circuit is electrically connected with the second display control end, the second end of the nth second driving energy storage circuit is electrically connected with the nth second driving control node, and the nth second driving energy storage circuit is used for storing electric energy; The control end of the nth second control driving circuit is electrically connected with the nth second driving control node, the first end of the nth second control driving circuit is electrically connected with the nth second driving node, the second end of the nth second control driving circuit is electrically connected with the nth opposite control node, and the nth second control driving circuit is used for controlling the communication or disconnection between the nth second driving node and the nth opposite control node under the control of the potential of the nth second driving control node. The nth fourth light-emitting control circuit is electrically connected with the light-emitting control end, the nth display low-voltage end and the nth second driving node respectively, and is used for controlling the communication or disconnection between the nth display low-voltage end and the nth second driving node under the control of a light-emitting control signal provided by the light-emitting control end; The nth second data writing circuit is electrically connected with the nth inverse control scanning end, the nth control data voltage end and the nth second driving node respectively, and is used for writing the nth control data voltage provided by the nth control data voltage end into the nth second driving node under the control of the nth inverse control scanning signal provided by the nth inverse control scanning end; The nth second control compensation circuit is electrically connected with the nth inverse control scanning end, the nth second driving control node and the nth inverse control node respectively, and is used for controlling the communication or disconnection between the nth second driving control node and the nth inverse control node under the control of the nth inverse control scanning signal; The nth second setting circuit is electrically connected with the nth control reset end, the nth inverse control initial voltage end and the nth second driving control node respectively, and is used for writing the nth inverse control initial voltage provided by the nth inverse control initial voltage end into the nth second driving control node under the control of the nth control reset signal provided by the nth control reset end.

14. The pixel circuit of claim 1, wherein, The pixel driving circuit comprises a driving circuit, a data writing circuit, a display energy storage circuit, a compensation control circuit, a first reset circuit, a display light-emitting control circuit, a display control circuit and a node control circuit; The driving circuit is electrically connected with a driving node, and is used for generating the driving current under the control of the potential of the driving node; The data writing circuit is electrically connected with a display scanning end, a data voltage end and a first end of the driving circuit respectively, and is used for writing the data voltage provided by the data voltage end into the first end of the driving circuit under the control of a display scanning signal provided by the display scanning end; The display energy storage circuit is electrically connected with the driving node, and is used for maintaining the potential of the driving node; The compensation control circuit is electrically connected with a compensation control end, the driving node and a second end of the driving circuit respectively, and is used for controlling the communication or disconnection between the driving node and the second end of the driving circuit under the control of a compensation control signal provided by the compensation control end; The first reset circuit is electrically connected with a reset control end, a display initial voltage end and the driving node respectively, and is used for writing the display initial voltage provided by the display initial voltage end into the driving node under the control of a reset control signal provided by the reset control end; The display light-emitting control circuit is electrically connected with a light-emitting control end, a power voltage end and the first end of the driving circuit respectively, and is used for controlling the communication or disconnection between the power voltage end and the first end of the driving circuit under the control of a light-emitting control signal provided by the light-emitting control end. The display control circuit is electrically connected with the display control node, the second end of the drive circuit and the drive current output end respectively, and is used for controlling the communication or disconnection between the second end of the drive circuit and the drive current output end under the control of the potential of the display control node. The node control circuit is electrically connected with the display control node, the reset control end, the display control data voltage end and the display control end respectively, and is used for writing the display control data voltage provided by the display control data voltage end into the display control node under the control of the reset control signal, and controlling the potential of the display control node according to the display control signal.

15. The pixel circuit of claim 1, wherein, The pixel drive circuit comprises a drive circuit, a data writing circuit, a display energy storage circuit, a compensation control circuit, a first reset circuit, a first display light emitting control circuit, a second display light emitting control circuit, a display control circuit, a control reset circuit and a node control circuit. The drive circuit is electrically connected with the drive node, and is used for generating the drive current under the control of the potential of the drive node. The data writing circuit is electrically connected with the display scanning end, the data voltage end and the first end of the drive circuit respectively, and is used for writing the data voltage provided by the data voltage end into the first end of the drive circuit under the control of the display scanning signal provided by the display scanning end. The display energy storage circuit is electrically connected with the drive node, and is used for maintaining the potential of the drive node. The compensation control circuit is electrically connected with the compensation control end, the drive node and the second end of the drive circuit respectively, and is used for controlling the communication or disconnection between the drive node and the second end of the drive circuit under the control of the compensation control signal provided by the compensation control end. The first reset circuit is electrically connected with the reset control end, the display initial voltage end and the drive node respectively, and is used for writing the display initial voltage provided by the display initial voltage end into the drive node under the control of the reset control signal provided by the reset control end. The first display light emitting control circuit is electrically connected with the light emitting control end, the power voltage end and the first end of the drive circuit respectively, and is used for controlling the communication or disconnection between the power voltage end and the first end of the drive circuit under the control of the light emitting control signal provided by the light emitting control end. The second display light emitting control circuit is electrically connected with the light emitting control end, the second end of the drive circuit and the light emitting control node respectively, and is used for controlling the communication or disconnection between the second end of the drive circuit and the light emitting control node under the control of the light emitting control signal. The display control circuit is electrically connected with the display control node, the light emitting control node and the drive current output end respectively, and is used for controlling the communication or disconnection between the light emitting control node and the drive current output end under the control of the potential of the display control node. The control reset circuit is electrically connected with the display scanning end, the reference voltage end and the light emitting control node respectively, and is used for writing the reference voltage provided by the reference voltage end into the light emitting control node under the control of the display scanning signal. The node control circuit is electrically connected with the display control node, a display control data voltage terminal and the display control terminal respectively, and is configured to control a potential of the display control node according to a display control data voltage provided by the display control data voltage terminal and the display control signal.

16. The pixel circuit of claim 15, wherein, The node control circuit comprises a display control energy storage circuit, a first write control circuit, a second write control circuit, a control set circuit and a control compensation control circuit. A first end of the display control energy storage circuit is electrically connected with the display control node, and a second end of the display control energy storage circuit is electrically connected with a display write node. The first write control circuit is electrically connected with a display scanning terminal, a display control data voltage terminal and the display write node respectively, and is configured to write the display control data voltage into the display write node under control of the display scanning signal. The second write control circuit is electrically connected with a light-emitting control terminal, the display control terminal and the display write node respectively, and is configured to write the display control signal into the display write node under control of a light-emitting control signal provided by the light-emitting control terminal. The control set circuit is electrically connected with a reset control terminal, a display initial voltage terminal, the display control node and the display write node respectively, and is configured to write a display initial voltage provided by the display initial voltage terminal into the display control node and the display write node under control of a reset control signal provided by the reset control terminal. The control compensation control circuit is electrically connected with a compensation control terminal, the driving current output terminal and the display control node respectively, and is configured to control the driving current output terminal and the display control node to be in communication or disconnected under control of a compensation control signal provided by the compensation control terminal.

17. The pixel circuit of claim 16, wherein, The pixel driving circuit further comprises a third display light-emitting control circuit. The third display light-emitting control circuit is electrically connected with the light-emitting control terminal, the display control circuit and the driving current output terminal respectively, and is configured to control the display control circuit and the driving current output terminal to be in communication or disconnected under control of the light-emitting control signal.

18. The pixel circuit of any one of claims 1 to 13, wherein, The pixel driving circuit comprises a driving circuit, a display energy storage circuit, a data write circuit, a compensation control circuit, a first reset circuit, a first display light-emitting control circuit, a second display light-emitting control circuit and a driving node control circuit. The driving circuit is electrically connected with a driving node, and is configured to generate the driving current under control of a potential of the driving node. The display energy storage circuit is electrically connected with the driving node, and is configured to maintain the potential of the driving node. The data write circuit is electrically connected with a display scanning terminal, a data voltage terminal and a first end of the driving circuit respectively, and is configured to write a data voltage provided by the data voltage terminal into the first end of the driving circuit under control of a display scanning signal provided by the display scanning terminal. The compensation control circuit is electrically connected with a compensation control terminal, the driving node and a second end of the driving circuit respectively, and is configured to control the driving node and the second end of the driving circuit to be in communication or disconnected under control of a compensation control signal provided by the compensation control terminal. The first reset circuit is electrically connected with a reset control end, a display initial voltage end and the driving node respectively, and is used for writing the display initial voltage provided by the display initial voltage end into the driving node under the control of a reset control signal provided by the reset control end; The first display light emitting control circuit is electrically connected with a light emitting control end, a power voltage end and the first end of the driving circuit respectively, and is used for controlling the power voltage end and the first end of the driving circuit to be connected or disconnected under the control of a light emitting control signal provided by the light emitting control end; The second display light emitting control circuit is electrically connected with a light emitting control end, the second end of the driving circuit and the driving current output end respectively, and is used for controlling the second end of the driving circuit and the driving current output end to be connected or disconnected under the control of the light emitting control signal; The driving node control circuit comprises a third light emitting control circuit, a control driving circuit, a data writing control circuit, a control energy storage circuit, a control reset circuit and a control compensation circuit; The control end of the control driving circuit is electrically connected with a control driving node, the first end of the control driving circuit is electrically connected with a light emitting node, the second end of the control driving circuit is electrically connected with a driving node, and the control driving circuit is used for controlling the light emitting node and the driving node to be connected or disconnected under the control of the potential of the control driving node; The third light emitting control circuit is electrically connected with a light emitting control end, a power voltage end and the light emitting node respectively, and is used for controlling the power voltage end and the light emitting node to be connected or disconnected under the control of a light emitting control signal provided by the light emitting control end; The data writing control circuit is electrically connected with a display control scanning end, a display control data voltage end and the light emitting node respectively, and is used for writing the display control data voltage provided by the display control data voltage end into the light emitting node under the control of a display control scanning signal provided by the display control scanning end; The first end of the control energy storage circuit is electrically connected with a first display control end, the second end of the control energy storage circuit is electrically connected with the control driving node, and the control energy storage circuit is used for storing electric energy; The control reset circuit is electrically connected with a reset control end, a display initial voltage end and the control driving node respectively, and is used for writing the display initial voltage provided by the display initial voltage end into the control driving node under the control of a reset control signal provided by the reset control end; The control compensation circuit is electrically connected with a display control scanning end, the control driving node and a driving node respectively, and is used for controlling the control driving node and the driving node to be connected or disconnected under the control of the display control scanning signal.

19. The pixel circuit of claim 6, wherein, The nth on-off control circuit comprises an nth first transistor, the nth writing circuit comprises an nth second transistor, and the nth control energy storage circuit comprises an nth first capacitor. The gate of the nth first transistor is electrically connected with the nth on-off control node, the first pole of the nth first transistor is electrically connected with the nth display driving control node, and the second pole of the nth first transistor is electrically connected with the nth display node; The gate of the nth second transistor is electrically connected with the nth control reset end, the first pole of the nth second transistor is electrically connected with the nth control data voltage end, and the second pole of the nth second transistor is electrically connected with the nth on-off control node; The first end of the nth first capacitor is electrically connected with the display control end, and the second end of the nth first capacitor is electrically connected with the nth on-off control node.

20. The pixel circuit of claim 10, wherein, The nth first driving circuit comprises a nth first driving transistor, the nth first light-emitting control circuit comprises a nth third transistor, the nth first compensation circuit comprises a nth fourth transistor, the nth first reset circuit comprises a nth fifth transistor, the nth first data writing circuit comprises a nth sixth transistor, and the nth first energy storage circuit comprises a nth second capacitor; The gate of the nth first driving transistor is electrically connected with the nth control node; The gate of the nth third transistor is electrically connected with the light-emitting control end, the first pole of the nth third transistor is electrically connected with the nth display power voltage end, and the second pole of the nth third transistor is electrically connected with the first pole of the nth first driving transistor; The gate of the nth fourth transistor is electrically connected with the nth compensation control end, the first pole of the nth fourth transistor is electrically connected with the nth control node, and the second pole of the nth fourth transistor is electrically connected with the second pole of the nth first driving transistor; The gate of the nth fifth transistor is electrically connected with the nth control reset end, the first pole of the nth fifth transistor is electrically connected with the nth control initial voltage end, and the second pole of the nth fifth transistor is electrically connected with the nth control node; The gate of the nth sixth transistor is electrically connected with the nth writing control end, the first pole of the nth sixth transistor is electrically connected with the nth display data voltage end, and the second pole of the nth sixth transistor is electrically connected with the first pole of the nth first driving transistor; The first end of the nth second capacitor is electrically connected with the nth control node, and the second end of the nth second capacitor is electrically connected with the direct current voltage end.

21. The pixel circuit of claim 11, wherein, The nth second driving circuit comprises a nth second driving transistor, the nth second light-emitting control circuit comprises a nth seventh transistor, the nth second compensation circuit comprises a nth eighth transistor, the nth second reset circuit comprises a nth ninth transistor, the nth second data writing circuit comprises a nth tenth transistor, and the nth second energy storage circuit comprises a nth third capacitor; The gate of the nth second driving transistor is electrically connected with the nth inverted control node; The gate of the nth seventh transistor is electrically connected with the light-emitting control end, the first electrode of the nth seventh transistor is electrically connected with the nth display low voltage end, and the second electrode of the nth seventh transistor is electrically connected with the first electrode of the nth second driving transistor; The gate of the nth eighth transistor is electrically connected with the nth inverse compensation control end, the first electrode of the nth eighth transistor is electrically connected with the nth inverse control node, and the second electrode of the nth eighth transistor is electrically connected with the second electrode of the nth second driving transistor; The gate of the nth ninth transistor is electrically connected with the nth control reset end, the first electrode of the nth ninth transistor is electrically connected with the nth inverse control initial voltage end, and the second electrode of the nth ninth transistor is electrically connected with the nth inverse control node; The gate of the nth tenth transistor is electrically connected with the nth inverse write control end, the first electrode of the nth tenth transistor is electrically connected with the nth display data voltage end, and the second electrode of the nth tenth transistor is electrically connected with the first electrode of the nth second driving transistor; The first end of the nth third capacitor is electrically connected with the nth inverse control node, and the second end of the nth third capacitor is electrically connected with a direct current voltage end.

22. The pixel circuit of claim 14 or 15, wherein, The driving circuit comprises a display driving transistor, the data write circuit comprises a first control transistor, the display energy storage circuit comprises a storage capacitor, the compensation control circuit comprises a second control transistor, the first reset circuit comprises a third control transistor, the display light-emitting control circuit comprises a fourth control transistor, and the display control circuit comprises a fifth control transistor; The gate of the display driving transistor is electrically connected with the driving node; The gate of the first control transistor is electrically connected with the display scanning end, the first electrode of the first control transistor is electrically connected with the data voltage end, and the second electrode of the first control transistor is electrically connected with the first electrode of the display driving transistor; The first end of the storage capacitor is electrically connected with the driving node, and the second end of the storage capacitor is electrically connected with a direct current voltage end; The gate of the second control transistor is electrically connected with the compensation control end, the first electrode of the second control transistor is electrically connected with the driving node, and the second electrode of the second control transistor is electrically connected with the second electrode of the display driving transistor; The gate of the third control transistor is electrically connected with the reset control end, the first electrode of the third control transistor is electrically connected with the display initial voltage end, and the second electrode of the third control transistor is electrically connected with the driving node; The gate of the fourth control transistor is electrically connected with the light-emitting control end, the first electrode of the fourth control transistor is electrically connected with the power voltage end, and the second electrode of the fourth control transistor is electrically connected with the first electrode of the display driving transistor; The gate of the fifth control transistor is electrically connected with the display control node, the first electrode of the fifth control transistor is electrically connected with the first electrode of the display driving transistor, and the second electrode of the fifth control transistor is electrically connected with the driving current output end.

23. The pixel circuit of claim 14, wherein, The node control circuit comprises a sixth control transistor and a first control capacitor; The gate of the sixth control transistor is electrically connected with the reset control end, the first electrode of the sixth control transistor is electrically connected with the display control data voltage end, and the second electrode of the sixth control transistor is electrically connected with the display control node. The first end of the first control capacitor is electrically connected with the display control end, and the second end of the first control capacitor is electrically connected with the display control node.

24. The pixel circuit of claim 7, wherein, The nth on-off control circuit comprises an nth eleventh transistor, the nth control energy storage circuit comprises an nth fourth capacitor, the nth setting circuit comprises an nth twelfth transistor and an nth thirteenth transistor, the nth control compensation circuit comprises an nth fourteenth transistor, the nth initialization circuit comprises an nth fifteenth transistor, the nth first voltage providing circuit comprises an nth sixteenth transistor, and the nth second voltage providing circuit comprises an nth seventeenth transistor; The gate of the nth eleventh transistor is electrically connected with the nth on-off control node, the first electrode of the nth eleventh transistor is electrically connected with the nth display driving control node, and the second electrode of the nth eleventh transistor is electrically connected with the nth intermediate node. The first end of the nth fourth capacitor is electrically connected with the nth on-off control node, and the second end of the nth fourth capacitor is electrically connected with the nth write-in node. The gate of the nth twelfth transistor is electrically connected with the nth control reset end, the first electrode of the nth twelfth transistor is electrically connected with the nth control initial voltage end, and the second electrode of the nth twelfth transistor is electrically connected with the nth on-off control node. The gate of the nth thirteenth transistor is electrically connected with the nth control reset end, the first electrode of the nth thirteenth transistor is electrically connected with the nth control initial voltage end, and the second electrode of the nth thirteenth transistor is electrically connected with the nth write-in node. The gate of the nth fourteenth transistor is electrically connected with the nth compensation control end, the first electrode of the nth fourteenth transistor is electrically connected with the nth display driving control node, and the second electrode of the nth fourteenth transistor is electrically connected with the nth on-off control node. The gate of the nth fifteenth transistor is electrically connected with the nth write-in control end, the first electrode of the nth fifteenth transistor is electrically connected with the reference voltage end, and the second electrode of the nth fifteenth transistor is electrically connected with the nth intermediate node. The gate of the nth sixteenth transistor is electrically connected with the nth write-in control end, the first electrode of the nth sixteenth transistor is electrically connected with the nth control data voltage end, and the second electrode of the nth sixteenth transistor is electrically connected with the nth write-in node. The gate of the nth seventeenth transistor is electrically connected with the light-emitting control end, the first electrode of the nth seventeenth transistor is electrically connected with the display control end, and the second electrode of the nth seventeenth transistor is electrically connected with the nth write-in node.

25. The pixel circuit of claim 16, wherein, The control reset circuit comprises a sixth control transistor; the display control energy storage circuit comprises a first control capacitor, the first write control circuit comprises a seventh control transistor; the second write control circuit comprises an eighth control transistor; the control set circuit comprises a ninth control transistor and a tenth control transistor, and the control compensation control circuit comprises an eleventh control transistor; The gate of the sixth control transistor is electrically connected with the display scanning end, the first electrode of the sixth control transistor is electrically connected with the reference voltage end, and the second electrode of the sixth control transistor is electrically connected with the light-emitting control node; The first end of the first control capacitor is electrically connected with the display control node, and the second end of the first control capacitor is electrically connected with the display write node; The gate of the seventh control transistor is electrically connected with the display scanning end, the first electrode of the seventh control transistor is electrically connected with the display control data voltage end, and the second electrode of the seventh control transistor is electrically connected with the display write node; The gate of the eighth control transistor is electrically connected with the light-emitting control end, the first electrode of the eighth control transistor is electrically connected with the display control end, and the second electrode of the eighth control transistor is electrically connected with the display write node; The gate of the ninth control transistor is electrically connected with the reset control end, the first electrode of the ninth control transistor is electrically connected with the display initial voltage end, and the second electrode of the ninth control transistor is electrically connected with the display control node; The gate of the tenth control transistor is electrically connected with the reset control end, the first electrode of the tenth control transistor is electrically connected with the display initial voltage end, and the second electrode of the tenth control transistor is electrically connected with the display write node; The gate of the eleventh control transistor is electrically connected with the compensation control end, the first electrode of the eleventh control transistor is electrically connected with the driving current output end, and the second electrode of the eleventh control transistor is electrically connected with the display control node.

26. The pixel circuit of claim 17, wherein, The third display light-emitting control circuit comprises a twelfth control transistor; The gate of the twelfth control transistor is electrically connected with the light-emitting control end, the first electrode of the twelfth control transistor is electrically connected with the display control circuit, and the second electrode of the twelfth control transistor is electrically connected with the driving current output end.

27. The pixel circuit of claim 12, wherein, The nth first driving circuit comprises an nth first driving transistor, the nth first light-emitting control circuit comprises an nth first transistor, the nth first compensation circuit comprises an nth second transistor, the nth first reset circuit comprises an nth third transistor, the nth first energy storage circuit comprises an nth first capacitor, and the nth first write circuit comprises an nth fourth transistor; The gate of the nth first driving transistor is electrically connected with the nth control node; The gate of the nth first transistor is electrically connected with the light-emitting control end, the first electrode of the nth first transistor is electrically connected with the nth display power voltage end, and the second electrode of the nth first transistor is electrically connected with the first electrode of the nth first driving transistor; The gate of the nth second transistor is electrically connected with an nth compensation control end, the first pole of the nth second transistor is electrically connected with the nth control node, and the second pole of the nth second transistor is electrically connected with the second pole of the nth first driving transistor; The gate of the nth third transistor is electrically connected with an nth control reset end, the first pole of the nth third transistor is electrically connected with an nth control initial voltage end, and the second pole of the nth third transistor is electrically connected with the nth control node; The first end of the nth first capacitor is electrically connected with the nth control node, and the second end of the nth first capacitor is electrically connected with a direct current voltage end; The gate of the nth fourth transistor is electrically connected with an nth write control end, the first pole of the nth fourth transistor is electrically connected with an nth display data voltage end, and the second pole of the nth fourth transistor is electrically connected with the first pole of the nth first driving transistor.

28. The pixel circuit of claim 12, wherein, The nth first driving energy storage circuit comprises an nth second capacitor, the nth first control driving circuit comprises an nth fifth transistor, the nth third light-emitting control circuit comprises an nth sixth transistor, the nth first data write circuit comprises an nth seventh transistor, the nth first setting circuit comprises an nth eighth transistor, and the nth first control compensation circuit comprises an nth ninth transistor; The first end of the nth second capacitor is electrically connected with a first display control end, and the second end of the nth second capacitor is electrically connected with an nth first driving control node; The gate of the nth fifth transistor is electrically connected with the nth first driving control node, the first pole of the nth fifth transistor is electrically connected with an nth first driving node, and the second pole of the nth fifth transistor is electrically connected with the nth control node; The gate of the nth sixth transistor is electrically connected with a light-emitting control end, the first pole of the nth sixth transistor is electrically connected with an nth display power voltage end, and the second pole of the nth sixth transistor is electrically connected with the nth first driving node; The gate of the nth seventh transistor is electrically connected with an nth control scanning end, the first pole of the nth seventh transistor is electrically connected with an nth control data voltage end, and the second pole of the nth seventh transistor is electrically connected with the nth first driving node; The gate of the nth eighth transistor is electrically connected with an nth control reset end, the first pole of the nth eighth transistor is electrically connected with an nth control initial voltage end, and the second pole of the nth eighth transistor is electrically connected with the nth first driving control node; The gate of the nth ninth transistor is electrically connected with the nth control scanning end, the first pole of the nth ninth transistor is electrically connected with the nth first driving control node, and the second pole of the nth ninth transistor is electrically connected with the nth control node.

29. The pixel circuit of claim 13, wherein, The nth second driving circuit comprises an nth second driving transistor, the nth second light-emitting control circuit comprises an nth tenth transistor, the nth second compensation circuit comprises an nth eleventh transistor, the nth second reset circuit comprises an nth twelfth transistor, and the nth second energy storage circuit comprises an nth third capacitor; the nth second data writing circuit comprises an nth thirteenth transistor; The gate of the nth second driving transistor is electrically connected to the nth inverted control node; The gate of the nth tenth transistor is electrically connected to the light-emitting control end, the first pole of the nth tenth transistor is electrically connected to the nth display low voltage end, and the second pole of the nth tenth transistor is electrically connected to the first pole of the nth second driving transistor; The gate of the nth eleventh transistor is electrically connected to the nth inverted compensation control end, the first pole of the nth eleventh transistor is electrically connected to the nth inverted control node, and the second pole of the nth eleventh transistor is electrically connected to the second pole of the nth second driving transistor; The gate of the nth twelfth transistor is electrically connected to the nth control reset end, the first pole of the nth twelfth transistor is electrically connected to the nth inverted control initial voltage end, and the second pole of the nth twelfth transistor is electrically connected to the nth inverted control node; The first end of the nth third capacitor is electrically connected to the nth inverted control node, and the second end of the nth third capacitor is electrically connected to the direct current voltage end; The gate of the nth thirteenth transistor is electrically connected to the nth inverted writing control end, the first pole of the nth thirteenth transistor is electrically connected to the nth display data voltage end, and the second pole of the nth thirteenth transistor is electrically connected to the first pole of the nth second driving transistor.

30. The pixel circuit of claim 13, wherein, The nth second driving energy storage circuit comprises an nth fourth capacitor, the nth second control driving circuit comprises an nth fourteenth transistor, the nth fourth light-emitting control circuit comprises an nth fifteenth transistor, the nth second data writing circuit comprises an nth sixteenth transistor, the nth second control compensation circuit comprises an nth seventeenth transistor, and the nth second set circuit comprises an nth eighteenth transistor; The first end of the nth fourth capacitor is electrically connected to the second display control end, and the second end of the nth fourth capacitor is electrically connected to the nth second driving control node; The gate of the nth fourteenth transistor is electrically connected to the nth second driving control node, the first pole of the nth fourteenth transistor is electrically connected to the nth second driving node, and the second pole of the nth fourteenth transistor is electrically connected to the nth inverted control node; The gate of the nth fifteenth transistor is electrically connected to the light-emitting control end, the first pole of the nth fifteenth transistor is electrically connected to the nth display low voltage end, and the second pole of the nth fifteenth transistor is electrically connected to the nth second driving node; The gate of the nth sixteenth transistor is electrically connected with the nth inverse control scanning end, the first electrode of the nth sixteenth transistor is electrically connected with the nth control data voltage end, and the second electrode of the nth sixteenth transistor is electrically connected with the nth second driving node; The gate of the nth seventeenth transistor is electrically connected with the nth inverse control scanning end, the first electrode of the nth seventeenth transistor is electrically connected with the nth second driving control node, and the second electrode of the nth seventeenth transistor is electrically connected with the nth inverse control node; The gate of the nth eighteenth transistor is electrically connected with the nth control reset end, the first electrode of the nth eighteenth transistor is electrically connected with the nth inverse control initial voltage end, and the second electrode of the nth eighteenth transistor is electrically connected with the nth second driving control node.

31. The pixel circuit of claim 8, wherein, The nth display control circuit comprises an nth nineteenth transistor; The gate of the nth nineteenth transistor is electrically connected with the light-emitting control end, the first electrode of the nth nineteenth transistor is electrically connected with the nth display node, and the second electrode of the nth nineteenth transistor is electrically connected with the nth display driving control node.

32. The pixel circuit of claim 18, wherein, The driving circuit comprises a display driving transistor, the data writing circuit comprises a first control transistor, the display energy storage circuit comprises a storage capacitor, the compensation control circuit comprises a second control transistor, the first reset circuit comprises a third control transistor, the first display light-emitting control circuit comprises a first light-emitting control transistor, and the second display light-emitting control circuit comprises a second light-emitting control transistor; The gate of the display driving transistor is electrically connected with the driving node; The first end of the storage capacitor is electrically connected with the driving node, and the second end of the storage capacitor is electrically connected with a direct-current voltage end; The gate of the first control transistor is electrically connected with the display scanning end, the first electrode of the first control transistor is electrically connected with the data voltage end, and the second electrode of the first control transistor is electrically connected with the first electrode of the display driving transistor; The gate of the second control transistor is electrically connected with the compensation control end, the first electrode of the second control transistor is electrically connected with the driving node, and the second electrode of the second control transistor is electrically connected with the second electrode of the display driving transistor; The gate of the third control transistor is electrically connected with the reset control end, the first electrode of the third control transistor is electrically connected with the display initial voltage end, and the second electrode of the third control transistor is electrically connected with the driving node; The gate of the first light-emitting control transistor is electrically connected with the light-emitting control end, the first electrode of the first light-emitting control transistor is electrically connected with the power voltage end, and the second electrode of the first light-emitting control transistor is electrically connected with the first electrode of the display driving transistor; The gate of the second light-emitting control transistor is electrically connected with the light-emitting control end, the first electrode of the second light-emitting control transistor is electrically connected with the first electrode of the display driving transistor, and the second electrode of the second light-emitting control transistor is electrically connected with the driving current output end.

33. The pixel circuit of claim 18, wherein, The third light-emitting control circuit comprises a sixth control transistor, the control driving circuit comprises a seventh control transistor, the data writing control circuit comprises an eighth control transistor, the control energy storage circuit comprises a control capacitor, the control reset circuit comprises a ninth control transistor, and the control compensation circuit comprises a tenth control transistor The gate of the sixth control transistor is electrically connected to the light-emitting control end, the first electrode of the sixth control transistor is electrically connected to the power voltage end, and the second electrode of the sixth control transistor is electrically connected to the light-emitting node. The gate of the seventh control transistor is electrically connected to the control driving node, the first electrode of the seventh control transistor is electrically connected to the light-emitting node, and the second electrode of the seventh control transistor is electrically connected to the driving node. The gate of the eighth control transistor is electrically connected to the display control scanning end, the first electrode of the eighth control transistor is electrically connected to the display control data voltage end, and the second electrode of the eighth control transistor is electrically connected to the light-emitting node. The first end of the control capacitor is electrically connected to the first display control end, and the second end of the control capacitor is electrically connected to the control driving node. The gate of the ninth control transistor is electrically connected to the reset control end, the first electrode of the ninth control transistor is electrically connected to the display initial voltage end, and the second electrode of the ninth control transistor is electrically connected to the control driving node. The gate of the tenth control transistor is electrically connected to the display control scanning end, the first electrode of the tenth control transistor is electrically connected to the control driving node, and the second electrode of the tenth control transistor is electrically connected to the driving node.

34. A display device comprising the pixel circuit according to any one of claims 1 to 33.

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