Component carrier with embedded components and gaps filled with non-fibrous resin

Abstract

A component carrier (100) comprising: a stack (102) comprising a layer body (104), a first electrically insulating layer structure (106) without fibers comprising a first resin (108) on a bottom main surface of the layer body (104), and a second electrically insulating layer structure (110) without fibers comprising a second resin (112) on a top main surface of the layer body (104); and a component (114) inserted in a cavity (116) of the stack (102), wherein at least a portion of a gap (118) between the component (114) and a side wall (154) of the stack (102) delimiting the cavity (116) is partially filled with the first resin (108) and partially filled with the second resin (112).

Description

Technical Field

[0001] This invention relates to component carriers and methods for manufacturing component carriers. Background Technology

[0002] With the increasing functionality of products equipped with component carriers containing one or more electronic components, the miniaturization of such components, and the growing number of components to be mounted on or embedded in component carriers such as printed circuit boards, increasingly robust array-shaped components or packages with multiple contacts or connections with increasingly smaller spacing are being adopted. Heat removal generated by such components and the component carriers themselves during operation is becoming an increasingly important issue. Simultaneously, the component carriers must be mechanically robust and electrically reliable to operate even under harsh conditions.

[0003] To embed components within a stack, through-holes can be formed in the stack, and these through-holes can be sealed from the bottom side using a temporary carrier such as adhesive tape. A dielectric layer can be formed on top of the stack and the component. The temporary carrier is then released. Structures incorporating copper can also be formed. However, reliably securing and electrically connecting the embedded components remains a challenge.

[0004] EP 3,081,056 B1 discloses a method for embedding a component into a printed circuit board or a printed circuit board intermediate product, wherein the printed circuit board or the printed circuit board intermediate product has at least one insulating layer made of a prepreg material, and the component is fixed by a resin of the prepreg material. The method comprises the steps of: providing a composite of layers of the printed circuit board or the printed circuit board intermediate product, wherein the composite of layers of the printed circuit board or the printed circuit board intermediate product includes a plurality of layers of curable prepreg material and outer copper layers located on both sides; forming a void in the composite for receiving the component to be embedded; covering at least a region of the void on a first side of the composite by a first temporary carrier layer; positioning the component to be embedded in the void by means of the first temporary carrier layer; covering at least a region of the void on a second side of the composite by a second temporary carrier layer; compressing the composite having the component while curing the curable prepreg material; and removing the temporary carrier layer.

[0005] A component carrier with embedded parts may be needed, which can be manufactured in a simple manner and with high reliability. Summary of the Invention

[0006] According to an exemplary embodiment of the present invention, a component carrier is provided, wherein the component carrier includes: a stack comprising a layer body, a fiberless first electrical insulating layer structure comprising a first resin on a bottom main surface of the layer body, and a fiberless second electrical insulating layer structure comprising a second resin on a top main surface of the layer body; and a component inserted into a cavity of the stack, wherein at least a portion of the gap between the component and a sidewall defining the cavity of the stack is partially filled with the first resin and partially filled with the second resin.

[0007] According to another exemplary embodiment of the present invention, a method for manufacturing a component carrier is provided, wherein the method includes: forming a stack by arranging a fiberless first electrically insulating layer structure comprising a first resin on a bottom main surface of a layer body and by arranging a fiberless second electrically insulating layer structure comprising a second resin on a top main surface of a layer body; forming a cavity in the stack; inserting a component into the cavity of the stack; and partially filling at least a portion of the gap between the component and the sidewalls defining the cavity of the stack with the first resin and partially with the second resin.

[0008] In the context of this application, the term "component carrier" may specifically refer to any support structure capable of accommodating one or more components on and / or within a component carrier to provide mechanical support and / or electrical connection. In other words, a component carrier can be configured as a mechanical and / or electronic carrier for a component. Specifically, a component carrier can be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. A component carrier can also be a hybrid board combining different types of component carriers of the aforementioned types.

[0009] In the context of this application, the term "stacked structure" may specifically refer to an arrangement of multiple planar layers installed vertically and horizontally in parallel with each other.

[0010] In the context of this application, the term "layer body" may specifically refer to a flat or planar sheet-like body that may include one or more electrically insulating layers. For example, a layer body may be a laminate, particularly a laminated laminate or a superimposed laminate. Such a laminate can be formed by joining multiple layered structures by applying mechanical pressure and / or heat. In examples, at least a portion of the layer body may include mechanically reinforcing structures, such as glass cloth or glass fiber. These glass structures can form a mesh, and one or more mesh structures can be stacked on top of each other to form a mechanically stable structure.

[0011] In the context of this application, the term "layer structure" may specifically refer to a continuous layer, a graphical layer, or multiple non-continuous islands in a common plane.

[0012] In the context of this application, the term "fiber-free electrical insulating layer structure" may specifically refer to a layer structure made of an electrically insulating material and free of reinforcing fibers such as glass fibers. For example, such a fiber-free electrical insulating layer structure may include a resin (e.g., epoxy resin), optionally include filler particles (e.g., ceramic beads or spheres), and optionally include one or more additives (e.g., adhesion promoters, stabilizers, etc.).

[0013] In the context of this application, the term "resin" may specifically refer to a solid or liquid synthetic or natural organic polymer. An example of resin is epoxy resin. For instance, a resin may be a thermosetting resin.

[0014] In the context of this application, the term "component" can specifically refer to any bulky, rather than layered, block. A component can be an electronic component, such as an active electronic component (e.g., a semiconductor chip or semiconductor package) embedded or to be embedded within a component carrier, or a passive electronic component (e.g., a capacitor or inductor). However, a component can also be a non-electronic component without electronic functionality. For example, a component can be a component with thermal functionality, such as a component with heat removal and / or heat diffusion functions. For example, a component can be a block of metal (e.g., copper) and / or a block of ceramic. Thus, exemplary embodiments can be implemented with one or more electronic components or with any other bulky metal structure (e.g., for heat transfer) or inlay (e.g., an inorganic inlay, such as glass).

[0015] In the context of this application, the term "cavity" may specifically refer to a recess, groove, or hole (particularly a blind hole or through hole) extending through and / or into a stack. Preferably, all sides of the cavity may be defined by the layered structure of the stack.

[0016] In the context of this application, the term "main surface" of a body can specifically refer to one of two opposing largest surfaces of the body. Main surfaces can be connected by circumferential sidewalls. The thickness of a body, such as a stack, can be defined by the distance between the two opposing main surfaces.

[0017] According to an exemplary embodiment, a component carrier (e.g., a printed circuit board) has a (e.g., laminated) stack. A central layer body (e.g., a core) can be sandwiched between a bottom-side fiberless first electrically insulating layer structure and a top-side fiberless second electrically insulating layer structure, the first electrically insulating layer structure having a first resin and the second electrically insulating layer structure having a second resin. At least one component can be embedded in a cavity of the stack. A first portion of the lateral gap between the component and the sidewalls defining the cavity of the stack can be filled with the first resin from the fiberless first electrically insulating layer structure. Furthermore, a second portion of the lateral gap between the component and the sidewalls defining the cavity of the stack can be filled with the second resin from the fiberless second electrically insulating layer structure. Advantageously, this architecture of a component carrier with embedded components allows for reliable and precise component fixation by resin flowing symmetrically upward and downward from two opposite horizontal surfaces into the gap between the component and the stack. With this design, very thin packaged component carriers can be achieved. Utilizing this manufacturing concept, there are no limitations in component miniaturization. Furthermore, very short signal paths can be achieved due to the possible direct component connections. The symmetrical stacked component construction reliably prevents undesirable phenomena such as warping and delamination.

[0018] Advantageously, both the first and second resins can be fiber-free. This results in lower roughness. Consequently, smaller traces can be patterned on the exposed surfaces of the stack. This enables miniaturization with a copper wire space ratio of 1 μm / 1 μm or less. Furthermore, fiber-free resin layers offer improved flatness compared to fiber-containing layers.

[0019] In the following sections, further exemplary embodiments of the component carrier and manufacturing method will be described.

[0020] Advantageously, the component carrier can be formed with an electrically conductive layer directly formed on at least one of the first and second electrically insulating layer structures. Preferably, the electrically conductive layer can be implemented by an additive or semi-additive method. In embodiments, by avoiding the use of copper foil on the first and / or second electrically insulating layer structures, it is unnecessary to structure the copper foil by subtractive methods such as etching—which is not optimal for fine-line structures. However, such fine traces can be achieved with excellent quality by an additive or semi-additive method. Therefore, a preferred embodiment of the invention can use a temporary layer for lamination.

[0021] In embodiments, the layer body is a core, and more particularly, the layer body is a core having a fully cured resin. In the context of this application, the term "core" can specifically refer to a rigid plate structure for a component carrier, comprising a preferably fully cured dielectric body (e.g., a central plate), which may optionally be covered on one or both opposite main surfaces by a corresponding electrically conductive layer structure such as a patterned metal layer. Furthermore or alternatively, the core may comprise a glass and / or ceramic plate structure, and more particularly, at least a portion of the core may comprise a glass and / or ceramic plate structure. For example, the dielectric body may comprise a resin (e.g., epoxy resin) and reinforcing particles (e.g., glass fiber or glass spheres), and the dielectric body may be, for example, FR4. Optionally, the two opposite main surfaces of the core may be electrically coupled to each other by vertical through-connections such as copper-plated laser vias or mechanically drilled and copper-plated vias. More specifically, the core of a component carrier, such as a printed circuit board (PCB), may be a rigid base material, which may optionally be laminated with copper on one or both sides. This core can be used to manufacture single-sided and double-sided boards, but it can also be used to produce multi-layer component carriers (especially PCBs).

[0022] As an alternative, the layer body can be a different layer stack from the core. For example, the layer body can be a layer stack comprising one or more electrically conductive layer structures and / or one or more electrically insulating layer structures.

[0023] In this embodiment, the first electrically insulating layer structure has a roughness Ra in the range of 10 nm to 800 nm on the main surface of the back layer body, and more particularly, the first electrically insulating layer structure has a roughness Ra in the range of 20 nm to 400 nm on the main surface of the back layer body. Due to the fiber-free nature of the first electrically insulating layer, a very smooth surface can be obtained under the first electrically insulating layer. Regarding the first electrically insulating layer structure, the roughness of the main surface of the back layer body of the first electrically insulating layer structure can be lower than the roughness of the other main surface of the facing layer body of the first electrically insulating layer structure. Therefore, the main surface of the back layer body can be a smoother surface, while the other main surface of the facing layer body can be a rougher surface than the main surface of the back layer body. Furthermore, temporary laminated foils (e.g., adhesive tapes) and / or dielectric separation foils can be attached to the first electrically insulating layer structure and can be used to influence the roughness characteristics of the first electrically insulating layer structure.

[0024] In this embodiment, the second electrically insulating layer structure has a roughness Ra in the range of 10 nm to 800 nm on the main surface of the back layer body, and more particularly, the second electrically insulating layer structure has a roughness Ra in the range of 20 nm to 400 nm on the main surface of the back layer body. Due to the fiber-free nature of the second electrically insulating layer, a very smooth surface can be obtained on the top of the second electrically insulating layer. Regarding the second electrically insulating layer structure, the roughness of the main surface of the back layer body of the second electrically insulating layer structure can be lower than the roughness of the other main surface of the facing layer body of the second electrically insulating layer structure. The main surface of the back layer body can be a smoother surface, while the other main surface of the facing layer body can be a rougher surface than the main surface of the back layer body.

[0025] Referring to the above embodiments, very smooth exposed surfaces can be obtained at the fiberless first electrical insulating layer structure and / or the fiberless second electrical insulating layer structure. This allows for the formation of electrically conductive traces with very high integration density, very thin and narrow dimensions, and precise definition on the smooth outer surface of the respective fiberless electrical insulating layer structure. Furthermore, such electrically conductive traces formed (particularly directly) on the very smooth surface of the respective fiberless first electrical insulating layer structure and / or the fiberless second electrical insulating layer structure can achieve significantly improved high-frequency (RF) and / or high-speed behavior. In short, the skin effect allows current to flow only within the thin surface skin of the electrically conductive trace at high signal frequencies. Therefore, given the skin effect, a smoother surface can lead to lower losses.

[0026] In one embodiment, the component carrier includes a first electrically conductive fine line pattern located on the main surface of the opposing layer body of the first electrically insulating layer structure. This fine line pattern may include electrically conductive traces and / or electrically conductive pads located on the smoother main surface of the two opposite main surfaces of the first electrically insulating layer structure. Preferably, these electrically conductive traces and / or electrically conductive pads are located directly on the smoother main surface of the two opposite main surfaces of the first electrically insulating layer structure. Due to the significant smoothness of the surface caused by the absence of fibers, thin and minute fine line structures can be formed on the surface, for example, by sputtering or plating followed by patterning.

[0027] In one embodiment, the component carrier includes a second electrically conductive fine line pattern located on the main surface of the opposing layer body of the second electrically insulating layer structure. This fine line pattern may also include electrically conductive traces and / or electrically conductive pads located on the smoother main surface of the two opposite main surfaces of the second electrically insulating layer structure; preferably, these electrically conductive traces and / or electrically conductive pads are located directly on the smoother main surface of the two opposite main surfaces of the second electrically insulating layer structure. Due to the significant smoothness of the surface caused by the absence of fibers, thin and minute fine line structures can be formed on the surface, for example, by sputtering or plating followed by patterning.

[0028] In an embodiment, the first fine-line pattern portion and / or the second fine-line pattern portion includes electrically conductive traces having a width in the range of 1 μm to 15 μm, for example, the electrically conductive traces having a width in the range of 1.5 μm to 8 μm. Furthermore or alternatively, the distance between adjacent traces can be in the range of 1 μm to 15 μm, for example, the distance between adjacent traces can be in the range of 1.5 μm to 8 μm. This extremely small structure enables low loss of electrical signals propagating thereon and allows for excellent trace density, i.e., the number of traces per unit area or unit volume of the component carrier.

[0029] In an embodiment, the first electrical insulating layer structure includes first filler particles. Additionally or alternatively, the second electrical insulating layer structure includes second filler particles. Therefore, the first resin and / or the second resin can be mixed with the filler particles. The filler particles of the first resin and the filler particles of the second resin can be the same, or the filler particles of the first resin and the filler particles of the second resin can differ in at least one property; for example, the filler particles of the first resin and the filler particles of the second resin can differ in terms of material and / or material distribution, size and / or size distribution, shape, hollow, solid, or porous characteristics, and / or amount. For example, the filler particles can be added to the corresponding resin to provide at least one additional function, such as enhanced thermal conductivity, electrical shielding, enhanced electrical insulation, etc. When the corresponding resin is mixed with the filler particles, the corresponding portion of the gap between the component and the cavity sidewall can include a mixture of the corresponding resin and the dispensed filler particles.

[0030] In an embodiment, the component carrier includes an electrically conductive layer (e.g., a sputtered layer or a plating layer) formed directly on at least one electrically conductive pad of the component and / or directly on at least one of a first electrically insulating layer structure and a second electrically insulating layer structure. Accordingly, the method may include sputtering the electrically conductive sputtered layer directly onto at least one pad of the component and / or directly onto at least one of a first electrically insulating layer structure and a second electrically insulating layer structure. Thus, the electrically conductive sputtered layer can be formed by a sputtering process. Sputtering can refer to a process in which microscopic particles of a solid material are ejected from its surface after the solid material itself has been bombarded by high-energy particles of plasma or gas. Through this sputtering process, metal can be directly deposited onto the corresponding electrically insulating layer structure and / or directly deposited onto the electrically conductive pad of the component. Furthermore and / or alternatively, other additive methods, such as chemical vapor deposition or other types of physical vapor deposition, can be used. Given the very smooth exposed surfaces of the corresponding electrically insulating layer structures, fine line patterning based on this sputtered layer is possible on two opposite main surfaces of the component carrier. This allows electrical contacts to be located on pads on one or both opposite main surfaces of the component. Alternatively, the method may include: directly plating (e.g., non-electroplated and then electroplated) an electrically conductive plating layer on at least one pad of the component and / or directly plating it on at least one of a first electrical insulation layer structure and a second electrical insulation layer structure.

[0031] In one embodiment, the component includes one or more pads located on the bottom main surface of the component. Such a component may be referred to as a downward-facing component. In another embodiment, the component includes one or more pads located on the top main surface of the component. Such a component may be referred to as an upward-facing component. In yet another embodiment, the component includes one or more pads located on the bottom main surface of the component and includes one or more pads located on the top main surface of the component. Such a component may be referred to as a component with dual-sided electrical connections. Advantageously, the manufacturing process according to an exemplary embodiment of the invention allows for precise electrical contact of components of any of these three alternative solutions. In particular, after the first resin of the first electrical insulating layer structure and the second resin of the second electrical insulating layer structure are cured, at least a portion of the pad may remain exposed. Other portions of the pad may be connected via vias such as laser vias. This can facilitate the establishment of electrical coupling between the pad and the metal layer structure formed on the pad.

[0032] In one embodiment, the electrically conductive layer (e.g., a sputtered layer or a plating layer) comprises an adhesion-promoting sublayer and a metal layer situated on the adhesion-promoting sublayer. Preferably, this adhesion-promoting sublayer is electrically conductive; however, in other embodiments, it may be electrically insulating. Advantageously, the adhesion-promoting sublayer can promote adhesion between one or more pads of a corresponding electrically insulating layer structure and / or component on one side and a wiring structure including electrically conductive traces situated on the adhesion-promoting sublayer on the other side. This adhesion-promoting sublayer can enhance the integrity of the entire component carrier and can suppress undesirable effects such as delamination. This adhesion-promoting sublayer can aid in the adhesion of the applied metal material during and after sputtering or plating.

[0033] In one embodiment, the component has at least one electrically conductive pad made of a material different from copper. Since direct electrical contact with one or more exposed component carrier pads can be accomplished by sputtering or plating, there is freedom of choice regarding the material of the one or more component pads, and the material of the one or more component pads is not limited to copper. However, copper pads can also be used to connect the components according to exemplary embodiments.

[0034] In this embodiment, the thickness of at least one of the first and second electrical insulating layer structures is in the range of 5 μm to 100 μm, for example, the thickness of at least one of the first and second electrical insulating layer structures is in the range of 10 μm to 50 μm. Therefore, an ultra-thin electrical insulating layer structure can be provided as a resin reservoir. Simultaneously, this thin electrical insulating layer structure can promote the overall vertical compactness of the component carrier. More generally, the thickness of at least one of the first and second electrical insulating layer structures can be up to 250 μm. In short, the larger the volume to be filled, the greater the thickness of the corresponding insulating layer structure.

[0035] In embodiments, the thickness of the layer body ranges from 15 μm to 500 μm, and more particularly, from 20 μm to 100 μm. Therefore, the layer body—preferably implemented as a core—can also have a small thickness, which can result in a compact component carrier with embedded components such as semiconductors. More generally, the thickness of the layer body can be up to 800 μm.

[0036] In this embodiment, the first and second electrical insulating layer structures are made of the same material. In one example, the resin material of the first and second electrical insulating layers can be the same. In another example, the filler particles of the first and second electrical insulating materials can have the same filler material and / or size and / or shape. However, an interface can exist between the first and second resins, and this interface can be visible, for example, in a cross-sectional view. Using the same resin for both the first and second electrical insulating layer structures can achieve homogeneous properties within the component carrier and thus suppress undesirable phenomena such as warping, delamination, and CTE (coefficient of thermal expansion) mismatch.

[0037] In a preferred embodiment, the resins of the first electrically insulating layer structure, the second electrically insulating layer structure, and the layer body can be the same. Advantageously, this allows for a very homogeneous stacked structure, resulting in low warpage and low risk of delamination.

[0038] In another embodiment, the first and second electrical insulating layer structures are made of different materials. In one example, the resin materials or resin material compositions of the first and second electrical insulating layers may differ. In another example, the filler material and / or size and / or shape of the first electrical insulating material may differ from the filler material and / or size and / or shape of the filler particles of the second electrical insulating material. This individual selection of different materials allows for fine-tuning of the properties of the component carrier and its individual components, even allowing for spatially resolved fine-tuning of the properties of the component carrier and its individual components.

[0039] In this embodiment, the material composition of the first electrically insulating layer structure on the layer body and on the component is the same as the material composition in the connecting portion of the gap. This may be a trace of the fact that the first electrically insulating layer structure can be a resin source for filling the corresponding portion of the gap. For example, the first electrically insulating layer structure may include a filler. For example, the filler may also be disposed in the gap.

[0040] In this embodiment, the material composition of the second electrical insulating layer structure on the layer body and on the component is the same as the material composition in the connecting portion of the gap. This may be a trace of the fact that the second electrical insulating layer structure can be a resin source for filling the corresponding other portion of the gap. For example, the second electrical insulating layer structure may include a filler. For example, the filler may also be disposed in the gap.

[0041] In one embodiment, the method includes filling at least a portion of the gap by curing a first resin and a second resin. Curing may be triggered, in particular, by applying pressure and / or heat and / or UV (ultraviolet) light. Therefore, the first and second resins may be at least partially uncured before the gap between the component and the cavity sidewall is filled. After the gap between the component and the cavity sidewall is filled, the first and second resins may be cured.

[0042] In the context of this application, the term "uncured resin" may specifically refer to a resin material that is at least partially uncured, particularly a crosslinkable material (e.g., a resin that can undergo crosslinking under elevated temperature and / or pressure) and / or a polymerizable resin material. Uncured resin specifically refers to a material that at least partially melts or becomes flowable upon application of elevated pressure and / or elevated temperature, and becomes fully hardened or cured (and thus becomes a permanent solid) after a certain period of time under elevated pressure and / or temperature and / or UV light. Therefore, applying elevated pressure and / or elevated temperature can cause a curable or at least partially uncured resin to transform into a flowable material, for example, by melting above the glass transition temperature and then irreversibly hardening upon release of the applied high pressure and / or high temperature. In particular, at least partially uncured resin may comprise stage B materials and / or stage A materials, or at least partially uncured resin may be composed of stage B materials and / or stage A materials. By providing the corresponding resin for the stage B material, the corresponding resin for the stage B material can be remelted during lamination and / or the material can undergo a phase or state transition, allowing the resin to flow to interconnect various elements and close gaps or voids, and thus aiding in the stable internal interconnection of components to be embedded within a component carrier during manufacturing. For example, a curing agent can be added to a liquid (e.g., epoxy) resin in stage A and cured until stage B conditions are reached. Stage B can be a solid thermoplastic stage. When additional heat and / or pressure is applied, the stage B (e.g., epoxy) resin can flow and continue curing to crosslinking conditions or stage C. In stage C, the resin can be fully cured and can remain permanently in a solid phase. For example, the degree of polymerization of the uncured resin can be between 0.1% and 85%, and in particular, the degree of polymerization of the uncured resin can be between 25% and 70%.

[0043] In the context of this application, the term "cured resin" may specifically refer to a resin that has undergone or fully undergone a curing process and is therefore no longer flowable, no longer polymerizable, and / or no longer crosslinkable. The cured resin may be in a cured, irreversibly hardened state. For example, the cured resin may be in stage C. For example, the degree of polymerization of the cured resin may be at least 90%, and more specifically, the degree of polymerization of the cured resin may be at least 95%.

[0044] In one embodiment, a first dielectric separation foil is disposed on the main surface of the back layer body of the first electrical insulating layer structure, and / or a second dielectric separation foil is disposed on the main surface of the back layer body of the second electrical insulating layer structure. The first dielectric separation foil can serve as a barrier to the first resin to facilitate oriented flow of the first resin into the gap, but without exceeding the boundary defined by the first dielectric separation foil in the vertical direction. Correspondingly, the second dielectric separation foil can serve as a barrier to the second resin to facilitate oriented flow of the second resin into the gap, but without exceeding the boundary defined by the second dielectric separation foil in the vertical direction.

[0045] In one embodiment, the method includes removing a first dielectric separation foil from the main surface of a first electrically insulating layer structure and / or removing a second dielectric separation foil from the main surface of a second electrically insulating layer structure before completing the fabrication of the component carrier. Therefore, the dielectric separation foil can be a temporary foil and thus does not contribute to the thickness of the fabricated component carrier. For example, the method includes completely removing the first and second dielectric separation foils after curing a first and a second resin. After heating and / or pressurizing the first and second electrically insulating layer structures to cure and trigger resin flow into the gap between the component and the cavity sidewall, the dielectric separation foil is no longer needed and can be removed to reduce the size of the fabricated component carrier.

[0046] Specifically, the following approach is possible: the method includes filling at least a portion of the gap by curing a first resin and a second resin, and then removing a first dielectric separation foil from the main surface of the first electrical insulating layer structure and / or removing a second dielectric separation foil from the main surface of the second electrical insulating layer structure before completing the manufacture of the component carrier, specifically by curing the first resin and the second resin by applying pressure and / or heat.

[0047] In one embodiment, the bottom side of the first electrical insulating layer structure has a stepped portion at a position corresponding to the sidewall of the stacked member. Figure 9 The stepped portion shown can be a trace of temporary dielectric separation foil, which can be removed before the component carrier is manufactured.

[0048] In this embodiment, the (fiber-free) first electrical insulation layer structure and / or the (fiber-free) second electrical insulation layer structure can have a thermal conductivity greater than 0.1 W / mK. This can provide the following advantages: for example, at least a portion of the heat generated by the electronic components can be transferred to the heat sink and / or exposed surfaces via the fiber-free first electrical insulation layer structure and / or the fiber-free second electrical insulation layer structure, thereby achieving good and reliable thermal management of the component carrier.

[0049] In one embodiment, the method includes removing a portion of the layer body, a portion of the first electrically insulating layer structure, a portion of the second electrically insulating layer structure, a portion of the first dielectric separation foil, and a portion of the second dielectric separation foil to form the cavity. For example, the cavity can be formed by laser cutting, mechanical cutting, milling, or etching. For example, removing the portion can create a through-hole type cavity.

[0050] In one embodiment, the method includes forming a reference mark in and / or on the layer body before arranging the first and second electrically insulating layer structures on the layer body. Such a reference mark may be, for example, a through-hole extending through the stack, or, for instance, a through-hole surrounded by an annular metal (e.g., copper) structure at one or both opposite ends of the stack. Advantageously, one or more such reference marks can be used for alignment purposes, which can improve the accuracy of the manufacturing process. At least one reference mark can be removed before the manufacturing of the component carrier is completed.

[0051] In one embodiment, the method includes attaching a temporary carrier to the stack to close the cavity before inserting the component into the cavity and placing it on the temporary carrier. For example, such a temporary carrier may be adhesive for temporarily adhering one or more components to be placed in the cavity for subsequent embedding. For example, the temporary carrier may be adhesive tape.

[0052] In one implementation, the method includes removing the temporary carrier after the curing process. Therefore, the temporary carrier can be removed from the component carrier after the manufacturing process of the component carrier is completed. This allows for a highly compact component carrier. Alternatively, the temporary carrier can be formed as part of the already manufactured component carrier.

[0053] In one embodiment, the method includes: disposing a first electrically insulating layer structure in a at least partially uncured state on a bottom main surface of a layer body, and disposing a second electrically insulating layer structure in a at least partially uncured state on a top main surface of the layer body, and subsequently filling at least a portion of the gap by simultaneously curing the first and second electrically insulating layer structures. Specifically, the curing process can be triggered by applying heat and / or mechanical pressure and / or UV light. By initiating curing, the first and / or second resins can simultaneously (or with a small time offset) become flowable, such that the first and / or second resins can also flow into the gap between the component and the cavity sidewall and can bond to each other. During curing, the respective resins can polymerize and / or crosslink to become fully cured. The fully cured respective resins then harden to permanently retain the embedded component in the cavity.

[0054] The component can be embedded in a core-shaped layer body. In an alternative embodiment, the component can be embedded in a coreless component carrier.

[0055] In an embodiment, at least a portion of the component is directly surrounded by at least one of a first resin, a second resin, and optionally a first electrical insulating layer structure and / or a second electrical insulating layer structure. Any of the aforementioned dielectric components can be functionalized as a buffer structure for buffering stress. Preferably, the buffer structure comprises a material with a Young's modulus value less than 25 GPa, particularly less than 10 GPa, and more particularly less than 5 GPa, or the buffer structure is composed of a material with a Young's modulus value less than 25 GPa, particularly less than 10 GPa, and more particularly less than 5 GPa. Such a material can be used as a mechanical buffer structure, i.e., as a mechanically relatively flexible or elastic electrical insulating structure. This makes the material very suitable (particularly directly) for embedded components surrounding a component carrier. Such a mechanical buffer structure can have a locally reduced Young's modulus value and can therefore be used, for example, as a mechanical damping or force balancing structure under thermal stress. Therefore, excellent results can be achieved when the component is embedded in a low Young's modulus dielectric. The dielectric buffer structure can have a lower Young's modulus value than any other dielectric material of the component carrier.

[0056] In the following sections, different embedding techniques that can be used to embed components in a layer body according to exemplary embodiments will be described: In one embodiment, a method of manufacturing a component carrier includes embedding a component into a cavity of a layer body (particularly a laminate), wherein, during embedding, the cavity is at least temporarily closed at its bottom side by an adhesive layer. In the context of this application, the term "adhesive layer" may specifically refer to a tape, film, foil, sheet, or plate having an adhesive surface. In use, the adhesive layer may be used to adhere to the main surface of the layer body to close an opening extending through the layer body. The component to be embedded may be adhered to the adhesive layer to define the position of the component in the opening and thus define the position of the component relative to the layer body in the opening, wherein two electrically insulating layer structures are attached to opposite main surfaces of the component. When the adhesive layer is removed from the layer body having the two attached electrically insulating layer structures before the manufacturing of the component carrier is completed, the adhesive layer may be referred to as a temporary carrier. However, in other embodiments, the adhesive layer may form part of a manufactured component carrier. By adhering the component to the adhesive tape during the embedding process, the spatial accuracy of the component embedding can be significantly improved.

[0057] In another embodiment, the method includes mounting a component onto at least one layer structure or onto a temporary support, and then covering the component with a layer body or another layer structure, wherein the layer body has openings for receiving the component. For example, the openings in the layer body may be cut into the layer body as through holes. Further alternatively, the component attached to the temporary support or to one or more layer structures may be covered with a flowable medium, such as resin, which may form the layer body.

[0058] In another embodiment, the method includes: embedding a release layer in a stack, then forming an opening (e.g., a blind hole) in the stack by removing a segment of the stack defined by the release layer at its bottom side, and then receiving a component in the opening, i.e., receiving it in the remaining portion of the stack forming the layer body. For example, this release layer can be made of a material that exhibits poor adhesion properties relative to the surrounding layer body material. Suitable materials for the release layer, for example, are polytetrafluoroethylene (PTFE, Teflon) or waxy compounds. The method may include: forming a circumferentially cut groove extending into the release layer in the layer body segment of the stack, thereby separating the segment from the rest of the stack and its layer body portion. Cutting the groove can be done, for example, by laser drilling or mechanical drilling.

[0059] In another embodiment, the method includes forming an opening (e.g., a blind hole) in the stack by milling (preferably depth milling), and then receiving a component in the opening and on the bottom surface of the milled stack. Milling is a suitable and simple mechanism for precisely defining a blind hole-type opening for subsequent receiving of a component. The milled portion of the stack can form a layer body.

[0060] In an embodiment, the component carrier comprises a stack of at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a laminate of one or more electrically insulating layer structures and one or more electrically conductive layer structures, formed specifically by applying mechanical pressure and / or heat. The aforementioned stack can provide a plate-like component carrier that provides a large mounting surface for other components while remaining extremely thin and compact.

[0061] In this implementation, the component carrier is shaped as a plate. This contributes to a compact design, where the component carrier still provides a large base for mounting components. Furthermore, bare wafers, particularly examples of embedded electronic components, can be conveniently embedded in thin plates such as printed circuit boards due to their small thickness.

[0062] In one embodiment, the component carrier is configured as one of a printed circuit board, a substrate (particularly an IC substrate), and an interposer.

[0063] In the context of this application, the term "printed circuit board" (PCB) can specifically refer to a plate-shaped component carrier formed by laminating multiple electrically conductive layer structures with multiple electrically insulating layer structures, for example, by applying pressure and / or by supplying heat. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may include resin and / or glass fiber, i.e., so-called prepreg or FR4 material. The individual electrically conductive layer structures can be connected to each other in a desired manner by forming holes through the laminate, for example, by laser drilling or mechanical drilling, and by partially or completely filling these holes with an electrically conductive material (particularly copper), thereby forming vias or any other through-hole connections. A filled hole connects the entire stack (a through-hole connection extending through multiple layers or the entire stack), or a filled hole connects at least two electrically conductive layers, referred to as a via. Similarly, optical interconnects can be formed through the individual layers of the stack to receive an electro-optical circuit board (EOCB). In addition to one or more components that can be embedded in a printed circuit board, a printed circuit board is typically configured to house one or more components on one or two opposite surfaces of the board-shaped printed circuit board. The one or more components can be soldered to the respective main surfaces. The dielectric portions of the PCB may be made of resin with reinforcing fibers (e.g., glass fiber).

[0064] In the context of this application, the term "substrate" can specifically refer to a small component carrier. A substrate can be a relatively small component carrier relative to a PCB, on which one or more components can be mounted, and which can serve as a connection medium between one or more chips and another PCB. For example, a substrate can have approximately the same size as the components (particularly electronic components) to be mounted thereon (e.g., in the case of chip-scale packages (CSPs)). More specifically, a substrate can be understood as a carrier for electrical connections or electrical networks and a component carrier equivalent to a printed circuit board (PCB), but with a considerably high density of lateral and / or vertically arranged connections. Lateral connections are, for example, conductive paths, while vertical connections can be, for example, drilled holes. These lateral and / or vertical connections are arranged within the substrate and can be used to provide electrical, thermal, and / or mechanical connections between mounted or unmounted components (e.g., bare wafers), particularly IC chips, and printed circuit boards or intermediate printed circuit boards. Therefore, the term "substrate" also includes "IC substrate." The dielectric portion of the substrate can be composed of resin with reinforcing particles (e.g., reinforcing spheres, particularly glass spheres).

[0065] The substrate or interlayer may include or be composed of at least one of the following: glass, silicon (Si) and / or photosensitive or dry-etchable organic materials (e.g., epoxy stacked materials, such as epoxy stacked films) or polymer compounds (which may or may not include photosensitive and / or thermosensitive molecules), such as polyimide or polybenzoxazole.

[0066] In embodiments, the at least one electrically insulating layer structure comprises at least one of the following: resins or polymers, such as epoxy resins, cyanate ester resins, benzocyclobutene resins, bismaleimide-triazine resins, polyphenylene derivatives (e.g., based on polyphenylene ether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymers (LCP), polytetrafluoroethylene (PTFE), and / or combinations thereof. Reinforcing structures, such as meshes, fibers, spheres, or other types of filler particles made of, for example, glass (multilayer glass), may also be used to form the composite. The semi-cured resin combined with the reinforcing agent, such as fibers impregnated with the aforementioned resins, is referred to as a prepreg. These prepregs are typically named for their properties, such as FR4 or FR5, which describe their flame-retardant properties. While prepregs (especially FR4) are generally preferred for rigid PCBs, other materials may also be used, particularly epoxy-based stacking materials (e.g., stacked films) or photosensitive dielectric materials. For high-frequency applications, high-frequency materials, such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate ester resins, may be preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low, very low or ultra-low DK materials can be used as electrical insulation structures in component carriers.

[0067] In an embodiment, the at least one electrically conductive layer structure comprises at least one of the following: copper, aluminum, nickel, silver, gold, palladium, tungsten, titanium, and magnesium. Although copper is generally preferred, other materials or coated versions thereof are also possible, particularly those coated with superconducting materials or conductive polymers, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT).

[0068] The at least one component may be selected from at least one of the following: non-electrically conductive inlays, electrically conductive inlays (e.g., metallic inlays, preferably including copper or aluminum), heat transfer units (e.g., heat pipes), optical guiding elements (e.g., optical waveguides or optical conductor connectors), electronic components, or combinations thereof. The inlay may be, for example, a metal block (IMS-inlay) with or without an insulating material coating, which may be embedded or surface-mounted to facilitate heat dissipation. Suitable materials are defined by their thermal conductivity, which should be at least 2 W / mK. Such materials are typically based on, but not limited to, metals, metal oxides, and / or ceramics, such as copper, alumina (Al₂O₃), or aluminum nitride (AlN). Other geometries with increased surface area are also frequently used to improve heat exchange capacity. In addition, components can be active electronic components (implemented with at least one pn junction), passive electronic components (e.g., resistors, inductors, or capacitors), electronic chips, storage devices (e.g., DRAM or other data memories), filters, integrated circuits (e.g., field-programmable gate arrays (FPGAs), programmable array logic (PALs), general-purpose array logic (GALs), and complex programmable logic devices (CPLDs)), signal processing components, power management components (e.g., field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, junction field-effect transistors (JFETs), or... Insulated-gate field-effect transistors (IGFETs), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), and / or any other suitable inorganic compound, optoelectronic interface elements, light-emitting diodes, optocouplers, voltage converters (e.g., DC / DC converters or AC / DC converters), cryptographic components, transmitters and / or receivers, electromechanical transducers, sensors, actuators, microelectromechanical systems (MEMS), microprocessors, capacitors, resistors, inductors, batteries, switches, cameras, antennas, logic chips, and energy harvesting units. However, other components can be embedded within component carriers. For example, magnetic elements can be used as components. Such magnetic elements can be permanent magnetic elements (e.g., ferromagnetic, antiferromagnetic, multiferroic, or ferrimagnetic elements, such as ferrite cores) or paramagnetic elements. However, components can also be IC substrates, interposers, or other component carriers, such as board-in-board configurations. Components may be surface-mounted on a component carrier and / or embedded within the component carrier. Furthermore, other components, particularly those that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment, may also be used as components.

[0069] In one embodiment, the component carrier is a laminated component carrier. In this embodiment, the component carrier is a multilayer composite structure that is stacked and connected together by applying pressure and / or heat.

[0070] After the internal layer structure of the component carrier has been treated, one or two opposite main surfaces of the treated layer structure can be symmetrically or asymmetrically covered with one or more additional electrically insulating and / or electrically conductive layer structures (particularly by lamination). In other words, stacking can continue until the desired number of layers is obtained.

[0071] After the stacked components of the electrical insulation layer structure and the electrical conductivity layer structure are formed, the obtained layer structure or component carrier can be surface treated.

[0072] In particular, regarding surface treatment, an electrically insulating solder resist layer can be applied to one or two opposite main surfaces of the laminate or component carrier. For example, such a solder resist layer can be formed over the entire main surface and subsequently patterned to expose one or more electrically conductive surface portions that will be used to electrically couple the component carrier to electronic peripherals. The surface portions of the component carrier that remain covered by the solder resist layer, especially those containing copper, can be effectively protected against oxidation or corrosion.

[0073] In terms of surface treatment, a surface treatment portion can also be selectively applied to the exposed electrically conductive surface portion of the component carrier. This surface treatment portion can be an electrically conductive covering material on the exposed electrically conductive layer structure (e.g., pads, conductive paths, etc., particularly including or composed of copper) on the surface of the component carrier. If this exposed electrically conductive layer structure is not protected, the exposed electrically conductive component carrier material (particularly copper) may oxidize, reducing the reliability of the component carrier. The surface treatment portion can then be formed, for example, as an interface between the surface mount component and the component carrier. The surface treatment portion protects the exposed electrically conductive layer structure (particularly copper circuitry) and enables bonding processes (e.g., by soldering) with one or more components. Examples of suitable materials for the surface treatment portion are organic solderable corrosion inhibitors (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), gold (particularly hard gold), electroless tin, nickel-gold, nickel-palladium, etc.

[0074] The aspects defined above and other aspects of the invention will be apparent from examples of embodiments described below, and will be explained with reference to these examples of embodiments. Attached Figure Description

[0075] Figure 1 A cross-sectional view of a component carrier according to an exemplary embodiment of the present invention is shown.

[0076] Figures 2 to 13 It shows the process of manufacturing. Figure 1 The cross-sectional view of the structure obtained during the method of the component carrier according to an exemplary embodiment of the present invention is shown.

[0077] Figure 14 and Figure 15 A cross-sectional view of a structure obtained during the execution of a method for manufacturing a component carrier according to another exemplary embodiment of the present invention is shown.

[0078] Figure 16 A cross-sectional view of a structure obtained during the execution of a method for manufacturing a component carrier according to yet another exemplary embodiment of the present invention is shown.

[0079] Figure 17 A cross-sectional view of a structure obtained during the execution of a method for manufacturing a component carrier according to yet another exemplary embodiment of the present invention is shown.

[0080] The illustrations in the accompanying drawings are schematic. In different drawings, similar or identical elements are provided with the same reference numerals. Detailed Implementation

[0081] Before describing the exemplary embodiments in more detail with reference to the accompanying drawings, some basic considerations on which the exemplary embodiments of the present invention are based will be summarized.

[0082] According to an exemplary embodiment of the present invention, a component carrier (e.g., a PCB or IC substrate) based on a laminate is provided, which can be formed by lamination. The laminate may include a layer body (e.g., a core) in the middle of the laminate. Optionally, at least a portion of the layer body may include a glass and / or ceramic plate structure; particularly, at least a portion of the core may include a glass and / or ceramic plate structure. The core may be disposed above a fiberless first electrically insulating layer structure located on the bottom side and below a fiberless second electrically insulating layer structure located on the top side. The first electrically insulating layer structure may have a first resin but no fibers, and the second electrically insulating layer structure may have a second resin (which may be made of the same material as the first resin or a different material) but no fibers. Optionally, even if the material of the first resin of the fiberless first electrically insulating layer structure is the same as the material of the second resin of the fiberless second electrically insulating layer structure, the fiberless first electrically insulating layer structure may differ from the fiberless second electrically insulating layer structure in the material and / or size and / or shape and / or amount of the filler material and / or filler particles. One or more electronic components may be encapsulated within one or more recesses of the stack. The at least one recess or cavity includes two opposing sidewalls. A first portion (particularly the bottom portion) of the lateral gap between the electronic component and the cavity sidewall is filled with a first resin from a fiberless first electrical insulating layer structure, while a second portion (particularly the top portion) of the lateral gap is filled with a second resin from a fiberless second electrical insulating layer structure. This allows for reliable positioning of the electronic component within the cavity, where symmetrical resin flow from two vertically opposite sides into the gap is possible, enabling a very thin and compact component carrier. Furthermore, this compactness, combined with the possibility of direct electrical connection to embedded electronic components, allows for short signal paths, resulting in low loss and high signal integrity. In addition, the symmetrical stack design suppresses warping.

[0083] More specifically, exemplary embodiments of the invention can provide an embedding technique also applicable to dual-sided component connections. Advantageously, component fixation can be achieved by simultaneously flowing resin in a horizontal flow direction at the bottom and top sides of the component, wherein the resin flow is then guided into the gap between the component and the stack. When implementing the manufacturing architecture of the exemplary embodiments of the invention, very thin packages can be achieved. Descriptively, the thickness of the packaged component carrier can be approximately the thickness of the embedded electronic component plus the thickness of the fiberless resin layer. In another example, the thickness of the packaged component carrier in the stack thickness direction can be greater than the thickness of the embedded electronic component plus the thickness of the fiberless resin layer, because an electrically conductive layer structure and / or an electrically insulating layer structure are also included. Advantageously, there are virtually no limitations in terms of component metallization. Furthermore, very short signal paths can be achieved due to the possibility of direct component connections. For example, electrically conductive materials (such as copper) can be directly deposited (e.g., sputtered) onto exposed component pads, thereby achieving the aforementioned short signal paths. Advantageously, warping problems do not occur due to the symmetrical stack. Furthermore, the workload of manufacturing the component carrier according to an exemplary embodiment of the present invention can be reasonably low.

[0084] According to an exemplary embodiment of the invention, a manufacturing architecture with a process flow is provided that allows for direct fan-out packaging on both sides. Advantageously, this allows for proper securing of embedded components via horizontal resin flow from both the top and bottom sides. For example, the components can be embedded using semi-cured Ajinomoto stacked film® (ABF) material. Since ABF is available in various thicknesses, very thin packages can be produced. Registration design rules can also be met. Depending on the height difference of the available liner foil, a small gap close to the filling cavity can be obtained on the back side.

[0085] Figure 1 A cross-sectional view of a component carrier 100 according to an exemplary embodiment of the present invention is shown. In the illustrated embodiment, the component carrier 100 is implemented as a printed circuit board (PCB). However, the component carrier 100 may also be an integrated circuit (IC) substrate, etc.

[0086] according to Figure 1 The component carrier 100 can be configured as a generally plate-shaped printed circuit board (PCB). Therefore, Figure 1The component carrier 100 shown can be highly compact in the vertical direction. More specifically, the component carrier 100 may include a stack 102 comprising one or more electrically conductive layer structures 150 and / or one or more electrically insulating layer structures 152. The electrically conductive layer structure 150 may include horizontal wiring structures (e.g., having traces and pads) and vertical through-connections, such as copper-filled vias or copper-filled through-holes, which may be formed by mechanical drilling or laser drilling and plating. A portion of the electrically insulating layer structure 152, particularly the central layer body 104 of the electrically insulating layer structure 152, may include a corresponding resin (e.g., a corresponding epoxy resin), which preferably includes reinforcing fibers (e.g., glass fibers) located within the resin. For example, the central layer body 104 may be made of FR4. In another example, at least a portion of the layer body may include a glass and / or ceramic plate structure, particularly at least a portion of the core may include a glass and / or ceramic plate structure. Other electrical insulation layer structures 152, particularly the first electrical insulation layer structure 106 and the second electrical insulation layer structure 110, may be fiber-free and may include, for example, resins 108, 112 and optionally filler particles 128, 130.

[0087] In the illustrated embodiment, the stack 102 includes: a layer body 104 made of fully cured FR4 material; and a vertical through-connection 178 made of copper and optionally other metals such as palladium and extending vertically through the layer body 104. The layer body 104 may be a core having a fully cured resin.

[0088] Furthermore, the component carrier 100 includes an electronic component 114 (or any other component, such as a non-electronic component, like a copper or ceramic block), which is at least partially embedded in the stack 102, preferably, the electronic component 114 is fully embedded in the stack 102. For example, the component 114 may be an active electronic component, such as a semiconductor chip (e.g., a silicon chip). For example, the electronic component 114 may be configured for power applications and / or high-frequency applications. In the illustrated embodiment, the electronic component 114 has three metal pads 132 on its lower main surface and one metal pad 132 on its upper main surface.

[0089] More specifically, the illustrated component carrier 100 includes a stack 102 having: a central layer body 104, a fiberless first electrical insulating layer structure 106 comprising a first resin 108 on the bottom main surface of the layer body 104, and a fiberless second electrical insulating layer structure 110 comprising a second resin 112 on the top main surface of the layer body 104. An electronic component 114 is inserted into and embedded in the cavity of the stack 102 (see [link to documentation]). Figure 6 In the accompanying reference numeral 116, as shown, the gap between the sidewall 154 defining the cavity 116 of the electronic component 114 and the stack 102 (see Figure 116). Figure 8 A portion of the gap 118 (reference numeral 118) is partially filled with the first resin 108 and partially with the second resin 112. More specifically, the bottom portion of the gap 118 may be filled with the first resin 108, while the top portion of the gap 118 may be filled with the second resin 112. Optionally, the bottom portion of the gap 118 may be filled with the second resin 112, and / or the top portion of the gap 118 may be filled with the first resin 108. A discontinuous interface may be formed between the first resin 108 and the second resin 112, or a mixed region comprising a resin mixture of the first resin 108 and the second resin 112 may be formed between a region of pure first resin 108 and a region of pure second resin 112. This can be adjusted by the selection of resin materials and processing conditions during the manufacture of the component carrier 100.

[0090] like Figure 1 As shown in details 160 and 162, each of the first resin 108 and the second resin 112 may include corresponding filler particles 128 and 130, which may be different or the same. Additional functionalities, such as enhanced thermal conductivity, electromagnetic shielding, preferred flow behavior, etc., can be added to the respective resin 108 or 112 through the filler particles 128 and 130. To facilitate a symmetrical stack, the first electrical insulating layer structure 106 and the second electrical insulating layer structure 110 may be made of the same material; that is, the first electrical insulating layer structure 106 and the second electrical insulating layer structure 110 may include the same resin material for the resins 108 and 112 and the same filler material for the filler particles 128 and 130. This can suppress artifacts such as warping and delamination on the component carrier 100. Alternatively, different resin materials and / or different filler particle materials may be used for the electrical insulating layer structures 106 and 110, which allows for spatially dependent adjustment of the properties of the dielectric surrounding the electronic component 114.

[0091] For example, the main portion of the electronic component 114 can be directly surrounded by a first resin 108 and a second resin 112, which can be implemented as a dielectric buffer structure for stress buffering. Preferably, the buffer structure is composed of resin materials of resins 108 and 112, both of which can have a Young's modulus value of less than 8 GPa, particularly less than 3 GPa, and more particularly less than 1 GPa. This dielectric resin material can be used as a flexible or elastic electrical insulation surrounding the embedded electronic component 114 and can reliably protect the electronic component 114 from stress during operation of the component carrier 100. In another example, the fiberless first electrical insulation layer structure and / or the fiberless second electrical insulation layer structure can have a thermal conductivity greater than 0.1 W / mK. This can provide the advantage that, for example, at least a portion of the heat generated by the electronic component can be transferred to the heat sink and / or exposed surfaces via the fiberless first electrical insulation layer structure and / or the fiberless second electrical insulation layer structure, thereby achieving good and reliable thermal management of the component carrier.

[0092] Advantageously, the material composition of the first electrical insulating layer structure 106 on the layer body 104 and on the electronic component 114 can be the same as the material composition in the lower portion of the connection between the electronic component 114 and the sidewall 154 defining the cavity of the stack 102. Correspondingly, the material composition of the second electrical insulating layer structure 110 on the layer body 104 and on the electronic component 114 can be the same as the material composition in the upper portion of the connection between the electronic component 114 and the sidewall 154 defining the cavity of the stack 102. This allows for a symmetrical stack and thus high reliability of the component carrier 100.

[0093] Advantageously, the first electrical insulating layer structure 106 has a very low roughness Ra on the main surface of the back layer body 104, i.e., on the lower main surface. Preferably, this roughness Ra is in the range of 20 nm to 400 nm. See [reference needed] Figure 1 The figure references Ra (l). Correspondingly, the second electrical insulating layer structure 110 can also have a very low roughness Ra on the main surface of the back-off layer body 104, i.e., on the upper main surface. Preferably, this roughness Ra is in the range of 20 nm to 400 nm. See [reference needed]. Figure 1The reference numeral Ra (2) in the figures is used. One reason for the very low roughness is that the electrically insulating layer structures 106 and 110 are made of pure resin 108 and 112, respectively, having filler particles 128 and 130 but no reinforcing glass fibers. This very low roughness allows the first electrically conductive fine line pattern portion 120 to be formed directly on the extremely smooth main surface of the back layer body 104 of the first electrically insulating layer structure 106. Correspondingly, this allows the second electrically conductive fine line pattern portion 122 to be formed directly on the extremely smooth main surface of the back layer body 104 of the second electrically insulating layer structure 110. In view of the high smoothness, the first fine line pattern portion 120 and the second fine line pattern portion 122 may each include electrically conductive traces and / or stacked pads or discs having a width w in the range of 2 μm to 15 μm. More specifically, the first fine line pattern portion 120 can be directly formed on the smooth surface of the first electrical insulating layer structure 106 and directly formed on one or more pads 132 (three pads in the illustrated embodiment) located on the lower main surface of the electronic component 114. Preferably, the first fine line pattern portion 120 can be directly formed on the smooth surface of the first electrical insulating layer structure 106 and directly formed on one or more pads 132 (three pads in the illustrated embodiment) located on the lower main surface of the electronic component 114 by sputtering. Correspondingly, the second fine line pattern portion 122 can be directly formed on the smooth surface of the second electrical insulating layer structure 110 and directly formed on one or more pads 132 (one pad in the illustrated embodiment) located on the upper main surface of the electronic component 114. Preferably, the second fine line pattern portion 122 can be directly formed on the smooth surface of the second electrical insulating layer structure 110 and directly formed on one or more pads 132 (one pad in the illustrated embodiment) located on the upper main surface of the electronic component 114 by sputtering. Therefore, the upper and lower electrically conductive sputtered layers 134 can be directly formed on one or more corresponding electrically conductive pads 132 of the electronic component 114, and can be directly formed on the exposed portions of the first electrically insulating layer structure 106 and the second electrically insulating layer structure 110. The electrically conductive sputtered layers 134 can form corresponding fine line pattern portions 120, 122 for forming traces with the highest integration density, and can achieve electrical contact with the component pads 132. All of this can be achieved with the highest precision, the highest density, and the smallest size. Furthermore, this direct electrical contact architecture allows the resulting component carrier 100 to have a very small thickness in the vertical direction, which is essentially defined only by the height of the component 114, the height of the electrically insulating layer structures 106, 110, and the height of the sputtered layer 134.

[0094] As from Figure 1As can be seen from detail 164, the sputtered layer 134 may include an adhesion-promoting sublayer 136, which can promote the adhesion of the sputtered layer 134 to the respective electrically insulating layer structures 106, 110 and to the pad 132. The adhesion-promoting sublayer 136 is preferably electrically conductive. Furthermore, a metal layer 138 may be formed on the adhesion-promoting sublayer 136 and can be used as a practical electrical signal transmission structure.

[0095] Due to the manufacturing process of component carrier 100 (see...) Figures 2 to 13 The conductive pad 132 of the electronic component 114 can be made of any desired metal or alloy material, and in particular, the conductive pad 132 of the electronic component 114 can also be made of a material other than copper. This design freedom stems from the sputtered layer 134 being formed directly on the electrically insulating layer structures 106, 110 and the pad 132.

[0096] Figures 2 to 13 It shows the process of manufacturing. Figure 1 The cross-sectional view of the structure obtained during the method of the component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0097] Reference Figure 2 An initial stack 102 is provided, comprising: a central layer body 104, a first metal layer 170 located on the lower main surface of the central layer body 104, and a second metal layer 172 located on the upper main surface of the central layer body 104. The central layer body 104 may be made of a fully cured core, which may include, for example, a cured resin (e.g., epoxy resin) and reinforcing fibers (e.g., glass fiber), and optionally includes filler particles (e.g., ceramic filler particles, which may be made of, for example, silicon oxide). For example, such a core may be made of FR4 material. The vertical thickness D of the central layer body 104 may preferably be in the range of 40 μm to 80 μm. Alternatively, the vertical thickness D of the central layer body 104 may preferably be in the range of 15 μm to 300 μm. For example, the first metal layer 170 and the second metal layer 172 may be copper foil. In short, Figure 2 The layered structure can be copper-clad core.

[0098] Reference Figure 3 A reference mark 142 can be formed in the layer body 104 and the metal layers 170, 172. In the illustrated embodiment, the reference mark 142 is formed by forming a vertically extending through... Figure 2 The entire layer structure shown is formed by through-holes. For example, this can be achieved by mechanical drilling using a frame drill.

[0099] Reference Figure 4Then, the metal layers 170 and 172 can be patterned to remove all metal material from the layer body 104 except for the direct surrounding portion around the through-hole forming the reference mark 142. This can be accomplished by photolithography and etching processes.

[0100] Reference Figure 5 The processing of the stack 102 can continue: it will include a first resin 108 (and optionally filler particles 128, see...) Figure 1 A fiber-free first electrical insulating layer structure 106 is disposed on the bottom main surface of the layer body 104. Furthermore, a second resin 112 may be included (and optionally filler particles 130, see [link]). Figure 1 A fiber-free second electrical insulating layer structure 110 is disposed on the top main surface of the layer body 104. For example, the electrical insulating layer structures 106 and 110 may be ABF sheets, thereby remaining at least partially uncured when laminated to the layer body 104. Figure 5 The state remains uncured. Advantageously, two at least partially uncured electrical insulating layer structures 106, 110 can be simultaneously connected to the layer body 104. For example, the connection can be achieved by lamination, i.e., by supplying heat and / or pressure, but only to the extent that the electrical insulating layer structures 106, 110 remain at least partially uncured even after being connected to the layer body 104. Advantageously, this allows for subsequent reference to... Figure 9 In the described additional lamination process, the resins 108 and 112 of the electrically insulating layer structures 106 and 110 are allowed to flow again, thereby enabling the gaps 118 to be filled with the resins 108 and 112. Only after the subsequent additional lamination process can the resins 108 and 112 become fully cured by permanent curing. Therefore, the first electrically insulating layer structure 106 can be attached to the bottom main surface of the layer body 104 in a at least partially uncured state, and the second electrically insulating layer structure 110 can be attached to the top main surface of the layer body 104 in a at least partially uncured state.

[0101] like Figure 5As shown, the respective thicknesses d1, d2 of each of the first electrical insulating layer structure 106 and the second electrical insulating layer structure 110 can preferably be in the range of 15 μm to 20 μm. Alternatively, the respective thicknesses d1, d2 of each of the first electrical insulating layer structure 106 and the second electrical insulating layer structure 110 can be in the range of 5 μm to 50 μm. In another example, the respective thicknesses d1, d2 of each of the first electrical insulating layer structure 106 and the second electrical insulating layer structure 110 can be greater than 50 μm, but still less than 500 μm. Advantageously, the two thicknesses d1, d2 can be the same to achieve symmetrical stacking and thus suppress undesirable warping. With such small thicknesses, a very thin component carrier 100 can be obtained.

[0102] Furthermore, a first dielectric separation foil 140 may be provided on the main surface of the back layer body 104 of the first electrical insulating layer structure 106. A second dielectric separation foil 144 may be provided simultaneously with the first dielectric separation foil 140 on the main surface of the back layer body 104 of the second electrical insulating layer structure 110. For example, the dielectric separation foils 140 and 144 may be made of a plastic material, such as polyethylene terephthalate (PET). The dielectric separation foils 140 and 144 may be referred to below. Figure 9 The subsequent additional lamination process described provides external separation of the resins 108 and 112 from the dielectric layer structures 106 and 110. It can be seen that at least a portion of reference mark 142 does not have the first electrical insulating layer structure 106 and the second electrical insulating layer structure 110.

[0103] Reference Figure 6 A cavity 116 is formed in the stack 102. More precisely, a through-hole constituting the cavity 116 is formed. To form the cavity 116, a portion of the layer body 104, a portion of the first electrical insulating layer structure 106, a portion of the second electrical insulating layer structure 110, a portion of the first dielectric separation foil 142, and a portion of the second dielectric separation foil 144 are removed. This can be achieved, for example, by laser cutting. In short, Figure 6 A process involving skiving for forming a cavity is illustrated. The cavity 116 includes two sidewalls 154 positioned opposite each other, the two sidewalls 154 having a generally vertical, straight orientation. Alternatively, the cavity 116 may have inclined sidewalls 154.

[0104] Reference Figure 7 A temporary support 146 is attached to the bottom side of the stack 102 to close the cavity 116 at the bottom side. For example, the temporary support 140 is an adhesive tape. For example, the temporary support 146 may be laminated onto the stack 102.

[0105] Reference Figure 8The electronic component 114 is inserted into the cavity 116 of the stack 102 and temporarily attached to the adhesive surface of the temporary carrier 140 by adhesive means. Alternatively, multiple components 114 can be inserted into the cavity 116 of the stack 102. The above insertion process ensures that the electronic component 114 to be embedded is temporarily fixed in place in the cavity 116. The permanent fixation of the electronic component 114 is later accomplished by curing the resin 108, 112 so that the resin 108, 112 flows into the gap 118 and glues the electronic component 114 into place.

[0106] In the illustrated embodiment, electronic component 114 includes electrically conductive pads 132 on both its bottom and top main surfaces. Alternatively, component 114 may include at least one electrically conductive pad 132 on either its bottom or top main surface. For example, electronic component 114 may be a semiconductor wafer, such as for radio frequency applications or as a control chip.

[0107] For example, the vertical thickness H of the electronic component 114 can be 60 μm, and more generally, the vertical thickness H of the electronic component 114 can be in the range of 30 μm to 100 μm. Preferably, the total thickness of the layer body 104 and the layer structures 106 and 110 can be no more than 10 μm greater than the thickness H of the electronic component 114, and more preferably, the total thickness of the layer body 104 and the layer structures 106 and 110 can be no more than 5 μm greater than the thickness H of the electronic component 114. Therefore, an ultra-thin component carrier 100 can be manufactured using the described manufacturing architecture.

[0108] Reference Figure 9 The gap 118 between the sidewall 154 defining the cavity 116 of the electronic component 114 and the stack 102 is partially filled with a first resin 108 and partially filled with a second resin 112. This is achieved by... Figure 8 The structure is achieved by applying pressure and / or heat to cure the first resin 108 and the second resin 112 of the electrical insulation layer structures 106, 110 through a single identical process. By applying pressure and / or heat, the at least partially uncured resins 108, 112 will become flowable and will begin to cure (particularly through polymerization and / or cross-linking). At least a portion, preferably all, of the material filling the gaps 118 is free of glass fibers, and / or at least a portion, preferably all, of the material filling the gaps 118 can be derived from the material of the first resin 108 and the second resin 112. After the curing process is completed, the now-cured resins 108, 112 will become permanent solids and will bond the embedded electronic component 114 in place. During the curing process, horizontal resin flow occurs simultaneously below and above the component 114, as... Figure 9As indicated by arrow 174. Due to the geometry shown, the dual resin flow will then be guided into gap 118. The horizontal resin flow will be facilitated by the dielectric separation foils 140, 144, making it impossible for the resin flow to flow vertically before reaching gap 118. Filling the gap 118 can be accomplished by simultaneously curing the first electrical insulating layer structure 106 and curing the second electrical insulating layer structure 110, i.e., during a single identical process. As flowing into gap 118, resins 108, 112 will flow in opposite and / or the same directions, and will form a common interface in gap 118 and between the two opposite main surfaces of the embedded electronic component 114. The first resin 108 and the second resin 112 may have different viscosities and / or flow behaviors. Thus, the corresponding resin with a lower viscosity compared to the other of the individual resins can fill the core and / or edges located inside cavity 116. This allows for a void-free or bubble-free structure. As from Figure 9 As can be seen, the presence of dielectric separation foils 140 and 144 causes a circumferential stepped portion 198 to be formed on the bottom side of the first electrical insulating layer structure 106 and at a position corresponding to the sidewall 154 of the stacked member 102.

[0109] Reference Figure 10 Detail 196 illustrates the material distribution within gap 118. As shown, the lower portion of gap 118 is filled with a first resin 108 (and optionally a first filler particle 128) of a first electrical insulating layer structure 106, while the upper portion of gap 118 is filled with a second resin 112 (and optionally a second filler particle 130) of a second electrical insulating layer structure 110. An interface can be formed between the first resin 108 and the second resin 112, which can be detected by analytical measurements, such as microscopy.

[0110] according to Figure 10 The temporary support 146 can be removed from the stack 102 after curing. Thereafter, the remaining portion of the first dielectric separation foil 140 can be removed from the main surface of the first electrical insulating layer structure 106 after curing. Furthermore, the remaining portion of the second dielectric separation foil 144 can be removed from the main surface of the second electrical insulating layer structure 110 after curing.

[0111] Reference Figure 11 According to Figure 10 Vertical through-holes 176 are formed in the obtained layer structure. This can be achieved, for example, by laser drilling or mechanical drilling.

[0112] Reference Figure 12 Electrically conductive materials can be deposited on Figure 11The structure is exposed on the surface. For example, this can be accomplished by plating (e.g., non-electroplated, then electroplated) and / or physical vapor deposition (PVD) or sputtering. Thus, the electrically conductive sputtered layer 134 is formed directly on the pad 132 located on the two main surfaces of the electronic component 114, directly on the lower main surface of the first electrically insulating layer structure 106, and directly on the upper main surface of the second electrically insulating layer structure 110. Furthermore, the sputtered electrically conductive material can fill the holes 176, thereby forming a vertical through-connection 178 for electrically coupling the two opposite main surfaces of the stack 102.

[0113] An adhesion-promoting sublayer can be formed before metal deposition (not in) Figure 12 As shown in the figure, refer to Figure 1 Reference numeral 136 in the figure serves as a support for the sputtered layer 134, and this adhesion promoting sublayer can promote the adhesion of the sputtered layer 134 to the corresponding electrical insulating layer structures 106, 110 and to the pad 132.

[0114] Advantageously, the exposed pads 132 on the two opposite main surfaces of the electronic component 114 can be directly connected to the electrically conductive sputtered layer 134 over the entire length of the pads without drilling laser vias prior to sputtering. This achieves a compact design, short electrical paths, low electrical losses, and low heat dissipation.

[0115] Reference Figure 13 The electrically conductive sputtered layers 134 on the two opposite main surfaces of the obtained component carrier 100 can be patterned to form wiring patterns, which may include electrically conductive traces and metal pads or disks. For example, the patterning can be performed by a photolithography process. More specifically, the patterning can be achieved by a combination of photolithography and etching processes. Given that the exposed lower main surface of the first electrically insulating layer structure 106 (fiber-free) and the exposed upper main surface of the second electrically insulating layer structure 110 (fiber-free) have significant smoothness or low roughness Ra, the wiring patterns can be formed with high integration density and small size.

[0116] Although not shown, individual component carriers 100 can be separated from the processed panel by separating the processed panel along separation line 178. For example, this separation can be accomplished by laser cutting or mechanical cutting. Therefore, according to... Figure 1 Component 100.

[0117] Figure 14 and Figure 15 A cross-sectional view of a structure obtained during the execution of a method for manufacturing a component carrier 100 according to another exemplary embodiment of the present invention is shown.

[0118] Reference Figure 14Electronic component 114 is mounted on first electrical insulating layer structure 106, which includes at least partially uncured material and is arranged on support body 182 of stack 102 (e.g., a laminated arrangement of one or more electrically conductive layer structures and / or one or more electrically insulating layer structures).

[0119] Reference Figure 15 ,according to Figure 14 The structure is covered by a layer body 104 having through holes defining the cavity 116, such that the electronic component 114 is disposed inside the cavity 116 and a gap 118 is present between the electronic component 114 and the layer body 104. A complete layer in the form of a second electrically insulating layer structure 110 comprising at least partially uncured material is provided on top of the obtained structure to cover the upper main surface of the layer body 104 and the upper main surface of the electronic component 114.

[0120] Although not shown, the initially uncured electrical insulation layer structures 106, 110 can then be fully cured, such that the first resin 108 and the second resin 112 fill the gap 118.

[0121] Figure 16 A cross-sectional view of the structure obtained during the execution of a method for manufacturing a component carrier 100 according to yet another exemplary embodiment of the present invention is shown.

[0122] according to Figure 16 A stack 102 is provided, the stack 102 including a support body 182 (the support body 182 may be implemented according to...) Figure 14 The support body 182, the first electrical insulating layer structure 106 located on the support body 182 and at least partially uncured, and the layer body 104 on the first electrical insulating layer structure 106.

[0123] Furthermore, a release layer 186 can be formed at the interface between the first electrical insulating layer structure 106 and the layer body 104. For example, this release layer 186 can be made of a material that exhibits poor adhesion properties relative to the surrounding material. Suitable materials for the release layer 186, for example, are polytetrafluoroethylene (PTFE, Teflon) or wax compounds. Subsequently, a cavity 116 is formed in the layer body 104 by removing (see reference numeral 190) the piece 188 defined by the release layer 186 at the bottom side of the layer body 104. To separate the piece 188 circumferentially, a circumferentially cut groove extending to the release layer 186 can be formed in the layer body 104, thereby separating the piece 188 from the remainder of the layer body 104. Cutting the groove can be accomplished, for example, by laser drilling using a laser source 184 or by mechanical drilling. Figure 16The cavity 116 may include vertically straight or vertically inclined sidewalls 154.

[0124] After removing segment 188, release layer 186 can be removed (e.g., by peeling), and then electronic component 114 can be disposed in the resulting cavity 116 and on the exposed portion of at least partially uncured first electrical insulating layer structure 106. Then, partially uncured second electrical insulating layer structure 110 can be disposed on top of layer body 104 and on top of electronic component 114, thereby obtaining a corresponding... Figure 15 The structure. Then, you can refer to the above text. Figure 15 Further processing will be performed at the location specified.

[0125] Figure 17 A cross-sectional view of the structure obtained during the execution of a method for manufacturing a component carrier 100 according to yet another exemplary embodiment of the present invention is shown.

[0126] according to Figure 17 Implementation methods and basis Figure 16 The difference in the implementation method is particularly that: according to Figure 17 Instead of using release layer 186 and laser cutting, the cavity 116 is milled out in layer body 104 using a milling machine 192.

[0127] Subsequently, electronic components 114 can be disposed in the obtained cavity 116 and on the exposed portion of the at least partially uncured first electrical insulating layer structure 106. Then, a partially uncured second electrical insulating layer structure 110 can be disposed on top of the layer body 104 and on top of the electronic components 114, thereby obtaining a corresponding... Figure 15 The structure. Then, you can refer to the above text. Figure 15 Further processing will be performed at the location specified.

[0128] It should be noted that the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude multiple. Furthermore, elements described in conjunction with different embodiments can be combined.

[0129] It should also be noted that the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

[0130] Implementations of the present invention are not limited to the preferred embodiments shown in the figures and described above. Rather, even in fundamentally different embodiments, various modifications using the illustrated solutions and principles according to the invention are possible.

Claims

1. A component carrier (100), wherein, The component carrier (100) includes: A stack (102) comprising a layer body (104), a fiberless first electrical insulating layer structure (106) on the bottom main surface of the layer body (104), and a fiberless second electrical insulating layer structure (110) on the top main surface of the layer body (104), the first electrical insulating layer structure (106) comprising a first resin (108), and the second electrical insulating layer structure (110) comprising a second resin (112); and Component (114) is inserted into cavity (116) of stack (102); Wherein, at least a portion of the gap (118) between the component (114) and the sidewall (154) of the stack (102) that defines the cavity (116) is partially filled with the first resin (108) and partially filled with the second resin (112).

2. The component carrier (100) according to claim 1, wherein, The first electrically insulating layer structure (106) has a roughness Ra in the range of 10 nm to 800 nm on the main surface opposite to the layer body (104), and in particular, the first electrically insulating layer structure (106) has a roughness Ra in the range of 20 nm to 400 nm on the main surface opposite to the layer body (104), and / or wherein, The second electrical insulating layer structure (110) has a roughness Ra in the range of 10 nm to 800 nm on the main surface away from the layer body (104), and in particular, the second electrical insulating layer structure (110) has a roughness Ra in the range of 20 nm to 400 nm on the main surface away from the layer body (104).

3. The component carrier (100) according to any one of claims 1 to 2, the component carrier (100) comprising a first electrically conductive fine line pattern portion (120) located on the main surface of the first electrically insulating layer structure (106) opposite to the layer body (104), and / or the component carrier (100) comprising a second electrically conductive fine line pattern portion (122) located on the main surface of the second electrically insulating layer structure (110) opposite to the layer body (104), wherein, in particular, the first fine line pattern portion (120) and / or the second fine line pattern portion (122) comprises electrically conductive traces having a width (w) in the range of 1 μm to 15 μm.

4. The component carrier (100) according to any one of claims 1 to 3, wherein, The first electrical insulating layer structure (106) includes first filler particles (128), and / or wherein, The second electrical insulating layer structure (110) includes second filler particles (130).

5. The component carrier (100) according to any one of claims 1 to 4, the component carrier (100) comprising an electrically conductive layer formed directly on at least one electrically conductive pad (132) of the component (114) and / or formed directly on at least one of the first electrically insulating layer structure (106) and the second electrically insulating layer structure (110), for example, the electrically conductive layer being a sputtered layer (134).

6. The component carrier (100) according to any one of claims 1 to 5, wherein, The thickness (d1, d2) of at least one of the first electrical insulating layer structure (106) and the second electrical insulating layer structure (110) is in the range of 5 μm to 100 μm. For example, the thickness (d1, d2) of at least one of the first electrical insulating layer structure (106) and the second electrical insulating layer structure (110) is in the range of 10 μm to 50 μm.

7. The component carrier (100) according to any one of claims 1 to 6, wherein, The thickness (D) of the layer body (104) is in the range of 15 μm to 500 μm, and in particular, the thickness (D) of the layer body (104) is in the range of 20 μm to 100 μm.

8. The component carrier (100) according to any one of claims 1 to 7, wherein, The first electrical insulation layer structure (106) and the second electrical insulation layer structure (110) are made of the same material.

9. The component carrier (100) according to any one of claims 1 to 8, wherein, The material composition of the first electrical insulating layer structure (106) on the layer body (104) and on the component (114) is the same as the material composition in the connection portion of the gap (118), and / or wherein, The material composition of the second electrical insulation layer structure (110) on the layer body (104) and on the component (114) is the same as the material composition in the connection portion of the gap (118).

10. The component carrier (100) according to any one of claims 1 to 9, wherein the component carrier (100) comprises at least one of the following features: in, The bottom side of the first electrical insulation layer structure (106) has a stepped portion (198) at a position corresponding to the sidewall (154) of the stack (102).

11. A method for manufacturing a component carrier (100), wherein, The method includes: A stack (102) is formed by arranging a fiberless first electrical insulating layer structure (106) on the bottom main surface of the layer body (104) and by arranging a fiberless second electrical insulating layer structure (110) on the top main surface of the layer body (104), wherein the first electrical insulating layer structure (106) comprises a first resin (108) and the second electrical insulating layer structure (110) comprises a second resin (112). A cavity (116) is formed in the stacked member (102); Insert the component (114) into the cavity (116) of the stack (102); and At least a portion of the gap (118) between the component (114) and the sidewall (154) of the stack (102) that defines the cavity (116) is partially filled with the first resin (108) and partially filled with the second resin (112).

12. The method according to claim 11, wherein, A first dielectric separation foil (140) is provided on the main surface of the first electrical insulating layer structure (106) opposite to the layer body (104), and / or a second dielectric separation foil (144) is provided on the main surface of the second electrical insulating layer structure (110) opposite to the layer body (104), wherein, in particular, the method includes: after the curing, completely removing the first dielectric separation foil (142) and the second dielectric separation foil (144).

13. The method according to claim 11 or 12, wherein, The method includes: filling at least a portion of the gap (118) by curing the first resin (108) and the second resin (112), and then removing the first dielectric separation foil (140) from the main surface of the first electrical insulating layer structure (106) and / or removing the second dielectric separation foil (144) from the main surface of the second electrical insulating layer structure (110) before completing the manufacture of the component carrier (100), in particular, curing the first resin (108) and the second resin (112) by applying pressure and / or heat.

14. The method according to claim 12 or 13, wherein, The method includes removing a portion of the layer body (104), a portion of the first electrical insulating layer structure (106), a portion of the second electrical insulating layer structure (110), a portion of the first dielectric separation foil (142), and a portion of the second dielectric separation foil (144) to form the cavity (116).

15. The method according to any one of claims 11 to 14, wherein, The method includes forming a reference mark (142) in and / or on the layer body (104) before arranging the first electrical insulating layer structure (106) and the second electrical insulating layer structure (110) on the layer body (104).

16. The method according to any one of claims 11 to 15, wherein, The method includes: directly sputtering an electrically conductive sputtered layer (134) onto at least one pad (132) of the component (114) and / or directly sputtering it onto at least one of the first electrically insulating layer structure (106) and the second electrically insulating layer structure (110).

17. The method according to any one of claims 11 to 16, wherein, The method includes attaching the temporary support (146) to the stack (102) to close the cavity (116) before inserting the component (114) into the cavity (116) and placing it on the temporary support (146), wherein, in particular, the method includes removing the temporary support (146) after the curing.

18. The method according to any one of claims 11 to 17, wherein, The method includes: The first electrical insulating layer structure (106) is disposed on the bottom main surface of the layer body (104) in a state that is at least partially uncured, and the second electrical insulating layer structure (110) is disposed on the top main surface of the layer body (104) in a state that is at least partially uncured; and Subsequently, at least a portion of the gap (118) is filled by simultaneously curing the first electrical insulating layer structure (106) and the second electrical insulating layer structure (110).

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