Semiconductor processing integration of bipolar junction transistors (BJTs)

Abstract

A semiconductor device (3600, 4300) includes a semiconductor substrate (102), a base dielectric layer (202b), a collector layer (902), a base layer (1102), and an emitter layer (1602). The semiconductor substrate (102) includes a bipolar junction transistor region (104). The base dielectric layer (202b) is in the bipolar junction transistor region (104) and over an upper surface (120) of the semiconductor substrate (102). The collector layer (902) is on the upper surface (120) of the semiconductor substrate (102) and through the base dielectric layer (202b). The base layer (1102) is on the collector layer (902) and an upper surface (120) of the base dielectric layer (202b). The base dielectric layer (202b) extends laterally from the base layer (1102) over the upper surface (120) of the semiconductor substrate (102). The emitter layer (1602) is on the base layer (1102).

Description

Background Technology

[0001] Integrated circuits may include bipolar junction transistors (BJTs). BJTs may be desired to meet high-performance and high-current drive requirements due to their high-gain characteristics. Scaling devices in integrated circuits to smaller nodes may require novel methods for semiconductor fabrication of those devices. Furthermore, integrating BJTs with other devices can complicate semiconductor fabrication. Summary of the Invention

[0002] The example described herein is a semiconductor device. The semiconductor device includes a semiconductor substrate, a base dielectric layer, a collector layer, a base layer, and an emitter layer. The semiconductor substrate includes a bipolar junction transistor region. The base dielectric layer is located within the bipolar junction transistor region and is situated above the upper surface of the semiconductor substrate. The collector layer is situated on the upper surface of the semiconductor substrate and extends through the base dielectric layer. The base layer is situated on the upper surfaces of the collector layer and the base dielectric layer. The base dielectric layer extends laterally from the base layer above the upper surface of the semiconductor substrate. The emitter layer is situated on the base layer.

[0003] Another example is a method. A gate layer is formed above a semiconductor substrate. An opening through the gate layer is formed in a bipolar junction transistor (BJT) region. A collector layer is formed in the opening and on the upper surface of the semiconductor substrate. A base layer is formed on the collector layer. An emitter layer is formed on the base layer. After forming the emitter layer, the gate layer is patterned to resemble the gate electrode of a transistor in a complementary field-effect transistor (CFET) region of the semiconductor substrate.

[0004] Another example is a method. A base dielectric layer is formed above a semiconductor substrate in a bipolar junction transistor region. A gate layer is formed above the semiconductor substrate and above the base dielectric layer. A first opening is formed through the gate layer to reach the base dielectric layer. The sidewall of the gate layer defining the first opening is above the base dielectric layer. A second opening is formed through the first opening to reach the upper surface of the semiconductor substrate through the base dielectric layer. A collector layer is formed through the first opening, the second opening, and on the upper surface of the semiconductor substrate. A base layer is formed on the collector layer through the first opening. An emitter layer is formed on the base layer through the first opening. The gate layer is patterned into a first gate electrode of a p-type transistor and a second gate electrode of an n-type transistor. The p-type transistor and the n-type transistor are in a complementary field-effect transistor (CFET) region of the semiconductor substrate.

[0005] The foregoing summary provides a fairly broad overview of the various features of the examples in this specification in order to better understand the following detailed description. Various features and advantages of these examples will be described below. The described examples can be readily used as a basis for modifying or designing other examples within the scope of the appended claims. Attached Figure Description

[0006] To gain a detailed understanding of the above features, please refer to the following detailed description taken in conjunction with the accompanying drawings.

[0007] Figures 1 to 36 These are cross-sectional views of semiconductor devices at intermediate manufacturing stages, based on some examples.

[0008] Figures 37 to 43 These are cross-sectional views of semiconductor devices at intermediate manufacturing stages, based on some examples.

[0009] Figure 44 It is based on some examples Figure 36 and 43 The layout diagram of a bipolar junction transistor (BJT) in a semiconductor device.

[0010] The drawings and accompanying detailed description are provided to help understand the features of various examples and do not limit the scope of the appended claims. Examples shown in the drawings and described in the accompanying detailed description can be readily used as a basis for modifying or designing other examples within the scope of the appended claims. Where possible, the same reference numerals may be used to refer to the same elements common to each drawing. The drawings are drawn to clearly show the relevant elements or features, and the drawings are not necessarily drawn to scale. Detailed Implementation

[0011] Various features will be described below with reference to diagrams. Other examples may include any arrangement which includes or does not include the described aspects or features. The examples shown may not have all the aspects or advantages presented. The aspects or advantages described in connection with a particular example are not necessarily limited to the example described and may be practiced in any other example, even if not so stated or explicitly described. Furthermore, the methods described herein may be described in a specific order of operations, but other methods according to other examples may be implemented in various other orders with more or fewer operations (e.g., different serial or parallel executions involving various operations).

[0012] This specification generally, but not exclusively, relates to the semiconductor fabrication integration of bipolar junction transistors (BJTs). Some examples include semiconductor devices containing BJTs. A semiconductor substrate contains the BJT region. A base dielectric layer is in the BJT region and above the upper surface of the semiconductor substrate. A collector layer is on the upper surface of the semiconductor substrate and extends through the base layer. A base layer is on the upper surface of the collector layer and the base dielectric layer. The base dielectric layer extends laterally from the base layer above the upper surface of the semiconductor substrate. An emitter layer is on the base layer. Semiconductor fabrication methods used to form such BJTs allow for vertical and horizontal scaling of the BJT, which can improve the characteristics of the BJT (e.g., parasitic resistance and capacitance). Other benefits and advantages can be achieved.

[0013] Various examples are then described. While a particular example may illustrate various aspects of the features generally described above, examples may be incorporated into any combination of features generally described above (which are described in more detail in the examples below).

[0014] Figures 1 to 36 These are cross-sectional views of semiconductor devices at intermediate manufacturing stages, based on some examples. (Reference) Figure 1 A semiconductor substrate 102 is provided. The semiconductor substrate 102 includes a BJT region 104, a first transition region 106, a second transition region 108, a p-type field-effect transistor (pFET) region 110, and an n-type field-effect transistor (nFET) region 112. The pFET region 110 and the nFET region 112 are together contained in a complementary field-effect transistor (CFET) region.

[0015] Semiconductor substrate 102 may be or comprise a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or any other suitable substrate. Semiconductor substrate 102 may also comprise a support (or disposal) substrate and an epitaxial layer epitaxially grown on the support substrate. In some examples, semiconductor substrate 102 is or comprises a silicon substrate (which may be separated from a bulk silicon wafer at the end of semiconductor processing). In other examples, semiconductor substrate 102 comprises a silicon substrate on which an epitaxial silicon layer is grown. Semiconductor substrate 102 is or comprises a semiconductor material in which and / or on which devices such as BJTs, pFETs, and nFETs (described later) are formed. In some examples, the semiconductor material is or comprises silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), gallium nitride (GaN), and combinations thereof. Semiconductor substrate 102 has an upper surface 120 in which and / or on which devices (e.g., BJTs, pFETs, and nFETs) are formed. In the illustrated example, the semiconductor material of semiconductor substrate 102 is p-type doped with a p-type dopant. In some instances, the semiconductor substrate 102 uses a concentration of 1×10 14 cm -3 Up to 1×10 15 cm -3 p-type dopant (e.g., boron (B)) within the range can be p-type doped. Another dopant type and / or other doping concentrations may be implemented.

[0016] Isolation structures 122 (including first portion 122a and second portion 122b), 124 (including first portion 124a and second portion 124b), 126, and 128 are formed on the semiconductor substrate 102. In the illustrated example, isolation structures 122, 124, 126, and 128 extend from the upper surface 120 of the semiconductor substrate 102 to a shallow trench isolation structure (STI) within the semiconductor substrate 102. As shown, isolation structures 122 to 128 also protrude above the upper surface 120 of the semiconductor substrate 102, and in other examples, isolation structures 122 to 128 may have a corresponding upper surface coplanar with and / or below the upper surface 120 of the semiconductor substrate 102. Isolation structures 122 to 128 may include, for example, a liner layer, such as comprising silicon oxide or silicon nitride, conformally along the surface of the corresponding trench in the semiconductor substrate 102; and a filling isolation material, such as silicon oxide, above and over the liner layer.

[0017] As shown, isolation structures 122 to 128 can be formed by depositing a hard mask layer over a semiconductor substrate 102. The hard mask layer can be any suitable material, such as silicon nitride, silicon oxynitride, etc., and can be deposited using any suitable deposition process, such as chemical vapor deposition (CVD). For example, the hard mask layer can be patterned using photolithography and etching processes (e.g., reactive ion etching (RIE)). Using the patterned hard mask layer as a mask, grooves or trenches are etched in the semiconductor substrate 102, for example, by RIE. Subsequently, a liner layer can be conformally deposited in the grooves or trenches and over the patterned hard mask layer, for example, by plasma-enhanced CVD (PECVD) (or formed, for example, on the exposed surface of the grooves or trenches by an oxidation process), and a filling isolation material can be deposited over the liner layer, for example, by high aspect ratio CVD (HAR-CVD), flowable CVD (FCVD), etc. Excess filler material and liner layer can be removed from above the hard mask layer via a planarization process, such as chemical mechanical polishing (CMP). The hard mask layer can then be removed by selective etching, which can be a wet etching process. In other examples, isolation structures 122 to 128 can be field oxide structures, such as localized oxide of silicon (LOCOS) structures, at the upper surface 120 of the semiconductor substrate 102, which can be formed using a LOCOS process.

[0018] The isolation structure 122 laterally defines the active region of the BJT to be formed on the upper surface 120 of the semiconductor substrate 102. The isolation structure 122 laterally surrounds the active region of the BJT to be formed on the upper surface 120 of the semiconductor substrate 102. As indicated below, the active portion of the BJT (e.g., the base layer) extends laterally beyond the active region of the BJT formed on the upper surface 120 of the semiconductor substrate 102 and extends over the first portion 122a of the isolation structure 122. Furthermore, the isolation structure 124 defines the lateral boundary of the BJT region 104. The isolation structure 124 laterally surrounds the isolation structure 122, with a doped isolation well between them, as described below.

[0019] The first portion 124a of isolation structures 126 and 124 at least partially laterally defines the upper surface 120 of semiconductor substrate 102 over which an active region of a pFET will be formed. The active region of the pFET formed on the upper surface 120 of semiconductor substrate 102 defines the lateral boundary of pFET region 110. Similarly, isolation structures 126, 128 at least partially laterally define the upper surface 120 of semiconductor substrate 102 over which an active region of an nFET will be formed. The active region of the nFET formed on the upper surface 120 of semiconductor substrate 102 defines the lateral boundary of nFET region 112. CFET region includes pFET region 110 and nFET region 112. The lateral outer boundaries of pFET region 110 and / or nFET region 112 (or other pFET and / or nFET regions) define the lateral boundary of CFET region.

[0020] The first transition region 106 is defined as the lateral boundary from the BJT region 104 to the nearest lateral boundary of the CFET region (which in the illustrated example is the boundary of the pFET region 110). The first transition region 106 includes a first portion 124a of the isolation structure 124. The second transition region 108 is defined as the lateral boundary from the BJT region 104 to the nearest lateral boundary of another region (not shown). The second transition region 108 includes a second portion 124b of the isolation structure 124.

[0021] n-type doped wells 142 and 144 are formed in a semiconductor substrate 102. The n-type doped wells 142 and 144 can be formed by masking (e.g., using photolithography through photoresist) regions of the semiconductor substrate 102 where no n-type doped wells are formed and implanting n-type dopant into the semiconductor substrate 102. The n-type doped well 142 extends from the upper surface 120 of the semiconductor substrate 102 to a depth within the semiconductor substrate 102 and is laterally located in the BJT region 104 between portions 122a and 122b of the isolation structure 122. The n-type doped well 144 extends from the upper surface 120 of the semiconductor substrate 102 to a depth within the semiconductor substrate 102 and is laterally located in the pFET region 110 between the first portion 124a of the isolation structure 124 and the isolation structure 126. The concentration of the n-type dopant in the n-type doped wells 142 and 144 is greater than the concentration of the p-type dopant in the p-type doped semiconductor substrate 102. In some instances, n-type doped wells 142 and 144 are used with a concentration of 1 × 10⁻⁶. 15 cm -3 Up to 1×10 17 cm -3 Doping can be performed with n-type dopants within the range (e.g., phosphorus (P) or arsenic (As)). Another dopant type and / or other doping concentrations may be implemented.

[0022] An n-type doped sub-collector diffusion region 146 is formed in an n-type doped well 142 within a semiconductor substrate 102. The n-type doped sub-collector diffusion region 146 can be formed by masking (e.g., using photolithography through photoresist) regions of the semiconductor substrate 102 where no n-type doped sub-collector diffusion region is formed and by implanting an n-type dopant into the semiconductor substrate 102. The n-type doped sub-collector diffusion region 146 extends from the upper surface 120 of the semiconductor substrate 102 into the n-type doped well 142 within the semiconductor substrate 102 to a depth, and is laterally located between portions 122a and 122b of the isolation structure 122 within the BJT region 104. The concentration of the n-type doped sub-collector diffusion region 146 is greater than the concentration of the n-type dopant in the n-type doped well 142. In some examples, the n-type doped sub-collector diffusion region 146 uses a concentration of 1 × 10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 Doping can be performed with n-type dopants within the range. Another dopant type and / or other doping concentrations may also be implemented.

[0023] P-type doped wells 148 and 150 are formed in semiconductor substrate 102. These p-type doped wells 148 and 150 can be formed by masking (e.g., using photolithography through photoresist) regions of semiconductor substrate 102 where no p-type doped wells are formed and implanting p-type dopant into semiconductor substrate 102. P-type doped well 148 extends from the upper surface 120 of semiconductor substrate 102 to a depth within semiconductor substrate 102 and is laterally located between isolation structures 122 and 124 in BJT region 104. P-type doped well 148 is an isolation ring surrounding the active region where a BJT will be formed. P-type doped well 150 extends from the upper surface 120 of semiconductor substrate 102 to a depth within semiconductor substrate 102 and is laterally located between isolation structures 126 and 128 in nFET region 112. The concentration of p-type dopant in p-type doped wells 148 and 150 is greater than the concentration of p-type dopant in p-type doped semiconductor substrate 102. In some instances, p-type doped wells 148 and 150 are used with a concentration of 1 × 10⁻⁶. 15 cm -3 Up to 1×10 17 cm -3 Doping can be performed with p-type dopants (e.g., boron (B)) within the range. Another dopant type and / or other doping concentrations may be implemented.

[0024] Although the semiconductor substrate 102, n-type doped wells 142, 144, n-type doped subcollector diffusion region 146, and p-type doped wells 148, 150 are described herein as being doped with a certain dopant conductivity type, in other instances these components may be doped with the opposite conductivity type (e.g., n-type doped instead of p-type doped, and vice versa). Similarly, components subsequently described as being doped with a certain dopant conductivity type may in other instances be doped with the opposite conductivity type.

[0025] refer to Figure 2 A pedestal dielectric layer 202 is formed over a semiconductor substrate 102. The pedestal dielectric layer 202 is conformally deposited over the upper surface 120 of the semiconductor substrate 102 and the isolation structures 122 to 128. In some instances, the pedestal dielectric layer 202 is silicon oxide (e.g., tetraethyl orthosilicate (TEOS) oxide) deposited by CVD, but in other instances other dielectric materials and / or other deposition processes may be used.

[0026] refer to Figure 3The substrate dielectric layer 202 is etched, thereby placing the substrate dielectric layer 202a within the BJT region 104. Appropriate photolithography and etching processes can be used to etch the substrate dielectric layer 202. For example, anisotropic etching, such as RIE, can be performed. The substrate dielectric layer 202a extends laterally over the upper surface 120 of the semiconductor substrate 102 within the BJT region 104, such that the sidewalls 302 of the substrate dielectric layer 202a are positioned over the upper surface 120 of the semiconductor substrate 102 within the BJT region 104. The substrate dielectric layer 202a extends laterally over the first portion 122a of the isolation structure 122 within the BJT region 104, such that the sidewalls 304 of the substrate dielectric layer 202a are positioned over the first portion 122a of the isolation structure 122 within the BJT region 104.

[0027] refer to Figure 4 A gate dielectric layer 402 is formed above the upper surface of the semiconductor substrate 102. In the illustrated example, the gate dielectric layer 402 is formed in the BJT region 104, pFET region 110, and nFET region 112 on the exposed portion of the upper surface 120 of the semiconductor substrate 102. In the illustrated example, the gate dielectric layer 402 can be formed by an oxidation process, such as in-situ water vapor oxidation (ISSG), which oxidizes the exposed portion of the upper surface 120 of the semiconductor substrate 102 to form an oxide as the gate dielectric layer 402. In other examples, other dielectric materials can be formed using appropriate deposition processes that conformally deposit the gate dielectric layer above the semiconductor substrate 102.

[0028] refer to Figure 5 A gate layer 502 is formed over a semiconductor substrate 102, and a dielectric protective layer 504 is formed over the gate layer 502. The gate layer 502 is formed over the gate dielectric layer 402, isolation structures 122 to 128, and a base dielectric layer 202a. In some examples, the gate layer 502 is or contains a semiconductor material, such as polycrystalline silicon, and can be formed by any deposition process, such as CVD. In some examples, the semiconductor material can be doped in situ during deposition, and / or implanted by dopant after deposition. In some examples, the gate layer 502 is formed after deposition and / or implantation with a concentration of 1 × 10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 The polysilicon is doped with p-type dopant within the specified range. Other materials (e.g., conductive materials) may be implemented as gate layer 502, which can be formed by any deposition process. In some instances, dielectric protective layer 504 is silicon oxide (e.g., TEOS oxide) deposited by CVD, but in other instances other dielectric materials and / or other deposition processes may be used.

[0029] refer to Figure 6 The dielectric protective layer 504 and the gate layer 502 are etched to form an opening 602 extending through the dielectric protective layer 504a and the gate layer 502a to the base dielectric layer 202a. The opening 602 is in the BJT region 104. The opening 602 is at least partially defined by the sidewalls 604, 606 of the gate layer 502a (and further defined by corresponding sidewalls of the dielectric protective layer 504a not indicated by reference numerals). The sidewall 604 of the gate layer 502a is in the BJT region 104 above the base dielectric layer 202a and the first portion 122a of the isolation structure 122. The sidewall 606 of the gate layer 502a is in the BJT region 104 above the base dielectric layer 202a. As will be shown later, the BJT is formed through the opening 602 through the gate layer 502a. The dielectric protective layer 504 and the gate layer 502 can be etched using suitable photolithography and etching processes. For example, anisotropic etching, such as RIE, can be implemented.

[0030] refer to Figure 7 A hard mask layer 702 is conformally formed over the semiconductor substrate 102. The hard mask layer 702 is conformally formed over the dielectric protective layer 504a, along the sidewalls 604, 606, and over the base dielectric layer 202a exposed through the opening 602. In some instances, the hard mask layer 702 is or comprises silicon nitride deposited by CVD, but in other instances other hard mask (e.g., dielectric) materials and / or other deposition processes may be used.

[0031] refer to Figure 8 The hard mask layer 702 and the base dielectric layer 202a are etched to form a collector opening 802 through the hard mask layer 702a and the base dielectric layer 202b. The hard mask layer 702 and the base dielectric layer 202a are etched through the opening 602 to form the collector opening 802. The upper surface 120 of the semiconductor substrate 102 is exposed through the collector opening 802. The collector opening 802 extends laterally away from the first portion 122a of the isolation structure 122 in the BJT region 104, generally from the vicinity of (or a certain lateral distance from) the first portion 122a of the isolation structure 122. The hard mask layer 702 and the base dielectric layer 202a can be etched using appropriate photolithography and etching processes. For example, anisotropic etching, such as RIE, can be implemented.

[0032] refer to Figure 9A collector layer 902 is formed above (e.g., on) the upper surface 120 of the semiconductor substrate 102 and in the collector opening 802. In some examples, the collector layer 902 is or comprises a semiconductor layer doped with an n-type dopant (e.g., the same type of dopant as the n-type doped sub-collector diffusion region 146). In some examples, the collector layer 902 is or comprises silicon. In some examples, the collector layer 902 is doped with a concentration of 1 × 10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 The collector layer 902 is doped with an n-type dopant within a certain range. It can be epitaxially grown on the upper surface 120 of the semiconductor substrate 102. In some instances, the collector layer 902 can be epitaxially grown using a selective epitaxial growth process. Epitaxial growth of the collector layer 902 on the upper surface 120 of the semiconductor substrate 102 may result in a single-crystal collector layer 902. Alternatively, the collector layer 902 can be doped in situ during the epitaxial growth process (e.g., a selective epitaxial growth process). The epitaxial growth process can be a CVD process, such as low-pressure CVD (LPCVD), reduced-pressure CVD (RPCVD), metal-organic CVD (MOCVD), etc. Other materials, dopant types, dopant concentrations, and / or deposition processes can be implemented.

[0033] refer to Figure 10 The hard mask layer 702a is removed. The hard mask layer 702a can be removed using an etching process that is selective to the material of the hard mask layer 702a; this etching can be a wet etching process. For example, when the hard mask layer 702a is silicon nitride, a wet etching process containing phosphoric acid (H3PO4) can be used to remove the hard mask layer 702a.

[0034] refer to Figure 11 A base layer 1102 is formed above the collector layer 902. The base layer 1102 comprises a single-crystal base layer 1102a and a polycrystalline base layer 1102b. The single-crystal base layer 1102a and the polycrystalline base layer 1102b are formed together to form the base layer 1102. In some examples, the base layer 1102 is or comprises a semiconductor layer doped with a p-type dopant (e.g., a dopant type opposite to that of the collector layer 902). In some examples, the base layer 1102 is or comprises silicon germanium. In some examples, the base layer 1102 is doped with a concentration of 1 × 10⁻⁶. 17 cm -3 Up to 1×10 21 cm -3The base layer 1102 is doped with p-type dopants within the specified range. The base layer 1102 may also be doped with carbon (C) to prevent or reduce the diffusion of p-type dopants. The base layer 1102 may be epitaxially grown on the collector layer 902, the base dielectric layer 202b, the gate layer 502a, and the dielectric protection layer 504a. In some embodiments, the base layer 1102 may be epitaxially grown using a non-selective epitaxial growth process. The non-selective epitaxial growth process grows a single-crystal base layer 1102a from the collector layer 902 and a polycrystalline base layer 1102b on other amorphous or polycrystalline surfaces (e.g., the base dielectric layer 202b). The single-crystal base layer 1102a may be adjacent to the polycrystalline base layer 1102b at a small facet not specifically shown. The non-selective deposition of the base layer 1102 conformally forms the base layer 1102 within and outside the opening 602 on the dielectric protection layer 504a. The base layer 1102 can be doped in situ during the epitaxial growth process. The base layer 1102 (e.g., a single-crystal base layer 1102a and a polycrystalline base layer 1102b, respectively) may further comprise multiple sublayers, such as a nucleation sublayer of the same material as the collector layer 902, an undoped sublayer, a doped sublayer, and a capping layer of the same material as the emitter layer (described later). The epitaxial growth process can be a CVD process, such as LPCVD, RPCVD, MOCVD, etc. Other materials, dopant types, dopant concentrations, and / or deposition processes can be implemented.

[0035] refer to Figure 12 A first dielectric spacer layer 1202 is conformally formed over the base layer 1102. A second dielectric spacer layer 1204 is conformally formed over the first dielectric spacer layer 1202, and a third dielectric spacer layer 1206 is conformally formed over the second dielectric spacer layer 1204. In some examples, the first dielectric spacer layer 1202 and the third dielectric spacer layer 1206 are made of the same dielectric material, and the second dielectric spacer layer 1204 is made of a different dielectric material than the first dielectric spacer layer 1202 and the third dielectric spacer layer 1206. In some examples, the first dielectric spacer layer 1202 and the third dielectric spacer layer 1206 are made of silicon oxide (e.g., TEOS oxide), and the second dielectric spacer layer 1204 is made of silicon nitride. The dielectric spacer layers 1202 to 1206 can be deposited by CVD. In other examples, other dielectric materials and / or other deposition processes can be used.

[0036] refer to Figure 13Dielectric spacer layers 1202 to 1206 are etched to form a first emitter opening 1302 through the first dielectric spacer layer 1202a, the second dielectric spacer layer 1204a, and the third dielectric spacer layer 1206a. Dielectric spacer layers 1202 to 1206 are etched through opening 1202 to form the first emitter opening 1302. The single-crystal base layer 1102a (of base layer 1102) is exposed through the first emitter opening 1302. The first emitter opening 1302 is located in the BJT region 104. Suitable photolithography and etching processes can be used to etch dielectric spacer layers 1202 to 1206. For example, anisotropic etching, such as RIE, can be implemented.

[0037] refer to Figure 14 An emitter dielectric spacer layer 1402 is conventionally formed over the third dielectric spacer layer 1206a and the first emitter opening 1302. In some instances, the emitter dielectric spacer layer 1402 is silicon oxide (e.g., TEOS oxide) deposited by CVD, but in other instances other dielectric materials and / or other deposition processes may be used.

[0038] refer to Figure 15 The emitter dielectric spacer layer 1402 is anisotropically etched to form an emitter dielectric spacer 1402a along the sidewall defining the first emitter opening 1302. The emitter dielectric spacer 1402a narrows the first emitter opening 1302 to form a second emitter opening 1502. Furthermore, residual dielectric spacers 1402b remain on the vertical surface of the third dielectric spacer layer 1206a. For example, the anisotropic etching can be a re-etching process (RIE).

[0039] refer to Figure 16 An emitter layer 1602 is formed above the base layer 1102 (e.g., on a single-crystal base layer 1102a). The emitter layer 1602 comprises a single-crystal emitter layer 1602a and a polycrystalline emitter layer 1602b. The single-crystal emitter layer 1602a and the polycrystalline emitter layer 1602b together form the emitter layer 1602. In some instances, the emitter layer 1602 is or comprises a semiconductor layer doped with an n-type dopant (e.g., a dopant type opposite to that of the base layer 1102). In some instances, the emitter layer 1602 is or comprises silicon. In some instances, the emitter layer 1602 uses a dopant concentration of 1 × 10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3The emitter layer 1602 is doped with an n-type dopant within the specified range. The emitter layer 1602 can be epitaxially grown on the base layer 1102 (e.g., a single-crystal base layer 1102a), emitter dielectric spacer 1402a, and third dielectric spacer layer 1206a, which are exposed through the second emitter opening 1502. In some embodiments, the emitter layer 1602 can be epitaxially grown using a non-selective epitaxial growth process. This non-selective epitaxial growth process grows a single-crystal emitter layer 1602a from the single-crystal base layer 1102a and a polycrystalline emitter layer 1602b on other amorphous or polycrystalline surfaces (e.g., emitter dielectric spacer 1402a and third dielectric spacer layer 1206a). The single-crystal emitter layer 1602a may be adjacent to the polycrystalline emitter layer 1602b at a small facet not specifically shown. The emitter layer 1602 is non-selectively deposited on the third dielectric spacer layer 1206a both inside and outside the opening 602 to form the emitter layer 1602. The emitter layer 1602 can be doped in situ during the epitaxial growth process. The epitaxial growth process can be a CVD process, such as LPCVD, RPCVD, MOCVD, etc. Other materials, dopant types, dopant concentrations, and / or deposition processes can be implemented.

[0040] refer to Figure 17 An emitter dielectric capping layer 1702 is conformally formed above the emitter layer 1602. In some instances, the emitter dielectric capping layer 1702 is silicon oxide (e.g., TEOS oxide) deposited by CVD, but in other instances other dielectric materials and / or other deposition processes may be used.

[0041] refer to Figure 18 The emitter dielectric capping layer 1702, the polycrystalline emitter layer 1602b, the third dielectric spacer layer 1206a, and the second dielectric spacer layer 1204a are etched to form the emitter dielectric capping layer 1702a, the polycrystalline emitter layer 1602c, the third dielectric spacer 1206b, and the second dielectric spacer 1204b in the opening 602. Layers 1702, 1602b, 1206a, and 1204a can be etched using appropriate photolithography and etching processes. For example, anisotropic etching, such as RIE, can be implemented.

[0042] refer to Figure 19 An emitter dielectric protective spacer layer 1902 is conformally formed above the emitter dielectric capping layer 1702a and the second dielectric spacer layer 1204a and along the sidewalls of the emitter dielectric capping layer 1702a, the polycrystalline emitter layer 1602c, the third dielectric spacer 1206b, and the second dielectric spacer 1204b. In some instances, the emitter dielectric protective spacer layer 1902 is silicon oxide (e.g., TEOS oxide) deposited by CVD, but in other instances other dielectric materials and / or other deposition processes may be used.

[0043] refer to Figure 20 The emitter dielectric protective spacer layer 1902 is anisotropically etched to form emitter dielectric protective spacer 1902a along the sidewalls of the emitter dielectric cap layer 1702a, the polycrystalline emitter layer 1602c, the third dielectric spacer 1206b, and the second dielectric spacer 1204b. The emitter dielectric protective spacer 1902a protects the sidewalls of the polycrystalline emitter layer 1602c. Furthermore, residual dielectric spacer 1902b remains on the vertical surface of the first dielectric spacer layer 1202a. For example, the anisotropic etching can be a re-etching process (RIE).

[0044] refer to Figure 21 The first dielectric spacer layer 1202a is removed. The first dielectric spacer layer 1202a can be removed by masking (e.g., using photolithography through photoresist) the emitter dielectric cap layer 1702a and the emitter dielectric protection spacer 1902a and performing a selective wet etching of the first dielectric spacer layer 1202a. For example, when the first dielectric spacer layer 1202a is silicon oxide, it can be removed using dilute hydrochloric acid (dHCl). The wet etching can undercut the mask to remove the first dielectric spacer layer 1202a located beneath the emitter dielectric protection spacer 1902a and the second dielectric spacer 1204b. Furthermore, when the emitter dielectric protection spacer 1902a is made of the same material as the first dielectric spacer layer 1202a, wet etching of the undercut mask can further etch the lower portion of the emitter dielectric protection spacer 1902a, resulting in the emitter dielectric protection spacer 1902c, as shown, for example. Additionally, wet etching can remove residual dielectric spacers 1902b.

[0045] refer to Figure 22 A pull-back etching of the second dielectric spacer 1204b is performed. The pull-back etching pulls the second dielectric spacer 1204b back, creating a second dielectric spacer 1204c laterally away from the single-crystal emitter layer 1602a below the third dielectric spacer 1206b. As shown subsequently, the removal of the first dielectric spacer layer 1202a and the pull-back etching forming the second dielectric spacer 1204c open (e.g., expose) a region on the base layer 1102 near the single-crystal emitter layer 1602a where a raised base layer can be formed. The pull-back etching can be a wet etching selectively applied to the material of the second dielectric spacer 1204b. For example, when the second dielectric spacer 1204b is silicon nitride, the wet etching may include phosphoric acid.

[0046] refer to Figure 23A raised base layer 2302 is formed above the base layer 1102. The raised base layer 2302 comprises at least one polycrystalline raised base layer on the polycrystalline base layer 1102b. The raised base layer 2302 may comprise a single-crystal raised base layer. If the single-crystal base layer 1102a is exposed by removing the first dielectric spacer layer 1202a and pulling back etching to form the second dielectric spacer 1204c, then the raised base layer 2302 may comprise a single-crystal portion on the single-crystal base layer 1102a. In some instances, the raised base layer 2302 is or comprises a semiconductor layer doped with a p-type dopant (e.g., the same type of dopant as the base layer 1102). In some instances, the raised base layer 2302 is or comprises silicon. In some instances, the raised base layer 2302 is doped with a concentration of 1×10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 The p-type dopant within the specified range is used for doping. The raised base layer 2302 can be epitaxially grown on the base layer 1102. In some examples, the raised base layer 2302 can be epitaxially grown using a selective epitaxial growth process. The selective deposition of the raised base layer 2302 conformally forms the raised base layer 2302 on the crystalline (e.g., polycrystalline and single-crystal) surface both inside and outside the opening 602 (e.g., on the base layer 1102). Furthermore, the raised base layer 2302 can be in-situ doped during the epitaxial growth process (e.g., a selective epitaxial growth process). The epitaxial growth process can be a CVD process, such as LPCVD, RPCVD, MOCVD, etc. Other materials, dopant types, dopant concentrations, and / or deposition processes can be implemented.

[0047] refer to Figure 24 A dielectric protective layer 2402 is formed conformally over and along the emitter dielectric capping layer 1702a, the emitter dielectric protective spacer 1902c, and the raised base layer 2302. In some instances, the dielectric protective layer 2402 is silicon oxide (e.g., TEOS oxide) deposited by CVD, but in other instances other dielectric materials and / or other deposition processes may be used.

[0048] refer to Figure 25The dielectric protective layer 2402, the raised base layer 2302, and the base layer 1102 (e.g., polycrystalline base layer 1102b) are patterned. The raised base layer 2302 and the polycrystalline base layer 1102b are patterned to retain the raised base layer 2302a and the polycrystalline base layer 1102c within the opening 602. The dielectric protective layer 2402, the raised base layer 2302, and the base layer 1102 outside the opening 602 (and more precisely, outside the BJT region 104) are removed by patterning. Therefore, the base layer 1102 and the raised base layer 2302 are removed from the sidewalls 604, 606 of the gate layer 502a and from above the dielectric protective layer 504a. The base dielectric layer 202b extends laterally from the polycrystalline base layer 1102c over the first portion 122a of the isolation structure 122 in the BJT region 104 and over the upper surface 120 of the semiconductor substrate 102. The dielectric protective layer 2402, the raised base layer 2302, and the base layer 1102 can be patterned using appropriate photolithography and etching processes. For example, anisotropic etching, such as RIE, can be implemented.

[0049] A lower thermal budget can be implemented in subsequent processing used to form nFETs and pFETs. When the single-crystal base layer 1102a is a different material from the collector layer 902, a lower thermal budget can mitigate the relaxation of the single-crystal base layer 1102a. A lower thermal budget also mitigates the diffusion of dopants between the collector layer 902, the base layer 1102, and / or the emitter layer 1602. An example of such thermal processing with a lower thermal budget is provided below.

[0050] refer to Figure 26 A hard mask layer 2602 is conformally formed over the dielectric protective layer 504a and the opening 602. The hard mask layer 2602 is conformally formed over the dielectric protective layer 504a, along the sidewalls 604 and 606, and over the base dielectric layer 202a, base layer 1102, raised base layer 2302a, and dielectric protective layer 2402a exposed through the opening 602. In some instances, the hard mask layer 2602 is or comprises silicon nitride deposited by CVD, but in other instances other hard mask (e.g., dielectric) materials and / or other deposition processes may be used.

[0051] refer to Figure 27The gate layer 502a is patterned into gate electrodes 502b and 502c, and the gate dielectric layer 402 is patterned into gate dielectric layers 402a and 402b. A hard mask layer 2602 is patterned corresponding to the patterns of the gate electrodes 502b and 502c, and the patterned hard mask layer 2602 is used as a mask to pattern the gate layer 502a and the gate dielectric layer 402. The hard mask layer 2602 can be patterned using appropriate photolithography and etching processes, and the gate layer 502a and the gate dielectric layer 402 can be patterned using appropriate etching processes. For example, anisotropic etching, such as RIE, can be implemented. The gate electrode 502b is above (e.g., on) the gate dielectric layer 402a in the pFET region 110, and the gate electrode 502c is above (e.g., on) the gate dielectric layer 402b in the nFET region 112. The gate dielectric layer 402 is patterned and removed from the upper surface 120 of the semiconductor substrate 102 in the BJT region 104. Thereafter, the patterned hard mask layer 2602, dielectric protection layer 504a, and dielectric protection layer 2402a are removed, for example by wet etching selectively using the materials of these layers. For instance, when the hard mask layer 2602 is silicon nitride, wet etching containing phosphoric acid can remove the hard mask layer 2602, and when the dielectric protection layers 504a and 2402a are silicon oxide, wet etching containing dilute hydrochloric acid can remove the dielectric protection layers 504a and 2402a.

[0052] Although not shown, a protective oxide layer can be formed on the gate electrodes 502b and 502c after the hard mask layer 2602 and the dielectric protective layer 504a are removed. The protective oxide layer can be formed by an oxidation process (e.g., ISSG). In some instances with lower thermal budgets, the oxidation process can be performed at 750°C or lower for 5 seconds or less.

[0053] refer to Figure 28First gate dielectric spacers 2802a and 2802b are formed along the sidewalls of gate electrodes 502b and 502c. The first gate dielectric spacers 2802a and 2802b can be formed by conformally depositing a material layer of the first gate dielectric spacers 2802a and 2802b over the semiconductor substrate 102 and anisotropically etching the layer to retain the first gate dielectric spacers 2802a and 2802b. The material of the first gate dielectric spacers 2802a and 2802b can be any suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof. The layer can be deposited by CVD, PECVD, atomic layer deposition (ALD), etc. The formation of the first gate dielectric spacers 2802a and 2802b can further form residual dielectric spacers 2802c, 2802d, and 2802e on the sidewalls of the assembly in the BJT region 104. For example, residual dielectric spacer 2802c is on the corresponding sidewall of emitter dielectric protection spacer 1902c; residual dielectric spacer 2802d is formed on the corresponding sidewall of polycrystalline base layer 1102c and raised base layer 2302a; and residual dielectric spacer 2802e is formed on the corresponding sidewall of base dielectric layer 202b.

[0054] refer to Figure 29 In the semiconductor substrate 102, a p-type lightly doped drain region (LDD) 2902 and an n-type LDD 2904 are formed in the pFET region 110 and nFET region 112, respectively. The p-type LDD 2902 is located on the laterally opposite side of the gate electrode 502b in the semiconductor substrate 102, and the n-type LDD 2904 is located on the laterally opposite side of the gate electrode 502c in the semiconductor substrate 102. The p-type LDD 2902 can be formed by masking (e.g., using photolithography through photoresist) the BJT region 104, transition regions 106, 108, and nFET region 112 and implanting p-type dopant into the semiconductor substrate 102 in the pFET region 110. An n-type LDD 2904 can be formed by masking (e.g., using photolithography through photoresist) the BJT region 104, transition regions 106, 108, and pFET region 110 and implanting n-type dopant into the semiconductor substrate 102 in the nFET region 112. The concentration of p-type dopant in the p-type LDD 2902 is greater than the concentration of n-type dopant in the n-type doped well 144, and the concentration of n-type dopant in the n-type LDD 2904 is greater than the concentration of p-type dopant in the p-type doped well 150. In some examples, the p-type LDD 2902 uses a concentration of 1×10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 The p-type dopant within the specified range is used for doping, and the n-type LDD 2904 is doped with a concentration of 1×10⁻⁶. 19 cm-3 Up to 1×10 21 cm -3 Doping can be performed with n-type dopants within the specified range. Other doping concentrations can also be implemented.

[0055] After performing one or more implantations to form p-type LDD 2902 and n-type LDD 2904, activation annealing may be performed. In some instances with lower thermal budgets, activation annealing includes laser annealing after the first implantation (e.g., for n-type or p-type dopant) and spike annealing at a temperature of 930°C or lower after the second implantation (e.g., for the other of n-type or p-type dopant).

[0056] refer to Figure 30 The second gate dielectric spacers 3002a and 3002b are formed along the sidewalls of the first gate dielectric spacers 2802a and 2802b. The second gate dielectric spacers 3002a and 3002b can be formed by conformally depositing a material layer of the second gate dielectric spacers 3002a and 3002b over the semiconductor substrate 102 and anisotropically etching the layer to retain the second gate dielectric spacers 3002a and 3002b. The material of the second gate dielectric spacers 3002a and 3002b can be any suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, etc., or combinations thereof. The layer can be deposited by CVD, PECVD, ALD, etc. The formation of the second gate dielectric spacers 3002a and 3002b can further form residual dielectric spacers 3002c, 3002d, and 3002e on the sidewalls of the assembly in the BJT region 104. For example, residual dielectric spacer 3002c is on the corresponding sidewall of residual dielectric spacer 2802c; residual dielectric spacer 3002d is formed on the corresponding sidewall of residual dielectric spacer 2802d; and residual dielectric spacer 3002e is formed on the corresponding sidewall of residual dielectric spacer 2802e.

[0057] refer to Figure 31An embedded stress source 3102 is formed in the semiconductor substrate 102 within the pFET region 110. To form the embedded stress source 3102, a corresponding groove is formed in the semiconductor substrate 102. To form the groove, a conformal hard mask layer is formed above the semiconductor substrate 102 in the BJT region 104, transition regions 106, 108, and nFET region 112. The conformal hard mask layer can be or contains silicon nitride, silicon oxynitride, or combinations thereof. The conformal hard mask layer can be formed by conformally depositing and patterning the conformal hard mask layer. The conformal hard mask layer can be deposited by CVD, PECVD, ALD, etc. The conformal hard mask layer can be patterned using photolithography and etching processes. Next, a stress source groove is formed in the semiconductor substrate 102 within the pFET region 110. The stress source groove is etched in the semiconductor substrate 102 at the location where the embedded stress source is to be formed. Any suitable etching process can be used to form the stress source groove, and the etching process can be a wet or dry etching process. The etching process can be anisotropic and selective (e.g., preferential etching) on ​​the crystal planes of the semiconductor substrate 102. Next, an embedded stress source 3102 is formed in the stress source trench. The embedded stress source 3102 can be formed using a selective epitaxial growth process. MOCVD, molecular beam epitaxy (MBE), LPCVD, or another epitaxial process can be used to form the embedded stress source 3102. After forming the embedded stress source 3102, the conformal hard mask layer is removed. The conformal hard mask layer can be removed by an etching process selectively etching the material of the conformal hard mask layer; this etching process can be a wet or dry etching process.

[0058] Stress memory technology can be implemented, for example, in nFET region 112. A stress source dielectric layer is formed over the semiconductor substrate 102, gate electrode 502c, and gate dielectric spacers 2802b and 3002b in nFET region 112. The stress source dielectric layer can be or contains silicon nitride or a combination thereof. The stress source dielectric layer can be formed by conformally depositing and patterning the stress source dielectric layer. The stress source dielectric layer can be deposited by CVD, PECVD, ALD, etc. The stress source dielectric layer can be patterned using photolithography and etching processes. An annealing process is performed on the stress source dielectric layer in nFET region 112. The annealing process can be or includes millisecond laser annealing for dopant activation and peak rapid thermal annealing (RTA) with a reduced thermal budget. Peak RTA can last for approximately 1 second at the peak temperature, and the temperature drops rapidly to minimize dopant diffusion. The annealing process allows the lattice structure of the semiconductor substrate 102 to conform due to the stress induced by the stress source dielectric layer. After the annealing process, the stress source dielectric layer is removed. This can be done by a selective etching process, either wet or dry, that selectively etches the material of the stress source dielectric layer.

[0059] refer to Figure 32An n-type collector contact region 3202, an n-type source / drain (NSD) region 3204, and a p-type source / drain (PSD) region are formed in a semiconductor substrate 102. The n-type collector contact region 3202 is formed in a BJT region 104 within an n-type doped sub-collector diffusion region 146 in the semiconductor substrate 102. The n-type collector contact region 3202 is laterally located between the base dielectric layer 202b and the second portion 122b of the isolation structure 122. The NSD region 3204 is formed in an nFET region 112 within a p-type doped well 150 in the semiconductor substrate 102. The NSD region 3204 has an n-type LDD 2904 on the opposite lateral side of the gate electrode 502c. The PSD region is formed in the pFET region 110 and may be formed in an embedded stress source 3102 and / or may further extend below the embedded stress source 3102 into an n-type doped well 144 in the semiconductor substrate 102. The PSD region is located on the opposite lateral side of the gate electrode 502b, with a p-type LDD 2902 in between.

[0060] Implantation is performed to form an n-type collector contact region 3202 and an NSD region 3204. The n-type collector contact region 3202 and the NSD region 3204 can be formed by masking (e.g., using photolithography through photoresist) the base layer 1102, the raised base layer 2302a, and the emitter layer 1602 in the pFET region 110 and the BJT region 104, and implanting n-type dopants into the semiconductor substrate 102 in the nFET region 112 and the exposed portions of the BJT region 104. Implantation is then performed to form a PSD region. The PSD region can be formed by masking (e.g., using photolithography through photoresist) the BJT region 104 and the nFET region 112, and implanting p-type dopants into the semiconductor substrate 102 in the pFET region 110.

[0061] The concentration of n-type dopant in the n-type collector contact region 3202 is greater than the concentration of n-type dopant in the n-type doped sub-collector diffusion region 146. The concentration of n-type dopant in the NSD region 3204 is greater than the concentration of n-type dopant in the n-type LDD 2904 and the concentration of p-type dopant in the p-type doped well 150. The concentration of p-type dopant in the PSD region is greater than the concentration of p-type dopant in the p-type LDD 2902 and the concentration of n-type dopant in the n-type doped well 144. In some examples, the n-type collector contact region 3202 and the NSD region 3204 are equipped with a concentration of 1×10⁻⁶. 20 cm -3 Up to 1×10 21 cm -3 Doping is performed using n-type dopants within the specified range, and the PSD region is doped with a concentration of 1×10⁻⁶. 20 cm -3 Up to 1×10 21 cm -3Doping can be performed with p-type dopants within the specified range. Other doping concentrations can also be implemented.

[0062] After implantation to form the n-type collector contact region 3202, NSD region 3204, and PSD region, activation annealing may be performed. In some instances with a lower thermal budget, activation annealing includes laser annealing after the first implantation (e.g., for n-type or p-type dopants) and spike annealing at a temperature of 1,010 °C or lower after the second implantation (e.g., for the other of n-type or p-type dopants).

[0063] refer to Figure 33 The residual dielectric spacers 2802c to 2802e and 3002c to 3002e can be removed. The residual dielectric spacers 2802c to 2802e and 3002c to 3002e can be removed by masking (e.g., using photolithography through photoresist) the pFET region 110 and nFET region 112 and performing selective etching of the residual dielectric spacers 2802c to 2802e and 3002c to 3002e, said etching can be a wet or dry etching process.

[0064] refer to Figure 34 The emitter dielectric capping layer 1702a is removed. This can be done by masking (e.g., using photolithography through photoresist) the remainder of the BJT region 104 and transition regions 106, 108, pFET region 110, and nFET region 112 and performing selective etching of the emitter dielectric capping layer 1702a. In some instances where the emitter dielectric capping layer 1702a and the emitter dielectric protection spacer 1902c are the same material, removing the emitter dielectric capping layer 1702a may also involve etching the emitter dielectric protection spacer 1902c to form the emitter dielectric protection spacer 1902d.

[0065] refer to Figure 35Metal semiconductor compounds 3502, 3504, 3506, 3508, 3512, 3514, 3516, and 3518 are formed. Metal semiconductor compound 3502 is on the emitter layer 1602 (e.g., a polycrystalline emitter layer 1602c and / or a single-crystal emitter layer 1602a). Metal semiconductor compound 3504 is on the raised base layer 2302a. Metal semiconductor compound 3506 is on the upper surface 120 of the semiconductor substrate 102 at the n-type collector contact region 3202. Metal semiconductor compound 3508 is on the upper surface 120 of the semiconductor substrate 102 at the p-type doped well 148. Metal semiconductor compound 3512 is on the embedded stress source 3102. Metal semiconductor compound 3514 is on the NSD region 3204 in the semiconductor substrate 102. Metal semiconductor compounds 3516 and 3518 are located on gate electrodes 502b and 502c, respectively. Metal semiconductor compounds 3502, 3504, 3506, 3508, 3512, 3514, 3516, and 3518 can be silicides (e.g., NiSix, TiSix, CoSix, PtSix), germanides, etc.

[0066] The metal-semiconductor compounds 3502, 3504, 3506, 3508, 3512, 3514, 3516, and 3518 can be formed by depositing metals (e.g., Ni, Ti, Co, Pt) over the semiconductor substrate 102, for example, by physical vapor deposition (PVD), CVD, etc. The metal is reacted with a semiconductor material, such as the semiconductor material of the emitter layer 1602 (e.g., a polycrystalline emitter layer 1602c and / or a single-crystal emitter layer 1602a), the semiconductor material of the raised base layer 2302a, the semiconductor material of the semiconductor substrate 102, the semiconductor material of the embedded stress source 3102, and the semiconductor material of the gate electrodes 502b and 502c (e.g., silicon, such as polycrystalline silicon). An annealing process can be used to react the metal with the semiconductor material. For example, laser annealing (e.g., millisecond laser annealing) can be used in embodiments with reduced thermal budgets. Any unreacted metal can be removed, for example, by selective etching of the metal.

[0067] refer to Figure 36A dielectric layer 3602 is formed above a semiconductor substrate 102, and contacts 3612, 3614, 3616, 3618, 3622, and 3624 are formed through the dielectric layer 3602. The dielectric layer 3602 may include one or more dielectric layers. For example, the dielectric layer 3602 may include a conformal first dielectric layer above the semiconductor substrate 102 and a second dielectric layer above the first dielectric layer. The conformal first dielectric layer may be a stress source layer, an etch stop layer, etc., and may be or include silicon nitride, silicon oxynitride, etc., or combinations thereof. The second dielectric layer may be or include silicon oxide, silicon nitride, etc. The dielectric layer 3602 may be or include a pre-metal dielectric (PMD), an interlayer dielectric (ILD), etc. The dielectric layer 3602 may be deposited using CVD, PECVD, ALD, etc. The dielectric layer 3602 may be planarized, for example, by CMP.

[0068] Contacts 3612, 3614, 3616, 3618, 3622, and 3624 extend through dielectric layer 3602 and contact the corresponding metal semiconductor compounds 3502, 3504, 3506, 3508, 3512, and 3514. Contacts 3612, 3614, 3616, 3618, 3622, and 3624 may each comprise one or more barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof) conformally located in the corresponding openings through dielectric layer 3602, and a filler metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc., or combinations thereof) above and / or on the one or more barrier and / or adhesion layers.

[0069] To form contacts 3612, 3614, 3616, 3618, 3622, and 3624, appropriate photolithography and etching processes can be used to form corresponding openings through the dielectric layer 3602 to the metal semiconductor compounds 3502, 3504, 3506, 3508, 3512, and 3514. One or more metals of contacts 3612, 3614, 3616, 3618, 3622, and 3624 are deposited in the openings through the dielectric layer 3602. One or more metals can be deposited using one or more appropriate deposition processes, such as CVD and PVD. Any excess metal can be removed, for example, by CMP and / or by patterning using photolithography and etching processes.

[0070] Figures 37 to 43 These are cross-sectional views of semiconductor devices at intermediate manufacturing stages, based on some examples. (As described above...) Figure 11 The semiconductor processing continues as described.

[0071] refer to Figure 37A first dielectric spacer layer 3702 is conformally formed over the base layer 1102, and a second dielectric spacer layer 3704 is conformally formed over the first dielectric spacer layer 3702. In some examples, the second dielectric spacer layer 3704 is a different dielectric material than the first dielectric spacer layer 3702. In some examples, the first dielectric spacer layer 3702 is silicon oxide (e.g., TEOS oxide), and the second dielectric spacer layer 3704 is silicon nitride. The dielectric spacer layers 3702 and 3704 can be deposited by CVD. In other examples, other dielectric materials and / or other deposition processes can be used.

[0072] refer to Figure 38 The dielectric spacer layers 3702 and 3704 are etched to form an emitter opening 3802 through the first dielectric spacer layer 3702a and the second dielectric spacer layer 3704a. The dielectric spacer layers 3702 and 3704 are etched through the opening 3802 to form the emitter opening 3802. The single-crystal base layer 1102a (of the base layer 1102) is exposed through the emitter opening 3802. The emitter opening 3802 is located in the BJT region 104. The dielectric spacer layers 3702 and 3704 can be etched using appropriate photolithography and etching processes. For example, anisotropic etching, such as RIE, can be implemented.

[0073] refer to Figure 39 An emitter layer 1602 is formed above the base layer 1102 (e.g., on a single-crystal base layer 1102a), as per [the relevant information]. Figure 16 As described. The emitter layer 1602 may be epitaxially grown on the base layer 1102 (e.g., a single-crystal base layer 1102a) exposed through the emitter opening 3802 and on the second dielectric spacer layer 3704a. Reference Figure 40 The emitter dielectric capping layer 1702 is conformally formed above the emitter layer 1602, as per [the relevant information]. Figure 17 As described.

[0074] refer to Figure 41 The emitter dielectric capping layer 1702, the polycrystalline emitter layer 1602b, and the second dielectric spacer layer 3704a are etched to form the emitter dielectric capping layer 1702a, the polycrystalline emitter layer 1602c, and the second dielectric spacer 3704b in the opening 602. Layers 1702, 1602b, and 3704a can be etched using appropriate photolithography and etching processes. For example, anisotropic etching, such as RIE, can be implemented.

[0075] refer to Figure 42The first dielectric spacer layer 3702a and the base layer 1102 (e.g., a polycrystalline base layer 1102b) are patterned. The polycrystalline base layer 1102b is patterned to remain as a polycrystalline base layer 1102c within the opening 602. Similarly, the first dielectric spacer layer 3702a is patterned to remain as a first dielectric spacer layer 3702b within the opening 602. The first dielectric spacer layer 3702a and the base layer 1102 outside the opening 602 (and more precisely, outside the BJT region 104) are removed by patterning. Thus, the base layer 1102 is removed from the sidewalls 604, 606 of the gate layer 502a and from above the dielectric protective layer 504a. The base dielectric layer 202b extends laterally from the polycrystalline base layer 1102c over the first portion 122a of the isolation structure 122 in the BJT region 104 and also extends laterally from the polycrystalline base layer 1102c over the upper surface 120 of the semiconductor substrate 102 in the BJT region 104. The first dielectric spacer layer 3702a and the base layer 1102 can be patterned using appropriate photolithography and etching processes. For example, anisotropic etching, such as RIE, can be implemented.

[0076] refer to Figure 43 As mentioned above Figures 26 to 36 As described above, semiconductor processing continues. (This is in contrast to the previous section regarding...) Figure 35 The metal-semiconductor compound 3504 is formed on a base layer 1102 (e.g., a polycrystalline base layer 1102c). The deposited metal reacts with the semiconductor material of the base layer 1102 (e.g., the polycrystalline base layer 1102c).

[0077] Figure 36 and 43 The corresponding semiconductor devices 3600 and 4300 are shown. Each of the shown semiconductor devices 3600 and 4300 includes a BJT in a BJT region 104. The BJT includes a collector layer 902, a base layer 1102 (e.g., a monocrystalline base layer 1102a and a polycrystalline base layer 1102c) and an emitter layer 1602 (e.g., a monocrystalline emitter layer 1602a and a polycrystalline emitter layer 1602b). Figure 36 The BJT of the semiconductor device 3600 also includes a raised base layer 2302a on the base layer 1102 (e.g., on the polycrystalline base layer 1102c).

[0078] The collector layer 902 is above and over the upper surface 120 of the semiconductor substrate 102 and extends through an opening in the base dielectric layer 202b, which is also above and over the upper surface of the semiconductor substrate 102. The collector layer 902 is on the n-type doped sub-collector diffusion region 146 in the semiconductor substrate 102. The base layer 1102 (e.g., a single-crystal base layer 1102a) is above and over the collector layer 902, and the base layer 1102 (e.g., a polycrystalline base layer 1102c) is above and over the upper surface of the base dielectric layer 202b. The base dielectric layer 202b extends laterally from the base layer 1102, for example, in the lateral direction from the base layer 1102 toward the n-type collector contact region 3202, above and along the upper surface 120 of the semiconductor substrate 102, and along the first portion 122a of the isolation structure 122.

[0079] Emitter layer 1602 (e.g., monocrystalline emitter layer 1602a) is above and over base layer 1102 (e.g., monocrystalline base layer 1102a) and passes through the opening defined by the spacer structure, and emitter layer 1602 (e.g., polycrystalline emitter layer 1602c) is above and over the spacer structure. Figure 36 In the semiconductor device 3600, the spacer structure includes a second dielectric spacer 1204c, a third dielectric spacer 1206b, and an emitter dielectric spacer 1402a. Figure 43 In the semiconductor device 4300, the spacer structure includes a first dielectric spacer 3702c and a second dielectric spacer 3704b.

[0080] Metal-semiconductor compound 3502 is on the emitter layer 1602 (e.g., a polycrystalline emitter layer 1602c and / or a monocrystalline emitter layer 1602a). Metal-semiconductor compound 3506 is on the upper surface 120 of the semiconductor substrate 102 on the n-type collector contact region 3202. Figure 36 In the semiconductor device 3600, a metal semiconductor compound 3504 is disposed on a raised base layer 2302a. Figure 43 In the semiconductor device 4300, the metal semiconductor compound 3504 is on the base layer 1102 (e.g., polycrystalline base layer 1102c).

[0081] In some instances, the BJT can be a heterojunction BJT. As previously indicated, in some instances, the collector layer 902 and emitter layer 1602 can be silicon, and the base layer 1102 can comprise silicon germanium. Therefore, in some instances, the base layer 1102 can comprise a semiconductor material different from the corresponding semiconductor materials of the collector layer 902 and emitter layer 1602. Different semiconductor materials can form one or more heterojunctions in the BJT, and thus, the BJT can be a heterojunction BJT.

[0082] Each of the illustrated semiconductor devices 3600, 4300 includes a pFET in pFET region 110 and an nFET in nFET region 112. pFET region 110 and nFET region 112 are located within a CFET region. The pFET includes a gate electrode 502b, a gate dielectric layer 402a, an embedded stress source 3102, a PSD region, a p-type LDD 2902, and a channel region in the semiconductor substrate 102 below the gate electrode 502b. The gate electrode 502b is above and over the gate dielectric layer 402a, and the gate dielectric layer 402a is above and over the upper surface 120 of the semiconductor substrate 102. The p-type LDD 2902 is located on the laterally opposite side of the gate electrode 502b and within the semiconductor substrate 102. The channel region is laterally located between the p-type LDDs 2902. An embedded stress source 3102 and a PSD region are located on laterally opposite sides of the gate electrode 502b, with a p-type LDD 2902 and a channel region between them. Similarly, an nFET includes a gate electrode 502c, a gate dielectric layer 402b, an NSD region 3204, an n-type LDD 2904, and a channel region in a semiconductor substrate 102 below the gate electrode 502c. The gate electrode 502c is above and over the gate dielectric layer 402b, and the gate dielectric layer 402b is above and over the upper surface 120 of the semiconductor substrate 102. The n-type LDD 2904 is located on the laterally opposite sides of the gate electrode 502c and in the semiconductor substrate 102. The channel region is laterally located between the n-type LDDs 2904. The NSD region 3204 is located on the laterally opposite sides of the gate electrode 502c, with an n-type LDD 2904 and a channel region between them. pFET and nFET can be complementary devices (e.g., complementary metal-oxide-semiconductor (CMOS) devices). In some instances, pFET can be a p-type metal-oxide-semiconductor (PMOS) transistor, and nFET can be an n-type metal-oxide-semiconductor (NMOS) transistor.

[0083] The first transition region 106 lies between the BJT region 104 and the CFET region (e.g., in the illustrated example, the CFET region has the boundary of the pFET region 110). As per [reference to...] Figure 27 As described, gate layer 502a is patterned into gate electrodes 502b and 502c, such that gate layer 502a is removed from BJT region 104 and first transition region 106. Therefore, the BJT region 104, which extends laterally through the first transition region 106 from the sidewall 304 of base dielectric layer 202b, does not contain material for the gate electrodes 502b and 502c of pFETs and nFETs. Similarly, as per [reference to...] Figure 25 and 42As described, the base layer 1102 and (where appropriate) the raised base layer 2302 are removed from the sidewall 304 of the base dielectric layer 202b in the BJT region 104 that traverses laterally through the first transition region 106. Therefore, the BJT region 104 that traverses laterally through the sidewall 304 of the base dielectric layer 202b through the first transition region 106 does not contain the corresponding material of the base layer 1102 and the raised base layer 2302.

[0084] Used to form Figure 36 and 43 The semiconductor fabrication of the semiconductor devices 3600 and 4300 allows for both vertical and horizontal scaling. In some examples, for vertical scaling, the thicknesses of the collector layer 902, base layer 1102, and emitter layer 1602 can be reduced. In some examples, the thickness of the collector layer 902 does not exceed 200 nm, and the thickness of the base layer 1102 (e.g., a single-crystal base layer 1102a) does not exceed 100 nm. Furthermore, in some examples, the thickness of the collector layer 902 is in the range of 10 nm to 100 nm, and the thickness of the base layer 1102 (e.g., a single-crystal base layer 1102a) is in the range of 10 nm to 50 nm. Furthermore, in some examples, the thickness of the emitter layer 1602 (e.g., a single-crystal emitter layer 1602a) does not exceed 100 nm. In some examples, the thickness of the emitter layer 1602 (e.g., a single-crystal emitter layer 1602a) is in the range of 10 nm to 50 nm. Generally, the thickness of a given layer is in the direction perpendicular to the tangential plane of the underlying surface on which the given layer is formed. However, in some cases, such as in conformal deposition, the direction perpendicular to the tangential plane of the underlying surface may not be the thickness, for example, when the thickness from another tangential plane intersects the normal of the direction, for example, at a corner.

[0085] For horizontal scaling, the width of the respective openings in which the collector layer 902 and emitter layer 1602 (e.g., a single-crystal emitter layer 1602a) are formed can be reduced. The width of the collector opening 802 in which the collector layer 902 is formed can be reduced, and the width of the emitter openings 1502 and 3802 in which the single-crystal emitter layer 1602a is formed can be reduced. The semiconductor processing described above can achieve horizontal scaling to, for example, 28 nm technology nodes and larger technology nodes (e.g., 21 nm technology nodes or smaller technology nodes). Figure 44 Describing Formation Figure 36 and 43 The layout of BJT components in semiconductor devices 3600 and 4300. In particular, Figure 44 The lateral boundary of the base dielectric layer 202b is shown. The collector layer 902 is shown to be laterally located inside the base dielectric layer 202b, and the arrangement of the collector layer 902 corresponds to... Figure 8The collector opening 802 is shown. The collector layer 902 (and further, the collector opening 802) has a width of 4402. The arrangement of the base layer 1102 (e.g., a polycrystalline base layer 1102c) relative to the collector layer 902 is shown. Figure 15 and 38 The emitter openings 1502 and 3802 shown are relative to the base layer 1102 and the collector layer 902, and have a width 4404. An emitter layer 1602 (e.g., a single-crystal emitter layer 1602a) is formed in the emitter openings 1502 and 3802. One or both of the widths 4402 and 4404 can be reduced to achieve horizontal scaling. In some instances, the width 4402 does not exceed 200 nm, and the width 4404 does not exceed 120 nm. Furthermore, in some instances, the width 4402 is in the range of 80 nm to 180 nm, and the width 4404 is in the range of 40 nm to 100 nm.

[0086] Figure 36 and 43 The BJTs in the semiconductor devices 3600 and 4300 may have improved characteristics compared to other BJTs. The BJTs in the semiconductor devices 3600 and 4300 may have lower base resistance, lower collector resistance, and lower parasitic capacitance (e.g., including base-collector capacitance and collector-substrate capacitance). Furthermore, Figure 36 The BJT of the 3600 semiconductor device can have even lower base resistance. Figure 36 and 43 The BJTs in the semiconductor devices 3600 and 4300 can further have higher operating frequencies. For example, in some instances, Figure 36 The BJT in the semiconductor device 3600 has a maximum unity current gain frequency (ft_peak) of 608 GHz, and Figure 43 The BJT in the semiconductor device 4300 has a peak ft_peak of 614 GHz. Furthermore, in some instances, Figure 36 The BJT in the semiconductor device 3600 has a maximum power gain frequency (fmax_peak) of 768 GHz, and Figure 43 The BJT in the semiconductor device 4300 has an fmax_peak of 670 GHz.

[0087] The semiconductor fabrication described above contributes to improved characteristics. Shallow implantation forming a narrower n-type doped sub-collector diffusion region 146 contributes to collector-substrate capacitance. A narrower active region of semiconductor substrate 102 (e.g., between portions 122a, 122b of isolation structure 122) reduces base-collector capacitance, which increases fmax_peak. Selective epitaxial growth of collector layer 902 reduces collector resistance, which increases ft_peak. High doping concentration and selective epitaxial growth of bumped base layer 2302a reduce base resistance, which further increases fmax_peak and reduces noise figure of merit (NF). A thinner emitter layer 1602 contributes to reduced emitter resistance, which further increases ft_peak and fmax_peak. However, a narrower width 4404 of emitter layer 1602 contributes to increased emitter resistance, which may result in a decrease in emitter-base capacitance and base resistance. The response of ft_peak to the narrower width 4404 of the emitter layer 1602 can depend on other process conditions. When the emitter layer 1602 is narrower, the reduced base resistance can have a sufficiently large effect to increase fmax_peak. In instances where nickel (Ni) is used as the metal in the metal-semiconductor compound 3502, the emitter resistance can be reduced, which can further increase ft_peak. Furthermore, implementing a lower thermal budget (e.g., by incorporating laser annealing) can reduce dopant diffusion and increase dopant activation, which can reduce base resistance and increase both ft_peak and fmax_peak.

[0088] Within the scope of the claims, modifications to the described instances are possible, and other instances are also possible.

Claims

1. A semiconductor device comprising: A semiconductor substrate containing a bipolar junction transistor region; A base dielectric layer, which is located in the bipolar junction transistor region and above the upper surface of the semiconductor substrate; A collector layer that is located on the upper surface of the semiconductor substrate and extends through the base dielectric layer; A base layer, which is located on the upper surface of the collector layer and the base dielectric layer, the base dielectric layer extending laterally from the base layer above the upper surface of the semiconductor substrate; and The emitter layer is located on the base layer.

2. The semiconductor device of claim 1, wherein the semiconductor substrate comprises: The collector layer is located on the doped sub-collector diffusion region; and The doped collector contact region is located in the doped sub-collector diffusion region, in which at least a portion of the base dielectric layer is laterally located between the collector layer and the doped collector contact region.

3. The semiconductor device of claim 1, wherein the base layer comprises a material different from the material of the collector layer and the material of the emitter layer.

4. The semiconductor device according to claim 3, wherein: The material of the base layer comprises silicon germanium; The material of the current collector layer is silicon; and The material of the emitter layer is silicon.

5. The semiconductor device of claim 1, further comprising a raised base layer on the base layer.

6. The semiconductor device according to claim 5, further comprising: Base metal semiconductor compound on the raised base layer; and Emitter metal semiconductor compound on the emitter layer.

7. The semiconductor device according to claim 1, further comprising: Base metal semiconductor compound on the base layer; and Emitter metal semiconductor compound on the emitter layer.

8. The semiconductor device according to claim 1, wherein: The semiconductor substrate further includes a complementary field-effect transistor (CFET) region; The CFET region includes p-type field-effect transistors (PFETs) and n-type field-effect transistors (NFETs); and The region laterally located between the CFET region and the sidewall of the base dielectric layer is not included in the material of the gate electrode of the PFET or the gate electrode of the NFET above the upper surface of the semiconductor substrate.

9. The semiconductor device according to claim 1, wherein: The thickness of the current collector layer does not exceed 200 nm; and The thickness of the base layer does not exceed 100 nm.

10. The semiconductor device according to claim 9, wherein: The thickness of the current collector layer is in the range of 10 nm to 100 nm; and The thickness of the base layer is in the range of 10 nm to 50 nm.

11. A method comprising: A gate layer is formed above the semiconductor substrate; A first opening is formed in the bipolar junction transistor (BJT) region, passing through the gate layer; A collector layer is formed in the first opening and on the upper surface of the semiconductor substrate; A base layer is formed on the current collector layer; An emitter layer is formed on the base layer; and After the emitter layer is formed, the gate layer is patterned as the gate electrode of a transistor in the complementary field-effect transistor (CFET) region of the semiconductor substrate.

12. The method of claim 11, wherein after the gate layer is patterned as the gate electrode of the transistor, a portion of the gate layer is not retained in a region laterally located between the CFET region and the sidewall of the collector layer.

13. The method of claim 11, further comprising: A base dielectric layer is formed above the upper surface of the semiconductor substrate, and the first opening extends through the gate layer to the base dielectric layer; and A second opening is formed through the first opening, extending through the base dielectric layer to the upper surface of the semiconductor substrate, and the collector layer is formed in the second opening.

14. The method of claim 13, wherein the base layer is further formed on the base dielectric layer.

15. The method of claim 11, further comprising: After the emitter layer is formed, a raised base layer is formed on the base layer.

16. The method of claim 15, further comprising reacting the metal with the semiconductor material of the raised base layer.

17. The method of claim 11, further comprising reacting the metal with the semiconductor material of the base layer.

18. The method of claim 11, wherein the base layer comprises a material different from the material of the collector layer and the material of the emitter layer.

19. The method according to claim 11, wherein: The thickness of the current collector layer does not exceed 200 nm; and The thickness of the base layer does not exceed 100 nm.

20. A method comprising: A base dielectric layer is formed above the semiconductor substrate in the bipolar junction transistor region; A gate layer is formed above the semiconductor substrate and above the base dielectric layer; A first opening is formed through the gate layer to reach the base dielectric layer, wherein the sidewall of the gate layer defining the first opening is above the base dielectric layer; A second opening is formed through the first opening, extending through the base dielectric layer to the upper surface of the semiconductor substrate; A collector layer is formed in the second opening and on the upper surface of the semiconductor substrate through the first opening; A base layer is formed on the current collector layer through the first opening; An emitter layer is formed on the base layer through the first opening; and The gate layer is patterned into a first gate electrode of a p-type transistor and a second gate electrode of an n-type transistor, the p-type transistor and the n-type transistor being located in a complementary field-effect transistor (CFET) region of the semiconductor substrate.

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