Monolithic rgb micro-led array

Abstract

A light emitting diode (LED) pixel array and a method of manufacturing the same. A semiconductor wafer template includes a continuous stack of a first n-GaN layer, a first MQW layer, a p-GaN layer, and a dielectric layer. A plurality of openings are formed through the dielectric layer, extending to the p-GaN layer. A plurality of mesas are formed by forming, within each opening, a second MQW layer, and a second n-GaN layer over each second MQW layer. The second n-GaN layer and the second MQW layer of each mesa form a respective mesa LED with the p-GaN layer. The first n-GaN layer and the first MQW layer form a lower LED with the p-GaN layer.

Description

Priority Statement

[0001] This application claims the priority of U.S. Provisional Application Serial No. 63 / 596,150, filed November 3, 2023, and U.S. Patent Application Serial No. 18 / 921,819, filed October 21, 2024, each of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates generally to the manufacture of light-emitting diodes (LEDs), and more specifically to the manufacture of monolithic red micro-LED / green micro-LED / blue micro-LED pixel arrays. Background Technology

[0003] III-nitride LEDs grown at the micrometer scale are called micro-LEDs, or simply micro-LEDs, micro-LEDs, or μLEDs. Typically, μLEDs have a diameter of 50 micrometers or less. μLEDs are expected to provide the foundation for next-generation displays and visible light communication (VLC) applications. Compared to organic light-emitting diodes (OLEDs) and liquid crystal displays (LCDs), III-nitride μLEDs exhibit several unique characteristics for display applications. Unlike LCDs, III-nitride micro-displays using μLEDs are self-emitting. Monochrome displays using μLEDs typically exhibit high resolution, high efficiency, and high contrast. OLEDs typically operate at current densities several orders of magnitude lower than semiconductor LEDs to maintain a reasonable lifetime. Therefore, the brightness of OLEDs is lower than that of III-nitride μLEDs. Furthermore, compared to OLEDs, III-nitride μLEDs inherently exhibit longer operating lifetimes and chemical robustness. Therefore, it is anticipated that in the near future, III-nitride μLEDs may potentially replace LCDs and OLEDs in a wide range of applications, such as smartphones, for high-resolution and high-brightness displays. Attached Figure Description

[0004] In accompanying drawings that are not necessarily drawn to scale, the same reference numerals may describe similar parts in different views. To facilitate identification of any particular element or action being discussed, one or more of the highest-ranking digits in the reference numerals indicate the drawing number in which that element was first introduced. Some non-limiting examples are shown in the figures below:

[0005] Figure 1 An example method for manufacturing an LED pixel array is shown, based on some examples.

[0006] Figure 2 A cross-sectional view of a first example semiconductor wafer template is shown, based on some examples.

[0007] Figure 3 The following is illustrated, according to some examples, after the first LED pixel array manufacturing operation. Figure 2 A cross-sectional view of a semiconductor wafer template.

[0008] Figure 4 The following are examples of LED pixel array manufacturing operations. Figure 2 A cross-sectional view of a semiconductor wafer template.

[0009] Figure 5 Four different orientations of surfaces formed by a hexagonal crystal structure are shown, based on some examples.

[0010] Figure 6 The following are examples of LED pixel array manufacturing operations. Figure 2 A cross-sectional view of a semiconductor wafer template.

[0011] Figure 7 The following are examples of LED pixel array manufacturing operations. Figure 2 A cross-sectional view of a semiconductor wafer template.

[0012] Figure 8 The following are examples of LED pixel array manufacturing operations. Figure 2 A cross-sectional view of a semiconductor wafer template.

[0013] Figure 9 The illustration shows, according to some examples, the subsequent LED pixel array manufacturing operations used to form the first example LED pixel array. Figure 2 A cross-sectional view of a semiconductor wafer template.

[0014] Figure 10 The following are examples of the basis. Figure 9 A top view of the LED pixel structure. Detailed Implementation

[0015] Examples of this disclosure provide monolithic red-green-blue (RGB) LED pixels, LED pixel arrays, and methods for manufacturing the same. In some examples, the LED pixel structure (e.g., a micro-LED pixel structure) can be fabricated using a semiconductor wafer template to include a first multiple quantum well (MQW) layer and one or more mesa formed above the first MQW layer. The first MQW layer can be configured as part of an LED to emit a single color of light, such as blue light, or the LED can be configured to be tunable between two colors of light, such as a tunable blue LED / green LED. Each mesa provides additional LEDs, such as red LEDs or tunable red LEDs / green LEDs. The LED pixel structure can be formed using wafer-level epitaxial and etching techniques to create an array of LED pixel structures.

[0016] Therefore, some of the examples described herein attempt to address one or more technical problems in the fabrication of micro-LEDs. By using epitaxial growth to fabricate monolithic multicolor micro-LED arrays at the wafer level, some examples can avoid the need to stack and bond multiple wafers. Additionally, some examples can avoid damage to the sidewalls of micro-LEDs typically caused by etching in conventional micro-LED fabrication methods, potentially improving LED performance.

[0017] As used herein, the “color” of an LED, multi-quantum-well stack, or other light-emitting component can refer to the dominant or center wavelength of the light emitted by the component. The wavelength of light emitted by a given LED can be controlled using various techniques, such as controlling the size of the LED, and / or the structure, material composition, and / or size of the multi-quantum-well stack of the LED.

[0018] Some examples described herein can utilize tunable multicolor LEDs, such as red / green or blue / green LEDs. Tunable multicolor LEDs can be fabricated using various techniques: for example, blue-green light emission from a blue LED / green LED or red-green light emission from a red LED / green LED can be achieved by utilizing a blue shift phenomenon caused by band-filling and piezoelectric shielding effects. In examples using group III nitride LEDs, this blue shift phenomenon is unavoidable but can be reduced by optimizing the LED epitaxial structure. For example, more quantum well (QW) layers can be grown to reduce the carrier density between each QW, V-shaped pits can be formed on the MQW surface to increase the uniformity of current injection into each QW, and / or the strain on the MQW can be reduced to decrease the piezoelectric field. However, the tunable LEDs described herein can utilize the blue shift phenomenon to modulate the wavelength of the emitted light by modulating the current injection, such that an increase in the injection current shifts the light wavelength toward a shorter (bluer) wavelength.

[0019] As used herein, terms such as “above,” “below,” “upper,” “lower,” and other terms referring to relatively vertical positions are intended to denote the relative positions of various features with respect to a reference frame in which a surface perpendicular to the substrate surface used in semiconductor fabrication (e.g., a crystal substrate surface) defines an upward direction. It will be understood that portions of the fabricated semiconductor device remote from the substrate surface are referred to as “above” those portions closer to the substrate surface, even though the semiconductor device may be fabricated in contact with the substrate surface in any orientation relative to the Earth’s gravitational field or any other reference frame, and even though the semiconductor device may be used in any orientation after fabrication.

[0020] Other technical features and / or benefits will be readily apparent to those skilled in the art from the accompanying drawings, description and claims.

[0021] Figure 1 An example method 100 for manufacturing an LED pixel array is shown. Although the example method 100 depicts a specific sequence of operations, this sequence can be changed without departing from the scope of this disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not substantially affect the functionality of method 100. In other examples, different components of the example apparatus or system implementing method 100 may perform their functions substantially simultaneously or in a specific order.

[0022] Refer to the example LED pixel structure (for example, see below) Figure 9 The example method 100 is described in connection with the fabrication of the pixel structure 900. It will be understood that in other examples, method 100 may be performed to fabricate devices with structures or properties different from the example pixels and pixel arrays described herein. In some examples, the operation of method 100 may be performed at the wafer level to form a micro-LED pixel array, such that thousands or millions of LED pixel structures are simultaneously formed within the wafer. Wafer-level deposition techniques such as metal-organic chemical vapor deposition (MOCVD) may be used to perform epitaxial or overgrowth operations and other deposition operations, and selective etching operations may be performed using photolithography combined with wafer-level or at least multi-pixel-level wet or dry etching. In some examples, wet etching may be used only in etching operations contacting p-GaN material or MQW stacks to prevent damage to the p-GaN structure caused by dry etching.

[0023] The following reference is provided. Figures 2 to 9 The example method 100 is described by way of example LED pixel array fabrication operations performed on the first example semiconductor wafer template 200. It will be understood that in other examples, method 100 may be performed using operations different from the example operations and structures shown and described.

[0024] According to some examples, method 100 includes obtaining a semiconductor wafer template at operation 102. In some examples, operation 102 includes up to four sub-operations: sub-operation 104, sub-operation 106, sub-operation 108, and / or sub-operation 110. See below for reference. Figure 2 Describe an example semiconductor wafer template.

[0025] Figure 2 A cross-sectional view of a first example semiconductor wafer template 200 is shown. In some examples, the semiconductor wafer template 200 is obtained in a pre-fabricated form as a laminated structure of continuously stacked layers: a first n-GaN layer 206, a first MQW layer 208, a p-GaN layer 210, and a dielectric layer 212. In some examples, the semiconductor wafer template 200 is formed (or further formed) by a sequence of one or more sub-operations of operation 102: sub-operation 104, sub-operation 106, sub-operation 108, and / or sub-operation 110.

[0026] According to some examples, operation 102 of method 100 includes growing a first n-GaN layer 206 on a substrate at sub-operation 104. In some examples, the substrate is a substrate layer 202 suitable for semiconductor growth. In some examples, the substrate also includes a buffer, such as an undoped gallium nitride layer (shown as a u-GaN buffer layer 204), grown above the substrate layer 202.

[0027] According to some examples, operation 102 of method 100 includes growing a first MQW layer 208 on the first n-GaN layer 206 at sub-operation 106. In some examples, the first MQW layer 208 is a multi-quantum-well stack optimized or configured to emit light of a single specific color, such as a blue MQW layer configured to emit blue light. In some examples, the first MQW layer 208 is a tunable multi-quantum-well stack configured to be tunable between the emission of two colors of light, such as a blue MQW layer / green MQW layer configured to be tunable between blue and green light.

[0028] According to some examples, operation 102 of method 100 includes growing a p-GaN layer 210 above the first MQW layer 208 at sub-operation 108. When stimulated by an electrical signal delivered via a p-contact formed on the p-GaN layer 210 and an n-contact formed on the first n-GaN layer 206, the p-GaN layer 210, the first MQW layer 208, and the first n-GaN layer 206 together form a first LED, such as a blue LED or a tunable blue-green LED, as shown below. Figure 9 As described.

[0029] According to some examples, operation 102 of method 100 includes forming a dielectric layer 212 over the p-GaN layer 210 at sub-operation 110. The dielectric layer 212 may be formed of a suitable dielectric material such as an oxide like SiO2.

[0030] According to some examples, method 100 includes forming an opening 302 through dielectric layer 212 at operation 112 (e.g. Figure 3 (As depicted). In some examples, the aperture 302 is formed by selective etching using photolithography.

[0031] Figure 3 A cross-sectional view of the semiconductor wafer template 200 after operation 112 is shown. The opening 302 can be formed by etching (e.g., wet etching) through the dielectric layer 212 to the p-GaN layer 210. In some examples, such as the one shown, two openings 302 can be formed at operation 112 to form two mesa, as described below. However, it will be understood that the techniques described herein can be adapted, with appropriate modifications, to LED pixel structures comprising one mesa or two or more mesa.

[0032] According to some examples, method 100 includes growing a second MQW layer 402 in each opening 302 at operation 114 (in Figure 4 (As depicted in the text). In some examples, the second MQW layer 402 can be formed through selective MOCVD overgrowth.

[0033] Figure 4 A cross-sectional view of the semiconductor wafer template 200 after operation 114 is shown. In the example shown, two second MQW layers 402 are grown in two openings 302 (not labeled). In some examples, both second MQW layers 402 are configured to emit the same color to form a red LED or a tunable red / green LED. In other examples, the two second MQW layers 402 are configured differently: for example, one second MQW layer 402 may be configured to form a red LED, while the other second MQW layer 402 is configured to form a green LED.

[0034] Each second MQW layer 402 forms the base of a mesa 404 within the aperture 302. The sidewalls of the mesa can be formed as a semi-polar surface of the GaN material used to form the second MQW layer 402, as shown below. Figure 5 As described.

[0035] In some cases, a second n-GaN layer 602 is grown on top of the p-GaN layer 210 (in Figure 7(As depicted in the diagram) challenges may exist. If the semiconductor wafer template 200 is formed in the same growth chamber used for operation 114, surface cleaning of the top surface of the p-GaN layer 210 may be required before further overgrowth over the p-GaN layer 210. Surface cleaning removes magnesium and / or other materials used during p-GaN growth that pose a risk of contaminating the second n-GaN layer 602, resulting in a vertical doping gradient from p-type to n-type doping within the second n-GaN layer 602 as magnesium is depleted during the overgrowth process of operation 114. In some examples, the surface of the semiconductor wafer template 200 is cleaned after the dielectric layer 212 is formed over the p-GaN layer 210 as part of the process to complete the fabrication of the semiconductor wafer template 200.

[0036] Figure 5 Four different orientations of the surface formed by the hexagonal crystal structure 502 of GaN material are shown. The hexagonal crystal structure 502 shown represents GaN and its various related ternary compounds such as indium gallium nitride (InGaN) and aluminum gallium nitride (AlGaN), all of which can be referred to herein as GaN materials.

[0037] The hexagonal crystal structure 502 of the GaN material defines several surface orientations that can be formed through the material. A polar (c-plane) surface 504 (also called the (0001) surface) defines a horizontal plane orientation perpendicular to the c-vector 512. A semi-polar surface 506 (also called the (10-11) surface) defines an oblique plane orientation in which the plane intersects the top centerline of the hexagonal crystal structure 502 and one of the two bottom edges of the hexagonal crystal structure 502 parallel to the top centerline. A non-polar (m-plane) surface 508 (also called the (10-10) surface) defines a vertical plane orientation coplanar with one of the six sides of the hexagonal crystal structure 502. A non-polar (a-plane) surface 510 (also called the (11-20) surface) defines another vertical plane orientation extending from two non-adjacent top vertices of the hexagonal crystal structure 502 and parallel to the c-vector 612 that contacts the two corresponding bottom vertices. The radial direction of the hexagonal crystal structure 502 is specified by vectors a1 514, a2 516, and a3 518.

[0038] therefore, Figure 4 and Figure 6 The sidewalls of the mesa 404 shown can be formed by a second MQW layer 402 (and a second n-GaN layer 602, hereinafter referred to) Figure 6 The hexagonal crystal structure 502 (described) has a semi-polar surface 506 that extends obliquely from the top of the mesa. Specifically, the semi-polar surface 506 forms a 62° angle with the horizontal plane. Therefore, in some examples, the sidewalls of the mesa 404 may be tilted at a 62° angle.

[0039] According to some examples, method 100 includes growing a second n-GaN layer 602 on top of each second MQW layer 402 at operation 116. In some examples, the second n-GaN layer 602 can be formed by selective MOCVD overgrowth.

[0040] Figure 6 A cross-sectional view of the semiconductor wafer template 200 after operation 116 is shown. A second n-GaN layer 602 forms the top of each mesa 404. The sidewalls of each mesa 404 may continue to be aligned with the semi-polar surface 506 of the GaN material of the second n-GaN layer 602, for example, at a 62° angle to the surface of the p-GaN layer 210.

[0041] According to some examples, method 100 includes removing a portion of dielectric layer 212 at operation 118 to expose a portion of p-GaN layer 210. In some examples, this portion of dielectric layer 212 can be removed by selective etching using photolithography (e.g., wet etching).

[0042] Figure 7 A cross-sectional view of the semiconductor wafer template 200 after operation 118 is shown. The dielectric layer 212 between the two mesa 404 has been removed to provide a first exposed portion 702 of the p-GaN layer 210. The dielectric layer 212 to the right of the second mesa 404 has been removed to provide a second exposed portion 704 of the p-GaN layer 210.

[0043] In some examples, in the first iteration of operation 118, only the first exposed portion 702 is removed. This is followed by the deposition of the p-contact portion 904 at operation 120 (see below). Figure 9 (Description) During the second iteration of operation 118, the p-contact 904 is masked (e.g., photolithographic masking) to selectively remove the second exposed portion 704.

[0044] According to some examples, method 100 includes etching at operation 120 through a portion of the p-GaN layer 210 and a portion of the first MQW layer 208 to expose a portion of the first n-GaN layer 206. As in operations 112 and 118, wet etching may be used to prevent damage to the p-GaN layer 210, the first MQW layer 208, and / or the second MQW layer 402. In some examples, dry etching may be used instead of wet etching, or in addition to wet etching, to maintain the straight edges of the etched openings and the dimensions of the openings at the layers beneath them.

[0045] Figure 8A cross-sectional view of the semiconductor wafer template 200 after operation 120 is shown. Wet etching can be used to etch through the portion located on the right side of the figure, passing through the p-GaN layer 210 and the first MQW layer 208, exposing the exposed portion 802 of the first n-GaN layer 206. In some examples, as described above, dry etching can be used instead of wet etching or in addition to wet etching to maintain the straight edges of the etched openings and the dimensions of the openings in the layers beneath them.

[0046] As described above, in some examples, operation 120 occurs only at the p contact 904 (see below). Figure 9 (Description) This is performed after the first exposed portion 702 of the p-GaN layer 210 has been deposited and masked to protect the p-contact 904 from damage from the etching step of operation 120.

[0047] According to some examples, method 100 includes forming a p-contact 904 on the exposed p-GaN layer 210 (e.g., on a first exposed portion 702 of the p-GaN layer 210) at operation 122. The p-contact 904 is a p-type electrical contact.

[0048] According to some examples, method 100 includes forming an n-contact 902 above each second n-GaN layer 602 at operation 124. The n-contact 902 is an n-type electrical contact.

[0049] According to some examples, method 100 includes forming additional n-contacts 902 on the exposed portion (e.g., exposed portion 802) of the first n-GaN layer 206 at operation 126.

[0050] Figure 9 The following are shown: operations 122, 124, and 126 Figure 2 A cross-sectional view of the semiconductor wafer template. n-contacts 902 have been deposited on the top of each mesa above the second n-GaN layer 602, and on the exposed portion 802 (not shown) of the first n-GaN layer 206. p-contacts 904 have been deposited on the first exposed portion 702 (not shown) of the p-GaN layer 210.

[0051] In some examples, the n-contact 902 may be formed of a suitable conductive material for forming electrical contacts on the n-GaN material, such as aluminum or an aluminum-containing compound or alloy. In some examples, the p-contact 904 may be formed of a suitable conductive material for forming electrical contacts on the p-GaN material, such as a transparent conductive oxide like indium tin oxide (ITO).

[0052] In the final pixel structure 900, the second n-GaN layer 602 and the second MQW layer 402 of each mesa form a corresponding mesa LED 906 with the p-GaN layer 210. The mesa LED 906 is activated by a p-contact 904 and an n-contact 902 formed on the top of the mesa. The first n-GaN layer 206 and the first MQW layer 208 form a lower LED 908 with the p-GaN layer 210. The lower LED 908 is activated by a p-contact 904 and an n-contact 902 formed on the first n-GaN layer 206.

[0053] Figure 10 It shows including Figure 9 A top view of a 900-tile LED pixel array with multiple tiled pixel structures. Figure 9 The cross-sectional view can be considered as passing through Figure 10 The view of section line AA shown.

[0054] In the example LED pixel array layout shown, each mesa 404 has six sidewalls defining a generally hexagonal shape for each mesa 404. Each second n-GaN layer 602 and the second MQW layer 402 are hexagonal. The mesa 404 are arranged to form a honeycomb or hexagonal grid layout. Therefore, a pair of mesa 404 can be considered as forming a single pixel structure 900, as shown by the dashed outline.

[0055] What will be understood is... Figure 10 The layout shown may constitute only a small part of the entire LED pixel array, which in some examples may include hundreds, thousands or millions of pixel structures 900.

[0056] In some examples, different top-view shapes can be used for mesa 404, and / or mesa 404 can be laid out in different patterns. However, the hexagonal crystal structure 502 of the second n-GaN layer 602 and the second MQW layer 402 can facilitate the formation of mesa 404 with a hexagonal shape, such as... Figure 10 As shown in the figure.

[0057] In some examples, the various structures shown and described herein have dimensions configured to form microLED pixels. In a first example, the first n-GaN layer 206 has a thickness approximately between several hundred nanometers (nm) and several (e.g., less than ten) micrometers (µm). The first MQW layer 208 has a thickness approximately between 10 nm and several hundred nm. The p-GaN layer 210 has a thickness approximately between 50 nm and several hundred nm. The mesa height depends on the total thickness of the MOCVD overgrowth, and therefore ranges approximately from 100 nm to several (e.g., < 10) micrometers. The mesa width and pixel pitch can be selected according to the desired pixels per inch (PPI) specification of the pixel array; in various examples, the mesa width can range from tens of nm to hundreds of micrometers.

[0058] in conclusion

[0059] This article describes LED pixel arrays and their manufacturing methods with reference to various examples.

[0060] Example 1 is a method for fabricating a light-emitting diode (LED) pixel array from a semiconductor wafer template, the semiconductor wafer template comprising a first n-type gallium nitride (n-GaN) layer, a first multiple quantum well (MQW) layer, a p-type gallium nitride (p-GaN) layer, and a dielectric layer stacked sequentially, the method comprising: forming a plurality of openings through the dielectric layer and extending to the p-GaN layer; and forming a plurality of mesas by forming the following layers in each opening: a second MQW layer; and a second n-GaN layer above each second MQW layer, such that: the second n-GaN layer and the second MQW layer of each mesas form a corresponding mesas LED with the p-GaN layer; and the first n-GaN layer and the first MQW layer form a lower LED with the p-GaN layer.

[0061] In Example 2, the subject of Example 1 includes: removing a portion of the dielectric layer to expose a portion of the p-GaN layer; and forming a p-type electrical contact on the exposed portion of the p-GaN layer.

[0062] In Example 3, the subject of Example 2 includes, wherein: the p-type electrical contact comprises a transparent conductive oxide.

[0063] In Example 4, the subject matter of Examples 1 to 3 includes: etching through the dielectric layer, the p-GaN layer, and the first MQW layer to expose a portion of the first n-GaN layer; and forming an n-type electrical contact on the exposed portion of the first n-GaN layer.

[0064] In Example 5, the subject of Example 4 includes, wherein: the n-type electrical contact comprises aluminum.

[0065] In Example 6, the subject of Examples 1 to 5 includes: forming n-type electrical contacts on the second n-GaN layer of each mesa.

[0066] In Example 7, the subject matter of Examples 1 to 6 includes: removing a portion of the dielectric layer to expose a portion of the p-GaN layer; forming a p-type electrical contact on the exposed portion of the p-GaN layer; masking the p-type electrical contact; etching through the dielectric layer, the p-GaN layer, and the first MQW layer to expose a portion of the first n-GaN layer; forming an n-type electrical contact on the exposed portion of the first n-GaN layer; and forming an n-type electrical contact on the second n-GaN layer of each mesa.

[0067] In Example 8, the subject matter of Examples 1 to 7 includes, wherein: each mesa has sidewalls formed at an angle defined by the semi-polar surface of the crystal structure of the second MQW layer and the second n-GaN layer.

[0068] In Example 9, the subject matter of Examples 1 through 8 includes, where: the lower LED is a blue LED.

[0069] In Example 10, the subject of Example 9 includes the following: each tabletop LED is a tunable red LED / green LED.

[0070] In Example 11, the subject matter of Examples 9 and 10 includes: the tabletop LED includes at least one red LED and at least one green LED.

[0071] In Example 12, the subject matter of Examples 1 to 11 includes: the lower LED is a tunable blue LED / green LED; and each tabletop LED is a red LED.

[0072] In Example 13, the subject matter of Examples 1 to 12 includes, wherein: the semiconductor wafer template further includes a continuously stacked substrate layer and an undoped gallium nitride (u-GaN) layer below the first n-GaN layer.

[0073] In Example 14, the subject of Example 13 includes forming a semiconductor wafer template by means of the following steps: epitaxially forming a u-GaN layer on a substrate layer; epitaxially forming a first n-GaN layer on the u-GaN layer; epitaxially forming a first MQW layer over the first n-GaN layer; epitaxially forming a p-GaN layer over the first MQW layer; and epitaxially forming a dielectric layer over the p-GaN layer.

[0074] In Example 15, the subject matter of Examples 1 to 14 includes, wherein: each tabletop has six sidewalls defining the approximate hexagonal shape of each tabletop.

[0075] Example 16 is a pixel array formed according to the method of Example 1.

[0076] Example 17 is a light-emitting diode (LED) pixel array comprising a plurality of LED pixel structures, each LED pixel structure comprising: a lower LED comprising a first n-GaN layer, a first MQW layer and a p-GaN layer stacked sequentially; and a plurality of mesas formed above the p-GaN layer, each mesas defining a corresponding mesas LED comprising a second MQW layer between the p-GaN layer and the second N-GaN layer.

[0077] In Example 18, the subject matter of Example 17 includes, wherein each LED pixel structure further includes: a p-type electrical contact formed on a portion of the p-GaN layer; an n-type electrical contact formed on an exposed portion of the first n-GaN layer; and an n-type electrical contact formed on a second n-GaN layer on each mesa.

[0078] In Example 19, the subject matter of Examples 17 and 18 includes the following: the lower LED is a tunable blue LED / green LED; and each tabletop LED is a red LED.

[0079] In Example 20, the subject matter of Examples 17 to 19 includes, where: the lower LED is a blue LED; and each tabletop LED is a tunable red / green LED.

[0080] Example 21 is at least one machine-readable medium including instructions that, when executed by a processing circuitry system, cause the processing circuitry system to perform operations to implement any one of Examples 1 to 20.

[0081] Example 22 is an apparatus that includes means for implementing any one of Examples 1 to 20.

[0082] Example 23 is a system for implementing any one of Examples 1 through 20.

[0083] Example 24 is a method for implementing any one of Examples 1 through 20.

[0084] Other technical features and / or benefits will be readily apparent to those skilled in the art from the accompanying drawings, descriptions and claims herein.

Claims

1. A method for fabricating a light-emitting diode (LED) pixel array from a semiconductor wafer template, said semiconductor wafer template comprising a first n-type gallium nitride (n-GaN) layer, a first multiple quantum well (MQW) layer, a p-type gallium nitride (p-GaN) layer, and a dielectric layer stacked sequentially, said method comprising: Multiple openings are formed that penetrate the dielectric layer and extend to the p-GaN layer; as well as Multiple platform surfaces are formed by creating the following layers within each opening: Second MQW layer; as well as The second n-GaN layer above each second MQW layer, Make: The second n-GaN layer and the second MQW layer of each mesa form a corresponding mesa LED with the p-GaN layer; and The first n-GaN layer and the first MQW layer together with the p-GaN layer form the lower LED.

2. The method according to claim 1, further comprising: Remove a portion of the dielectric layer to expose a portion of the p-GaN layer; as well as A p-type electrical contact is formed on the exposed portion of the p-GaN layer.

3. The method according to claim 2, wherein: The p-type electrical contact comprises a transparent conductive oxide.

4. The method according to claim 1, further comprising: Etching through the dielectric layer, the p-GaN layer, and the first MQW layer to expose a portion of the first n-GaN layer; as well as An n-type electrical contact is formed on the exposed portion of the first n-GaN layer.

5. The method according to claim 4, wherein: The n-type electrical contact comprises aluminum.

6. The method according to claim 1, further comprising: An n-type electrical contact is formed on the second n-GaN layer of each mesa.

7. The method according to claim 1, further comprising: Remove a portion of the dielectric layer to expose a portion of the p-GaN layer; A p-type electrical contact is formed on the exposed portion of the p-GaN layer; The p-type electrical contact portion is shielded; Etching through the dielectric layer, the p-GaN layer, and the first MQW layer to expose a portion of the first n-GaN layer; An n-type electrical contact is formed on the exposed portion of the first n-GaN layer; as well as An n-type electrical contact is formed on the second n-GaN layer of each mesa.

8. The method according to claim 1, wherein: Each mesa has sidewalls formed at an angle defined by the semi-polar surfaces of the crystal structure of the second MQW layer and the second n-GaN layer.

9. The method according to claim 1, wherein: The lower LED is a blue LED.

10. The method according to claim 9, wherein: Each tabletop LED is a tunable red / green LED.

11. The method according to claim 9, wherein: The tabletop LED includes at least one red LED and at least one green LED.

12. The method according to claim 1, wherein: The lower LED is a tunable blue / green LED; and Each LED on the tabletop is a red LED.

13. The method according to claim 1, wherein: The semiconductor wafer template further includes a continuously stacked substrate layer and an undoped gallium nitride (u-GaN) layer below the first n-GaN layer.

14. The method of claim 13, further comprising forming the semiconductor wafer template by the following step: The u-GaN layer is epitaxially formed on the substrate layer; The first n-GaN layer is epitaxially formed on the u-GaN layer; The first MQW layer is epitaxially formed above the first n-GaN layer; The p-GaN layer is epitaxially formed above the first MQW layer; and The dielectric layer is epitaxially formed above the p-GaN layer.

15. The method according to claim 1, wherein: Each countertop has six sidewalls, defining the approximate hexagonal shape of each countertop.

16. A pixel array formed by the method according to claim 1.

17. A light-emitting diode (LED) pixel array, comprising a plurality of LED pixel structures, each LED pixel structure comprising: The lower LED comprises a first n-GaN layer, a first MQW layer, and a p-GaN layer that are stacked sequentially. as well as Multiple mesas are formed above the p-GaN layer, each mesas defining a corresponding mesas LED, the mesas LED being included in a second MQW layer between the p-GaN layer and the second N-GaN layer.

18. The pixel array according to claim 17, wherein, Each LED pixel structure also includes: A p-type electrical contact is formed on a portion of the p-GaN layer; n-type electrical contacts formed on the exposed portion of the first n-GaN layer; and n-type electrical contacts are formed on the second n-GaN layer of each mesa.

19. The pixel array according to claim 17, wherein: The lower LED is a tunable blue / green LED; and Each LED on the tabletop is a red LED.

20. The pixel array according to claim 17, wherein: The lower LED is a blue LED; as well as Each tabletop LED is a tunable red / green LED.

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