Methods of fabricating semiconductor devices by forming and removing epitaxial (EPI) structures on engineered substrates

Abstract

A method for fabricating a semiconductor device includes providing an engineered substrate (ES) [40] having a core [12], an engineered layer (ELY) [44] on the core [12], and a lattice-matched layer (LML) [46] on the engineered layer (ELY) [44]. The method also includes providing a plurality of epitaxial (EPI) layers [42] on the engineered substrate (ES) [40]. The method also includes forming a plurality of device epitaxial (EPI) structures [54] separated by vias [58] in the epitaxial (EPI) layers [42], forming a plurality of connecting metal layers (C-MLs) [62] connecting the device epitaxial (EPI) structures [54], and removing the core [12] of the engineered substrate [40], leaving new device structures [70] connected by the connecting metal layers (C-MLs) [62]. The method can also include attaching a temporary substrate [68], such as a UV release substrate, to the device epitaxial (EPI) structures [54], and performing additional fabrication steps.

Description

Cross-references to related applications

[0001] This application claims priority to U.S. Patent Application Serial No. 18 / 937,127, filed November 5, 2024, which claims the benefit of U.S. Provisional Application No. 63 / 599,041, filed November 15, 2023, both of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the manufacture of semiconductor devices, and more particularly to a method for manufacturing semiconductor devices and removing epitaxial structures from an engineered substrate.

[0003] Device fabrication systems have been developed capable of manufacturing high-performance devices, such as power devices, RF devices, and high-brightness light-emitting diodes (LEDs). These systems utilize pre-fabricated engineered substrates with standard thicknesses, dimensions, and shapes. Engineered substrates are made from materials that form the basis of growth or fabrication processes for various semiconductor structures. Engineered substrates can be purchased from substrate manufacturers, and device epitaxial layers (EPIs) can be deposited on the substrates by wafer fabs or device manufacturers. Engineered substrates allow the use of high-quality semiconductor materials in applications that were previously impossible and provide improved performance and reliability compared to conventional substrates. For example, engineered substrates are marketed by Qromis Corporation of Santa Clara, California, under the trademark QST® (QROMIS Substrate Technology).

[0004] like Figure 1A and Figure 1B As shown, the exemplary engineered substrate (ES) 10 includes a CTE-matched core 12 having engineered layers 14, 16 on its opposite sides. The CTE-matched core 12 may include a core material with high thermal conductivity and high mechanical strength, having a coefficient of thermal expansion that closely matches the coefficient of thermal expansion of the device epitaxial layer over a wide temperature range. The engineered substrate (ES) 10 also includes an engineered layer (ELY) 18, such as SiO2, and a Si layer 20 formed on the engineered layer (ELY) 18.

[0005] Figure 2A and Figure 2B An epitaxial layer (EPI) 22 is illustrated on a Si (111) layer 20 formed on an engineered substrate (ES) 10. For example... Figure 2BAs shown, the epitaxial (EPI) layer 22 includes an AlN layer 24, a u-GaN layer 26, a 1500 nm n-GaN layer 28, a 5000 nm n-GaN layer 30, a p-GaN layer 32, and an n-GaN layer 34. The epitaxial (EPI) layer 22 can be fabricated using suitable deposition and growth processes known in the art. For example, a metal-organic chemical vapor deposition (MOCVD) reactor can be used to form the epitaxial (EPI) layer 22.

[0006] In the fabrication of various semiconductor devices, such as power devices, RF devices, and optoelectronic devices such as lasers or LEDs (LS), it is advantageous to have an independent epitaxial (EPI) layer 22 by removing the epitaxial (EPI) layer 22 from the engineered substrate (ES); thus, by recycling the engineered substrate (ES) 10 for further EPI growth, vertical devices can have better electrical, thermal, and reliability performance as well as lower costs.

[0007] This disclosure relates to a method for fabricating a semiconductor device by forming an epitaxial (EPI) structure and then removing the epitaxial structure from an engineered substrate (ES). Summary of the Invention

[0008] A method for manufacturing a semiconductor device includes the steps of: providing an engineered substrate (ES) and providing a plurality of epitaxial (EPI) layers on the engineered substrate (ES). The method further includes the step of: forming a plurality of device epitaxial (EPI) structures separated by a pattern of vias in the epitaxial (EPI) layers. In an exemplary embodiment, the device epitaxial (EPI) structures include epitaxial (EPI) structure islands (EPI-ISLs). The device epitaxial (EPI) structures may, as needed, include integrated circuits, such as transistors, power driver devices, and other devices. The method further includes the step of: forming a plurality of interconnect metal layers (C-MLs) connecting the device epitaxial (EPI) structures. The method further includes the step of: removing the device epitaxial (EPI) structures still connected by the interconnect metal layers (C-MLs) from the engineered substrate (ES). The method may also include the steps of: attaching a temporary substrate to the device epitaxial (EPI) structures and performing additional manufacturing steps, such as the formation of device contacts and / or metal interconnects.

[0009] In an exemplary embodiment, the engineered substrate (ES) includes a CTE-matched core, an engineered layer (ELY) on the core, and a lattice-matched layer (LML) on the engineered layer (ELY) configured to facilitate epitaxial (EPI) growth. Exemplary materials for the engineered layer (ELY) include Si, Al, C, and N, and combinations thereof. Exemplary materials for the lattice-matched layer (LML) include Si, C, GaN, Al2O3, AlN, and SiC. The engineered layer (ELY) is engineered together with the CTE-matched core such that the CTE of the engineered substrate (ES) closely matches the CTE of the epitaxial (EPI) layer. For example, it is desirable that the CTE of the engineered substrate (ES) at the epitaxial (EPI) deposition temperature is within + / - 25% of the CTE of the epitaxial (EPI) layer.

[0010] In an exemplary embodiment, the method includes the steps of: forming a metal layer with selectively patterned openings on an epitaxial (EPI) layer; using the openings in the metal layer to define a plurality of epitaxial structure (EPI-ISL) islands; forming a connection metal layer (C-ML) on the epitaxial (EPI) structure islands (EPI-ISL), thereby leaving the plurality of selectively patterned openings; and using the openings in the connection metal layer (C-ML) to remove portions of an insulating layer. In an exemplary embodiment, the connection metal layer (C-ML) is formed on the metal layer. In an alternative embodiment, the step of forming the epitaxial structure (EPI-ISL) islands includes etching the epitaxial (EPI) layer, and the connection metal layer (C-ML) is formed directly on the device epitaxial (EPI) structure. The method further includes the step of removing the epitaxial (EPI) structure islands (EPI-ISL) still connected by the connection metal layer (C-ML) from the core of the engineered substrate (ES), thereby leaving a new device structure. Attached Figure Description

[0011] The accompanying diagrams are schematic in nature and may not be drawn to scale.

[0012] Figure 1A This is a schematic cross-sectional view of an existing engineered substrate (ES). Figure 1B It is along Figure 1A Enlarged schematic perspective view of the engineered substrate (ES) taken from section line 1B-1B; Figure 2A This is a schematic side view of a prior art epitaxial (EPI) layer on an engineered substrate (ES); Figure 2B This is a schematic cross-sectional view of a prior art epitaxial (EPI) layer on an engineered substrate (ES); Figure 3AThis is a schematic cross-sectional view illustrating the steps of providing an engineered substrate (ES) and providing an epitaxial (EPI) layer on the engineered substrate (ES); Figure 3B This is a schematic cross-sectional view illustrating the steps of depositing contact metal on the upper surface of an epitaxial (EPI) layer; Figure 3C This is a schematic cross-sectional view illustrating the steps of forming a metal layer on a contact metal having a selected patterned opening; Figure 3D This is a schematic cross-sectional view illustrating the steps of forming multiple device epitaxial (EPI) structures separated by pathways in an epitaxial (EPI) layer; Figure 3E This is a schematic plan view of the engineered substrate (ES) after the step of forming the device epitaxial (EPI) structure; Figure 3F It is along Figure 3E The section line taken from 3F Figure 3E The enlarged portion illustrates a device epitaxial (EPI) structure separated by pathways; Figure 3G This is a schematic cross-sectional view illustrating the steps of forming multiple interconnect metal layers (C-ML) of an interconnect device epitaxial (EPI) structure; Figure 3H This is a schematic plan view of the engineered substrate (ES) after the step of forming the interconnecting metal layer (C-ML) with the first pattern; Figure 3I This is a schematic plan view of the engineered substrate (ES) after the step of forming a connecting metal layer (C-ML) with an alternative second pattern; Figure 3J This is a schematic cross-sectional view illustrating a portion of the steps involved in removing the engineered layer (ELY). Figure 3K This is a schematic cross-sectional view illustrating the steps of removing the engineered substrate (ES) from the device epitaxial (EPI) structure; Figure 3L This is a schematic cross-sectional view illustrating the steps of attaching a temporary substrate to a device epitaxial (EPI) structure; Figure 3M-3N This is a schematic diagram illustrating an example of GaN peeling and cracking caused by an excessively thick metal layer; Figure 3O-3P This is a schematic diagram illustrating an example of GaN cracking without optimization of the metal layer; Figure 3Q This is a schematic cross-sectional view illustrating a device epitaxial (EPI) structure on a temporary substrate; Figure 3RThis is a schematic cross-sectional view illustrating a device epitaxial (EPI) structure separated from a temporary substrate; Figure 4A This is a schematic cross-sectional view illustrating an alternative embodiment of an interconnecting metal layer (C-ML) in the form of an elongated strip of interconnecting multiple epitaxial (EPI) structural islands (EPI-ISL); Figure 4B This is a schematic plan view of an alternative embodiment for forming a cross-shaped electrical network, connecting the metal layers (C-ML). Figure 4C This is an alternative implementation of the method, in which the interconnect metal layer (C-ML) is also formed along the sidewall of the device epitaxial (EPI) structure, thereby opening up the remaining via region; Figure 5A This is a schematic cross-sectional view of an alternative embodiment of the exemplary method, wherein a connection metal layer (C-ML) is formed directly on the device epitaxial (EPI) structure. Figure 5B This is a schematic cross-sectional view illustrating the steps of forming a connection metal layer (C-ML) directly on a device epitaxial (EPI) structure; Figure 5C An alternative embodiment of the method is provided, wherein a connecting metal layer (C-ML) is formed along the corner sidewall of the device epitaxial (EPI) structure. Figure 5D This is a schematic plan view of an alternative implementation scheme connecting the metal layer (C-ML); Figures 6A to 6C This is a schematic cross-sectional view illustrating an exemplary manufacturing sequence of the interconnecting metal layer (C-ML); and Figures 7A to 7E This is a schematic cross-sectional view illustrating another exemplary manufacturing sequence of the connecting metal layer (C-ML). Detailed Implementation

[0013] exist Figures 3A to 3R The steps in a method for manufacturing a semiconductor device are illustrated below. (Reference) Figure 3A This illustrates the steps of providing an engineered substrate (ES) 40 and providing an epitaxial (EPI) layer 42 on the engineered substrate (ES) 40. The engineered substrate (ES) 40 can be substantially the same as the engineered substrate 10 previously described for the prior art. Figure 2AThe substrate is configured as described. The engineered substrate (ES) 40 includes an engineered layer (ELY) 44 and a lattice-matched layer (LML) 46 on the engineered layer (ELY) 44. Exemplary elements of the engineered layer (ELY) 44 include O, N, C, and Si. The engineered layer (ELY) 44 may also include oxide or nitride compounds such as SiO2, Si3N4, and Al2O3. The engineered layer (ELY) 44 has engineered properties that make it a suitable material for bonding the lattice-matched layer (LML) 46. Exemplary materials for the lattice-matched layer (LML) 46 include Si, C, SiC, GaN, AlN, AlGaN, InGaN, AlCGaN, and AlSiGaN. These materials have lattice parameters that closely match the lattice parameters of the grown epitaxial (EPI) layer 42. For example, one element of the lattice-matched layer (LML) 46 typically includes similar elements required for the epitaxial growth of the epitaxial (EPI) layer 42, such as Si, Al, C, and Ni. Commercial examples of the engineered substrate (ES) 40 may include QST® substrates manufactured by Qromis, Inc. in Santa Clara, California, with a thickness of 100 μm to 2000 μm. The engineered layer (ELY) 44 may have a thickness of 0.1 μm to 5 μm. The lattice-matched layer (LML) 46 may have a thickness of approximately 0.1 μm to 5 μm. However, it should be understood that these thicknesses and manufacturing methods are exemplary, as other thicknesses and manufacturing methods known in the art may be employed.

[0014] Still referencing Figure 3A Epitaxial layer 42 can be substantially the same as previously described for prior art epitaxial layer 22 ( Figure 2AThe configuration is as described. Exemplary materials for the epitaxial (EPI) layer 42 include Si, C, GaN, AlN, SiC, AlGaN, InGaN, AlCGaN, and AlSiGaN. The epitaxial (EPI) layer 42 can be fabricated using suitable deposition and growth processes known in the art. For example, metal-organic chemical vapor deposition (MOCVD), MBE, and HPCVD can be used to form the epitaxial (EPI) layer 42. Depending on the desired epitaxial structure and the desired electrical performance of the device, various epitaxial layers and structures can be fabricated on the lattice-matched layer (LML) 46. As an example, for a Si IC device, the lattice-matched layer (LML) 46 may comprise a Si epitaxial layer. As another example, for an LED device, the lattice-matched layer (LML) 46 may comprise GaN, AlGaN, InGaN, or AlN. The epitaxial (EPI) layer 42 may comprise at least one of the following elements: Ga, Si, C, Al, and In. Many organometallic compounds (MOs) with CHx can be used in conjunction with nitrogen-containing gases (e.g., NH3, N2) for epitaxial growth. The epitaxial (EPI) layer 42 can also be doped with Al, In, or Si to adjust the band gap in the LED device. The epitaxial (EPI) layer 42 can have a thickness between 1 μm and 50 μm. A single layer of the epitaxial (EPI) layer 42 can have… Figure 2B The thicknesses shown are exemplary. It should be understood that these thicknesses and manufacturing methods are exemplary, as other thicknesses and manufacturing methods known in the art may be employed.

[0015] The engineered substrate (ES) 40 with the layers described above is available as a unit purchased from Shin-Etsu Chemical Industries, Ltd. in Tokyo, Japan, rather than being manufactured from scratch. In addition to producing QST®, Shin-Etsu Chemical Industries, Ltd. also supplies QST® substrates for GaN growth according to customer requirements. Currently, the company sells substrates with diameters of 6" and 8" with a sample 12" substrate available. One advantage of the QST® substrate is its ability to match the desired epitaxial (EPI) structure, such as the coefficient of thermal expansion (CTE) of GaN. This characteristic mitigates warping and cracking issues in the epitaxial (EPI) layer 42, enabling the formation of thick, large-diameter GaN epitaxial layers with excellent quality.

[0016] refer to Figure 3B The method further includes the step of depositing contact metal 48 on the upper surface of epitaxial (EPI) layer 42. For Figure 2B The epitaxial (EPI) layer 22 shown in the figure has a contact metal 48 that can be deposited on the surface of the n-GaN layer 34. Figure 2BThe contact metal 48 can be deposited using a suitable deposition process, such as sputtering, dip coating, or thermal deposition. Exemplary metals for the contact metal 48 include Ni, Cu, Ti, Cr, W, Au, and Pt. The contact metal 48 can be formed as a continuous layer or a stack of different metals, such as a Ti / Cu or TiW / Cu stack. As an alternative, non-metals, such as epoxy resin, silicone resin, or acrylic resin, can be used instead of the aforementioned metals.

[0017] refer to Figure 3C The method further includes the step of forming a metal layer 50 on a contact metal 48 having metal layer openings 52 of a selected pattern. An additive process, such as photolithography, can be used to form the metal layer 50 with the metal layer openings 52, wherein a photomask (not shown) is formed with photomask openings (not shown) corresponding to the selected pattern of the metal layer openings 52 in the metal layer 50. A deposition process, such as chemical vapor deposition (CVD), can then be used to deposit the metal layer 50 into the photomask openings (not shown), followed by removal of the photomask (not shown). For example, the metal layer 50 may include one or more metals, such as Ni, Co, Cu, Ti, Cr, Mo, W, Au, Ag, and Pt. The solid portion of the metal layer 50 is associated with the subsequent device epitaxial (EPI) structure 54. Figure 3D The desired active region alignment is shown in the diagram. Alternatively, non-metallic materials such as epoxy, silicone, or acrylic resins can be used instead of the aforementioned metals. Alternatively, a process can be used to form the metal layer 50 with metal layer openings 52, which may include removing the metal layer 50 to form the openings 52 using conventional metal deposition, photomask, and metal etching. For applications where the metal layer 50 forms good adhesion to the epitaxial (EPI) layer 42, the contact metal 48 will not be necessary or required. However, if an electroplating process is used to form the metal layer 50 (e.g., EP of Cu), the contact metal 48 will be needed to act as a seed layer to form the metal layer 50. In an exemplary process, a patterned photoresist layer (not shown) can be employed, allowing the metal layer 50 to form in openings in the photoresist layer on top of the contact metal 48, which serves as a seed layer during the EP process. After the EP process is completed, the patterned resist layer can be removed together with the contact metal 48 not covered by the metal layer 50 to expose the surface of the EPI layer 42 not covered by the contact metal 48 and the metal layer 50.

[0018] refer to Figure 3DThe method further includes the step of forming a plurality of device epitaxial (EPI) structures 54 having active regions separated by pathways 58 in an epitaxial (EPI) layer 42 using a metal layer 50. This step can be performed by removing a portion of the epitaxial (EPI) layer 42, some or all of the lattice matching layer (LML) 46, and the engineered layer (ELY) 44 using openings in the metal layer 52. Various etching methods can be used to perform this step, including dry etching (e.g., inductively coupled plasma reactive ion etching), laser dicing, sawing, wet etching, water jetting, and vapor-phase HF for oxide etching. These methods can be used individually or in combination. For example, for applications using SiO2 as the engineered layer (ELY) 44, a fluorine-containing gas or liquid can be used to etch the SiO2. Figure 3E As shown, the engineered substrate (ES) 40 can be in the form of a semiconductor wafer. For example... Figure 3F As shown, passage 58 has a cross-shaped pattern. Also, Figure 3F As shown, the device epitaxial (EPI) structure 54 includes an epitaxial (EPI) structure island (EPI-ISL) 60 with a checkerboard pattern polygonal outline separated by passages 58 on four sides.

[0019] refer to Figure 3G , Figure 3H and Figure 3I The method further includes the steps of: forming a plurality of interconnect metal layers (C-ML) 62 of an interconnect device epitaxial (EPI) structure 54; and includes the steps of: connecting the interconnect metal layers (C-ML) 62 to the via 58 ( Figure 3H ) multiple second openings 64 ( Figure 3G The connection metal layer (C-ML) 62 is defined to the engineered layer (ELY) 44. The connection metal layer (C-ML) 62 can have various designs. Furthermore, the design must form an opening 64 in the passage 58 leading to the engineered layer (ELY) 44. Figure 3G ). Figure 3H A first embodiment is illustrated, wherein connecting metal layers (C-ML) 62 are formed at the four corners of the device epitaxial (EPI) structure 54, connecting each adjacent device epitaxial (EPI) structure 54. Figure 3I A second embodiment is illustrated, wherein a connection metal layer (C-ML) 62 is formed in the middle of the side surface of the device epitaxial (EPI) structure 54. In both embodiments, the connection metal layer (C-ML) 62 has a square outer contour; however, other polygonal and circular contours or any other contour may be used, as long as the connection metal layer (C-ML) 62 is sufficiently robust to hold the device epitaxial (EPI) structures 54 together. In both embodiments, the connection metal layer (C-ML) 62 connects the device epitaxial (EPI) structures 54, thereby forming an interconnected physical structure.

[0020] The interconnect metal layer (C-ML) 62 may comprise one or more metals selected from Ni, Co, Cu, Ti, Cr, Mo, W, Au, Ag, and Pt. The interconnect metal layer (C-ML) 62 may also comprise another material, such as ITO, AlN, Si3N4, silicone, epoxy, or acrylic resin. In an exemplary embodiment, the interconnect metal layer (C-ML) 62 is formed by depositing a second metal 66 followed by a photolithographic deposition process, which will be described further. Alternatively, the interconnect metal layer (C-ML) 62 may be formed using various methods, such as evaporation, sputtering, electroplating, screen printing, metal tiling, or any other method configured to deposit a conductive material in a selected pattern. The following examples disclose two exemplary methods for forming the interconnect metal layer (C-ML) 62.

[0021] refer to Figure 3JThe method further includes the step of further removing the engineered layer (ELY) 44 of the lattice-matching layer (LML) 46 beneath the contact device epitaxial (EPI) structure 54 to separate the engineered substrate (ES) 40 from the device epitaxial (EPI) structure 54. The portion of the engineered layer (ELY) 44 in the opening 64 adjacent to the device epitaxial (EPI) structure 54 may have already been removed by the previously described etching steps. Additionally, accelerated horizontal etching of the device epitaxial (EPI) structure 54 beneath the lattice-matching layer (LML) 46 may be required to separate the engineered substrate (ES) 40 from the device epitaxial (EPI) structure 54. For example, for the engineered layer (ELY) 44 comprising SiO2, suitable removal methods include vapor-phase etching using HF, or other oxide etching techniques, such as atmospheric plasma with CHyFx and oxygen. However, other selective etching processes may also be employed. For wet chemical etching, to enhance the etching rate of the horizontal engineered layer (ELY) 44, high-frequency acoustic waves, such as ultrasound with frequencies from 10 kHz to 200 kHz and megasonic waves with frequencies from 200 kHz to 10 MHz, can be used. This technique further increases the horizontal wet etching rate of the engineered layer (ELY) 44 to minimize damage to the engineered substrate (ES) 40 during etching (e.g., surface roughness reduction >2x was found using high-frequency acoustic waves). For example, high-frequency acoustic waves passing through a liquid containing wet etching chemicals with fluoride ions will etch the engineered layer (ELY) 44 faster (more than 2x) than without acoustic waves. High-frequency acoustic waves generate tiny bubbles called cavitation, which implode and release energy to the etch sites, resulting in an increased etching rate within the channel beneath the device epitaxial (EPI) structure 54. During ultrasonic or megasonic wet etching, bubbles are generated, implode, and form even smaller bubbles floating in the etching solution. Some bubbles merge and form large bubbles, preventing the delivery of fresh chemicals to the etch sites beneath the device epitaxial (EPI) structure 54. This phenomenon increases as the aspect ratio of the etch channel increases with the depth of etching beneath the EPI structure 54. Importantly, the wafer should be vertically positioned in the bath to allow bubbles to escape to the surface of the etch bath due to Archimedes' forces. Using mechanical vibration alone during ultrasonic or megasonic wet etching, or combining mechanical vibration with vertical wafer positioning in the bath, can also improve horizontal etch rates and provide reproducible etching.

[0022] Still referencing Figure 3JThe method may further include the step of optimizing the thickness of the metal layer 50 to prevent stress damage to the device epitaxial (EPI) structure 54 after separation from the engineered substrate (ES) 40. Because the metal layer 50 exerts stress on the device epitaxial (EPI) structure 54, if the stress result is a sufficiently high force exceeding the Young's modulus of the material, this stress may cause the device epitaxial (EPI) structure 54 to crack or fracture. This situation occurs in… Figure 3M and Figure 3N As shown in the diagram. When the metal layer 50 has the optimal thickness, cracking will not occur. This situation is... Figure 3O and Figure 3P As shown in the image.

[0023] refer to Figure 3K The method further includes the step of physically separating the engineered substrate (ES) 40 from the epitaxial device (EPI) structure 54. This step can also be performed using a chemical stripping process utilizing liquids. The separated structure 70 includes the epitaxial device (EPI) structure 54 having a metal layer 50 thereon, and a connecting metal layer (C-ML) 62 physically connecting the epitaxial device (EPI) structure 54. If desired, the engineered substrate 40 can be refurbished and reused.

[0024] refer to Figure 3L The method may further include the step of attaching a temporary substrate 68 to the device epitaxial structure 54. Examples of the temporary substrate 68 include a UV-release substrate. Any gaps may be filled with a polymeric material such as a photoresist. The method may further include the step of performing other fabrication processes, such as forming device contacts. After the fabrication process, the temporary substrate 68 may be removed. For the temporary substrate 68 in the form of a UV-release substrate, an LED light source or laser may be used to expose the UV substrate to UV radiation. Furthermore, the device epitaxial (EPI) structure 54 may be divided into an array of two or more epitaxial structures connected by at least one conductive interconnect metal layer (C-ML) 62. Additionally, as... Figure 3Q As shown, the device epitaxial (EPI) structure 54 on the temporary substrate 68 can be separated from the metal layer 50 for further processing or use. Furthermore, as... Figure 3R As shown, the device epitaxial (EPI) structure 54 can be separated from the temporary substrate 68 for further processing or use.

[0025] refer to Figure 4A , Figure 4B and Figure 4CExample 1 illustrates alternative embodiments of connection metal layers (C-ML) 62A and 62B. Connection metal layers (C-ML) 62A and 62B are substantially similar to the previously described connection metal layer (C-ML) 62, but include elongated metal strips that electrically connect all device epitaxial structures in the cross-shaped electrical network of the device epitaxial (EPI) structure 54. Furthermore, connection metal layers (C-ML) 62A and 62B divide the device epitaxial (EPI) structure 54 in two and are oriented generally parallel to the via 58. Figure 4C An alternative embodiment of the method is illustrated, wherein the connecting metal layers (C-ML) 62A and 62B are also formed along the via sidewalls of the device epitaxial (EPI) structure 54A, thereby opening up the remaining via region.

[0026] refer to Figure 5A , Figure 5B , Figure 5C and Figure 5D An alternative embodiment of the method is illustrated. In this embodiment, the contact metal 48 ( Figure 3C A metal layer 50 is formed on it. Figure 3C The steps are as follows. Multiple device epitaxial (EPI) structures 54A are defined using subtractive processes such as dry etching (e.g., inductively coupled reactive ion etching or ICP / RIE), laser cutting, sawing, diamond cutting, wet etching, or water jetting. Furthermore, a bonding metal layer (C-ML) 62C is formed substantially directly on the device epitaxial (EPI) structures 54A as previously described. Figure 5C An alternative embodiment of the method is illustrated, wherein the interconnecting metal layer (C-ML) 62C is also formed along the corner sidewall of the device epitaxial (EPI) structure 54A.

[0027] Implementation Example 1: Reference Figures 6A to 6C An example is shown for forming the interconnect metal layer (C-ML) 62 ( Figure 6C An exemplary manufacturing sequence. In Figure 6A In this process, PR=50 photoresist is formed in the metal layer opening 52 and the passage 58, and patterned essentially as shown in the figure. Figure 6B In the process, a second metal layer 72 is formed, followed by patterning of PR=51 photoresist, and then electroplating of EP bonding metal layer 74. Figure 6C In this process, the second metal layer 72 is etched, followed by the removal of PR=51 and PR=50 photoresist, leaving the bonding metal layer (C-ML) 62. In this example, the bonding metal layer (C-ML) 62 may include Cu. Copper is an advantageous metal because it has high electrical conductivity, a melting point of about 1085°C, and a boiling point of about 2562°C.

[0028] Example 2: Reference Figures 7A to 7EAn example is shown for forming the plated bonding metal layer (C-ML) 62P ( Figure 7E An exemplary manufacturing sequence. In Figure 7A In this process, PR50 dry film photoresist is formed above the patterned metal layer openings 52, which are essentially as shown in the figure. Figure 7B In this process, a second metal layer 76 is formed on the metal layer 50 and on the PR50 photoresist. Figure 7C In this process, a second PR50 photoresist is formed on a second metal layer 76 that is patterned substantially as shown in the figure. Figure 7D In this process, a C-ML coating 78 is formed on the second metal layer 76. Figure 7E In this process, the PR50 photoresist and the second PR50 photoresist are removed, leaving a deposited interconnect metal layer (C-ML) 62P. In this example, C-ML may comprise Cu, substantially as previously described.

[0029] While many exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain modifications, substitutions, additions, and sub-combinations thereof. Therefore, the appended claims and the subsequently introduced claims are intended to be construed as including all such modifications, substitutions, additions, and sub-combinations within their true spirit and scope.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: An engineered substrate (ES) is provided, the engineered substrate comprising a core, an engineered layer (ELY) on the core, and a lattice-matching layer (LML) on the engineered layer (ELY). Multiple epitaxial (EPI) layers are provided on the lattice-matched layer (LML) of the engineered substrate (ES); Multiple device epitaxial (EPI) structures separated by pathways are formed in the epitaxial (EPI) layer; Multiple interconnect metal layers (C-ML) are formed to connect the epitaxial (EPI) structure of the device. as well as The core of the engineered substrate (ES) is removed from the device epitaxial (EPI) structure.

2. The method according to claim 1, further comprising: A temporary substrate is attached to the epitaxial structure of the device, and additional manufacturing steps are performed.

3. The method of claim 2, wherein the temporary substrate comprises a UV-release substrate.

4. The method of claim 1, wherein the step of forming the device epitaxial (EPI) structure comprises the following steps: A contact metal is deposited on the epitaxial (EPI) layer; a metal layer having a plurality of openings in a selected pattern is formed on the contact metal; And the metal layer is used to define the device epitaxial (EPI) structure.

5. The method of claim 1, wherein the step of forming the device epitaxial (EPI) structure comprises: The epitaxial (EPI) layer is dry etched.

6. The method of claim 1, wherein the device epitaxial (EPI) structure comprises semiconductor islands having polygonal profiles.

7. The method of claim 1, wherein the epitaxial (EPI) layer comprises a material selected from the group consisting of Si, C, GaN, AlN, SiC, AlGaN, InGaN, AlCGaN, and AlSiGaN.

8. The method of claim 1, wherein the epitaxial (EPI) layer comprises at least one element selected from the group consisting of Ga, Si, C and In.

9. The method of claim 1, wherein the engineered layer (ELY) comprises at least one element selected from the group consisting of Si, O, N and C.

10. The method of claim 1, wherein the lattice-matched layer (LML) comprises at least one element selected from the group consisting of Si, Al, C and N.

11. The method of claim 1, wherein the lattice-matched layer (LML) comprises a material selected from the group consisting of Si, C, SiC, GaN, AlN, AlGaN, InGaN, AlCGaN, and AlSiGaN.

12. The method of claim 1, wherein the connecting metal layer (C-ML) comprises a metal selected from the group consisting of Ni, Co, Cu, Ti, Cr, Mo, W, Au, Ag and Pt.

13. The method of claim 1, wherein the step of forming the plurality of interconnecting metal layers (C-ML) comprises: Light patterning and electroplating.

14. A method for manufacturing a semiconductor device, the method comprising: An engineered substrate (ES) is provided, the engineered substrate comprising a core, an engineered layer (ELY) on the core, and a lattice-matching layer (LML) on the engineered layer (ELY). Multiple epitaxial (EPI) layers are provided on the lattice-matched layer; Multiple epitaxial (EPI) structure islands (EPI-ISLs) separated by channels are formed in the epitaxial (EPI) layer by depositing contact metal on the epitaxial (EPI) layer, a metal layer having multiple openings in a selected pattern is formed on the contact metal, and the openings in the metal layer are used to define the epitaxial (EPI) structure islands (EPI-ISLs) and the contact metal defined by the openings is removed; Multiple connecting metal layers (C-ML) are formed to connect the epitaxial (EPI) structure islands (EPI-ISL). as well as The core of the engineered substrate (ES) is removed, leaving a new device structure.

15. The method according to claim 14, further comprising: A temporary substrate is attached to the epitaxial (EPI) structure island (EPI-ISL), and additional manufacturing steps are performed.

16. The method of claim 14, wherein the opening in the metal layer is aligned with the passage.

17. The method of claim 14, wherein the step of forming the interconnecting metal layer (C-ML) comprises: A first photoresist is formed in the opening, a second photoresist is formed on the metal layer having a second opening, metal is deposited in the second opening, and the first and second photoresists are removed.

18. The method of claim 14, wherein the step of forming the interconnect metal layer (C-ML) comprises: A first photoresist is formed above the opening, a second metal is deposited on the metal layer and the first photoresist, a second photoresist is formed on the metal layer, a C-ML coating is deposited on the first photoresist and the second photoresist, and the first photoresist and the second photoresist are removed.

19. The method of claim 14, wherein the epitaxial (EPI) layer comprises a material selected from the group consisting of Si, C, GaN, AlN, SiC, AlGaN, InGaN, AlCGaN, and AlSiGaN.

20. The method of claim 14, wherein the metal layer comprises a metal selected from the group consisting of Ni, Co, Cu, Ti, Cr, Mo, W, Au, Ag and Pt.

21. The method of claim 14, wherein the connecting metal layer (C-ML) comprises a metal selected from the group consisting of Ni, Co, Cu, Ti, Cr, Mo, W, Au, Ag and Pt.

22. The method of claim 14, wherein the epitaxial (EPI) layer comprises at least one element selected from the group consisting of Ga, Si, C and In.

23. The method of claim 14, wherein the engineered layer (ELY) comprises at least one element selected from the group consisting of Si, O, N and C.

24. The method of claim 14, wherein the lattice-matched layer (LML) comprises at least one element selected from the group consisting of Si, Al, C and N.

25. The method of claim 14, wherein the lattice-matched layer (LML) comprises a material selected from the group consisting of Si, C, SiC, GaN, AlN, AlGaN, InGaN, AlCGaN, and AlSiGaN.

26. The method of claim 14, wherein the epitaxial (EPI) structure island (EPI-ISL) comprises a semiconductor island having a polygonal profile.

27. The method of claim 14, wherein the epitaxial (EPI) structure island (EPI-ISL) comprises a semiconductor island having four corners, and the connecting metal layer (C-ML) comprises a polygon or a circle at the four corners.

28. The method of claim 14, wherein the epitaxial (EPI) layer comprises a layer having a first coefficient of thermal expansion (CTE), and the core of the engineered substrate (ES) has a second coefficient of thermal expansion (CTE) that closely matches the first coefficient of thermal expansion (CTE).

29. The method of claim 14, wherein the semiconductor device comprises a device selected from the group consisting of power devices, RF devices, and light-emitting diodes (LEDs).

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