Double-sided deep silicon etching method and MEMS device

Abstract

This invention provides a double-sided deep silicon etching method and a MEMS device. The double-sided deep silicon etching method includes: providing an SOI substrate, on which a top silicon layer, a buried oxide layer, and a bottom silicon layer are sequentially formed; performing a first deep silicon etching on the top silicon layer to form multiple blind vias stopping at the buried oxide layer; after completing the first deep silicon etching, depositing a protective layer on the top silicon layer, the protective layer being deposited on the surface of the top silicon layer and at the corners of the top silicon layer at the openings of the blind vias; after completing the protective layer deposition, attaching an electrostatic film to the top silicon layer, flipping the SOI substrate, and performing a second deep silicon etching on the bottom silicon layer to form vias communicating with the blind vias; after completing the second deep silicon etching, removing the protective layer of the top silicon layer. The double-sided deep silicon etching method provided by this invention can effectively improve the problem of damage to the front morphology of the silicon substrate during double-sided deep silicon etching.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, and particularly relates to a double-sided deep silicon etching method and MEMS devices. Background Technology

[0002] Microelectromechanical systems (MEMS) technology, by fabricating high aspect ratio three-dimensional microstructures on silicon substrates, is widely used in fields such as inertial sensors, optical micromirrors, radio frequency devices, and biochips. The fabrication of these devices often requires high-precision deep reactive ion etching (DRIE) on both sides of the silicon wafer to form complex through-holes, channels, and vias, whether penetrating or not, thereby enabling device functionalization, integration, or wafer-level packaging.

[0003] Fabricating microelectromechanical systems (MEMS) on a silicon-on-insulator (SOI) substrate involves the following steps: First, a first deep silicon etching is performed on the device layer (front side) of the SOI substrate, stopping after etching down to the buried silicon dioxide (BOX) layer, forming a series of semi-through cavities or blind vias with precise morphologies. Subsequently, the wafer is flipped, and its substrate layer (back side) is patterned and subjected to a second deep silicon etching to connect the back-side cavities to the front-side structures, ultimately forming through-holes. This process is crucial for realizing three-dimensional interconnects of devices, releasing movable structures, or forming optical windows.

[0004] However, this double-sided etching process faces a severe technical challenge: the second back-side etching process can severely damage the fine structural morphology already formed on the front side during the first etching, leading to loss of control over the device's critical dimension (CD), performance drift, and even the scrapping of the entire wafer. The reasons why backside deep silicon etching damages the front-side morphology of a wafer are as follows: First, backside deep silicon etching is a violent physicochemical process. For example, when using the Bosch process for alternating backside deep silicon etching, the different etching gases used (such as SF6 and C4F8) generate ion flows and active free radicals with specific energies and angles. When etching reaches the final buried oxide layer, these high-energy particles directly bombard the exposed front-side silicon structure through the micro-hole regions that are about to be penetrated, especially stress concentration areas such as sidewalls and substrate corners, causing localized physical sputtering and chemical erosion, resulting in irreversible morphological damage such as corner rounding and sidewall roughness deterioration.

[0005] Secondly, severe damage is more likely to occur at the moment of etching through the buried oxide layer to form a via. Typically, during back-side etching of the substrate, an electrostatic protective film is attached to the front side of the substrate. Before etching through, this film forms a sealed microcavity between itself and the front side of the silicon wafer. When the etching plasma suddenly breaks through the last thin silicon dioxide layer, the high-pressure process gas in the reaction chamber abruptly connects with the low-pressure region within the microcavity. This causes the electrostatic film to rapidly contract and diffuse, resulting in the risk of etching at the corners of the deep silicon etched area on the front side. Ultimately, this makes it impossible to effectively control the front-side morphology, affecting the critical dimensions of the device and the final yield, and may even directly lead to wafer scrap.

[0006] Therefore, there is an urgent need in the field for a double-sided deep silicon etching method that can improve the problem of damage to the front morphology of the silicon substrate during double-sided deep silicon etching. Summary of the Invention

[0007] This invention provides a double-sided deep silicon etching method that can effectively improve the problem of damage to the front morphology of the silicon substrate during double-sided deep silicon etching.

[0008] Other objects and advantages of the present invention can be further understood from the technical features disclosed herein.

[0009] To achieve one, some, or all of the above objectives or other objectives, the present invention provides a double-sided deep silicon etching method, comprising: providing an SOI substrate, wherein a top silicon layer, a buried oxide layer, and a bottom silicon layer are sequentially formed on the SOI substrate; performing a first deep silicon etching on the top silicon layer to form a plurality of blind vias stopping at the buried oxide layer; after completing the first deep silicon etching, depositing a protective layer on the top silicon layer, wherein the protective layer is deposited on the surface of the top silicon layer and at the corners of the top silicon layer at the openings of the blind vias; after completing the deposition of the protective layer, attaching an electrostatic film to the top silicon layer, flipping the SOI substrate, and performing a second deep silicon etching on the bottom silicon layer to form vias communicating with the blind vias; after completing the second deep silicon etching, removing the protective layer of the top silicon layer.

[0010] The electrostatic film is removed after the second deep silicon etching is completed; after removing the electrostatic film, the protective layer is removed.

[0011] The deposited protective layer is one of silicon nitride and silicon oxide.

[0012] During the second deep silicon etching, the bottom silicon layer is etched first, and the buried oxide layer is etched after the bottom silicon layer is etched.

[0013] A protective layer is deposited using a PECVD process to increase the low-frequency RF power, thereby increasing the thickness of the protective layer deposited at the corner of the blind via opening of the top silicon layer.

[0014] The gases used in the PECVD process for depositing silicon oxide include silicon source gas and oxidation gas. The pressure range of the reaction chamber is 1.0 Torr-2.0 Torr. The high-frequency radio frequency power range for maintaining plasma density is 80W-120W, and the low-frequency radio frequency power for providing ion orientation is 300W-400W.

[0015] The PECVD process for depositing silicon oxide includes an initial treatment stage, a main deposition stage, and a post-treatment stage. In the initial treatment stage, the high-frequency radio frequency power ranges from 90W to 100W, and the low-frequency radio frequency power ranges from 45W to 55W. In the main deposition stage, the high-frequency radio frequency power ranges from 90W to 100W, and the low-frequency radio frequency power ranges from 300W to 400W. In the post-treatment stage, the high-frequency radio frequency power ranges from 90W to 100W, and the low-frequency radio frequency power ranges from 45W to 55W.

[0016] The silicon source gas is silane, the oxidizing gas is nitrous oxide, and the flow ratio of silane to nitrous oxide is 1:4 to 1:5.

[0017] The first and second deep silicon etching processes use CF4 as the main reactive gas for dry etching; after the second deep silicon etching is completed, a wet etching process is used to remove the protective layer of the top silicon layer.

[0018] Another technical solution of the present invention provides a MEMS device comprising an SOI substrate prepared using a double-sided deep silicon etching method as described above.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The double-sided deep silicon etching method provided by the present invention deposits a dense protective layer (such as silicon oxide or silicon nitride) on the surface of the top silicon layer and at the corners of the blind via openings after the first front deep silicon etching and before the second back deep silicon etching. This protective layer is used for corner area etching compensation during the subsequent back deep silicon etching process (when high-energy ions etch the corner area, they preferentially etch this protective layer, avoiding etching the corner area), protecting the structure of the corner area of ​​the top silicon layer, protecting the substrate morphology of the top silicon layer, improving the performance of MEMS devices, and increasing product yield. 2. The double-sided deep silicon etching method provided by the present invention uses PECVD process to deposit a protective layer in the blind hole region of the top silicon layer. By limiting the high-frequency power and increasing the low-frequency power, the reaction precursor is preferentially deposited at the exposed horizontal plane and corner edges under higher chamber pressure. Without significantly increasing the sidewall film thickness inside the blind hole, the deposition effect of the protective layer in the corner region of the top silicon layer is improved, and the deposition thickness of the protective layer in the corner region is maximized to improve the protection effect.

[0020] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of the morphology of the top silicon layer damaged after etching using the existing double-sided deep silicon etching method.

[0023] Figure 2 This is a schematic flowchart of the double-sided deep silicon etching method of the present invention.

[0024] Figure 3 This is an image showing the etched top silicon layer morphology after etching using the double-sided deep silicon etching method of the present invention.

[0025] In the diagram: 1. Bottom silicon layer; 2. Top silicon layer; 3. Blind via; 4. Buried oxide layer; 5. Protective layer; 6. Photoresist; 7. Electrostatic film; 8. Metal layer; 9. Corner area. Detailed Implementation

[0026] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0028] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0029] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0030] Embodiments of the invention are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures) of this application, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.

[0031] Example 1 Example 1 provides a double-sided deep silicon etching method, which provides an SOI substrate on which a top silicon layer, a buried oxide layer, and a bottom silicon layer are sequentially formed. A first deep silicon etching is performed on the top silicon layer to form multiple blind vias that stop at the buried oxide layer. After the first deep silicon etching, a protective layer is deposited on the top silicon layer, including on the surface of the top silicon layer and at the corners of the blind via openings. After the protective layer is deposited, an electrostatic film is attached to the top silicon layer. The SOI substrate is then flipped, and a second deep silicon etching is performed on the bottom silicon layer to form vias communicating with the blind vias. After the second deep silicon etching, the protective layer of the top silicon layer is removed.

[0032] Example 1 provides a double-sided deep silicon etching method. After forming a blind via structure through the first deep silicon etching, a protective layer is deposited on the surface of the top silicon layer and at the corner structure formed at the location of the blind via in the top silicon layer. When the bottom silicon layer and buried oxide layer are etched and connected to the blind via in the top silicon layer, the protective layer plays a role in protecting the silicon substrate in the corner area of ​​the top silicon layer, preventing the silicon substrate in the corner area from being over-etched and causing damage to the morphology of the top silicon layer.

[0033] The following text, in conjunction with the appendix Figure 1-3 The double-sided deep silicon etching method provided in Example 1 will be explained in detail. The double-sided deep silicon etching method provided in Example 1 includes the following steps: Step 1: First deep silicon etching.

[0034] Provide an SOI substrate, such as Figure 2 As shown in Figure a, the SOI substrate has a top silicon layer 2, a bottom silicon layer 1, and a buried oxide layer 4 in between, which is typically silicon oxide. A metal layer 8 is deposited on the surface of the SOI substrate, and photoresist 6 is coated on top of the deposited metal layer. Photolithography is used to pattern the photoresist 6, and after etching the metal layer 8, the desired result is obtained. Figure 2 The device structure shown in b is as follows. After fabricating this device structure, photoresist is coated onto the patterned metal layer, and photolithography is used to pattern the photoresist, resulting in the structure shown in Figure b. Figure 2 The substrate structure shown in 'c' has a photoresist patterned with blind holes. Using the photoresist as a mask, the SOI substrate is dry-etched to obtain the desired result. Figure 2 The SOI substrate structure shown in d has several blind holes 3 that stop at the buried oxide layer 4 after etching.

[0035] When etching the top silicon layer 2, CF4 can be used as the main gas in combination with oxygen or argon to improve the etching rate of silicon.

[0036] Step 2: Deposit a protective layer on top of the silicon layer.

[0037] After the blind via 3 is etched in the top silicon layer 2, a protective layer is deposited on the top silicon layer 2. This protective layer is deposited on the surface of the top silicon layer 2 and in the corner region 9 located at the opening of the blind via 3. A detailed illustration of the corner region 9 can be found in [reference needed]. Figure 3 as well as Figure 1 ,by Figure 1 For example, Figure 1 This is an example of excessive etching in corner areas in existing technology. Figure 1 The corner region 9 is clearly visible in the middle, which has a chamfer (or rounded corner) due to excessive etching. This corner region 9 is located at the edge of the blind hole in the top silicon layer 2. Figure 3An example is given of depositing protective layer 5 in corner region 9. Figure 3 The protective layer 5 is not only deposited on the surface of the top silicon layer 2, but also deposited on the corner area 9 of the top silicon layer 2 at the opening of the blind hole 3 for full protection.

[0038] To address the aforementioned issues, the protective layer deposited in step 2 can be silicon oxide or silicon nitride. During deposition, it can be achieved using a PECVD process. It is important to note that the high-frequency radio frequency power used to maintain plasma density should be limited to an intensity value (e.g., not exceeding 100W), while the low-frequency radio frequency power used to provide ion orientation should be appropriately increased. The high-energy ions generated by the low-frequency power have stronger directionality and will bombard the silicon wafer surface vertically, greatly promoting the deposition rate and film density on the horizontal plane and entrance edges, while contributing very little to the deposition on the vertical sidewalls and bottom of the holes.

[0039] The following explanation uses the deposition of silicon oxide thin films as an example. It's important to clarify that the principles of depositing silicon nitride thin films and silicon oxide thin films are the same; the difference lies in the reaction gases and the specific etching process parameters. The specific steps for depositing silicon oxide thin films include: Step 2-1: Initial Processing Stage The pressure in the reaction chamber was maintained at 1.0 Torr-2.0 Torr. A higher gas pressure in the reaction chamber effectively limited the entry of the reaction precursor into the blind hole. Silane was used as the silicon source gas, and nitrous oxide as the oxidizing gas. The flow ratio of silane to nitrous oxide was controlled at 1:4-1:5. High-frequency and low-frequency radio frequency power were activated, with the high-frequency power ranging from 90W to 100W and the low-frequency power from 45W to 55W.

[0040] Using higher high-frequency power and lower low-frequency power in the initial treatment stage can promote the surface reaction between the reaction precursor and the substrate, form a good nucleation layer and stabilize the film.

[0041] Step 2-2: Main sedimentation stage: The main deposition stage differs from the initial processing stage in that the high-frequency and low-frequency RF powers are adjusted, specifically: the high-frequency RF power ranges from 90W to 100W, and the low-frequency RF power ranges from 300W to 400W. In the main deposition stage, significantly increasing the low-frequency power promotes the vertical bombardment of the silicon wafer surface by the generated high-energy ions, greatly accelerating the deposition rate and film density at the horizontal plane and the entrance corners of blind vias. This helps form a protective film in the corner areas while minimizing the formation of films on the sidewalls and bottom of the blind vias.

[0042] Steps 2-3: Post-processing stage: The post-processing stage uses the same RF power as the initial processing stage, with high-frequency RF power ranging from 90W to 100W and low-frequency RF power ranging from 45W to 55W.

[0043] The SOI deposition structure after the protective layer is deposited is as follows: Figure 2 As shown in e, a protective layer is formed on the surface of the top silicon layer 2 of the SOI substrate and in the corner region 9, while the protective layer deposited on the walls and bottom of the blind vias is less.

[0044] Step 3: Apply an electrostatic film to the top silicon layer.

[0045] After completing the protective layer deposition step in step 2, an electrostatic film 7 is attached to the surface of the top silicon layer 2 of the SOI substrate.

[0046] A schematic diagram of the SOI substrate with electrostatic film 7 attached is shown below. Figure 2 As shown in f in the figure.

[0047] Step 4: Etching the bottom silicon layer.

[0048] After completing step 3, the SOI substrate is flipped over, and a second deep silicon etching is performed on the bottom silicon layer 1 on the SOI substrate, using CF4 as the main reactive gas for dry etching.

[0049] The second deep silicon etching process includes etching the silicon material of the bottom silicon layer 1 and etching the silicon oxide of the buried oxide layer 4. When etching the bottom silicon layer 1, the Bosch deep silicon etching process can be used, or CF4 can be used as the main reactant gas in combination with oxygen or argon for dry etching. When etching the silicon oxide of the buried oxide layer 4, CF4 can be used as the main reactant gas in combination with hydrogen or a gas with a high carbon-to-fluorine ratio (e.g., CHF3) for dry etching.

[0050] The second deep silicon etching was performed to connect with blind via 3.

[0051] The substrate structure after the second deep silicon etching is as follows: Figure 2 As shown in g in the figure.

[0052] Step 5: Remove the electrostatic film 7 and the protective layer 5.

[0053] After completing step 4, the electrostatic film 7 on the top silicon layer 2 is peeled off, and the protective layer 5 remaining on the top silicon layer is removed using a wet etching method. This wet removal process is a prior art and will not be described in detail here. The substrate structure after removing the electrostatic film 7 and the remaining protective layer 5 on the top silicon layer 2 is as follows. Figure 2 As shown in h.

[0054] like Figure 1As shown, after performing a second deep silicon etching using conventional methods in the art, there may be a problem of over-etching in the corner area 9 (the opening area of ​​the blind hole 3 has a chamfer or rounded corner), which may cause the diameter of the blind hole 3 formed on the top silicon layer 2 to become larger, affecting the accuracy of critical dimensions and resulting in a decrease in yield.

[0055] like Figure 3 As shown, the through-hole structure prepared using the method in Example 1 has a protective layer 5 in the corner region 9. When excessive etching occurs, the protective layer 5 in the corner region 9 can compensate for the occurrence of excessive etching, avoid damage to the silicon material in the corner region 9, and thus improve the product yield.

[0056] Example 2 Example 2 provides a MEMS device. The MEMS device provided in Example 2 uses an SOI substrate prepared by the method in Example 1. The SOI substrate prepared by the method in Example 1 can effectively reduce excessive etching in the corner area and improve the yield of MEMS products.

[0057] The above provides a detailed description of the double-sided deep silicon etching method and MEMS device provided by this invention. Specific examples have been used to illustrate the structure and working principle of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the scope of protection of the claims of this invention.

Claims

1. A double-sided deep silicon etching method, characterized in that, An SOI substrate is provided, wherein a top silicon layer, a buried oxide layer and a bottom silicon layer are sequentially formed on the SOI substrate; The top silicon layer is subjected to a first deep silicon etching to form multiple blind vias that stop at the buried oxide layer; After the first deep silicon etching is completed, a protective layer is deposited on the top silicon layer. The protective layer is deposited on the surface of the top silicon layer and at the corner of the top silicon layer at the blind via opening. After the protective layer deposition is completed, an electrostatic film is attached to the top silicon layer, the SOI substrate is flipped, and a second deep silicon etching is performed on the bottom silicon layer to form a via that communicates with the blind via. After the second deep silicon etching is completed, the protective layer of the top silicon layer is removed.

2. The double-sided deep silicon etching method according to claim 1, characterized in that, The electrostatic film is removed after the second deep silicon etching is completed; After removing the electrostatic film, remove the protective layer.

3. The double-sided deep silicon etching method according to claim 1, characterized in that, The deposited protective layer is one of silicon nitride and silicon oxide.

4. The double-sided deep silicon etching method according to claim 1, characterized in that, During the second deep silicon etching, the bottom silicon layer is etched first, and the buried oxide layer is etched after the bottom silicon layer is etched.

5. The double-sided deep silicon etching method according to claim 3, characterized in that, A protective layer is deposited using a PECVD process to increase the low-frequency RF power, thereby increasing the thickness of the protective layer deposited at the corner of the blind via opening of the top silicon layer.

6. The double-sided deep silicon etching method according to claim 3, characterized in that, The gases used in the PECVD process for depositing silicon oxide include silicon source gas and oxidation gas, and the pressure range of the reaction chamber is 1.0 Torr-2.0 Torr; The high-frequency radio frequency power range for maintaining plasma density is 80W-120W, and the low-frequency radio frequency power for providing ion orientation is 300W-400W.

7. The double-sided deep silicon etching method according to claim 6, characterized in that, The PECVD process for depositing silicon oxide includes an initial treatment stage, a main deposition stage, and a post-treatment stage. In the initial processing stage, the high-frequency radio frequency power range is 90W-100W, and the low-frequency radio frequency power is 45W-55W; During the main deposition stage, the high-frequency radio frequency power ranges from 90W to 100W, and the low-frequency radio frequency power ranges from 300W to 400W. In the post-processing stage, the high-frequency radio frequency power range is 90W-100W, and the low-frequency radio frequency power is 45W-55W.

8. The double-sided deep silicon etching method according to claim 6, characterized in that, The silicon source gas is silane, the oxidizing gas is nitrous oxide, and the flow ratio of silane to nitrous oxide is 1:4 to 1:

5.

9. The double-sided deep silicon etching method according to claim 1, characterized in that, The first and second deep silicon etching processes use CF4 as the main reactive gas for dry etching. After the second deep silicon etching is completed, the protective layer of the top silicon layer is removed using a wet etching process.

10. A MEMS device, characterized in that, This includes SOI substrates prepared using a double-sided deep silicon etching method as described in any one of claims 1-9.

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