Masks, methods for manufacturing masks, and electronic devices

Abstract

This disclosure relates to masks, methods of manufacturing masks, and electronic devices. The mask includes: a first frame defining a first opening; and second frames respectively disposed in the first opening, wherein each of the second frames defines a second opening smaller than the first opening. The first frame includes a first-1 frame portion and a first-2 frame portion disposed on the first-1 frame portion, and each of the second frames includes a second-1 frame portion in a grid pattern and a second-2 frame portion disposed on the second-1 frame portion. The first-1 frame portion and the second-1 frame portion comprise a first material, and the first-2 frame portion and the second-2 frame portion comprise a second material different from the first material.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0176837, filed on December 2, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of the present invention generally relate to masks, methods of manufacturing masks, and electronic devices. Background Technology

[0003] Displays can be manufactured using a variety of processes. For example, a deposition process can be used in display manufacturing. In a deposition process used to manufacture a display, a mask for depositing organic materials can be used, which is adhered to a substrate. Summary of the Invention

[0004] The embodiments provide a mask that is easy to form into an inverted cone shape and inverted cone angle and has increased strength and reduced warpage, as well as a method for manufacturing the mask.

[0005] The embodiments provide a method for manufacturing a display device using a mask, and an electronic device including the display device.

[0006] According to an embodiment of the present invention, a mask includes: a first frame, wherein a first opening is defined by the first frame; and a second frame, respectively disposed in the first opening, wherein each of the second frames defines a second opening smaller than the first opening. In such an embodiment, the first frame includes a first-1 frame portion and a first-2 frame portion disposed on the first-1 frame portion. In such an embodiment, each of the second frames includes a second-1 frame portion in a grid pattern and a second-2 frame portion disposed on the second-1 frame portion. In such an embodiment, the first-1 frame portion and the second-1 frame portion comprise a first material, and the first-2 frame portion and the second-2 frame portion comprise a second material different from the first material.

[0007] In this embodiment, the first material may be silicon, and the second material may be silicon nitride.

[0008] In an implementation, the second-second frame portion may have a rectangular shape in cross-section.

[0009] In an implementation, in cross-section, the width of the 2-1 frame portion can decrease as it moves away from the 2-2 frame portion in the thickness direction of the mask.

[0010] In an implementation, the second-first frame portion may have an inverted conical shape in cross-section.

[0011] In the implementation, the inverted cone angle of the second-1 frame portion can be greater than approximately 90°.

[0012] In an implementation, the second-first frame portion may have an inverted triangular shape in cross-section.

[0013] In an embodiment, the width of the upper surface of the second-1 frame portion facing the lower surface of the second-2 frame portion may be smaller than the width of the lower surface of the second-2 frame portion.

[0014] In an implementation, the thickness of the second-1 frame portion may be approximately 1 μm or greater.

[0015] In an implementation, the thickness of each of the first-second frame portion and the second-second frame portion may be about 1 μm or less.

[0016] In an implementation, the mask may further include frame portions 1-3 disposed below frame portion 1-1, wherein frame portions 1-3 may include a second material.

[0017] According to an embodiment of the present invention, a method for manufacturing a mask includes: forming a layer on a base substrate; forming a first-2 frame portion and a second-2 frame portion including openings by etching the layer; forming a pattern in cross-section having a width that decreases away from the upper surface of the base substrate in the thickness direction of the base substrate by etching the upper surface of the base substrate; forming a second-1 frame portion and an oxide layer surrounding the second-1 frame portion by oxidizing the pattern; forming the first-1 frame portion by etching the lower surface of the base substrate; and removing the oxide layer.

[0018] In an implementation, the base substrate may include silicon, and the layer may include silicon nitride.

[0019] In an implementation, the thickness of the layer can be about 1 micrometer (μm) or less.

[0020] In an implementation, the thickness of each of the patterns can be about 1 μm or greater.

[0021] In one implementation, the pattern may have an inverted cone shape in cross-section.

[0022] In this implementation, the inverted cone angle of the pattern can be greater than approximately 90°.

[0023] In one embodiment, the oxide layer may surround the side surface of the second-first frame portion.

[0024] In one implementation, the pattern may have an inverted triangular shape in cross-section.

[0025] In one embodiment, the oxide layer may surround the side and bottom surfaces of the second-first frame portion.

[0026] In an implementation, the thickness of the oxide layer can be in the range of about 1,000 angstroms to about 10,000 angstroms.

[0027] According to an embodiment of the present invention, a method of manufacturing a display device includes: forming a pixel circuit layer on a substrate, and forming a light-emitting device on the pixel circuit layer. In such an embodiment, forming the light-emitting device includes depositing an emitting layer using a mask. In such an embodiment, the mask includes: a first frame defining a first opening; and a second frame disposed in the first opening, wherein each of the second frames defines a second opening smaller than the first opening. In such an embodiment, the first frame includes a first-1 frame portion and a first-2 frame portion disposed on the first-1 frame portion. In such an embodiment, each of the second frames includes a second-1 frame portion in a grid pattern and a second-2 frame portion disposed on the second-1 frame portion. In such an embodiment, the first-1 frame portion and the second-1 frame portion comprise a first material. In such an embodiment, the first-2 frame portion and the second-2 frame portion comprise a second material different from the first material.

[0028] According to an embodiment of the present invention, an electronic device includes a processor and a display device including an emissive layer. In such an embodiment, the display device displays an image in response to control by the processor. In such an embodiment, the emissive layer is deposited using a mask as described above. Attached Figure Description

[0029] The above and other features of the present invention will become more apparent from the description of embodiments of the invention in more detail with reference to the accompanying drawings.

[0030] Figure 1 It is a plan view of the mask according to the implementation method.

[0031] Figure 2 It is according to the implementation method along Figure 1 A cross-sectional view of the mask cut by line I-I'.

[0032] Figure 3 It is a cross-sectional view of the mask according to the implementation method.

[0033] Figure 4 It is a cross-sectional view of the mask according to the implementation method.

[0034] Figures 5 to 10 This is a diagram illustrating a method for manufacturing a mask according to an embodiment.

[0035] Figures 11 to 13 This is a diagram illustrating a method for manufacturing a mask according to an embodiment.

[0036] Figures 14 to 19 This is a diagram illustrating a method for manufacturing a mask according to an embodiment.

[0037] Figure 20 This is a plan view of a display device according to an embodiment.

[0038] Figure 21 It is a planar view of the sub-pixels according to the implementation method.

[0039] Figure 22 It is according to the implementation method along Figure 21 A cross-sectional view of the subpixel cut off by line II-II'.

[0040] Figure 23 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment.

[0041] Figure 24 This is a block diagram of an electronic device according to an embodiment.

[0042] Figure 25 Schematic diagrams illustrating various embodiments of an electronic device are shown. Detailed Implementation

[0043] The invention will now be described more fully with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this specification, the same reference numerals denote the same elements.

[0044] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element, or there can be an intervening element between them. Conversely, when an element is referred to as being "directly" on another element, there is no intervening element.

[0045] Throughout this specification, the phrase "connected" to another part includes not only cases where the part is directly connected, but also cases where the part is indirectly connected to one or more other elements inserted therebetween. The terminology used herein is for describing particular embodiments and is not intended to limit this disclosure.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. Thus, reference to an element “a” in a claim followed by a reference to the element “the” includes one element and multiple elements. For example, “an element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a” or “an”. “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. “At least one of X, Y, and Z” and “selected from at least one of X, Y, and Z” can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ). It will also be understood that when the terms “comprising” and / or “including” or “containing” and / or “comprise” are used in this specification, they specify the presence of the stated features, areas, integrals, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components and / or groups thereof.

[0047] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0048] For descriptive purposes, spatial relative terms such as “below” and “above” may be used to describe the relationship between one element or feature and another element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to also include other orientations of the device in use, operation, and / or manufacture. For example, if the device shown in the drawings is flipped, an element described as being “below” other elements or features would be positioned “above” other elements or features. Therefore, in embodiments, the term “below” can include both above and below orientations. Furthermore, the device may face other orientations (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0049] Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “about” or “approximately” as used herein include the stated value and the average value within an acceptable range of deviations from the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations of the stated value, or within ±30%, 20%, 10%, or 5%.

[0050] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having meanings consistent with their meanings in the relevant technical context and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0051] Embodiments are described herein with reference to cross-sectional views as schematic illustrations of idealized embodiments. Thus, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include variations in shape due to, for example, manufacturing processes. For example, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0052] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0053] Figure 1 This is a plan view of the mask 100 according to the implementation method.

[0054] refer to Figure 1 The mask 100 can be implemented to manufacture display devices. For example, deposition material (e.g., luminescent material) evaporated from a deposition source can pass through the mask 100 and be deposited on an object (e.g., a substrate) in a predetermined pattern. However, the implementation is not necessarily limited to this.

[0055] In an implementation, the mask 100 may include a first frame 110 and a second frame 120.

[0056] The first frame 110 can form the basic structure of the mask 100. In an embodiment, for example, the first frame 110 can have a rectangular shape, having a long side extending in a first direction DR1 and a short side extending in a second direction DR2. Here, the third direction DR3 can be a direction perpendicular to the first direction DR1 and the second direction DR2, or it can be the thickness direction of the first frame 110. However, the embodiment is not necessarily limited to this. In an embodiment, for example, the first frame 110 can have various shapes, such as circles, polygons, etc. The first frame 110 can be provided with (or define) a first opening OP1. In an embodiment, such as... Figure 1 As shown, the first frame 110 may be provided with two first openings OP1, but the implementation is not necessarily limited to this. The number of first openings OP1 may vary depending on the size of the mask 100, its use, etc.

[0057] The second frames 120 can be arranged in the first openings OP1 of the first frames 110. In an embodiment, for example, the second frames 120 can be arranged in a grid (or mesh) pattern in the first openings OP1 of the first frames 110. Although Figure 1 An embodiment with two second frames 120 is shown, but the embodiment is not necessarily limited to this. The number of second frames 120 can vary depending on the number of first openings OP1. The second frames 120 may be provided with (or define) a second opening OP2, which is smaller than the first opening OP1. The deposition material as described above can pass through the second opening OP2 of the second frame 120 and be deposited on the object.

[0058] Figure 2 It is according to the implementation method along Figure 1 A cross-sectional view of mask 100 cut off by line I-I'.

[0059] refer to Figure 2 In an embodiment, the first frame 110 of the mask 100 may include a first-1 frame portion (hereinafter referred to as the "first-1 frame portion") 111 and a first-2 frame portion (hereinafter referred to as the "first-2 frame portion") 112.

[0060] The first-1 frame portion 111 can support the first-2 frame portion 112. The first-2 frame portion 112 can be arranged on the first-1 frame portion 111. The width of the upper surface of the first-1 frame portion 111 can be different from the width of the lower surface of the first-2 frame portion 112. The width can be the length measured in the first direction DR1. In an embodiment, for example, the width of the upper surface of the first-1 frame portion 111 facing the lower surface of the first-2 frame portion 112 can be smaller than the width of the lower surface of the first-2 frame portion 112. That is, compared to the first-1 frame portion 111, the first-2 frame portion 112 can protrude in the first direction DR1 (or in a direction opposite to the first direction DR1).

[0061] The first-1 frame portion 111 and the first-2 frame portion 112 may include materials different from each other. The first-1 frame portion 111 may include or be formed of a first material. In an embodiment, for example, the first material may be silicon (Si). The first-2 frame portion 112 may include or be formed of a second material different from the first material. In an embodiment, for example, the second material may be silicon nitride (SiN). x ).

[0062] Each of the second frames 120 of the mask 100 may include a second-1 frame portion (hereinafter referred to as "second-1 frame portion") 121 and a second-2 frame portion (hereinafter referred to as "second-2 frame portion") 122.

[0063] The second-1 frame portion 121 can support the second-2 frame portion 122. The second-2 frame portion 122 can be arranged on the second-1 frame portion 121. The second-1 frame portion 121 and the second-2 frame portion 122 can have a grid (or mesh) shape. The width of the upper surface of the second-1 frame portion 121 can be different from the width of the lower surface of the second-2 frame portion 122. In an embodiment, for example, the width of the upper surface of the second-1 frame portion 121 facing the lower surface of the second-2 frame portion 122 can be smaller than the width of the lower surface of the second-2 frame portion 122. That is, compared with the second-1 frame portion 121, the second-2 frame portion 122 can protrude in the first direction DR1 (or in the direction opposite to the first direction DR1).

[0064] Frame portion 121 (2-1) and frame portion 122 (2-2) may include materials different from each other. Frame portion 121 (2-1) may include or be formed of a first material. In embodiments, for example, the first material may be silicon (Si). Frame portion 122 (2-2) may include or be formed of a second material different from the first material. In embodiments, for example, the second material may be silicon nitride (SiN). x ).

[0065] In cross-section, the width of the second-1 frame portion 121 can decrease as it moves away from the second-2 frame portion 122 in a direction opposite to the third direction DR3 (or in the thickness direction). In an embodiment, for example, the cross-section of the second-1 frame portion 121 can have an inverted conical shape. Reference will be made below. Figure 7 A detailed description is provided. In cross-section, the 2-2 frame portion 122 may have a rectangular shape. In an embodiment, for example, the width of the 2-2 frame portion 122 may be constant (e.g., without any significant increase or decrease) as it moves away from the 2-1 frame portion 121 in the third direction DR3. However, the embodiment is not necessarily limited to this.

[0066] Figure 3 This is a cross-sectional view of mask 100' according to the embodiment. Figure 3 middle, Figure 3 The same or similar elements shown are used in the above description Figures 1 to 2 The same reference numerals are used to denote the embodiments of the mask 100 shown, any repeated detailed descriptions will be omitted or simplified, and the description will focus on the differences.

[0067] refer to Figure 3 In an embodiment, the cross-section of the second-1st frame portion 121' of the mask 100' may have an inverted triangular shape. Figure 2 In contrast, the width of the upper surface of the second-1 frame portion 121' facing the lower surface of the second-2 frame portion 122 can be reduced. In an embodiment, for example, the width of the upper surface of the second-1 frame portion 121' can be less than... Figure 2 The width of the upper surface of the 2-1 frame portion 121 shown. (Refer to below) Figure 11 Provide a detailed description.

[0068] Figure 4 This is a cross-sectional view of mask 100'' according to the embodiment. Figure 4 middle, Figure 4 The same or similar elements shown are used in the above description Figures 1 to 2The same reference numerals are used to denote the embodiments of the mask 100 shown, any repeated detailed descriptions will be omitted or simplified, and the descriptions will focus on the differences.

[0069] refer to Figure 4 In an implementation, the first frame 110 of the mask 100'' may include a first-1 frame portion 111, a first-2 frame portion 112, and a first-3 frame portion (hereinafter referred to as "first-3 frame portion") 113.

[0070] The first-third frame portion 113 may be disposed below the first-first frame portion 111. The first-third frame portion 113 may support the first-first frame portion 111. The first-third frame portion 113 may include a material different from that of the first-first frame portion 111, and may include the same material as that of the first-second frame portion 112. In an embodiment, for example, the first-third frame portion 113 may include a second material, such as silicon nitride (SiN). x ).

[0071] Figures 5 to 10 This is a diagram illustrating a method for manufacturing a mask 100 according to an embodiment. Figures 5 to 10 The manufacturing process is illustrated schematically. Figure 2 An implementation of the method of mask 100 shown.

[0072] refer to Figure 5 In an embodiment of the method for manufacturing mask 100, layer 20 is formed on a base substrate 10. The base substrate 10 may include silicon (Si). In an embodiment, for example, the base substrate 10 may be a silicon wafer. Layer 20 may include silicon nitride (SiN). x The thickness t1 of the layer 20 formed on the base substrate 10 can be about 1 micrometer (μm) or less. The thickness t1 can be the length measured on the third-direction DR3.

[0073] refer to Figure 6 Etched layer 20 (see Figure 5 The first-second frame portion 112 and the second-second frame portion 122 are formed by etching. That is, layer 20 can be patterned into the first-second frame portion 112 and the second-second frame portion 122 by etching. In an embodiment, layer 20 can be etched, for example, by a dry etching method, but the embodiment is not necessarily limited thereto. The second-second frame portion 122 can be patterned in a lattice (or grid) pattern to include the second opening OP2. The thickness t1 of each of the first-second frame portion 112 and the second-second frame portion 122 can be about 1 μm or less.

[0074] refer to Figure 7The base substrate 10 is etched to form pattern 10a. In an embodiment, for example, this is achieved by etching the second opening OP2 of the base substrate 10 with the second-2 frame portion 122 (see [link]). Figure 6 Pattern 10a is patterned by overlapping upper surfaces. In an embodiment, for example, the base substrate 10 can be etched by a dry etching method, but the embodiment is not necessarily limited to this. The width of pattern 10a in the cross section may decrease as it moves away from the second-second frame portion 122 in the direction opposite to the third direction DR3 (or the thickness direction). In an embodiment, for example, each of the patterns 10a may have an inverted conical shape in the cross section. In an embodiment, for example, the thickness t2 of each of the patterns 10a may be about 1 μm or greater, i.e., greater than or equal to about 1 μm. In an embodiment, for example, the inverted conical angle θ of each of the patterns 10a may be greater than about 90°. The inverted conical angle θ may be an interior angle of each of the patterns 10a having an inverted conical shape in the cross section.

[0075] The bonding strength between silicon (Si) atoms (325 kJ / mol) is less than that between silicon (Si) and oxygen (O) (799.6 kJ / mol) and between silicon (Si) and nitrogen (N) (470.0 kJ / mol). Therefore, etching can be performed to include silicon (Si) (excluding silicon oxide (SiO)). x ) and silicon nitride (SiN) x The base substrate 10 can be used to easily form a pattern 10a with the specifications described above (i.e., inverted cone shape and inverted cone angle).

[0076] Furthermore, since pattern 10a is formed using a base substrate 10 including silicon (Si), the degree of warpage can be reduced or maintained even when the thickness t2 of each of patterns 10a increases. Therefore, the thickness t2 of each of patterns 10a can be increased to improve mask 100 (see...). Figure 2 The strength of ). If by etching including silicon oxide (SiO) x ) and / or silicon nitride (SiN) x If the base substrate 10 is used to form the pattern 10a, then as the thickness t2 of each of the patterns 10a increases, the warpage increases, and the quality and strength of the mask 100 may decrease. That is, in the embodiment, the base substrate 10 comprises silicon (Si) and may not include silicon oxide (SiO2). x ) and silicon nitride (SiN) x ).

[0077] The inverted conical shape of each of the patterns 10a can be formed using a Bosch process. In one embodiment, for example, sulfur hexafluoride (SF6) gas and a bias voltage are applied to isotropically etch the base substrate 10, octafluorocyclobutane (C4F8) gas is applied to form the protective layer 10b, and sulfur hexafluoride (SF6) gas is applied to anisotropically etch the base substrate 10. The above process can then be repeated to form the pattern 10a with the inverted conical shape. Therefore, a protective layer 10b with an irregular structure can be formed on the pattern 10a with the inverted conical shape. However, the embodiment is not necessarily limited to this.

[0078] refer to Figure 8 Pattern 10a (see Figure 7 An oxide layer 40 is formed on a base substrate 10. In an embodiment, for example, the oxide layer 40 can be formed by a wet oxidation method. In an embodiment, for example, the oxide layer 40 can be formed by providing water vapor (H2O) to the base substrate 10 and the pattern 10a comprising silicon (Si). The oxide layer 40 can be a silicon oxide layer (SiO2). The silicon (Si) on the surface of each of the patterns 10a can react with water vapor (H2O) to form a silicon oxide layer (SiO2) and a second-1 frame portion 121. In an embodiment, for example, the surface of each of the patterns 10a can be transformed into a silicon oxide layer (SiO2) to form a second-1 frame portion 121 having an inverted conical shape. Therefore, the width of the upper surface of the pattern 10a can be reduced by as much as the width of the portion forming the oxide layer 40, such that the width of the upper surface of the second-1 frame portion 121 can be smaller than that of the pattern 10a. Figure 7 The width of the upper surface of pattern 10a shown. Therefore, the width of the upper surface of the second-1 frame portion 121 facing the lower surface of the second-2 frame portion 122 can be smaller than the width of the lower surface of the second-2 frame portion 122. Even after the oxide layer 40 is formed, the inverted cone angle θ of each of the second-1 frame portions 121 (see Figure 7 It can also be constant.

[0079] The oxide layer 40 may surround the side surface of the second-first frame portion 121. In one embodiment, for example, the oxide layer 40 may contact the side surface of the second-first frame portion 121 but may not contact the lower surface of the second-first frame portion 121. In another embodiment, for example, the oxide layer 40 may be disposed on the side surface of the second-first frame portion 121 having an inverted conical shape, but may not be disposed on the upper and lower surfaces of the second-first frame portion 121. The thickness t3 of the oxide layer 40 may be between about 1000 angstroms (Å) and about 10000 Å, i.e., in the range of about 1000 Å to about 10000 Å.

[0080] refer to Figure 9 Etching the base substrate 10 (see Figure 8 The lower surface of the frame is used to form the first frame part 111.

[0081] refer to Figure 10 It can remove oxide layer 40 (see Figure 9 To finally manufacture mask 100.

[0082] Figures 11 to 13 This is a diagram illustrating a method for manufacturing a mask 100' according to an embodiment. Figures 11 to 13 The manufacturing process is illustrated schematically. Figure 3 An implementation of the method for manufacturing the mask 100' shown. Figure 3 When mask 100' is shown, it can be executed. Figures 5 to 7 The process described herein will be omitted or simplified, and any repetitive detailed descriptions will be omitted or simplified.

[0083] refer to Figure 11 In an embodiment of the method for manufacturing mask 100', pattern 10a (see...) Figure 7 A silicon oxide layer 40' and an oxide layer 40' are formed on the base substrate 10. In an embodiment, for example, the surface of each of the patterns 10a can be transformed into a silicon oxide layer (SiO2) to form the second-1 frame portion 121' having an inverted triangular shape. In such an embodiment, by adjusting the wet oxidation process conditions, the oxide layer 40' can become more... Figure 8 The oxide layer 40 shown is thick. In embodiments, for example, the supply of water vapor (H2O) and / or the oxidation temperature can be increased to form an oxide layer 40' with a large thickness, but embodiments are not necessarily limited thereto. The thickness t3' of the oxide layer 40' can be greater than that shown. Figure 8 The thickness t3 of the oxide layer 40 shown. Furthermore, the width of the upper surface of the second-1 frame portion 121' can be smaller than that shown. Figure 8 The width of the upper surface of the second-1 frame portion 121 shown. Even after the oxide layer 40' is formed, the inverted cone angle θ of each of the second-1 frame portions 121' (see...) Figure 7 The oxide layer 40' can also be constant. The oxide layer 40' can surround the side and bottom surfaces of the second-1 frame portion 121'. In one embodiment, for example, the oxide layer 40' can contact the side and bottom surfaces of the second-1 frame portion 121'. In another embodiment, for example, the oxide layer 40' can be disposed on the side and bottom surfaces of the second-1 frame portion 121' having an inverted triangular shape. The second-1 frame portion 121' can be spaced apart from the base substrate 10 by the oxide layer 40'.

[0084] refer to Figure 12 Etching the base substrate 10 (see Figure 11 The lower surface of the frame is used to form the first frame part 111.

[0085] refer to Figure 13 It can remove oxide layer 40' (see Figure 12 To finally manufacture mask 100'.

[0086] Figures 14 to 19 This is a diagram illustrating a method for manufacturing a mask 100'' according to an embodiment. Figures 14 to 19 The manufacturing process is illustrated schematically. Figure 4 An implementation of the method for mask 100'' shown is described below. Figure 14 and Figure 19 The same or similar elements shown are marked with the same reference numerals as those used above, and any repeated detailed descriptions will be omitted or simplified.

[0087] refer to Figure 14 A layer 20 (or a first layer) is formed on a base substrate 10, and a layer 30 (or a second layer) is formed below the base substrate 10. The second layer 30 may include the same material as the first layer 20, and may include a different material from the base substrate 10. In some embodiments, for example, the second layer 30 may include a second material, namely silicon nitride (SiN). x As a result, silicon nitrides (SiN) can be formed. x Silicon (Si)-Silicon (Si)-Silicon Nitride (SiN) x The second layer 30 has a sandwich structure. The second layer 30 can have the same thickness t1 as the first layer 20.

[0088] Then, they can be executed sequentially. Figures 15 to 17 The process shown is such that, except for the second layer 30 formed beneath the base substrate 10, Figures 15 to 17 The process shown can be used with Figures 6 to 8 The process is performed in the same manner as described in the document.

[0089] refer to Figure 18 Etch the second layer 30 (see Figure 17 The lower surface of the substrate 10 and the base substrate 10 (see Figure 17 The lower surface of the frame forms the first-1 frame portion 111 and the first-3 frame portion 113 arranged below the first-1 frame portion 111.

[0090] refer to Figure 19 It can remove oxide layer 40 (see Figure 18 To ultimately manufacture a 100'' mask.

[0091] Figure 20 This is a plan view of the display device DD according to the embodiment. Figure 20The display device DD can be manufactured using the embodiments of mask 100, 100' or 100'' described above.

[0092] refer to Figure 20 An implementation of a display device DD may include a display area DA and a non-display area NDA. The display device DD displays an image through the display area DA. The non-display area NDA is arranged around the display area DA.

[0093] Display device DD may include base layer SUB, sub-pixels SP and / or pads PD.

[0094] Subpixels SP are arranged on the base layer SUB in the display area DA. Subpixels SP can be arranged in a matrix on a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the implementation is not limited to this. In one implementation, for example, subpixels SP can be arranged in a zigzag pattern on the first direction DR1 and the second direction DR2. In another implementation, for example, subpixels SP can be arranged in a pentile pattern. The first direction DR1 can be a row direction, and the second direction DR2 can be a column direction. Two or more subpixels in subpixels SP can constitute a pixel PXL.

[0095] Components for controlling the sub-pixel SP can be arranged on the base layer SUB in the non-display area NDA. In an implementation, for example, wiring connected to the sub-pixel SP, such as gate lines and data lines, can be arranged in the non-display area NDA.

[0096] The pad PD is placed on the base layer SUB in the non-display area NDA. The pad PD can be electrically connected to the sub-pixel SP via wiring. In an implementation, for example, the pad PD can be connected to the sub-pixel SP via a data line.

[0097] Voltages and signals for the operation of components included in the display device DD can be provided from the driver integrated circuit via pad PD. In some embodiments, for example, data lines can be connected to the driver integrated circuit via pad PD. In some embodiments, for example, power supply voltage can be received from the driver integrated circuit via pad PD.

[0098] The circuit board can be electrically connected to the pads (PD) using conductive adhesive components such as anisotropic conductive layers. The circuit board can be a flexible circuit board or a flexible film with a flexible material. Driver integrated circuits can be mounted on the circuit board and electrically connected to the pads (PD).

[0099] The display area DA can have various shapes. The display area DA can have a closed-loop shape including straight edges and / or curved edges. In embodiments, for example, the display area DA can have shapes such as polygons, circles, semicircles, and ellipses when viewed from a third-party direction DR3. Here, the third-party direction DR3 can be the thickness direction of the display device DD.

[0100] The display device DD may have a flat display surface. However, the implementation is not necessarily limited to this. In some implementations, for example, the display device DD may have a display surface that is at least partially circular. The display device DD may be flexible, foldable, or rollable. The display device DD and / or the base layer SUB may include a material with flexible properties.

[0101] Figure 21 It is a plan view of the first sub-pixel SP1 to the third sub-pixel SP3 according to the implementation method.

[0102] refer to Figure 21 In an implementation, pixel PXL may include first sub-pixels SP1 to third sub-pixels SP3 arranged on the first direction DR1.

[0103] The first sub-pixel SP1 may include a first emitting region EMA1 and a non-emitting region NEA surrounding the first emitting region EMA1. The second sub-pixel SP2 may include a second emitting region EMA2 and a non-emitting region NEA surrounding the second emitting region EMA2. The third sub-pixel SP3 may include a third emitting region EMA3 and a non-emitting region NEA surrounding the third emitting region EMA3.

[0104] The first emission region EMA1 can be the first emission layer EML1 from the first sub-pixel SP1 (see...). Figure 22 The second emission region EMA2 can be the region from which light is emitted from the second emission layer EML2 of the second sub-pixel SP2 (see [link to EML2]). Figure 22 The third emission region EMA3 can be the region from which light is emitted from the third emission layer EML3 of the third sub-pixel SP3 (see [link to EML3]). Figure 22 The area from which light is emitted.

[0105] Figure 22 It is along Figure 21 A cross-sectional view of the first sub-pixel SP1 to the third sub-pixel SP3 cut off by line II-II'.

[0106] refer to Figure 22The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 each include a first emission region EMA1, a second emission region EMA2, and a third emission region EMA3, and the non-emission region NEA can be located between the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0107] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include a pixel circuit layer PCL, a display device layer DPL, and / or a thin film encapsulation layer TFE arranged sequentially on the base layer SUB.

[0108] The base layer SUB can form or provide a base surface. The base layer SUB may include a transparent insulating material to transmit light. The base layer SUB can be a rigid substrate or a flexible substrate. A rigid substrate can be, for example, a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystalline glass substrate. A flexible substrate can be, for example, a film substrate comprising a polymeric organic material and a plastic substrate. In embodiments, for example, the flexible substrate may include, but is not limited to, at least one selected from polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. In embodiments, for example, the base layer SUB may be a substrate comprising silicon. According to an embodiment, the display device DD may be an OLED-on-silicon (OLEDoS) display device comprising a display panel formed on a silicon substrate.

[0109] The pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, a passivation layer PSV, and / or a via layer VIA, which are sequentially stacked on the base layer SUB on the third-direction DR3.

[0110] The buffer layer BFL can be an inorganic insulating layer comprising inorganic materials. The buffer layer BFL may include materials selected from, for example, silicon nitrides (SiN). x ), silicon oxide (SiO) x ), silicon nitride oxide (SiO) x N y ) and aluminum oxide (AlO) x At least one of the inorganic compounds. The buffer layer BFL can be a single layer, but it can also be a multilayer structure with at least two layers. In an embodiment where the buffer layer BFL is multilayered, the layers may comprise the same or different materials from each other. In another embodiment, the buffer layer BFL may be omitted, depending on the material and processing conditions of the base layer SUB.

[0111] Transistor T can be disposed on buffer layer BFL. Transistor T may include active pattern ACT, gate electrode GE, first transistor electrode TE1 and / or second transistor electrode TE2.

[0112] The active pattern ACT can be disposed on the buffer layer BFL. The active pattern ACT can include polysilicon semiconductors. In an embodiment, for example, the active pattern ACT can be formed by a low-temperature polysilicon process. However, the invention is not limited thereto, and the active pattern ACT can include oxide semiconductors, metal oxide semiconductors, etc.

[0113] An active pattern (ACT) may include a channel region, a first contact region connected to one end of the channel region, and a second contact region connected to the opposite end of the channel region. The channel region, the first contact region, and the second contact region may include semiconductor layers that are doped or undoped. In some embodiments, for example, the first and second contact regions may include semiconductor layers doped with impurities, and the channel region may include an undoped semiconductor layer. As an impurity, for example, a p-type impurity may be used, but it is not limited thereto. One of the first and second contact regions may be a source region, and the other may be a drain region.

[0114] The gate insulating layer GI can be disposed on the active pattern ACT. The gate insulating layer GI can be an inorganic layer (or inorganic insulating layer) comprising an inorganic material. In an embodiment, for example, the gate insulating layer GI may comprise materials such as silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon nitride oxide (SiO) x N y ) and aluminum oxide (AlO) x The gate insulating layer GI is at least one of the inorganic compounds. However, the material of the gate insulating layer GI is not limited to the embodiments described above. According to embodiments, the gate insulating layer GI may include an organic layer (or an organic insulating layer) containing organic materials. The gate insulating layer GI may be a single layer, but may also be a multilayer with at least two layers.

[0115] The gate electrode GE can be disposed on the gate insulating layer GI. The gate electrode GE can overlap with the channel region of the active pattern ACT on the third-direction DR3. The gate electrode GE can include a single layer comprising at least one of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag) and alloys thereof, or a double-layer or multi-layer structure of a low-resistance material such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) or silver (Ag) to reduce wiring resistance.

[0116] The interlayer insulating layer (ILD) can be disposed on the gate electrode GE. The interlayer insulating layer (ILD) may include the same material as the gate insulating layer GI, or may include one or more materials selected from those listed above as constituent materials of the gate insulating layer GI.

[0117] The first transistor electrode TE1 and the second transistor electrode TE2 can be disposed on the interlayer insulating layer ILD. The first transistor electrode TE1 of transistor T can contact the first contact region of the active pattern ACT through a contact hole penetrating the interlayer insulating layer ILD and the gate insulating layer GI. In an embodiment where the first contact region is the source region, the first transistor electrode TE1 can be the first source electrode.

[0118] The second transistor electrode TE2 of transistor T can contact the second contact region at the opposite end of the active pattern ACT through a contact hole defined by the interlayer insulating layer ILD and the gate insulating layer GI. When the second contact region is a drain region, the second transistor electrode TE2 can be the second drain electrode.

[0119] The first transistor electrode TE1 and the second transistor electrode TE2 may include the same material as the gate electrode GE, or may include one or more materials selected from the materials listed above as constituent materials of the gate electrode GE.

[0120] The passivation layer PSV can be disposed on the first transistor electrode TE1 and the second transistor electrode TE2. The passivation layer PSV (e.g., a protective layer) can be an inorganic layer (or inorganic insulating layer) containing inorganic materials or an organic layer (or organic insulating layer) containing organic materials. The inorganic layer can, for example, include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO) x N y ) and aluminum oxide (AlO) x The organic layer may include at least one of the inorganic compounds selected from, for example, polyacrylate resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins, polyphenylene sulfide resins, and benzocyclobutene resins.

[0121] The passivation layer PSV may include the same material as the interlayer insulating layer (ILD), but the implementation is not necessarily limited to this. The passivation layer PSV may be a single layer, but it may also be a multilayer structure with at least two layers.

[0122] The via layer VIA can be disposed on the passivation layer PSV. The via layer VIA can include the same material as the passivation layer PSV, or can include one or more materials selected from the constituent materials of the passivation layer PSV, exemplified by the passivation layer PSV. In an embodiment, the via layer VIA can be an organic layer including an organic material.

[0123] The display device layer (DPL) can be arranged on the pixel circuit layer (PCL). The display device layer (DPL) may include light-emitting devices (e.g., LD1 to LD3). The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may each include the first light-emitting device LD1, the second light-emitting device LD2, and the third light-emitting device LD3, respectively.

[0124] The first light-emitting device LD1 may include an anode AE, a first emitting layer EML1, and a cathode CE. The second light-emitting device LD2 may include an anode AE, a second emitting layer EML2, and a cathode CE. The third light-emitting device LD3 may include an anode AE, a third emitting layer EML3, and a cathode CE. For example, the first light-emitting device LD1, the second light-emitting device LD2, and the third light-emitting device LD3 may be top-emitting organic light-emitting devices.

[0125] The anodes AE of each sub-pixel SP are arranged in the emission regions EMA1, EMA2, and EMA3, and may be spaced apart from each other. The anode AE ​​of each sub-pixel SP can be electrically connected to the first transistor electrode TE1 of the transistor T of each sub-pixel SP through a contact hole defined by the via layer VIA and the passivation layer PSV.

[0126] A dam PDL can be placed on the anode AE. The dam PDL can define (or separate) the emission regions EMA1, EMA2, and EMA3 of each sub-pixel SP. The dam PDL may include openings that partially expose the anode AE ​​of each sub-pixel SP.

[0127] The dam PDL can be an organic insulating layer comprising organic materials. Examples of organic materials may include acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, etc. However, this disclosure is not limited thereto, and the dam PDL can also be an inorganic insulating layer comprising inorganic materials.

[0128] According to embodiments, the diaphragm PDL may include a light-absorbing material, or a light-absorbing agent may be applied to absorb light introduced from the outside. In embodiments, for example, the diaphragm PDL may include a carbon-based black pigment. However, the invention is not necessarily limited thereto, and the diaphragm PDL may include opaque metallic materials such as chromium (Cr), molybdenum (Mo), an alloy of molybdenum (Mo) and titanium (Ti) (MoTi), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), manganese (Mn), cobalt (Co), or nickel (Ni) having a high light absorption rate.

[0129] The emitter layer EML of each sub-pixel SP can be arranged on the anode AE ​​exposed by the diaphragm PDL. The cathode CE can be arranged on the emitter layer EML. The cathode CE can be arranged throughout all the first sub-pixels SP1 to the third sub-pixels SP3. In an embodiment, for example, the cathode CE can be set as a common electrode, but is not necessarily limited to this.

[0130] The cathode CE may include a metal layer, such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and alloys thereof, and / or a transparent conductive layer such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO). According to embodiments, the cathode CE may include a multilayer comprising at least two thin metal layers, for example, a three-layer ITO / Ag / ITO.

[0131] A thin-film encapsulation layer (TFE) can be disposed on the display device layer (DPL). The TFE can have a single-layer or multi-layer structure. The TFE can include an insulating layer covering the light-emitting devices (e.g., LD1 to LD3). The TFE can include at least one inorganic layer and at least one organic layer. In some embodiments, for example, the TFE can have a structure in which inorganic and organic layers are alternately stacked. In some embodiments, for example, the TFE can include a first inorganic layer, an organic layer disposed on the first inorganic layer, and a second inorganic layer disposed on the organic layer.

[0132] The sensing layer TS can be disposed on the thin-film encapsulation layer TFE. The sensing layer TS may include a first insulating layer INS1, a first conductive layer MT1, a second insulating layer INS2, a second conductive layer MT2 and / or a third insulating layer INS3.

[0133] The first insulating layer INS1 can be disposed on the thin-film encapsulation layer TFE. The first insulating layer INS1 can be an inorganic insulating layer comprising inorganic materials. The inorganic insulating layer can include inorganic insulating materials such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO) x N y ), aluminum oxide (Al) x O y ), titanium oxide (TiO) x ), tantalum oxide (Ta x O y ), hafnium oxide (HfO) x ) or zinc oxide (ZnO) xAccording to the implementation, the first insulating layer INS1 can be omitted or can be configured as the top layer of the thin-film encapsulation layer TFE.

[0134] The first conductive layer MT1 may be disposed on the first insulating layer INS1. The first conductive layer MT1 may be partially open so as not to overlap with the light-emitting device (e.g., LD1, LD2, or LD3) of each sub-pixel SP. In an embodiment, for example, the first conductive layer MT1 may be disposed to overlap with the non-emitting region NEA surrounding the emitting regions EMA1, EMA2, and EMA3.

[0135] The first conductive layer MT1 may include a metal layer or a transparent conductive layer. In embodiments, for example, the metal layer may include at least one selected from molybdenum, titanium, copper, aluminum, and their alloys. The transparent conductive layer may include, but is not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, or metal nanowires. The first conductive layer MT1 may form a connection electrode for connecting to the sensing electrode.

[0136] The second insulating layer INS2 may be disposed on the first conductive layer MT1. The second insulating layer INS2 may include the same material as the first insulating layer INS1 described above, or may include one or more materials selected from the materials listed above as constituent materials of the first insulating layer INS1.

[0137] The second conductive layer MT2 can be disposed on the second insulating layer INS2. The second conductive layer MT2 can be partially open without overlapping with the light-emitting device (e.g., LD1, LD2, or LD3) of each sub-pixel SP. In an embodiment, for example, the second conductive layer MT2 can be disposed to overlap with the non-emitting region NEA surrounding the emitting regions EMA1, EMA2, and EMA3.

[0138] The second conductive layer MT2 may include the same material as the first conductive layer MT1 described above, or may include one or more materials selected from the constituent materials of the first conductive layer MT1.

[0139] The second conductive layer MT2 can be electrically connected to the first conductive layer MT1 through a contact hole defined by the second insulating layer INS2. The second conductive layer MT2 can form a sensing electrode.

[0140] The third insulating layer INS3 may be disposed on the second conductive layer MT2. The third insulating layer INS3 may be an organic insulating layer comprising organic materials. However, this disclosure is not necessarily limited thereto, and according to embodiments, the third insulating layer INS3 may comprise an inorganic layer or may have a structure in which organic and inorganic layers are alternately stacked.

[0141] The light-shielding layer LBP can be disposed on the display device layer DPL, the thin-film encapsulation layer TFE, and / or the sensing layer TS. The light-shielding layer LBP may include openings that overlap with the light-emitting devices (e.g., LD1, LD2, or LD3). In an embodiment, for example, the light-shielding layer LBP may be disposed to overlap with the non-emitting region NEA surrounding the emitting regions EMA1, EMA2, and EMA3.

[0142] The light-shielding layer (LBP) may include a light-shielding material to prevent light leakage and color mixing defects. In embodiments, for example, the LBP may include, but is not limited to, a black matrix. According to embodiments, the LBP may include carbon black (CB) and / or titanium black (TiBK).

[0143] A color filter layer (CFL) can be placed on a light-shielding layer (LBP). The color filter layer (CFL) can include color filters CF1 to CF3 that match the colors of each sub-pixel SP. By setting color filters CF1 to CF3 corresponding to the colors of the first sub-pixel SP1 to the third sub-pixel SP3 respectively, a full-color image can be displayed.

[0144] The color filter layer CFL may include a first color filter CF1 disposed in a first sub-pixel SP1 to selectively transmit light emitted from the first sub-pixel SP1, a second color filter CF2 disposed in a second sub-pixel SP2 to selectively transmit light emitted from the second sub-pixel SP2, and a third color filter CF3 disposed in a third sub-pixel SP3 to selectively transmit light emitted from the third sub-pixel SP3.

[0145] In the implementation, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can be a red color filter, a green color filter, and a blue color filter, respectively, but are not necessarily limited to these.

[0146] The first color filter CF1 may include a color filter material that selectively transmits light of a first color (or red). In an embodiment, for example, if the first sub-pixel SP1 is a red sub-pixel, the first color filter CF1 may include a red color filter material.

[0147] The second color filter CF2 may include a color filter material that selectively transmits light of a second color (or green). In an embodiment, for example, if the second sub-pixel SP2 is a green sub-pixel, the second color filter CF2 may include a green color filter material.

[0148] The third color filter CF3 may include a color filter material that selectively transmits light of a third color (or blue). In an embodiment, for example, if the third sub-pixel SP3 is a blue sub-pixel, the third color filter CF3 may include a blue color filter material.

[0149] An outer coating OC can be provided on the color filter layer CFL. The outer coating OC can include various materials suitable for protecting the underlying layer from foreign materials such as dust and moisture. In embodiments, for example, the outer coating OC can include at least one selected from inorganic and organic insulating layers. In embodiments, for example, the outer coating OC can include epoxy resin, but the embodiments are not limited thereto.

[0150] Figure 23 This is a flowchart illustrating a method for manufacturing a display device DD according to an embodiment. The method for manufacturing the display device DD may be to use the embodiments described above, such as mask 100, 100', or 100'', to manufacture the display device DD (see [link to documentation]). Figure 20 The method.

[0151] refer to Figure 23 An embodiment of the method for manufacturing a display device may include forming a pixel circuit layer on a substrate (S100), forming a light-emitting device on the pixel circuit layer (S200), and forming an encapsulation layer on the light-emitting device (S300).

[0152] In process S100, which forms a pixel circuit layer on a substrate, the pixel circuit layer can be formed on the substrate (or...) Figure 22 Patterned circuit devices can be placed on the substrate (SUB), and pixel circuit layers (PCL) can be formed on the substrate (see [reference]). Figure 22 ).

[0153] According to embodiments, conductive layers, insulating layers, etc., on a substrate can be formed based on conventional processes for manufacturing semiconductor devices. In embodiments, for example, the conductive or insulating layers on the substrate can be formed by photolithography, etched by various methods (wet etching, dry etching, etc.), and deposited by various methods (sputtering, chemical vapor deposition, etc.). This disclosure is not necessarily limited to specific examples.

[0154] In process S100, which forms the pixel circuit layer on the substrate, transistors T can be patterned on the substrate (see...). Figure 22 ).

[0155] In process S200, which forms the light-emitting device on the pixel circuit layer, the anode AE ​​(see...) Figure 22 ), EML1 to EML3 (see Figure 22 ) and cathode CE (see Figure 22 This can form a first light-emitting device LD1, a second light-emitting device LD2, and a third light-emitting device LD3 (see...). Figure 22 ).

[0156] In process S200, which forms the light-emitting device on the pixel circuit layer, the anode AE ​​can be patterned, and the dam PDL overlapping the anode AE ​​can be patterned (see [link to process flow]). Figure 22 ).

[0157] Subsequently, the deposition of the first emitter layers EML1 to the third emitter layers EML3 on the anode AE ​​can be performed. The first emitter layers EML1 to the third emitter layers EML3 can be deposited using the embodiments of masks 100, 100', or 100'' described above. In one embodiment, for example, the material used to form the first emitter layers EML1 to the third emitter layers EML3 can pass through the mask 100, 100', or 100'' and be disposed on the anode AE. Subsequently, the cathode CE can be formed on the first emitter layers EML1 to the third emitter layers EML3.

[0158] In process S300, which forms an encapsulation layer on a light-emitting device, the encapsulation layer (or Figure 22 A thin-film encapsulation layer (TFE) can be formed on the first light-emitting device LD1 to the third light-emitting device LD3. The underlying layer of the encapsulation layer TFE can be passivated.

[0159] The sensing layer TS can be arranged according to the implementation method (see Figure 22 ), light-shielding layer LBP (see Figure 22 ) and color filter layer CFL (see Figure 22 Furthermore, a display device DD according to the implementation method can be provided.

[0160] Figure 24 This is a block diagram of an electronic device 10 according to an embodiment.

[0161] refer to Figure 24 According to the embodiment, the display device DD (see Figure 20 This method is applicable to various types of electronic devices. In an embodiment, electronic device 10 includes the display device DD described above, and may also include other modules or devices with additional functions in addition to the display device DD. Electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0162] The processor 12 may include at least one selected from a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0163] The memory 13 can store data and / or information used to operate the processor 12 or the display module 11. When the processor 12 executes the application program stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11. The display module 11 can process the provided signals and output image information on the display screen.

[0164] The power module 14 may include a power module such as a power adapter or battery device, and a power conversion module. The power conversion module converts the power supplied by the power module and generates power to operate the electronic device 10.

[0165] According to the embodiments described above, at least one of the components of the electronic device 10 described above may be included in the display device DD. Furthermore, in terms of function, some of the individual modules included in a single module may be included in the display device DD, while other modules may be provided separately from the display device DD. In one embodiment, for example, the display module 11 is included in the display device DD, while the processor 12, memory 13, and power module 14 are not included in the display device DD but are provided separately in the electronic device 10.

[0166] Figure 25 Schematic diagrams of various embodiments of the electronic device 10 are shown.

[0167] refer to Figure 25 Application display device DD (see Figure 20 Various types of electronic devices 10 in the implementation of the ) may include: electronic devices for displaying images, such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, and desktop monitors 10_1e; wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays (HMDs) 10_2b, and smartwatches 10_2c; and automotive electronic devices 10_3 including display modules such as central information displays (CIDs) located on the dashboard, central instrument panels, vehicle dashboards, and interior mirror displays.

[0168] According to embodiments of the present invention, a mask that is easy to form into an inverted cone shape and an inverted cone angle, and has increased strength and reduced warpage, as well as a method for manufacturing the mask, can be provided.

[0169] The invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0170] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. Mask, including: A first frame, wherein a first opening is defined by the first frame; and The second frames are respectively arranged in the first opening, wherein each of the second frames defines a second opening smaller than the first opening. The first framework includes: Part 1-1 of the framework; and The first and second frame sections are arranged on the first and first frame sections. Each of the second frameworks includes: The second-1 frame section features a grid pattern; and The 2-2 frame section is arranged on the 2-1 frame section. Wherein, the first-1 frame portion and the second-1 frame portion include a first material, and The first-2 frame portion and the second-2 frame portion include a second material that is different from the first material.

2. The mask according to claim 1, wherein, The first material is silicon, and the second material is silicon nitride.

3. The mask according to claim 1, wherein, In cross-section, the second-2 frame portion has a rectangular shape.

4. The mask according to claim 1, wherein, In the cross-section, the width of the second-1 frame portion decreases as it moves away from the second-2 frame portion in the thickness direction of the mask.

5. The mask according to claim 4, wherein, In the cross-section, the second-first frame portion has an inverted conical shape.

6. The mask according to claim 5, wherein, The inverted cone angle of the second-first frame section is greater than 90°.

7. The mask according to claim 1, wherein, In cross-section, the second-1 frame portion has an inverted triangular shape.

8. The mask according to claim 1, wherein, The width of the upper surface of the second-1 frame portion facing the lower surface of the second-2 frame portion is smaller than the width of the lower surface of the second-2 frame portion.

9. The mask according to claim 1, wherein, The thickness of the second-1 frame portion is 1 μm or greater.

10. The mask according to claim 1, wherein, The thickness of each of the first-second frame portion and the second-second frame portion is 1 μm or less.

11. The mask according to claim 1, wherein, The first frame further includes: frame portions 1-3, disposed below frame portion 1-1, wherein frame portions 1-3 comprise the second material.

12. A method for manufacturing a mask, the method comprising: A layer is formed on the base substrate; The first-2 frame portion and the second-2 frame portion, including openings, are formed by etching the layer; A pattern with a width that decreases in cross-section as it moves away from the upper surface of the base substrate in the thickness direction is formed by etching the upper surface of the base substrate. The second-1 frame portion and the oxide layer surrounding the second-1 frame portion are formed by oxidizing the pattern; The first-1 frame portion is formed by etching the lower surface of the base substrate; as well as Remove the oxide layer.

13. The method according to claim 12, wherein, The base substrate comprises silicon, and the layer comprises silicon nitride.

14. The method according to claim 12, wherein, The thickness of the layer is 1 μm or less.

15. The method according to claim 12, wherein, Each of the patterns has a thickness of 1 μm or greater.

16. The method according to claim 12, wherein, The pattern has an inverted cone shape in cross-section.

17. The method according to claim 16, wherein, The inverted cone angle of the pattern is greater than 90°.

18. The method according to claim 16, wherein, The oxide layer surrounds the side surface of the second-first frame portion.

19. The method according to claim 12, wherein, In cross-section, the pattern has an inverted triangular shape, and The oxide layer surrounds the side and bottom surfaces of the second-first frame portion.

20. Electronic devices, including: processor; as well as A display device, including an emissive layer, wherein the display device displays an image in response to control by the processor. The emission layer is deposited using a mask according to claim 1.

Images