An on-chip frequency detection circuit

Abstract

This invention relates to an on-chip frequency detection circuit, comprising: a multi-mode frequency divider for obtaining a frequency-divided signal based on a preliminary detection frequency of the signal to be measured; and a gate signal controller for determining the frequency based on an initial state bit. a and end state bit b Generates a gate signal; a time-to-digital converter is used to count the rising edges of the reference signal during the gate time of the gate signal to obtain the counting result; a frequency calculation module is used to calculate the result based on the counting result, the frequency of the reference signal, and the start state bit. a and end state bit b The final detection frequency of the signal to be measured is obtained. This invention provides a broadband, high-precision, high-flexibility, low-power, and small-area frequency detection chip suitable for microwave and millimeter-wave frequency bands.

Description

Technical Field

[0001] This invention relates to the field of frequency detection technology, and more specifically to an on-chip frequency detection circuit. Background Technology

[0002] In the field of wireless radio frequency communication, to improve channel capacity and reduce interference between different frequency bands, high-frequency signals from different bands are often used as data transmission carriers, i.e., carrier waves. Traditional analog domain frequency detection devices need to know the carrier frequency range generated by the voltage-controlled oscillator (VCO) at the transmitter to ensure that the communication frequency bands of the transmitter, antenna, and data receiving modules are within the same range. Digital domain frequency detection methods, however, are mostly based on high-speed RF direct-sampling ADCs (Analog-to-Digital Converters) and software algorithms, which reduces the frequency detection speed. In high-speed communication systems, this detection method has extremely high requirements for real-time data transmission and interface data throughput, leading to complex system structures, high costs, and high power consumption, which is detrimental to chip integration and miniaturization.

[0003] Therefore, with the continuous increase in data rates of modern wireless communication systems, frequency detection modules are required to have properties such as high accuracy, small error, high flexibility, and fast real-time response. In addition, as the operating frequency of receivers has increased from sub-6GHz to microwave / millimeter-wave / terahertz bands, the matching frequency detection modules also need to achieve wide-range frequency detection functions in the high-frequency field.

[0004] Existing frequency detection modules fall into two categories. One type utilizes external digital signal processing (DSP) such as FPGAs (Field-Programmable Gate Arrays). In mid-to-low frequency circuits at the megahertz level, frequency detection is typically implemented using RF direct-sampling digital-to-analog converters (DACs) and external FPGA circuits or additional DSP modules. Compared to traditional analog circuits, this approach offers greater flexibility and adaptability to varying frequency ranges. However, due to the nature of digital signal processing, extremely high ADC sampling frequencies are required when processing high-frequency microwave signals, leading to a significant increase in data throughput and power consumption. This places extremely high demands on signal transmission links and interfaces, making this method unsuitable for microwave frequency detection. The other type uses phase-locked loop (PLL)-based frequency detection circuits, typically employing PLLs, voltage-controlled oscillators (VCOs), and phase detectors. It detects the frequency by comparing the phase difference between a reference frequency and the input signal frequency, continuously bringing the reference frequency closer to the target input frequency. This architecture is primarily used for precise frequency searching when the approximate range of the target frequency is known, but it is unsuitable for broadband frequency detection applications with unknown signal frequency ranges.

[0005] Therefore, providing a broadband, high-precision, highly flexible, low-power, and small-area frequency detection circuit suitable for microwave and millimeter-wave frequency bands has become an urgent problem to be solved. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides an on-chip frequency detection circuit. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides an on-chip frequency detection circuit, comprising: A multi-mode frequency divider is used to receive the signal under test and obtain the frequency-divided signal based on the initial detection frequency of the signal under test. A gate signal controller, connected to the multi-mode frequency divider, is used to receive the frequency-divided signal and, based on the initial state bit... a and end state bit b Generate a gate signal, wherein the initial state bit a Define the start time of the gate signal, and the end state bit. b Define the end time of the gate signal; A time-to-digital converter, connected to the gate signal controller, is used to receive the gate signal and a reset signal, and within the gate time of the gate signal, obtain a reference signal based on the oscillation generated by the reset signal, and count the rising edges of the reference signal to obtain a counting result; The frequency calculation module, connected to the time-to-digital converter, is used to calculate the frequency based on the counting result, the frequency of the reference signal, and the start state bit. a and the end state bit b The final detection frequency of the signal to be tested is obtained.

[0007] In one embodiment of the present invention, obtaining the frequency-divided signal based on the preliminary detection frequency result of the signal under test includes: When the initial detection frequency of the signal under test is greater than or equal to the preset frequency, the initial detection frequency of the signal under test belongs to the high-frequency range, and the multi-mode frequency divider switches to the high-frequency division mode to divide the signal under test. N The frequency-divided signal is obtained by further frequency division. When the initial detection frequency of the signal under test is less than the preset frequency, the initial detection frequency of the signal under test belongs to the low-frequency range. The multi-mode frequency divider switches to low-frequency division mode to divide the signal under test. M The frequency is divided again to obtain the frequency-divided signal, wherein... N > M .

[0008] In one embodiment of the present invention, the on-chip frequency detection circuit further includes a serial peripheral interface for providing the start state bit.a and the end state bit b .

[0009] In one embodiment of the present invention, the gate signal controller is connected to the serial peripheral interface and is specifically used to receive the frequency-divided signal and the start state bit. a and the end state bit b And according to the initial state bit a and end state bit b Generate a string of length ( b - a A gate signal with a frequency division period of 1. In one embodiment of the present invention, the serial peripheral interface is further configured to provide the reset signal; The time-to-digital converter includes: A multi-phase frequency source, connected to the serial peripheral interface, is used to receive the reset signal and start oscillating after receiving the reset signal to generate a reference signal; A counter, connected to the gate signal controller, is used to receive the gate signal and the reference signal, and count the rising edge of the reference signal during the gate time of the gate signal to obtain the counting result. In one embodiment of the present invention, based on the counting result, the frequency of the reference signal, and the start state bit... a and the end state bit b Obtaining the final detection frequency of the signal under test includes: The frequency calculation module is specifically used to calculate the frequency of the reference signal based on the counting result and the starting state bit. a and the end state bit b The frequency of the frequency-divided signal is obtained, and the frequency of the frequency-divided signal is expressed as:

[0010] in, The frequency of the signal after frequency division. For the counting results, The frequency of the reference signal; The final detection frequency of the signal under test is obtained based on the frequency of the divided signal. In one embodiment of the present invention, the on-chip frequency detection circuit further includes: The zero-crossing detection module, connected to the multi-mode frequency divider, is used to receive the modulation signal and extract the carrier information in the modulation signal by identifying the zero point of the modulation signal, so as to generate a carrier signal with the same carrier frequency as the modulation signal and transmit it to the multi-mode frequency divider as the signal to be tested. In one embodiment of the present invention, the zero-crossing detection module includes a multi-stage inverter. In one embodiment of the present invention, the on-chip frequency detection circuit further includes: An envelope detection module, connected to the gate signal controller, is used to receive the modulation signal, extract the envelope information of the modulation signal, and transmit the envelope information as an enable signal to the gate signal controller to control the operation of the gate signal controller.

[0011] In one embodiment of the present invention, the envelope detection module includes: An RC low-pass filter is used to receive the modulated signal and extract the envelope information of the modulated signal; A voltage comparator, connected to the RC low-pass filter and the gate signal controller, is used to compare the voltage of the envelope information with a reference voltage to obtain a comparison result, and generate an enable signal without envelope dips based on the comparison result and transmit it to the gate signal controller to control the operation of the gate signal controller.

[0012] Compared with the prior art, the beneficial effects of the present invention are as follows: The on-chip frequency detection circuit of this invention is based on the gate signal generation mechanism of the equal precision measurement method. By configuring start and end state bits, the gate signal length can be reconfigured, balancing the contradiction between measurement accuracy and response time when detecting signals in different frequency bands, further improving the flexibility of the module. With the advantages of TDC in time measurement, on-chip frequency detection is realized through actual circuitry, replacing the search measurement method of constantly adjusting and approximating the reference clock in traditional analog circuits. Finally, a broadband, high-precision, highly flexible, low-power, and small-area frequency detection chip suitable for microwave and millimeter-wave frequency bands is designed.

[0013] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0014] Figure 1 This is a circuit structure diagram of an on-chip frequency detection circuit provided by the present invention; Figure 2 This is a flowchart of the frequency detection process of an on-chip frequency detection circuit provided by the present invention; Figure 3 This is a waveform diagram of a key signal in the frequency detection process provided by the present invention; Figure 4 This is a circuit structure diagram of another on-chip frequency detection circuit provided by the present invention; Figure 5 This is a key waveform diagram of another on-chip frequency detection circuit provided by the present invention; Figure 6 This is a specific circuit structure diagram of another on-chip frequency detection circuit provided by the present invention. Detailed Implementation

[0015] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0016] Example 1 Traditional frequency detection technologies are mainly divided into two categories: digital frequency detection circuits based on high-speed sampling and digital signal processing, and analog frequency detection circuits based on feedback locking and frequency search. The two have fundamental differences in circuit structure, implementation method and performance characteristics, and each faces insurmountable structural defects, especially when applied to microwave / millimeter-wave bands, these defects are amplified.

[0017] Digital frequency detection circuits typically use a high-speed, high-resolution analog-to-digital converter to directly (or after a small amount of analog down-conversion) convert the radio frequency analog signal under test into a digital signal stream. This massive amount of data is then transmitted to an FPGA or a dedicated digital signal processor (DSP) to calculate the frequency of the signal by running digital signal processing algorithms.

[0018] In this circuit, the ADC's power consumption and design complexity increase approximately exponentially with the sampling rate. The high sampling rate required to capture microwave / millimeter-wave signals makes the ADC itself a power-intensive unit, contradicting the goal of low-power, miniaturized system-on-chip (SoC) integration. Even if the sampling rate requirement is met, the ADC's analog input bandwidth must be greater than the signal frequency. Designing extremely high-bandwidth ADC input buffers is extremely difficult, limiting the highest frequency of detectable signals, and the data stream generated by a GS / s-level ADC requires hundreds of Gbps of inter-chip transmission bandwidth. This forces the system to employ a complex multi-channel high-speed serial protocol, requiring precise clock distribution, strict synchronization, and complex link establishment and maintenance logic, significantly increasing system cost and design cycle time.

[0019] The fundamental flaw of digital frequency detection circuits stems from their "sample first, calculate later" circuit architecture paradigm. To process high-frequency signals, they must employ high-performance, high-power analog-to-digital converters (ADCs) at the very front end of the circuit, which in turn triggers a series of challenges in high-speed digital data transmission and processing, creating a bottleneck that is difficult to overcome in terms of performance, power consumption, cost, and integration.

[0020] In analog circuits, frequency detection typically employs a frequency search-iterative approximation approach. The core idea is to use a voltage-controlled oscillator (VCO) to generate a reference clock at a specific frequency. A comparison circuit then compares the frequency or phase of the reference clock with that of the signal under test (SUT). Based on the comparison results, the frequency of the reference clock generated by the VCO is iteratively updated to approximate the frequency of the SUT. The frequency search is complete when the frequency difference between the two signals is small or the phase difference remains constant. At this point, the frequency corresponding to the reference clock can be considered the frequency of the SUT. This approach cannot directly measure the frequency; instead, it approximates the frequency through multiple iterations of "guess-compare-adjust." Each iteration involves loop setup time, and the overall search time is directly related to the frequency uncertainty range, search step size, and loop bandwidth. To cover a wide frequency band, the total search time can be as long as tens of microseconds to milliseconds, which is insufficient for rapid frequency acquisition (such as radar pulse detection).

[0021] For analog frequency detection circuits, the detectable frequency range is fundamentally dependent on the electronic tuning range of the VCO. Designing a VCO with a continuous tuning range of multiple octaves in the microwave / millimeter-wave band is extremely difficult, usually requiring sacrifices in tuning linearity, phase noise, or output power flatness, and introducing additional techniques such as multi-core VCOs and band switching, which increases circuit complexity and area power consumption, affecting the measurement accuracy of frequency detection.

[0022] Furthermore, in many PLL-based structures, the detection accuracy or resolution is ultimately limited by the frequency of its internal reference clock. The gain nonlinearity of the PD in the analog circuit, the noise of the resistors and operational amplifiers in the loop filter, the phase noise of the VCO, as well as the power supply and substrate noise, all introduce errors, ultimately affecting the accuracy and stability of the locking point.

[0023] In modern radio frequency communication, when the input signal is an amplitude- or phase-modulated signal (such as AM or QAM) rather than a pure continuous wave (CW), fluctuations in its envelope or phase transitions can be misinterpreted as phase errors by the PLL's phase detector. This can lead to incorrect loop adjustment or even loss of lock, making it impossible to correctly track or measure the carrier frequency. Furthermore, to measure the carrier frequency of the modulated signal, a complex carrier recovery circuit is typically added to the front end of the PLL, further increasing the system's complexity, area, and power consumption.

[0024] The fundamental flaw of analog frequency detection schemes stems from their "feedback-adjustment-lock" circuit architecture paradigm. This architecture is essentially an indirect, iterative search process, whose speed, range, and accuracy are firmly limited by the core analog loop and iterative algorithm. This architecture is mainly used for precise frequency searches when the approximate range of the target frequency is known, and it is difficult to realize frequency detection applications with wide bandwidth and unknown signal frequency ranges.

[0025] Digital frequency measurement circuits require the use of a direct-sampling ADC to fully sample the signal to be detected. The high ADC sampling rate and digital circuit clock frequency lead to a significant increase in data throughput and power consumption, placing extremely high demands on the signal transmission link and interface. Therefore, this method is difficult to apply to microwave frequency detection. In phase-locked loop (PLL)-based frequency detection modules, the algorithm is based on a frequency search-iterative approximation approach. However, the system response time, chip area, and power consumption are far inferior to those of digital frequency detection circuits, and the frequency detection range is limited, making it difficult to achieve broadband frequency detection applications for unknown signal frequencies.

[0026] Therefore, considering the requirements of wide frequency detection range, high detection accuracy, and high flexibility in practical applications, this invention improves upon the shortcomings of traditional frequency detection circuits by leveraging the advantages of TDC (Time-to-Digital Converter) in time measurement to achieve direct on-chip frequency detection. Please see [link to relevant documentation]. Figure 1 and Figure 2 , Figure 1 This is a circuit structure diagram of an on-chip frequency detection circuit provided by the present invention. Figure 2 This is a flowchart illustrating the frequency detection process of an on-chip frequency detection circuit provided by the present invention. The on-chip frequency detection circuit provided by the present invention includes: A multi-mode frequency divider is used to receive the signal under test and obtain the divided signal based on the initial detection frequency of the signal under test. The gate signal controller, connected to a multi-mode frequency divider, receives the frequency-divided signal and determines its frequency based on the initial state bit. a and end state bit b Generate a gate signal, wherein the initial state bit a Define the start time and end status bit of the gate signal. b Define the end time of the gate signal; A time-to-digital converter, connected to a gate signal controller, is used to receive gate signals and reset signals. During the gate time of the gate signal, a reference signal is obtained based on the oscillation generated by the reset signal, and the rising edges of the reference signal are counted to obtain the counting result. The frequency calculation module, connected to the time-to-digital converter, is used to calculate the frequency based on the counting result, the frequency of the reference signal, and the start-state bit. a and end state bit b The final detection frequency of the signal to be tested is obtained.

[0027] Specifically, in this embodiment, the multi-mode frequency divider first receives the signal to be tested (which can be a sinusoidal signal). Then, the multi-mode frequency divider performs frequency division based on the magnitude of the initial detection frequency of the signal to be tested, thereby obtaining the frequency-divided signal. The initial detection frequency can be obtained by first running the on-chip frequency detection circuit once using default settings, and using the output of the on-chip frequency detection circuit at this time as the initial detection frequency. Afterwards, the multi-mode frequency divider transmits the frequency-divided signal to the gate signal controller. The gate signal controller can then determine the initial detection frequency based on the equal-precision measurement method and the initial state position. and end state bit A gate signal is generated. Then, the gate signal and a reset signal are transmitted to a time-to-digital converter (TD-SCDMA). Upon receiving the reset signal, the TD-SCDMA generates a known frequency through oscillation. The reference signal is used, and the rising edges of the reference signal are counted within the corresponding gate time to obtain the counting result. Based on this, the frequency of the divided signal can be determined. The frequency of the divided signal is calculated. Then, by using the operating mode of the multi-mode frequency divider, the final detection frequency of the signal under test can be derived backwards. .

[0028] This invention uses an on-chip frequency detection circuit based on a time-to-digital converter to replace the traditional RF direct-sample ADC. With advancements in manufacturing processes, power supply voltages have decreased, and transistor intrinsic speeds have increased. Time measurement based on digital gate delays is more advantageous than analog voltage amplification. Therefore, the on-chip frequency detection circuit of this invention can achieve high-precision, fast-response, and wide-range frequency measurement, while avoiding the pressure of high-speed signals on the interactive interface caused by the large data throughput in digital domain frequency detection modules.

[0029] In one specific embodiment, the multi-mode frequency divider is specifically used to: receive the signal under test; when the initial detection frequency of the signal under test is greater than or equal to a preset frequency, the initial detection frequency of the signal under test belongs to the high-frequency range; the multi-mode frequency divider switches to high-frequency division mode to perform frequency division on the signal under test. N The frequency is obtained by the next frequency division, and the frequency of the frequency-divided signal is: , For initial frequency detection, if the initial detection frequency of the signal under test is lower than the preset frequency, then the initial detection frequency of the signal under test belongs to the low-frequency range. The multi-mode frequency divider switches to low-frequency division mode to perform frequency division on the signal under test. M The frequency is divided again to obtain the divided signal, and the frequency of the divided signal is... ,in, N > M For example, the preset frequency is 10GHz. N It is 8.M The value is 4.

[0030] Specifically, the on-chip frequency detection circuit in this embodiment can realize wide-range frequency detection function in different frequency bands according to different design standards of the multi-mode divider. When the initial detection frequency of the signal under test is low, the multi-mode divider can be switched to low-frequency division mode to perform frequency detection on the signal under test. M Frequency detection is performed after secondary frequency division. By appropriately controlling the timing of the gate signal, the system's response speed can be improved. When the initial detection frequency of the signal under test is high, the multi-mode frequency divider can be switched to high-frequency division mode to further divide the signal under test. N After the frequency division, the length of the control gate is increased to ensure that the accuracy of frequency detection is not reduced due to the frequency of the signal under test being close to the reference clock. This widens the frequency range that the frequency detection circuit can detect, saves chip cost and area, and ultimately achieves a detection accuracy of 99.5%.

[0031] In a specific embodiment, such as Figure 1 As shown, the on-chip frequency detection circuit also includes a Serial Peripheral Interface (SPI) for providing a start status bit. a and end state bit b The serial peripheral interface is also used to provide a reset signal.

[0032] Specifically, the initial state bit of the gate can be determined based on the configuration information input into the serial peripheral interface. a and end state bit b .

[0033] In one specific embodiment, the gate signal controller is connected to a serial peripheral interface, specifically for receiving the frequency-divided signal and the start status bit. a and end state bit b And according to the initial state bit a and end state bit b Generate a string of length ( b - a A gate signal with a frequency division period of 1.

[0034] Specifically, the start status bit of the gate is configured through the serial peripheral interface. a and end state bit b initial state bit a and end state bit b The period numbers of the frequency-divided signals corresponding to the gate opening and closing times are defined, along with the initial state bit. a For from the first b The gate opens at the edge of the divided signal cycle, defining the start time of the gate signal and the end status bit. b When the count reaches the th bThe gate closes at the edge of the divided signal cycle, defining the end time of the gate signal. Therefore, based on the equal-precision measurement method, a length of [value missing] can be generated. The gate signal has a frequency division period of one.

[0035] In a specific embodiment, such as Figure 1 As shown, the time-to-digital converter includes: A multi-phase frequency source, connected to a serial peripheral interface, is used to receive a reset signal and starts oscillating upon receiving the reset signal to generate a reference signal; The counter, connected to the gate signal controller, is used to receive the gate signal and the reference signal, and count the rising edge of the reference signal during the gate time of the gate signal to obtain the counting result.

[0036] Specifically, after the gate signal and reset signal are sent to the time-to-digital converter, the multi-phase frequency source receives the reset signal and begins to oscillate to generate a known frequency. The reference signal is used as the reference signal, and the counter counts the rising edges of the reference signal within the corresponding gate time to obtain the counting result. .

[0037] In one specific embodiment, the frequency calculation module is specifically used to calculate based on the counting result, the frequency of the reference signal, and the start state bit. a and end state bit b The frequency of the divided signal is obtained, and the final detection frequency of the signal under test is obtained based on the frequency of the divided signal. The frequency of the divided signal is expressed as:

[0038] in, The frequency of the signal after frequency division. For the counting results, The frequency of the reference signal.

[0039] Specifically, after determining the frequency of the divided signal using the above formula, the frequency of the signal under test can be derived by working backward from the operating mode of the multi-mode frequency divider. If it is a high-frequency division mode, then If it is a low-frequency crossover mode, then During frequency detection, the waveforms of each key signal are shown below. Figure 3 As shown.

[0040] This invention designs a frequency detection circuit that achieves a wide frequency range and high detection accuracy within the microwave and millimeter-wave range. By introducing circuits such as a time-to-digital converter (TDC) and a counter, a wideband, highly integrated, highly flexible, and low-power frequency detection chip is realized. A multi-phase frequency source in the TDC generates high-frequency reference clocks of different phases. The input signal is captured over a period of time, and the number of cycles of both the input signal and the reference clock are counted. The target frequency can be calculated by the ratio of their cycles and the frequency of the reference clock. This on-chip frequency detection circuit avoids the high sampling rates introduced by direct RF sampling and digital frequency detection circuits, and breaks the traditional "search-approximation" paradigm of analog frequency detection circuits. It expands the applicability and flexibility of the frequency detection module and achieves high-precision frequency detection within the microwave range.

[0041] For a dual-mode configurable frequency divider design in the microwave / millimeter-wave bands, the on-chip frequency detection circuit provided by this invention supports configurable switching between low-frequency and high-frequency modes, intelligently adapting to the detection requirements of different frequency bands. This enables high-precision detection of microwave and millimeter-wave signals, expanding the frequency detection range and application scenarios of the module and improving its flexibility. Furthermore, based on a gate signal generation mechanism using equal-precision measurement, the gate signal length is reconfigurable by configuring start and end state bits, balancing the trade-off between measurement accuracy and response time when detecting signals in different frequency bands, further enhancing the module's flexibility.

[0042] Compared to existing frequency detection schemes, the on-chip frequency detection circuit provided by this invention integrates the frequency detection function, which traditionally relies on FPGAs or external discrete components, onto a single chip. It can be applied to high-frequency scenarios such as 5G / 6G, millimeter-wave communication, satellite communication, and radar systems, achieving a high-precision, high-flexibility, low-power, and small-area frequency detection module. This frequency detection circuit, with its wide frequency range and high detection accuracy, leverages the architectural advantages of TDC in time measurement to achieve on-chip frequency detection through actual circuitry, replacing the traditional analog circuit's method of continuously adjusting and approximating a reference clock. Ultimately, it designs a broadband, high-precision, high-flexibility, low-power, and small-area frequency detection chip suitable for microwave and millimeter-wave frequency bands.

[0043] Example 2 This invention considers that frequency detection circuits in the field of communication often need to directly detect signals with modulation information to determine their carrier frequency, facilitating the selection of the local oscillator signal frequency in the receiver's downmixing step. Therefore, based on the on-chip frequency detection circuit provided in Embodiment 1, another on-chip frequency detection circuit is provided, enabling it to directly process modulated signals. Please refer to [link to related documentation]. Figure 4 , Figure 4This is a circuit diagram of another on-chip frequency detection circuit provided by the present invention. This on-chip frequency detection circuit not only includes the frequency detection core unit of Embodiment 1 (the frequency detection core unit includes a multi-mode divider, a gate signal controller, a time-to-digital converter, and a frequency calculation module), but also includes: The zero-crossing detection module is connected to the multi-mode frequency divider. It is used to receive the modulated signal and extract the carrier information in the modulated signal by identifying the zero point of the modulated signal. It generates a first carrier signal with the same carrier frequency as the modulated signal as the signal to be tested and transmits it to the multi-mode frequency divider. The envelope detection module is connected to the gate signal controller. It is used to receive the modulated signal, extract the envelope information of the modulated signal, and transmit the envelope information as the first enable signal to the gate signal controller to control the operation of the gate signal controller.

[0044] Specifically, such as Figure 4 From a circuit perspective, the on-chip frequency detection circuit in this embodiment inserts an envelope detection module and a zero-crossing detection module between the antenna end and the frequency detection core unit. The zero-crossing detection module extracts the carrier information from the modulation signal by identifying the zero points of the modulation signal, and generates a carrier frequency that corresponds to the modulation signal. A square wave (first carrier signal) of uniform frequency is fed into the multimode divider as the signal to be tested, and the waveform changes as follows: Figure 5 As shown, after undergoing the same detection process and obtaining the frequency of the divided signal, the carrier frequency can be calculated. The envelope detection module primarily ensures the accuracy of frequency detection results. In high-order QAM modulated signals, due to the presence of multiple frequency components, the signal exhibits discontinuous periodic characteristics in the time domain, such as... Figure 5 As indicated by the red mark, the signal near this point does not exhibit periodic positive and negative changes (this point is called the envelope dip). In this case, the first carrier signal generated by zero-crossing detection will have significant errors, leading to a severe decrease in the accuracy of subsequent frequency detection results.

[0045] Therefore, an envelope detection module is introduced to extract the envelope information of the modulation signal as an enable signal. When the modulation signal changes continuously and periodically, the enable signal is 1, the gate signal is opened, and the frequency detection core unit works normally. However, when the amplitude of the envelope is too small, that is, when the modulation signal is near the envelope concavity point, the enable signal jumps to 0, the gate signal is turned off, and the frequency detection stops, so as to avoid errors in the frequency detection result due to the envelope concavity point.

[0046] In an optional embodiment, please refer to Figure 6The zero-crossing detection module includes a multi-stage inverter, which is connected to a multi-mode frequency divider to receive the modulation signal, extract the carrier signal from the modulation signal, and transmit the carrier signal as the signal to be tested to the multi-mode frequency divider.

[0047] In an optional embodiment, the envelope detection module includes: An RC low-pass filter is used to receive modulated signals and extract the envelope information of the modulated signals. The voltage comparator, connected to the RC low-pass filter and the gate signal controller, is used to compare the voltage of the envelope information with the reference voltage to obtain the comparison result, and generate an enable signal without envelope dips based on the comparison result and transmit it to the gate signal controller to control the operation of the gate signal controller.

[0048] Specifically, the externally input modulation signal is filtered by an RC low-pass filter to extract the low-frequency envelope information. The voltage of this low-frequency envelope information is then compared with an externally set reference voltage. If the voltage is greater than or equal to the reference voltage, a high-level output is generated, and the enable signal is set to 1. This generates an enable signal without envelope dips, which is then sent to the gate signal generator, allowing the gate signal generator to operate normally. If the voltage is less than the reference voltage, a low-level output is generated, and the enable signal is set to 0, thus turning off the gate signal and stopping frequency detection. Additionally, the modulation signal is processed by a multi-stage inverter to extract the carrier signal, which is then transmitted as the signal to be measured to a multi-mode divider. This allows for minimizing chip power consumption and area while maintaining the highest possible TDC resolution. The multi-stage inverter has three stages in low-frequency division mode and four stages in high-frequency division mode.

[0049] This invention enables the on-chip frequency detection circuit to detect the frequency of AM-modulated or high-order QAM-modulated signal carriers by inserting an envelope detection module and a zero-crossing detection module. It can be applied to high-frequency scenarios such as 5G / 6G, millimeter-wave communication, satellite communication, and radar systems, providing the receiver with fast and accurate carrier frequency detection capabilities and improving the system's adaptability and stability.

[0050] Example 3 This invention provides an example of frequency detection for mid-to-low frequency unmodulated signals. In this embodiment, a mid-to-low frequency unmodulated signal with a frequency of 5.8 GHz and a power of 11 dBm is input to the on-chip frequency detection circuit of Embodiment 1. The frequency detection process is as follows: When designing an on-chip frequency detection circuit, the pulse period of the multi-phase frequency source is... Designed to be 90.5ps, and generating a reference clock with 24 different phases, this effectively increases the reference clock frequency by 24 times, thus improving the overall resolution of the TDC. The frequency of the equivalent reference signal The lower the frequency of the divided signal, the longer the generated gate signal and the higher the detection accuracy. However, the system response time will increase accordingly. Therefore, when testing low-frequency signals, the end state bit should be reduced appropriately to control the time of the frequency detection module.

[0051] The configuration information for this test is set via SPI. The multi-mode divider operates in low-frequency division mode. M =4, initial state bit End state bit After passing through the on-chip frequency detection circuit, the counting result is output. It is 366.

[0052] For the frequency of the signal under test After frequency division by 4, the signal frequency The length of the gate signal can be determined based on the configuration information. According to the principle of equal precision measurement:

[0053] Combining the above derivations, we get:

[0054] Therefore, the frequency value obtained by the frequency detection module can be calculated to be 5.7965764 GHz, and the error in this test is 0.06%. In addition, the frequency detection module was tested sequentially for mid-low frequency signals of 6 GHz and 8 GHz, and the test accuracy of the frequency detection module reached over 99.9% in all cases.

[0055] Example 4 This invention provides an example of frequency detection for a high-frequency 64QAM modulated signal. In this embodiment, a high-frequency 64QAM modulated signal with a frequency of 29 GHz, a modulation bandwidth of 500 MHz, and a power of 25 dBm is input to the on-chip frequency detection circuit of Embodiment 2. The frequency detection process is as follows: The frequency of the equivalent reference signal of the on-chip frequency detection circuit The lower the frequency of the divided signal, the longer the generated gate signal and the higher the detection accuracy. However, the system response time will increase accordingly. Therefore, when testing high-frequency signals, the end state bit needs to be increased appropriately to ensure the accuracy of frequency detection.

[0056] The configuration information for this test is set via SPI. The frequency divider operates in high-frequency division mode. N =8, initial state bit End state bit After passing through the frequency detection module, the counting result is output. The value is 293.

[0057] For the frequency of the signal under test After being divided by 8, the signal frequency... The length of the gate signal can be determined based on the configuration information. According to the principle of equal precision measurement:

[0058] Combining the above derivations, we get:

[0059] Therefore, the frequency value obtained by the frequency detection module can be calculated to be 28.963098 GHz, and the error in this test is 0.127%. In addition, the frequency detection module was tested sequentially with 11 GHz carrier and 100 MHz modulation bandwidth and 25 GHz carrier and 100 MHz modulation bandwidth 64QAM signals, and the test accuracy of the frequency detection module reached more than 99.5% in both cases.

[0060] Therefore, compared with traditional analog frequency detection circuits, the on-chip frequency detection circuit provided by this invention skips the complex and multi-step "compare-adjust-lock" iterative loop, resulting in a faster system response speed and reduced chip area and power consumption. Furthermore, based on the direct counting principle of TDC, its accuracy is determined by a highly stable on-chip reference clock and is unaffected by feedback loop noise. Utilizing a reconfigurable multi-mode divider module, it achieves an accuracy better than 99.5% in the microwave and millimeter-wave frequency bands, overcoming the problem of analog schemes being limited by reference frequency and loop noise, thus improving the accuracy of frequency measurement.

[0061] In contrast, digital domain frequency detection circuits implemented on programmable gate arrays (FPGAs) require ultra-high sampling rate analog-to-digital converters (ADCs) to fully sample the RF signal under test in order to ensure detection accuracy. This results in massive data throughput and interface pressure. This invention completely avoids this problem. The on-chip frequency detection circuit provided by this invention does not directly sample the high-frequency RF signal. Instead, it reduces the frequency through a front-end frequency divider and then uses a time-divided DC to perform extremely high-resolution time measurement of the period of the divided signal. Therefore, the system completely eliminates its dependence on ultra-high sampling rate ADCs and their associated massive data links, thus enabling economical and efficient coverage of a wide frequency band up to the millimeter-wave front end.

[0062] Meanwhile, in digital domain frequency detection circuits, the final error originates from one cycle of the reference clock. The accuracy of this invention is based on the time resolution of the TDC (Time-Digital Clock), reducing the detection error to within a few picoseconds. The total system delay is extremely low and predictable, making it suitable for scenarios with extremely high real-time requirements, such as radar pulse detection and rapid frequency locking in communication systems.

[0063] Compared to other traditional frequency detection circuits, this invention can not only detect the frequency of continuous waves, but also detect the carrier frequency of high-order QAM, OFDM, and other signals with non-constant envelopes, thus solving the problem of decreased detection accuracy caused by non-periodic distortion in the modulation signal. This invention intelligently identifies and masks these non-effective periodic intervals through an envelope detection module, ensuring that only stable periodic segments of the signal are sent for TDC measurement; simultaneously, a zero-crossing detection module extracts the carrier frequency square wave from the modulation signal, facilitating equal-precision measurements by the frequency detection core unit.

[0064] This invention combines time-to-digital conversion technology with equal-precision measurement methods to create a novel on-chip frequency detection paradigm. It solves the trade-offs between detection accuracy, frequency range, response speed, low cost, and low power consumption in traditional digital and analog solutions. It integrates the frequency detection function, which traditionally relies on FPGAs or external discrete components, into a single chip, achieving wide-band, high-precision frequency detection. The system's response speed is improved by orders of magnitude, external interfaces and system interconnection are greatly simplified, and significant power consumption and area optimizations are achieved. It solves the carrier detection problem of high-order modulation signals, conforms to the semiconductor industry's trend of "integration, miniaturization, and low power consumption," and has significant technological advancements and broad market application prospects.

[0065] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0066] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0067] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.

Claims

1. An on-chip frequency detection circuit, characterized in that, include: A multi-mode frequency divider is used to receive the signal under test and obtain the frequency-divided signal based on the initial detection frequency of the signal under test. A gate signal controller, connected to the multi-mode frequency divider, is used to receive the frequency-divided signal and, based on the initial state bit... a and end state bit b Generate a gate signal, wherein the initial state bit a Define the start time of the gate signal, and the end state bit. b Define the end time of the gate signal; A time-to-digital converter, connected to the gate signal controller, is used to receive the gate signal and a reset signal, and within the gate time of the gate signal, obtain a reference signal based on the oscillation generated by the reset signal, and count the rising edges of the reference signal to obtain a counting result; The frequency calculation module, connected to the time-to-digital converter, is used to calculate the frequency based on the counting result, the frequency of the reference signal, and the start state bit. a and the end state bit b The final detection frequency of the signal to be tested is obtained.

2. The on-chip frequency detection circuit according to claim 1, characterized in that, The frequency-divided signal is obtained based on the preliminary detection frequency result of the signal to be tested, including: When the initial detection frequency of the signal under test is greater than or equal to the preset frequency, the initial detection frequency of the signal under test belongs to the high-frequency range, and the multi-mode frequency divider switches to the high-frequency division mode to divide the signal under test. N The frequency-divided signal is obtained by further frequency division. When the initial detection frequency of the signal under test is less than the preset frequency, the initial detection frequency of the signal under test belongs to the low-frequency range. The multi-mode frequency divider switches to low-frequency division mode to divide the signal under test. M The frequency is divided again to obtain the frequency-divided signal, wherein... N > M .

3. The on-chip frequency detection circuit according to claim 1, characterized in that, It also includes a serial peripheral interface for providing the start state bit. a and the end state bit b .

4. The on-chip frequency detection circuit according to claim 3, characterized in that, The gate signal controller is connected to the serial peripheral interface and is specifically used to receive the frequency-divided signal and the start state bit. a and the end state bit b And according to the initial state bit a and end state bit b Generate a string of length ( b - a A gate signal with a frequency division period of 1.

5. The on-chip frequency detection circuit according to claim 3, characterized in that, The serial peripheral interface is also used to provide the reset signal; The time-to-digital converter includes: A multi-phase frequency source, connected to the serial peripheral interface, is used to receive the reset signal and start oscillating after receiving the reset signal to generate a reference signal; A counter, connected to the gate signal controller, is used to receive the gate signal and the reference signal, and count the rising edge of the reference signal during the gate time of the gate signal to obtain the counting result.

6. The on-chip frequency detection circuit according to claim 1, characterized in that, Based on the counting result, the frequency of the reference signal, and the starting state bit a and the end state bit b Obtaining the final detection frequency of the signal under test includes: The frequency calculation module is specifically used to calculate the frequency of the reference signal based on the counting result and the starting state bit. a and the end state bit b The frequency of the frequency-divided signal is obtained, and the frequency of the frequency-divided signal is expressed as: in, The frequency of the signal after frequency division. For the counting results, The frequency of the reference signal; The final detection frequency of the signal under test is obtained based on the frequency of the divided signal.

7. The on-chip frequency detection circuit according to claim 1, characterized in that, Also includes: The zero-crossing detection module, connected to the multi-mode frequency divider, is used to receive the modulation signal and extract the carrier information in the modulation signal by identifying the zero point of the modulation signal, so as to generate a carrier signal with the same carrier frequency as the modulation signal and transmit it to the multi-mode frequency divider as the signal to be tested.

8. The on-chip frequency detection circuit according to claim 7, characterized in that, The zero-crossing detection module includes a multi-stage inverter.

9. The on-chip frequency detection circuit according to claim 7, characterized in that, Also includes: An envelope detection module, connected to the gate signal controller, is used to receive the modulation signal, extract the envelope information of the modulation signal, and transmit the envelope information as an enable signal to the gate signal controller to control the operation of the gate signal controller.

10. The on-chip frequency detection circuit according to claim 9, characterized in that, The envelope detection module includes: An RC low-pass filter is used to receive the modulated signal and extract the envelope information of the modulated signal; A voltage comparator, connected to the RC low-pass filter and the gate signal controller, is used to compare the voltage of the envelope information with a reference voltage to obtain a comparison result, and generate an enable signal without envelope dips based on the comparison result and transmit it to the gate signal controller to control the operation of the gate signal controller.

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