A SIMT deadlock risk-free compiling method, electronic equipment and storage medium
By inserting initialization and maintenance code for the thread group scheduling queue into the compiler, the execution order of basic blocks is rearranged, thus resolving the SIMT deadlock problem. This ensures that the GPU processor executes instructions in a predetermined order, avoiding deadlock and improving computational efficiency and reliability.
Patent Information
- Application Number
- CN202411752740.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2026-06-02
AI Technical Summary
The SIMT model is prone to deadlock when processing code with conditional branches, especially when there are complex mutual waiting and dependency relationships between threads, leading to resource contention and synchronization problems, forming a closed-loop deadlock.
By inserting initialization and maintenance code for the thread group scheduling queue into the compiler, rearranging the execution order of basic blocks, and inserting queue maintenance code at the end of each basic block, the target instruction to be executed and its thread group execution mask are detected and pushed into the tail of the thread group scheduling queue, thus solving the deadlock problem using the first-in-first-out principle.
It effectively solves the SIMT deadlock problem, ensuring that the processor executes instructions in a predetermined order, avoiding deadlock and improving the computing efficiency and reliability of the GPU.
Smart Images
Figure CN122132036A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design, and in particular to a compilation method, electronic device, and storage medium that are free from the risk of SIMT deadlock. Background Technology
[0002] With the ever-increasing demands for computer graphics processing and parallel computing, Graphics Processing Units (GPUs) have become a core component in the field of high-performance computing. Current GPU designs generally employ a Single Instruction Multiple Thread (SIMT) execution model. In the SIMT model, logically independent threads are divided into different groups, which are called warps in the NVIDIA architecture. Each warp contains a certain number of threads that execute the same instructions in a lockstep manner on a Single Instruction Multiple Data (SIMD) processor. This execution mode can fully utilize the parallel processing capabilities of SIMD processors, accelerating the computation process by executing multiple threads simultaneously.
[0003] However, the SIMT model faces challenges when handling code with conditional branches. On a CPU, conditional branches are typically implemented using jump instructions, allowing different threads to execute different instruction sequences based on the conditional decision. But in a GPU-based SIMT model, since threads execute in warps, a mechanism is needed to ensure all threads execute their instruction sequences in the correct order when encountering a conditional branch. To achieve this, the SIMT model introduces a predicate mask mechanism. A predicate mask is a bitmask corresponding to the number of threads in a warp, used to control the execution state of each thread. To achieve divergent branches within the same warp—allowing different threads in the warp to execute different instruction sequences—SIMT uses the predicate mask to shut down appropriate threads in the SIMD processor and traverses all basic blocks of the program in a certain order; this process is called linearization.
[0004] Due to various considerations, many GPUs employ stack-based control flow linearization methods. This approach utilizes a stack structure to save and restore the execution state of threads, enabling them to correctly jump and backtrack when encountering branches. However, stack-based linearization also introduces some problems. In particular, when complex mutual waits and dependencies exist between threads in a warp, it can lead to deadlocks on the GPU for code that runs normally on the CPU, a phenomenon known as SIMT deadlock. SIMT deadlocks typically occur due to resource contention and synchronization issues between threads. For example, when two or more threads wait for each other to release resources or complete a specific operation, a closed loop is formed, preventing all involved threads from continuing execution. Therefore, a compilation method free from the risk of SIMT deadlock is urgently needed. Summary of the Invention
[0005] To address the aforementioned technical problems, the present invention adopts the following technical solution: a compilation method without SIMT deadlock risk, the method comprising the following steps:
[0006] Obtain the target source code, which is code with a deadlock risk, and the target source code includes N basic blocks.
[0007] The compiler inserts initialization code for the thread group scheduling queue at the beginning of the target source code to obtain the thread group scheduling queue; wherein, the thread group scheduling queue is used to rearrange the execution order of basic blocks when the target source code is executed.
[0008] The compiler inserts queue maintenance code at the end of each basic block. The queue maintenance code is used to maintain the thread group scheduling queue. The thread group scheduling queue stores the next instruction to be executed for each thread group and the execution mask xmask. The xmask is the binary execution mask of the current thread group, and each bit of the binary number is a status flag bit of the active state of the corresponding thread.
[0009] Wherein, after the i-th basic block is executed, the value of i ranges from 1 to N, and the maintenance steps of the thread group scheduling queue include:
[0010] The processor executes queue maintenance code inserted at the end of the i-th basic block. The queue maintenance code is used to detect the next target instruction to jump from the i-th basic block. The target instruction is the first instruction of the next basic block to be executed after the jump. The processor binds the target instruction and the binary mask of the thread group executing the target instruction and pushes them to the tail of the thread group scheduling queue. The processor also scans the thread group scheduling queue, merges multiple threads jumping to the same target instruction into one thread group, and updates the xmask.
[0011] The head instruction of the thread group scheduling queue is dequeued, and the processor executes the head instruction.
[0012] Furthermore, the present invention also provides a non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, wherein the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the above-described method.
[0013] In addition, the present invention provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.
[0014] The present invention has at least the following beneficial effects:
[0015] This invention provides a compilation method, electronic device, and storage medium free from SIMT deadlock risk. The compiler inserts queue maintenance code at the end of each basic block. When the processor executes this queue maintenance code, it detects the next target instruction to be executed and pushes the target instruction and its thread group execution mask into the tail of the thread group scheduling queue. Essentially, the compiler uses a first-in-first-out thread group scheduling queue to rearrange the execution order of basic blocks during program execution, thus solving the deadlock problem. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 A flowchart of a compilation method without SIMT deadlock risk provided in an embodiment of the present invention;
[0018] Figure 2 A logical diagram illustrating a code example provided for an embodiment of the present invention;
[0019] Figure 3 for Figure 2 The code example illustrates the maintenance process of the thread group scheduling queue. Detailed Implementation
[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0021] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.
[0022] Please see Figure 1 It illustrates a compilation method without SIMT deadlock risk, the method comprising the following steps:
[0023] S100, Obtain the target source code, which is code with a deadlock risk, and the target source code includes N basic blocks.
[0024] In one implementation, the target source code is code that includes a loop body.
[0025] In one embodiment, the step of obtaining the target source code includes: when compiling the source code, the compiler extracts loops through control flow analysis, and further extracts loop control variables in the loops. The presence of deadlock risk is determined based on whether the loop control variables depend on global variables; if they do not depend on the global variables, there is no deadlock risk; if they depend on the global variables, there is a deadlock risk. Other methods of obtaining target source code with deadlock risk fall within the protection scope of this invention.
[0026] In one implementation, a basic block is a continuous sequence of instructions in the control flow graph (CFG) that does not contain any branches or merging. In one implementation, branching instructions are if statements or loop statements. As an example, a code snippet "if(x>0){y=x+1;z=y*2;}" can be divided into a first basic block and a second basic block. The first basic block is a conditional block containing the if(x>0) statement, while the second basic block is a statement block containing the y=x+1 and z=y*2 statements. In the control flow graph, the first basic block has an exit, i.e., the condition is true or false; while the second basic block has an entry and an exit. The entry jumps from the first basic block when the condition is true, and the exit is usually the sequential execution to the next statement or basic block.
[0027] S200, the compiler inserts initialization code for the thread group scheduling queue at the beginning of the target source code to obtain the thread group scheduling queue; wherein, the thread group scheduling queue is used to rearrange the execution order of basic blocks when executing the target source code.
[0028] The thread group scheduling queue follows the first-in-first-out (FIFO) principle.
[0029] In one implementation, the thread group scheduling queue is maintained by creating, updating, and destroying it. Other maintenance methods also fall within the scope of this invention.
[0030] In one implementation, before or during the processing of the target source code by the compiler, the compiler, or a tool or framework tightly integrated with the compiler, automatically adds preset code to the beginning of the target source code. This preset code is used to initialize the data structure of the thread group scheduling queue.
[0031] S300, the compiler inserts queue maintenance code at the end of each basic block. The queue maintenance code is used to maintain the thread group scheduling queue. The thread group scheduling queue stores the next instruction to be executed for each thread group and the execution mask xmask. The xmask is the binary execution mask of the current thread group, and each bit of the binary number is the status flag bit of the active state of the corresponding thread.
[0032] The end position of a basic block is the position of the instruction following the last instruction in its instruction sequence.
[0033] In one implementation, queue maintenance code is automatically inserted by the compiler during the control flow analysis phase, making it transparent to high-level language programmers.
[0034] In one implementation, when the status flag in the xmask is 0, it indicates that the corresponding thread is in an inactive state; when it is 1, it indicates that the corresponding thread is in an active state.
[0035] As an example, suppose a thread group has a total of 4 threads: thread0-3, and the xmask is represented by a 4-bit binary number. When the xmask bound to a thread group is equal to 0001, it means that thread0-2 is inactive and thread3 is active, that is, thread3 jumps to the basic block pointed to by the program counter PC bound to the xmask.
[0036] In this context, all threads within the same thread group have the same instruction to be executed.
[0037] In one implementation, the data length of the xmask is the same as the total number of threads. That is, when the total number of threads is M, the data length of the xmask is M.
[0038] S400, after the i-th basic block is executed, the value of i ranges from 1 to N. The maintenance steps of the thread group scheduling queue include:
[0039] S410, the processor executes queue maintenance code inserted at the end of the i-th basic block. The queue maintenance code is used to detect the next target instruction to jump from the i-th basic block. The target instruction is the first instruction of the next basic block to be executed after the jump. The processor binds the target instruction and the binary mask of the thread group executing the target instruction and pushes them into the tail of the thread group scheduling queue. The processor also scans the thread group scheduling queue, merges multiple threads jumping to the same target instruction into one thread group, and updates the xmask.
[0040] In one implementation, the processor is a graphics processing unit (GPU), a multi-core processor, a vector processor, or an AI processor. Other types of processors supporting the SIMT architecture also fall within the scope of this invention.
[0041] In one implementation, after the i-th basic block has been executed, when the queue maintenance code detects that there are U target instructions for the next i-th basic block, where the U target instructions are BLOCK = {block1, block2, ..., block...} j ,…,block U}, block j For the j-th target instruction, where j ranges from 1 to U, and U is greater than or equal to 1, the U target instructions in the BLOCK and their thread group execution masks are sequentially pushed into the tail of the thread group scheduling queue; and the thread group scheduling queue is scanned, wherein, for block j The block to be executed j Multiple threads are merged into a block j The thread group updates the xmask.
[0042] In one implementation, thread groups are divided according to basic blocks to be executed, with each basic block corresponding to one thread group. When multiple thread groups exist within a given thread group, the xmasks of all threads in the current thread group are merged. The block... j xmask j Satisfy: xmask j =xmask j1 &xmask j2 &…xmask jq &…&xmask jQ , where & is the AND operator, xmask jq block to be executed jThe q-th thread, where q ranges from 1 to Q, and Q is a block. j The total number of threads in a thread group, Q is greater than 1. When there is only one thread in a thread group, that thread is a separate thread group. That is, when Q = 1, then xmask... j =xmask j1 .
[0043] As an example, when two threads, xmask=1000 and xmask=0100, execute a block... j If the xmask is not found in the target instruction to be executed in the block, then the two threads are merged into a single thread group. After performing a bitwise AND operation on the xmask, the xmask of the thread group is 1100. The xmasks of the thread groups are different. For example, when the xmask of the first thread group is 1100, the xmask of the second thread group is 0011.
[0044] S420, the head instruction of the thread group scheduling queue is dequeued, and the processor executes the head instruction.
[0045] It should be noted that, according to the first-in-first-out principle followed by the thread group scheduling queue, the processor retrieves the head instruction of the thread group scheduling queue for execution each time.
[0046] To facilitate understanding, an example is used to further illustrate a compilation method without SIMT deadlock risk. The following is a logical description of a code snippet: First, a global variable `lock` of type boolean is declared and initialized to `true`. It should be noted that `lock` is a boolean variable; a value of `true` represents truth, and a value of `false` represents false. Second, a function named `function` is defined, which has no return value. Inside the `function` function, an `if` statement first checks if the thread index variable `threadid` is not equal to 0. If `threadid` is not equal to 0, the code within the `if` block is executed. The code within the `if` block contains a `while` loop. The `while` loop executes when `lock` is true, and ends when `lock` is false. Within the `while` loop, a function named `A` is called. If `threadid` is equal to 0, the code within the `else` block is executed. Within the `else` block, a function named `B` is first called, and then the value of `lock` is set to false. Regardless of how the `if-else` statements execute, the `function` function will ultimately call a function named `C`. The call to function `C` is not controlled by the `if-else` statements; it is executed every time the `function` function is called. Without the method provided by this invention, when this code segment is executed, a deadlock occurs because the `lock` condition of the `while` loop is set to `false`. However, this condition is in the `else` loop, and the `if` and `else` loops cannot execute simultaneously. The method provided by this invention eliminates the risk of deadlock, as detailed below.
[0047] Please see Figure 2 , Figure 2 The flowchart for the code example is in Figure 2 The five basic blocks in the code example above are represented by corresponding labels: "p0" represents the conditional expression of the "if" statement, "p1" represents the loop conditional expression of the "while" statement, "A" represents function A, "B" represents function B and setting the value of lock to false, and "C" represents function C. The compiler inserts queue maintenance code at the end of each basic block, represented by "β". In "p0 / 1111", "1111" indicates that the xmask of the total thread group is "1111", meaning that all four threads in thread0-3 execute the p0 instruction. In "p1 / 0111", "0111" indicates that thread1-3 executes the p1 instruction. In "A / 0111", "0111" indicates that thread1-3 executes the A instruction. "B / 1000" indicates that thread0 executes the B instruction.
[0048] Please see Figure 3 It illustrates the maintenance process of the thread group scheduling queue. Figure 3 This includes the thread group scheduling queue, and the instruction PC and its xmask to be executed by the processor. At the start of the program, the processor first executes p0, then executes β at the end of p0. β pushes the next target instruction p1 and B to be executed after p0 onto the tail of the queue. Then, the processor fetches the head instruction p1 from the thread group scheduling queue and executes it. Next, it executes β at the end of p1, and β pushes the next target instruction A to be executed after p1 onto the tail of the queue. Then, the processor fetches the head instruction B from the thread group scheduling queue and executes it. Next, it executes β at the end of B, and β pushes the next target instruction C to be executed after B onto the tail of the queue. Finally, the processor fetches the head instruction A from the thread group scheduling queue and executes it, then executes the instruction at the end of A... β pushes the next target instruction p1 to be executed for A to the tail of the queue; then, the processor fetches the head instruction C of the thread group scheduling queue and executes it, then executes β at the end position of C, and β finds that there is no next target instruction to be executed for C; then, the processor fetches the head instruction p1 of the thread group scheduling queue and executes it, then executes β at the end position of p1, and β pushes the next target instruction C to be executed for p1 to the tail of the queue; then, the processor fetches the head instruction C of the thread group scheduling queue and executes it, then executes β at the end position of C, and β finds that there is no next target instruction to be executed for C; at this time, the queue is empty, and all threads have finished executing.
[0049] Depend on Figure 2 and Figure 3 As the examples show, this method can ensure that all the next basic blocks to be executed are pushed to the tail of the thread group scheduling queue in advance, and jump to execute according to the order in the thread group scheduling queue, thereby effectively solving the deadlock problem.
[0050] In summary, the present invention provides a compilation method without SIMT deadlock risk. It inserts queue maintenance code at the end of each basic block by the compiler. When the processor executes the queue maintenance code, it detects the next target instruction to be executed and pushes the target instruction to be executed and its thread group execution mask into the tail of the thread group scheduling queue. This allows the processor to jump and execute instructions in the order of the instructions in the thread group scheduling queue, thus solving the deadlock problem.
[0051] Embodiments of the present invention also provide a non-transitory computer-readable storage medium that can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiments, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiments.
[0052] Embodiments of the present invention also provide an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.
[0053] Embodiments of the present invention also provide a computer program product including program code, which, when the program product is run on an electronic device, causes the electronic device to perform the steps of the methods described above in various exemplary embodiments of the present invention.
[0054] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.
[0055] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.
Claims
1. A compilation method without SIMT deadlock risk, characterized in that, The method includes the following steps: Obtain the target source code, which is code with a deadlock risk, and the target source code includes N basic blocks; The compiler inserts initialization code for the thread group scheduling queue at the beginning of the target source code to obtain the thread group scheduling queue; wherein, the thread group scheduling queue is used to rearrange the execution order of basic blocks when the target source code is executed; The compiler inserts queue maintenance code at the end of each basic block. This queue maintenance code is used to maintain the thread group scheduling queue. The thread group scheduling queue stores the next instruction to be executed for each thread group and the execution mask xmask. The xmask is the binary execution mask of the current thread group, and each bit of the binary number is a status flag bit of the corresponding thread's active state. Wherein, after the i-th basic block is executed, the value of i ranges from 1 to N, and the maintenance steps of the thread group scheduling queue include: The processor executes queue maintenance code inserted at the end of the i-th basic block. This queue maintenance code detects the next target instruction to be jumped from the i-th basic block. The target instruction is the first instruction of the next basic block to be executed after the jump. The processor binds the target instruction and the binary mask of the thread group executing the target instruction and pushes them to the tail of the thread group scheduling queue. The processor then scans the thread group scheduling queue, merges multiple threads jumping to the same target instruction into one thread group, and updates the xmask. The head instruction of the thread group scheduling queue is dequeued, and the processor executes the head instruction.
2. The method according to claim 1, characterized in that, The queue maintenance code is automatically inserted by the compiler during the control flow analysis phase.
3. The method according to claim 1, characterized in that, After the i-th basic block is executed, when the queue maintenance code detects that there are U target instructions for the next i-th basic block, where the U target instructions are BLOCK = {block1, block2, ..., block...} j ,…,block U }, block j For the j-th target instruction, where j ranges from 1 to U, and U is greater than or equal to 1, the U target instructions in the BLOCK and their thread group execution masks are sequentially pushed into the tail of the thread group scheduling queue; and the thread group scheduling queue is scanned, wherein, for block j The block to be executed j Multiple threads are merged into a block j The thread group updates the xmask.
4. The method according to claim 3, characterized in that, The block j xmask j Satisfy: xmask j =xmask j1 &xmask j2 &…xmask jq &…&xmask jQ , where & is the AND operator, xmask jq block to be executed j The q-th thread, where q ranges from 1 to Q, and Q is a block. j The total number of threads in the thread group, Q is greater than 1.
5. The method according to claim 1, characterized in that, The data length of the xmask is the same as the total number of threads.
6. The method according to claim 1, characterized in that, The target source code is code that includes a loop body.
7. The method according to claim 1, characterized in that, The steps for obtaining the target source code include: when compiling the source code, the compiler extracts loops through control flow analysis, and further extracts loop control variables in the loops. It determines whether there is a risk of deadlock based on whether the loop control variables depend on global variables. If they do not depend on the global variables, there is no risk of deadlock; if they depend on the global variables, there is a risk of deadlock.
8. The method according to claim 1, characterized in that, The processor is a graphics processor.
9. A non-transitory computer-readable storage medium, wherein the storage medium stores at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by the processor to implement the method as described in any one of claims 1-8.
10. An electronic device, characterized in that, Includes a processor and the non-transitory computer-readable storage medium as described in claim 9.