Heterogeneous parallel data processing method and apparatus

Abstract

This application relates to a heterogeneous parallel data processing method and apparatus. The method includes: acquiring multiple messages to be processed; allocating process resources to the multiple messages to be processed, allocating a dedicated sub-engine corresponding to the current process for process scheduling to process the messages of the current process; decoding the messages according to the dedicated sub-engine, and executing the next operation of the current process; wherein, the next operation refers to one of process storage, sub-engine process scheduling, and peripheral interface operation; when the decoding representation in the decoding process indicates that the dedicated sub-engine cannot handle it independently, instructing the current process to be scheduled to a general sub-engine for processing; the general sub-engine is used to process the corresponding operation commands according to the programmable logic and return to the current process. This method can achieve parallel data processing in a heterogeneous architecture that balances the high performance of RDMA, the programmability of the architecture, and the efficient utilization of resources.

Description

Technical Field

[0001] This application relates to the field of computer network technology, and in particular to a heterogeneous parallel data processing method and apparatus. Background Technology

[0002] With the development of information technology, network interface cards (NICs) are evolving from traditional basic data transmission functions to intelligent, high-speed, and programmable technologies. Responsive Direct Memory Access (RDMA) technology, as a core element supporting high-performance data transmission in NICs, enables direct data interaction between computing and storage nodes, reducing CPU intervention. Therefore, it is widely used in AI, cloud computing, and other scenarios, and its performance requirements are constantly increasing. However, limited by board-level design, the hardware area of ​​NICs cannot be infinitely expanded according to performance needs, resulting in limited resource expansion. Furthermore, the diversified development of AI scenarios presents more variable demands for RDMA applications (such as dynamic network load and complex data processing logic). Traditional fixed pipeline (PIPE) architectures lack flexibility and struggle to adapt to changing requirements. In addition, in traditional architectures, resource sharing easily leads to access conflicts, resulting in performance loss. Simultaneously, functional expansion often involves resource redundancy, further exacerbating hardware cost pressures.

[0003] Therefore, there is an urgent need for a heterogeneous architecture that can perform parallel data processing while maintaining high performance of RDMA, programmability of the architecture, and efficient utilization of resources under limited hardware resources. Summary of the Invention

[0004] Therefore, it is necessary to provide a heterogeneous parallel data processing method and apparatus that can balance the high performance of RDMA, the programmability of the architecture, and the efficient utilization of resources, in order to address the above-mentioned technical problems.

[0005] Firstly, this application provides a heterogeneous parallel data processing method, including:

[0006] Retrieve multiple pending messages;

[0007] The process resources are allocated to the multiple pending messages, and a dedicated sub-engine corresponding to the current process is allocated for process scheduling to process the messages of the current process;

[0008] The dedicated sub-engine decodes the message and executes the next operation of the current process; wherein the next operation refers to one of process storage, sub-engine process scheduling, and peripheral interface operation.

[0009] When the decoding representation in the decoding process is such that the dedicated sub-engine cannot handle it independently, the current process is instructed to be scheduled to the general sub-engine for processing in the next step; the general sub-engine is used to process the corresponding operation commands according to the programmable process and return to the current process.

[0010] In one embodiment, the process resource allocation for the plurality of pending messages, and the allocation of a dedicated sub-engine corresponding to the current process for process scheduling, includes:

[0011] Obtain sub-engine status data from the dedicated heterogeneous engine group;

[0012] Based on the sub-engine status data and the task process status corresponding to the multiple pending messages, process resources are allocated, and a dedicated sub-engine corresponding to the current process is allocated.

[0013] In one embodiment, the step of decoding the message according to the dedicated sub-engine and executing the next operation of the current process includes:

[0014] The dedicated sub-engine reads the general-purpose registers of the process corresponding to the message to obtain the execution operation instruction and payload data; wherein, the execution operation instruction is used to execute the next operation of the current process; and the payload data is used to store the operation data returned by the external interface.

[0015] In one embodiment, after reading the general-purpose register of the process corresponding to the message according to the dedicated sub-engine to obtain the execution operation instructions and payload data, the method further includes:

[0016] When the opcode information of the execution operation instruction represents a peripheral interface operation, the message to be processed is temporarily stored in the general-purpose register, and the peripheral interface operation is executed to obtain the operation result data;

[0017] The operation result data is stored in the load data.

[0018] In one embodiment, the method further includes:

[0019] Obtain interface configuration instructions; wherein, the interface configuration instructions are used to configure the operations that the general sub-engine needs to perform;

[0020] The configuration opcode is obtained by fetching the interface configuration instructions based on the general sub-engine.

[0021] The operation corresponding to the configuration opcode is executed according to the general sub-engine.

[0022] In one embodiment, the method further includes:

[0023] Data flow for obtaining special messages;

[0024] If the data flow is a known data flow, the data flow is processed according to the dedicated sub-engine;

[0025] If the data flow is an unknown data flow, obtain the modification instruction, and process the data flow according to the general sub-engine and the modification instruction.

[0026] Secondly, this application also provides a heterogeneous parallel data processing apparatus, comprising:

[0027] The acquisition module is used to acquire multiple messages to be processed;

[0028] The process resource allocation module is used to allocate process resources to the multiple pending messages and allocate a dedicated sub-engine corresponding to the current process for process scheduling to process the messages of the current process.

[0029] The decoding processing module is used to decode the message according to the dedicated sub-engine and execute the next operation of the current process; wherein, the next operation refers to one of process storage, sub-engine process scheduling and peripheral interface operation;

[0030] A general processing module is used to instruct the current process to be scheduled to the general sub-engine for processing when the decoding representation in the decoding process is something that the dedicated sub-engine cannot handle independently; the general sub-engine is used to process the corresponding operation commands according to the programmable process and return to the current process.

[0031] In one embodiment, the process resource allocation module is further configured to obtain sub-engine status data of the dedicated heterogeneous engine group; allocate process resources according to the sub-engine status data and the task process status corresponding to the multiple pending messages, and allocate the dedicated sub-engine corresponding to the current process.

[0032] In one embodiment, the decoding processing module is further configured to read the general-purpose register of the process corresponding to the message according to the dedicated sub-engine to obtain the execution operation instruction and the load data; wherein, the execution operation instruction is used to execute the next operation of the current process; and the load data is used to store the operation data returned by the external interface.

[0033] In one embodiment, the device further includes:

[0034] The peripheral interface operation module is used to temporarily store the message to be processed in the general-purpose register and execute the peripheral interface operation to obtain operation result data when the opcode information of the execution operation instruction represents a peripheral interface operation; and to store the operation result data in the payload data.

[0035] In one embodiment, the apparatus further includes: a configuration module, configured to acquire interface configuration instructions; wherein the interface configuration instructions are used to configure the operations to be performed by the general sub-engine; the general sub-engine fetches the interface configuration instructions to obtain configuration opcodes; and the general sub-engine executes the operations corresponding to the configuration opcodes.

[0036] In some embodiments, the apparatus further includes: a special message processing module, configured to acquire the data flow of a special message; if the data flow is a known data flow, process the data flow according to the dedicated sub-engine; if the data flow is an unknown data flow, acquire a modification instruction, and process the data flow according to the general sub-engine and the modification instruction.

[0037] The aforementioned heterogeneous parallel data processing method and apparatus acquire multiple messages to be processed; allocate process resources to the multiple messages to be processed, allocate a dedicated sub-engine corresponding to the current process for process scheduling to process the messages of the current process; decode the messages according to the dedicated sub-engine, and execute the next operation of the current process; wherein, the next operation refers to one of process storage, sub-engine process scheduling, and peripheral interface operation; when the decoding representation in the decoding process is that the dedicated sub-engine cannot handle it independently, the current process is instructed to be scheduled to the general sub-engine for processing; the general sub-engine is used to process the corresponding operation commands according to the programmable process and return to the current process. Therefore, multiple dedicated sub-engines corresponding to the current process are allocated through process resources to process multiple pending messages in parallel. These dedicated sub-engines decode the messages and execute the next operation of the current process. This enables parallel processing of processes such as process storage, sub-engine process scheduling, and peripheral interface operations. When a message cannot be processed independently, the current process is instructed to be scheduled to a configurable and programmable general-purpose sub-engine for processing. This allows the current process to follow the programmable operation commands. Due to the programmability of the opcodes, the overall architecture achieves high programmability while maintaining the high performance of RDMA, and the overall parallel processing flow utilizes resources efficiently. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a diagram illustrating the application environment of a heterogeneous parallel data processing method in one embodiment.

[0040] Figure 2 This is a flowchart illustrating a heterogeneous parallel data processing method in one embodiment;

[0041] Figure 3 This is a schematic diagram of a special message processing flow of a heterogeneous parallel data processing method in one embodiment;

[0042] Figure 4 A flowchart of the multi-process parallel processing architecture of a heterogeneous parallel data processing method in another embodiment;

[0043] Figure 5 This is a schematic diagram illustrating the collaborative operation of sub-engines in a heterogeneous parallel data processing method in another embodiment;

[0044] Figure 6 This is a software-integrated processing flowchart of a heterogeneous parallel data processing method in another embodiment;

[0045] Figure 7 This is a structural block diagram of a heterogeneous parallel data processing device in one embodiment;

[0046] Figure 8 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0048] The heterogeneous parallel data processing method provided in this application can be applied to, for example... Figure 1In the application environment shown, the host client 102 communicates with the storage device via the NIC 104 connected to the front-end network. The storage device can store the data that the NIC 104 needs to process. The NIC 104 can be integrated into the storage device or placed in the cloud or on another network server. The NIC 104 acquires multiple pending packets; allocates process resources for the multiple pending packets, assigns a dedicated sub-engine corresponding to the current process for process scheduling to process the packets of the current process; decodes the packets according to the dedicated sub-engine, and executes the next operation of the current process; the next operation refers to one of the following: process storage, sub-engine process scheduling, and peripheral interface operation; when the decoding representation in the decoding process indicates that the dedicated sub-engine cannot handle it independently, it instructs the current process to be scheduled to the general sub-engine for processing; the general sub-engine is used to process the corresponding operation commands according to the programmable logic and return to the current process. The host client 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, projection devices, etc. Portable wearable devices can include smartwatches, smart bracelets, head-mounted devices, etc. Head-mounted devices can be virtual reality (VR) devices, augmented reality (AR) devices, smart glasses, etc. The NIC network card 104 in this embodiment can also be called a network interface controller, network adapter, network interface card, local area network adapter, etc., and is computer hardware designed to allow computers to communicate on a computer network.

[0049] In one exemplary embodiment, such as Figure 2 As shown, a heterogeneous parallel data processing method is provided, which can be applied to... Figure 1 Taking NIC 104 as an example, the explanation includes steps 202 to 208. Wherein:

[0050] Step 202: Obtain multiple messages to be processed.

[0051] Among them, pending messages are messages, data packets, requests, or instructions generated by one or more tasks that have arrived at the system but have not yet been processed or have not been fully processed.

[0052] In some embodiments, multiple pending messages input by the target user can be directly obtained through the process controller of the multi-process parallel processing architecture of the NIC, or multiple pending messages generated by the target program can be read, and this is not limited to these embodiments.

[0053] Step 204: Allocate process resources for multiple pending messages and allocate a dedicated sub-engine corresponding to the current process for process scheduling to process the messages of the current process.

[0054] Process resource allocation includes sub-engine allocation and process allocation.

[0055] In some embodiments, process resource allocation is performed on multiple pending messages, and a dedicated sub-engine corresponding to the current process is allocated for process scheduling, including: obtaining sub-engine status data of a dedicated heterogeneous engine group; performing process resource allocation based on the sub-engine status data and the task process status corresponding to multiple pending messages, and allocating a dedicated sub-engine corresponding to the current process.

[0056] Among them, the dedicated heterogeneous engine group refers to the RDMA dedicated heterogeneous engine group, which contains multiple dedicated sub-engines. The dedicated sub-engine can be SUB_ENG (sub-engine).

[0057] In some embodiments, during the resource allocation process, obtaining the sub-engine status data of the dedicated heterogeneous engine group involves the resource scheduling phase. Specifically, when a process in the process controller that is processing in parallel has a processing task and the operation that needs to be performed has been completed, the obtained sub-engine status data is in an active state.

[0058] In some embodiments, resource allocation is performed based on sub-engine status data and the task process status corresponding to multiple pending messages. At this time, by determining whether the active process and the sub-engine it needs to process are in an idle state, the corresponding process is scheduled to the corresponding dedicated sub-engine for processing, thereby obtaining multiple available dedicated sub-engines.

[0059] In this embodiment, by allocating resources to multiple messages to be processed, multi-process parallel processing and pipeline optimization of the RDMA dedicated sub-engine are achieved, meeting the requirements of high-bandwidth scenarios and realizing efficient resource utilization.

[0060] Step 206: Decode the message according to the dedicated sub-engine and execute the next operation of the current process; wherein, the next operation refers to one of the following: process storage, sub-engine process scheduling, and peripheral interface operation.

[0061] The decoding process requires first extracting the code from the message and then performing further parsing and decoding.

[0062] In some embodiments, decoding the message according to a dedicated sub-engine and executing the next operation of the current process includes: reading the general-purpose register of the process corresponding to the message according to the dedicated sub-engine to obtain the execution operation instruction and payload data; wherein, the execution operation instruction is used to execute the next operation of the current process; and the payload data is used to store the operation data returned by the external interface.

[0063] The execution operation instruction can be metadata containing the opcode, that is, METADATA (including OPCODE) and load data (LOAD DATA).

[0064] In some embodiments, multiple dedicated sub-engines read the general-purpose registers of the processes corresponding to multiple pending messages to obtain the execution operation instructions, namely metadata and payload data containing opcodes. The dedicated sub-engines parse the opcodes to update the corresponding metadata and the operations to be performed on the corresponding pending message, and refresh the updated operations and new metadata to the corresponding process storage (similar to a first-level PIPE pipeline) so that the next required operation can be performed.

[0065] In some embodiments, after reading the general-purpose register of the process corresponding to the message according to the dedicated sub-engine to obtain the execution operation instruction and payload data, the method further includes: when the opcode information of the execution operation instruction represents a peripheral interface operation, temporarily storing the message to be processed in the general-purpose register, and performing the peripheral interface operation to obtain the operation result data; storing the operation result data in the payload data.

[0066] In some embodiments, the process scheduling corresponds to the operation flow to be executed. When the opcode information represents a peripheral interface operation, that is, if the operation flow requires external interface interaction, the data of the message to be processed will be temporarily stored in a general-purpose register, and the corresponding peripheral interface operation will be initiated to the external interface. The operation result data will be returned and stored in the load data.

[0067] In this embodiment, during the process of process execution, the dedicated sub-engine can process the verification tasks of other processes in parallel. When the task enters the process controller to allocate the process serially, all processes share the dedicated sub-engine to perform different operations, and the dedicated sub-engine can complete the processing of RDMA messages with planned data structures.

[0068] Step 208: When the decoding representation in the decoding process is such that the dedicated sub-engine cannot handle it independently, the current process is instructed to be scheduled to the general sub-engine for processing in the next step; the general sub-engine is used to process the corresponding operation commands according to the programmable process and return to the current process.

[0069] In this case, when the decoding characterization indicates that the message cannot be processed independently, it means that during the decoding of the message, it was determined that the hardware cannot independently process the task flow corresponding to the message to be processed.

[0070] In some embodiments, when the decoded characterization is deemed unprocessable, the process returns to process handling to execute the corresponding operation, which is then scheduled to the general sub-engine for processing. The general sub-engine fetches the execution operation instruction and retrieves the corresponding opcode information from the corresponding execution operation instruction.

[0071] In some embodiments, the method further includes: obtaining an interface configuration instruction; wherein the interface configuration instruction is used to configure the operations to be performed by the general sub-engine; fetching the interface configuration instruction according to the general sub-engine to obtain a configuration opcode; and performing the operation corresponding to the configuration opcode according to the general sub-engine.

[0072] The interface for obtaining configuration instructions is unified, and different numbers of dedicated or general sub-engines can be flexibly inserted to expand functionality.

[0073] In this embodiment, the unified sub-engine interface design facilitates hardware function expansion, and the software and hardware co-processing mode improves the adaptability of the architecture, enabling rapid response to new business needs.

[0074] In some embodiments, based on the programmability of the general sub-engine, interface configuration instructions can be obtained through the APB interface. The general sub-engine then fetches these instructions to obtain configuration opcodes, allowing for the configuration of different opcodes. The general sub-engine then executes the operations corresponding to these opcodes. For example, if the opcode is CACHE_HOST_MV, the processed data is moved from the cache to the host memory, completing the hardware-software interaction.

[0075] It should be noted that the configuration method for obtaining interface configuration instructions can be configured through the APB / AHB interface. The configuration opcodes can execute various opcodes such as MV (data move), ADD (addition), CMP (compare), JMP (jump), MEM_RD, MEM_WR, etc., and are not limited to these.

[0076] In this embodiment, the general sub-engine supports programmable configuration, adapts to the variable network requirements of AI scenarios, can flexibly insert sub-engines with different functions, supports functional expansion (such as out-of-order processing, DIF verification, etc.), and supports jumping or looping between sub-engines to adapt to complex business logic.

[0077] In some embodiments, after the process controller completes the operation corresponding to the opcode information, it can schedule to different general sub-engines or decompose the remaining tasks into dedicated hardware sub-engines that can process the corresponding data and then schedule to the dedicated sub-engines for processing, so that the process controller can execute the data processing operation corresponding to the opcode information.

[0078] In this embodiment, all sub-engines in the process controller use a fixed 4-time slot, with no resource access conflicts, and can stably achieve a processing performance of 250M pps at a 1GHz main frequency without increasing hardware resources. It also supports extended functions such as out-of-order processing and DIF.

[0079] In the above heterogeneous parallel data processing method, multiple messages to be processed are acquired; process resources are allocated to the multiple messages to be processed, and a dedicated sub-engine corresponding to the current process is allocated for process scheduling to process the messages of the current process; the messages are decoded according to the dedicated sub-engine, and the next operation of the current process is executed; the next operation refers to one of the following: process storage, sub-engine process scheduling, and peripheral interface operation; when the decoding representation in the decoding process is that the dedicated sub-engine cannot handle it independently, the current process is instructed to be scheduled to the general sub-engine for processing; the general sub-engine is used to process the corresponding operation commands according to the programmable logic and return to the current process. Therefore, multiple dedicated sub-engines corresponding to the current process are allocated through process resources to process multiple pending messages in parallel. These dedicated sub-engines decode the messages and execute the next operation of the current process. This enables parallel processing of processes such as process storage, sub-engine process scheduling, and peripheral interface operations. When a message cannot be processed independently, the current process is instructed to be scheduled to a configurable and programmable general-purpose sub-engine for processing. This allows the current process to follow the programmable operation commands. Due to the programmability of the opcodes, the overall architecture achieves high programmability while maintaining the high performance of RDMA, and the overall parallel processing flow utilizes resources efficiently.

[0080] In one exemplary embodiment, such as Figure 3 As shown, the special message processing steps include steps 302 to 306. Wherein:

[0081] Step 302: Obtain the data flow for special messages.

[0082] Among them, the data flow of special messages refers to the data flow that is processed in cooperation with certain special message processing software.

[0083] In some embodiments, preset conditions for special messages can be defined in a pre-defined manner, and the data flow of special messages can be obtained by filtering the messages to be processed according to the preset conditions. This is not limited to this.

[0084] Step 304: If the data flow is a known data flow, process the data flow according to the dedicated sub-engine.

[0085] In this case, if the data flow is a known data flow, that is, the special message has been processed before.

[0086] In some embodiments, if the data flow is a known data flow, the data flow is processed according to a dedicated sub-engine. Using a dedicated sub-engine to process known data flows can ensure the processing efficiency of the data flow.

[0087] Step 306: If the data flow is unknown, obtain the modification instruction and process the data flow according to the general sub-engine and the modification instruction.

[0088] Among them, the modification command is a configuration command used to configure the general sub-engine. If the data flow is an unknown data flow, that is, the special message has not been processed.

[0089] In some embodiments, if the data flow is an unknown data flow, it is necessary to obtain modification instructions and process the data flow according to the general sub-engine and modification instructions, thereby ensuring the flexibility of completing special messages.

[0090] In this embodiment, a process involving the combined processing of some specialized message processing software is achieved through an overall workflow. For known data flows, a dedicated sub-engine ensures efficiency; for unknown data flows, modifications to the instructions of a general sub-engine ensure flexibility.

[0091] In some embodiments, to better understand the solution of this application, the following are combined with Figure 4 , Figure 5 and Figure 6 The explanation is as follows:

[0092] First, such as Figure 4 As shown, Figure 4 This diagram illustrates the network interface card (NIC) architecture used in this solution and its high-performance RDMA processing flow, showing the specific optimizations compared to the serial PIPE process. Figure 4 The pipelined processing architecture is a serial processing flow. As performance requirements increase, the pipeline is divided into increasingly finer segments. Each pipeline stage may have different data that needs to be temporarily cached; to ensure performance, each stage's cache is relatively large. Because the metadata of all processes is reusable, this architecture can achieve resource sharing of all metadata / load data across different pipelines.

[0093] Secondly, such as Figure 5 As shown, Figure 5The parallel processing flow of the RDMA dedicated circuit is demonstrated. The multi-process parallel processing architecture includes four stages: **Scheduling Stage:** Processes in the process controller that are processing concurrently are in an active state when they have tasks to process and the required operations have been completed. The active process is scheduled to the SUB_ENG for processing based on whether the SUB_ENG it needs to process is idle. **Instruction Fetch Stage:** The SUB_ENG reads the corresponding process's general-purpose registers to obtain METADATA (including OPCODE) and LOAD DATA for the next required operation. **Decoding Stage:** The RDMA-dedicated SUB_ENG parses the OPCODE, updates the corresponding METADATA and the required operations for the corresponding message, and refreshes the corresponding operations and the new METADATA to the corresponding process's storage (similar to the previous first-level PIPE pipeline). **Execution Stage:** The process schedules the required operation flow. If external interface interaction is needed, data is temporarily stored in general-purpose registers, and the corresponding operation is initiated to the external interface. The returned data is stored in LOAD DATA. During the execution of process processing operations, SUB_ENG can process the verification tasks of other processes in parallel; when a task enters the process controller serially to allocate a process, all processes share SUB_ENG to perform different operations, and a dedicated SUB_ENG can complete the processing of RDMA messages with planned data structures.

[0094] In some embodiments, a CPU-like parallel processing architecture is adopted to achieve efficient process-level scheduling and processing, including the following steps: Scheduling: The process controller schedules processes to be processed in real time; Instruction fetch: The process controller fetches general-purpose register data and LOAD DATA data and sends them to SUB_ENG; Decoding: SUB_ENG decodes the OPCODE of METADATA in the general-purpose register; Execution: SUB_ENG executes the decoded operation, modifies the OPCODE, temporarily stores METADATA, marks the process as "to be executed", and sends a response execution command to the outside to advance the next instruction. The RDMA-dedicated SUB_ENG is a dedicated processing unit designed for RDMA operations, with the following characteristics: Function: Executes fixed RDMA operations based on the message METADATA and OPCODE, including data verification, CACHE access, address translation, PCIe access, etc.

[0095] Finally, as Figure 6 As shown, Figure 6The software-integrated processing flowchart is shown, where: Step 1: The message is brought into the process controller, and a process is assigned to handle the message. Step 2: The process is scheduled to the dedicated SUB_ENG0 for processing and performs message decoding. If the hardware cannot handle the task independently, the corresponding operation will be performed in the process controller (scheduled to the general SUB_ENG0). Step 3: After the process completes the corresponding operation, it is scheduled to the general SUB_ENG0, retrieves the corresponding OPCODE information from the corresponding instruction MEM, and then returns to the process controller to perform the corresponding operation. Step 4: The process controller performs the corresponding peripheral interface operation. Step 5: After the process completes the corresponding operation, it continues to be scheduled to the general SUB_ENG0, retrieves the corresponding OPCODE information from the corresponding instruction MEM, and then returns to the process controller to perform the corresponding operation (different instruction operations can be executed repeatedly in the general SUB_ENG0). Step 6: After the general SUB_ENG0 completes execution, it can be scheduled to different general SUB_ENGs, or the remaining tasks can be decomposed into hardware-specific SUB_ENGs that can process the corresponding data and then scheduled to the hardware-specific SUB_ENGs for processing; the overall process achieves a workflow that involves the cooperation of some special message processing software. For processing known data flows, dedicated SUB_ENGs are used to ensure efficiency; for processing unknown data flows, instructions can be modified in conjunction with general SUB_ENGs to ensure flexibility.

[0096] In some embodiments, a process of "dedicated SUB_ENG0 processing → general SUB_ENG data migration to HOST → software processing → dedicated SUB_ENG1 reprocessing" is implemented to achieve hardware and software collaborative processing. Scalability is ensured by supporting DFX (debuggable, extensible) functionalities beyond the main functions. The architecture allows for flexible combination of RDMA dedicated SUB_ENG and general SUB_ENG, supporting mutual switching or cyclic processing within the same SUB_ENG. Through a unified interface and fixed time slot design, resource sharing and efficient parallelism are achieved, avoiding performance loss.

[0097] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0098] Based on the same inventive concept, this application also provides a heterogeneous parallel data processing apparatus for implementing the heterogeneous parallel data processing method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more embodiments of the heterogeneous parallel data processing apparatus provided below can be found in the limitations of the heterogeneous parallel data processing method described above, and will not be repeated here.

[0099] In one exemplary embodiment, such as Figure 7 As shown, a heterogeneous parallel data processing device is provided, including: an acquisition module 701, a resource allocation module 702, a decoding and execution module 703, an instruction fetch module 704, and a data processing module 705, wherein:

[0100] The acquisition module 701 is used to acquire multiple messages to be processed;

[0101] The process resource allocation module 702 is used to allocate process resources to multiple pending messages and allocate a dedicated sub-engine corresponding to the current process for process scheduling to process the messages of the current process.

[0102] The decoding processing module 703 is used to decode the message according to the dedicated sub-engine and execute the next operation of the current process; wherein, the next operation refers to one of the following: process storage, sub-engine process scheduling, and peripheral interface operation;

[0103] The general processing module 704 is used to instruct the current process to be scheduled to the general sub-engine for processing when the decoding representation in the decoding process is something that the dedicated sub-engine cannot handle independently; the general sub-engine is used to process the corresponding operation commands according to the programmable process and return to the current process.

[0104] In some embodiments, the process resource allocation module 702 is further configured to obtain sub-engine status data of the dedicated heterogeneous engine group; allocate process resources according to the sub-engine status data and the task process status corresponding to multiple pending messages, and allocate the dedicated sub-engine corresponding to the current process.

[0105] In some embodiments, the decoding and execution module 703 is further configured to read the general-purpose register of the process corresponding to the message according to the dedicated sub-engine to obtain the execution operation instruction and the payload data; wherein, the execution operation instruction is used to execute the next operation of the current process; and the payload data is used to store the operation data returned by the external interface.

[0106] In some embodiments, the apparatus further includes: a peripheral interface operation module, configured to temporarily store the message to be processed in a general-purpose register and perform a peripheral interface operation to obtain operation result data when the opcode information of the operation instruction represents a peripheral interface operation; and store the operation result data in the load data.

[0107] In some embodiments, the apparatus further includes: a configuration module, configured to acquire interface configuration instructions; wherein the interface configuration instructions are used to configure the operations to be performed by the general sub-engine; fetch the interface configuration instructions according to the general sub-engine to obtain a configuration opcode; and execute the operation corresponding to the configuration opcode according to the general sub-engine.

[0108] In some embodiments, the apparatus further includes: a special message processing module, configured to acquire the data flow of a special message; if the data flow is a known data flow, process the data flow according to a dedicated sub-engine; if the data flow is an unknown data flow, acquire a modification instruction, and process the data flow according to a general sub-engine and the modification instruction.

[0109] In the aforementioned heterogeneous parallel data processing device, multiple messages to be processed are acquired; process resources are allocated to the multiple messages to be processed, and a dedicated sub-engine corresponding to the current process is allocated for process scheduling to process the messages of the current process; the messages are decoded according to the dedicated sub-engine, and the next operation of the current process is executed; wherein, the next operation refers to one of the following: process storage, sub-engine process scheduling, and peripheral interface operation; when the decoding representation in the decoding process indicates that the dedicated sub-engine cannot handle it independently, the current process is instructed to be scheduled to the general sub-engine for processing; the general sub-engine is used to process the corresponding operation commands according to the programmable logic and return to the current process. Therefore, multiple dedicated sub-engines corresponding to the current process are allocated through process resources to process multiple pending messages in parallel. These dedicated sub-engines decode the messages and execute the next operation of the current process. This enables parallel processing of processes such as process storage, sub-engine process scheduling, and peripheral interface operations. When a message cannot be processed independently, the current process is instructed to be scheduled to a configurable and programmable general-purpose sub-engine for processing. This allows the current process to follow the programmable operation commands. Due to the programmability of the opcodes, the overall architecture achieves high programmability while maintaining the high performance of RDMA, and the overall parallel processing flow utilizes resources efficiently.

[0110] Each module in the aforementioned heterogeneous parallel data processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0111] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 8 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and databases. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media to run. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a heterogeneous parallel data processing method.

[0112] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0113] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0114] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0115] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0116] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A heterogeneous parallel data processing method, characterized in that, The method includes: Retrieve multiple pending messages; The process resources are allocated to the multiple pending messages, and a dedicated sub-engine corresponding to the current process is allocated for process scheduling to process the messages of the current process; The dedicated sub-engine decodes the message and executes the next operation of the current process; wherein the next operation refers to one of process storage, sub-engine process scheduling, and peripheral interface operation. When the decoding representation in the decoding process is such that the dedicated sub-engine cannot handle it independently, the current process is instructed to be scheduled to the general sub-engine for processing in the next step; the general sub-engine is used to process the corresponding operation commands according to the programmable process and return to the current process.

2. The method according to claim 1, characterized in that, The process resource allocation for the plurality of pending messages, and the allocation of a dedicated sub-engine corresponding to the current process for process scheduling, includes: Obtain sub-engine status data from the dedicated heterogeneous engine group; Based on the sub-engine status data and the task process status corresponding to the multiple pending messages, process resources are allocated, and a dedicated sub-engine corresponding to the current process is allocated.

3. The method according to claim 1, characterized in that, The step of decoding the message according to the dedicated sub-engine and executing the next operation of the current process includes: The dedicated sub-engine reads the general-purpose registers of the process corresponding to the message to obtain the execution operation instruction and payload data; wherein, the execution operation instruction is used to execute the next operation of the current process; and the payload data is used to store the operation data returned by the external interface.

4. The method according to claim 3, characterized in that, After reading the general-purpose registers of the process corresponding to the message according to the dedicated sub-engine to obtain the execution operation instructions and payload data, the method further includes: When the opcode information of the execution operation instruction represents a peripheral interface operation, the message to be processed is temporarily stored in the general-purpose register, and the peripheral interface operation is executed to obtain the operation result data; The operation result data is stored in the load data.

5. The method according to claim 1, characterized in that, The method further includes: Obtain interface configuration instructions; wherein, the interface configuration instructions are used to configure the operations that the general sub-engine needs to perform; The configuration opcode is obtained by fetching the interface configuration instructions based on the general sub-engine. The operation corresponding to the configuration opcode is executed according to the general sub-engine.

6. The method according to claim 1, characterized in that, The method further includes: Data flow for obtaining special messages; If the data flow is a known data flow, the data flow is processed according to the dedicated sub-engine; If the data flow is an unknown data flow, obtain the modification instruction, and process the data flow according to the general sub-engine and the modification instruction.

7. A heterogeneous parallel data processing device, characterized in that, The device includes: The acquisition module is used to acquire multiple messages to be processed; The process resource allocation module is used to allocate process resources to the multiple pending messages and allocate a dedicated sub-engine corresponding to the current process for process scheduling to process the messages of the current process. The decoding processing module is used to decode the message according to the dedicated sub-engine and execute the next operation of the current process; wherein, the next operation refers to one of process storage, sub-engine process scheduling and peripheral interface operation; A general processing module is used to instruct the current process to be scheduled to the general sub-engine for processing when the decoding representation in the decoding process is something that the dedicated sub-engine cannot handle independently; the general sub-engine is used to process the corresponding operation commands according to the programmable process and return to the current process.

8. The apparatus according to claim 7, characterized in that, The process resource allocation module is also used to obtain the sub-engine status data of the dedicated heterogeneous engine group; allocate process resources according to the sub-engine status data and the task process status corresponding to the multiple pending messages, and allocate the dedicated sub-engine corresponding to the current process.

9. The apparatus according to claim 7, characterized in that, The decoding processing module is further configured to read the general-purpose register of the process corresponding to the message according to the dedicated sub-engine to obtain the execution operation instruction and the load data; wherein, the execution operation instruction is used to execute the next operation of the current process; and the load data is used to store the operation data returned by the external interface.

10. The apparatus according to claim 9, characterized in that, The device further includes: The peripheral interface operation module is used to temporarily store the message to be processed in the general-purpose register and execute the peripheral interface operation to obtain operation result data when the opcode information of the execution operation instruction represents a peripheral interface operation; and to store the operation result data in the payload data.

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