System on chip, performance real-time detection method and task scheduling method

Abstract

This invention discloses a system-on-a-chip (SoC), a real-time performance monitoring method, and a task scheduling method. The SoC includes an on-chip bus, a peripheral interface controller, and a hardware-based monitoring module. The monitoring method includes: monitoring the transmission status of the on-chip bus based on the monitoring module; counting the number of valid data interaction events and determining the actual transmission bandwidth of the peripheral interface controller based on the number of events; recording the current first timestamp and the corresponding request transaction identifier when a data request event is detected on the on-chip bus; recording the current second timestamp when a data response event is detected and the obtained response transaction identifier matches the request transaction identifier; and determining the data transmission delay based on the first and second timestamps. This method, by directly counting traffic and matching identifiers at the underlying hardware level, achieves accurate measurement of the actual data transmission bandwidth and underlying hardware delay, eliminating system overhead interference at the software level.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit chip design, and in particular to a system-on-a-chip, a real-time performance monitoring method, and a task scheduling method. Background Technology

[0002] With the development of integrated circuit chip design technology, PCIe (Peripheral Component Interconnect Express), as the current mainstream high-speed serial interface protocol, is an indispensable and important component in CPU chip systems of various architectures. To facilitate the integration of SOC (System-on-Chip), in specific implementations, the PCIe subsystem often interconnects with the system bus through on-chip bus interfaces such as AXI (Advanced eXtensible Interface) and exchanges data with external PCIe devices through PCIe Link.

[0003] In practical chip applications and testing, users typically pay close attention to two key performance indicators: PCIe data bandwidth and data request latency. However, a chip after tape-out (post-silicon chip) is physically equivalent to a "black box," and its internal data transmission status is invisible to the outside. Currently, testers often rely solely on software tools running on the operating system for observation and statistical analysis when conducting bandwidth and latency tests.

[0004] This existing purely software-based statistical approach has significant drawbacks: First, due to the complexity of the SOC's internal structure, the results obtained from software testing are actually a comprehensive result of the combined effects of multiple factors, including the CPU core, system bus, PCIe subsystem, and external PCIe devices. For example, the latency path measured by software includes not only the latency of the PCIe system but also the transmission latency of data in the CPU core and system bus (such as the CMN bus). Second, this comprehensive statistical result may lead to larger traffic values ​​and lower latency measured in the test environment, but in actual business use, the test standards are often not met. Faced with a black box-like chip, users cannot obtain the true bandwidth utilization of the PCIe ports, nor can they distinguish whether the high latency of the system is caused by the CPU core / system bus or by the PCIe system itself. Therefore, existing technologies cannot accurately locate the system's performance bottlenecks, which in turn prevents the operating system from making effective policy adjustments based on the actual hardware operating state (e.g., it cannot accurately balance scheduling between I / O-intensive and compute-intensive tasks), resulting in a waste of system resources. Summary of the Invention

[0005] The purpose of this invention is to provide a system-on-a-chip (SoC) performance real-time detection method and task scheduling method based on the statistical analysis of real data traffic and transmission latency using on-chip hardware modules.

[0006] To achieve the above objectives, the present invention provides a method for real-time performance monitoring of an on-chip system, wherein the on-chip system includes an on-chip bus and a peripheral interface controller, and a hardware-based monitoring module is provided between the on-chip bus and the peripheral interface controller; the method includes: Within a preset time window, the transmission status of the on-chip bus is monitored based on the monitoring module; Based on the transmission status, the number of valid data interaction events is counted, and the actual transmission bandwidth of the peripheral interface controller is determined based on the number of occurrences. When a data request event is detected by the on-chip bus, the current first timestamp and the corresponding request transaction identifier are recorded; When a data response event is detected and the obtained response transaction identifier matches the request transaction identifier, the current second timestamp is recorded; The data transmission delay is determined based on the first timestamp and the second timestamp.

[0007] Preferably, the length of the time window is configurable; the actual transmission bandwidth is obtained by dividing the number of occurrences by the number of clock cycles contained in the time window.

[0008] Preferably, the on-chip bus adopts the Scalable Interface (AXI) protocol; Methods for counting the number of valid data interaction events include counting the number of handshakes between valid signals and ready signals in each channel of the on-chip bus.

[0009] Preferably, the monitoring module is equipped with a hardware counter. The first timestamp is the first count value of the hardware counter when the data request event is triggered, and the second timestamp is the second count value of the hardware counter when the data response event is triggered; The difference between the second count value and the first count value is calculated as the data transmission delay.

[0010] Preferably, the method for detecting the on-chip bus triggering a data request event includes: detecting that a valid handshake has occurred on the read address channel of the on-chip bus, and that the request transaction identifier is a read address identifier; The method for detecting a triggered data response event includes: detecting a valid handshake on the read data channel of the on-chip bus, and the response transaction identifier being a read response identifier.

[0011] The present invention also provides an on-chip system task scheduling method, comprising: The actual transmission bandwidth of the peripheral interface controller is obtained by using the on-chip system performance real-time detection method described above. Compare the actual transmission bandwidth with the benchmark bandwidth; If the difference between the actual transmission bandwidth and the benchmark bandwidth is greater than a preset first threshold, then an I / O intensive service will be added to the operating system. If the difference between the actual transmission bandwidth and the benchmark bandwidth is less than or equal to the first threshold, then a computationally intensive service is added to the operating system.

[0012] This invention also provides another on-chip system task scheduling method, which includes: The data transmission delay is obtained using the on-chip system performance real-time detection method described above; Compare the data transmission latency with the benchmark latency; If the data transmission delay is greater than the benchmark test delay, and the difference between the data transmission delay and the benchmark test delay reaches a preset second threshold, then the access services to the devices connected to the peripheral interface controller are reduced.

[0013] The present invention also provides a system-on-a-chip, comprising: On-chip bus; A peripheral interface controller; and a hardware-based monitoring module disposed between the on-chip bus and the peripheral interface controller; the monitoring module is configured to perform the following operations: Within a preset time window, monitor the transmission status of the on-chip bus; Based on the transmission status, the number of valid data interaction events is counted and stored in a register for the external operating system to read and determine the actual transmission bandwidth of the peripheral interface controller. When a data request event is detected by the on-chip bus, the current first timestamp and the corresponding request transaction identifier are recorded; When a data response event is detected and the obtained response transaction identifier matches the request transaction identifier, the current second timestamp is recorded; The first timestamp and the second timestamp are stored in a register so that the external operating system can read them and determine the data transmission delay.

[0014] Compared to existing technologies, the on-chip system performance real-time monitoring method provided by the above technical solution breaks the "black box" limitation of the silicon chip by introducing a hardware-based monitoring module between the on-chip bus and the peripheral interface controller, effectively eliminating interference from the CPU core and system bus in traditional pure software statistical solutions. Specifically, by directly counting the number of effective data interactions within a time window at the hardware level, it can accurately reflect the true transmission bandwidth utilization of the peripheral interface; at the same time, by using a transaction identifier matching mechanism to record the precise timestamps of requests and responses, it achieves accurate measurement of the actual data transmission latency of the underlying hardware. This solution not only helps users accurately identify and locate system performance bottlenecks, but also provides the system with real and reliable underlying hardware operating status data, thereby assisting in more efficient service scheduling and resource allocation, significantly improving the accuracy of on-chip system performance evaluation and resource utilization. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the on-chip system detection path in an embodiment of the present invention.

[0016] Figure 2 This is a flowchart of the real-time performance detection method for on-chip systems in an embodiment of the present invention.

[0017] Figure 3 This is a flowchart of a system-on-chip task scheduling method in one embodiment of the present invention.

[0018] Figure 4 This is a flowchart of a system-on-chip task scheduling method in another embodiment of the present invention. Detailed Implementation

[0019] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0020] This embodiment discloses a real-time performance monitoring method for a system-on-a-chip (SoC), applicable to a SoC that includes an on-chip bus and peripheral interface controller. In a specific hardware architecture, such as... Figure 1 A hardware-based monitoring module is provided between the on-chip bus and the peripheral interface controller. For example, in an ARM architecture CPU chip, the on-chip bus can be a bridged CMN (Coherent Mesh Network) bus, and the peripheral interface controller can be a PCIe RP (Root Port). The monitoring module is located at the entry point of the PCIe RP to directly listen to the underlying hardware signals, avoiding the CPU core and system bus latency interference caused by pure software statistics.

[0021] like Figure 2 The on-chip system performance real-time detection method specifically includes the following steps: S11: Within a preset time window, monitor the transmission status of the on-chip bus based on the monitoring module.

[0022] Specifically, the monitoring module acquires the level transition status of control signals and data signals on the on-chip bus in real time through hardware probes or bypass listening.

[0023] S12: Based on the transmission status, count the number of valid data interaction events, and determine the actual transmission bandwidth of the peripheral interface controller based on the number of occurrences.

[0024] By directly counting at the underlying level using pure hardware logic, the data throughput of the peripheral interface controller within the current time window can be accurately reflected.

[0025] S13: When a data request event is detected by the on-chip bus, record the current first timestamp and the corresponding request transaction identifier.

[0026] This step is used to mark the start time and unique identity of a data transaction.

[0027] S14: When a data response event is detected and the obtained response transaction identifier matches the request transaction identifier, record the current second timestamp. A hardware identifier matching mechanism ensures that the start time and end time belong to the same data transaction.

[0028] S15: Determine the data transmission delay based on the first timestamp and the second timestamp.

[0029] This embodiment achieves accurate measurement of real data transmission bandwidth and underlying hardware latency by directly counting traffic and matching identifiers at the underlying hardware level, eliminating system overhead interference at the software level.

[0030] In another embodiment, the length of the time window is configurable. Specifically, the monitoring module has a time window register, and external software or the operating system can dynamically adjust the statistical period by configuring the value of this register.

[0031] When calculating the actual transmission bandwidth, the number of occurrences is divided by the number of clock cycles contained in the time window to obtain the actual transmission bandwidth.

[0032] Assuming a system clock frequency of 1 GHz (i.e., a single clock cycle of 1 ns), the operating system configures the time window register to 1000 clock cycles (i.e., a time window length of 1 µs). If the monitoring module detects 800 valid data interaction events within this time window, then the actual transmission bandwidth utilization of the current peripheral interface controller is 800 / 1000 = 80%. In boundary case handling, if the time window register is configured to 0, the hardware logic can default to the factory preset value (e.g., 1000) to prevent division by zero errors.

[0033] In another embodiment, the on-chip bus adopts the Advanced eXtensible Interface (AXI) protocol. For example, CHI protocol data inside the on-chip system is converted to AXI protocol via the CHI2AXI bridge and then input to the peripheral interface controller.

[0034] To this end, the method for counting the number of valid data interaction events includes counting the number of handshakes between the valid and ready signals in each channel of the on-chip bus. Specifically, the monitoring module contains combinational logic circuitry. When the valid and ready signals of a certain channel of the AXI bus are simultaneously high (i.e., logic 1) on the same rising edge of the clock, it is determined as a valid handshake, and the internal flow counter is incremented by 1.

[0035] In another embodiment, the monitoring module has a clock-driven hardware counter internally. When external software enables the delay statistics function by configuring the enable register, the hardware counter starts to increment with the system clock.

[0036] In this regard, the first timestamp is the first count value of the hardware counter when the data request event is triggered (denoted as counter start), and the second timestamp is the second count value of the hardware counter when the data response event is triggered (denoted as counter end).

[0037] The difference between the second count value and the first count value (i.e., counter end - counterstart) is then calculated as the data transmission delay. Because a hardware counter is used, the accuracy of this delay calculation can reach the clock cycle level (e.g., nanosecond level).

[0038] Furthermore, the method for detecting the on-chip bus triggering a data request event includes: detecting that a valid handshake has occurred on the read address channel (AR channel) of the on-chip bus (i.e., the arvalid and already signals are both 1), and the request transaction identifier is a read address identifier (arid).

[0039] The method for detecting the triggering data response event includes: detecting that a valid handshake has occurred on the read data channel (R channel) of the on-chip bus (i.e., the rvalid and rready signals are both 1), and the response transaction identifier is a read response identifier (rid).

[0040] The monitoring module compares the currently captured RID with the previously recorded AID in the register in real time using a hardware comparator. If they match, it triggers the recording of a second count value.

[0041] In another preferred embodiment of the present invention, a system-on-chip task scheduling method is also disclosed, such as... Figure 3 It includes the following steps: S21: Using the on-chip system performance real-time detection method in the above embodiments, the actual transmission bandwidth of the peripheral interface controller is obtained.

[0042] S22: Compare the actual transmission bandwidth with the benchmark bandwidth (i.e., the ideal bandwidth limit measured in a pure test scenario). If the difference between the actual transmission bandwidth and the benchmark bandwidth is greater than a preset first threshold (indicating that the current peripheral interface controller has low bandwidth utilization and is in an idle state), proceed to S23; if the difference between the actual transmission bandwidth and the benchmark bandwidth is less than or equal to the first threshold (indicating that the current peripheral interface controller is close to full load operation), proceed to S24.

[0043] S23: Add scheduling for input / output (I / O) intensive services in the operating system to fully utilize peripheral bandwidth.

[0044] S24: Add scheduling for computationally intensive services to the operating system to avoid bus congestion caused by continuing to issue IO requests.

[0045] Similarly, in another preferred embodiment of the present invention, another on-chip system task scheduling method is also provided, such as... Figure 4 It includes the following steps: S31: Use the on-chip system performance real-time detection method as described in the embodiment to obtain the data transmission delay.

[0046] S32: Compare the data transmission delay with the benchmark delay.

[0047] If the data transmission delay is greater than the benchmark test delay, and the difference between the data transmission delay and the benchmark test delay reaches a preset second threshold, then it is determined that the device (such as PCIeDevice) connected to the current peripheral interface controller is busy and slow to respond. In this case, execute S33; otherwise, return to S31.

[0048] S33: The operating system reduces access to devices connected to the peripheral interface controller to avoid CPU cores wasting system resources due to long waiting times for I / O responses.

[0049] In another preferred embodiment of the present invention, a system-on-a-chip is also disclosed, such as Figure 1 This system-on-a-chip is used to implement the detection method in the above embodiments. Specifically, the system-on-a-chip includes: an N2 CPU core, an on-chip bus, a CHI2AXI bridge, a peripheral interface controller, and a hardware-based monitoring module disposed between the on-chip bus and the peripheral interface controller.

[0050] The monitoring module is configured to perform the following operations: Within a preset time window, monitor the transmission status of the on-chip bus; Based on the transmission status, the number of valid data interaction events is counted and stored in a register for the external operating system to read and determine the actual transmission bandwidth of the peripheral interface controller; when the on-chip bus triggers a data request event, the current first timestamp and the corresponding request transaction identifier are recorded. When a data response event is detected and the obtained response transaction identifier matches the request transaction identifier, the current second timestamp is recorded; The first timestamp and the second timestamp are stored in a register so that the external operating system can read them and determine the data transmission delay.

[0051] After the external operating system finishes reading, it can clear the values ​​of the counter and each status register by configuring the clear register to start the next round of statistics.

[0052] The system-on-chip in this embodiment can achieve the above functions with fewer registers and combinational logic, without consuming too many additional hardware resources. It also breaks the "black box" state of the silicon chip and provides real underlying hardware data support for system performance optimization.

[0053] In summary, the on-chip system performance real-time detection method, task scheduling method, and on-chip system provided in the various embodiments of this invention achieve accurate capture of real data bandwidth and underlying hardware transmission latency by introducing a purely hardware monitoring module between the on-chip bus and the peripheral interface controller within the chip. This solution effectively eliminates the additional latency and interference caused by the software layer, CPU core, and system bus, making the actual operating state of the back-end chip visible to the upper-level operating system. Based on this accurate underlying hardware data, the operating system can dynamically and reasonably balance I / O-intensive and compute-intensive tasks, thereby significantly improving the overall operating efficiency and resource utilization of the on-chip system.

[0054] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A method for real-time performance detection of an on-chip system, characterized in that, The system-on-a-chip includes an on-chip bus and a peripheral interface controller, and a hardware-based monitoring module is provided between the on-chip bus and the peripheral interface controller; the method includes: Within a preset time window, the transmission status of the on-chip bus is monitored based on the monitoring module; Based on the transmission status, the number of valid data interaction events is counted, and the actual transmission bandwidth of the peripheral interface controller is determined based on the number of occurrences. When a data request event is detected by the on-chip bus, the current first timestamp and the corresponding request transaction identifier are recorded; When a data response event is detected and the obtained response transaction identifier matches the request transaction identifier, the current second timestamp is recorded; The data transmission delay is determined based on the first timestamp and the second timestamp.

2. The method for real-time performance detection of a system-on-a-chip according to claim 1, characterized in that, The length of the time window is configurable; the actual transmission bandwidth is obtained by dividing the number of occurrences by the number of clock cycles contained in the time window.

3. The method for real-time performance detection of a system-on-a-chip according to claim 1, characterized in that, The on-chip bus adopts the Scalable Interface (AXI) protocol. Methods for counting the number of valid data interaction events include counting the number of handshakes between valid signals and ready signals in each channel of the on-chip bus.

4. The method for real-time performance detection of a system-on-a-chip according to claim 1, characterized in that, The monitoring module is equipped with a hardware counter. The first timestamp is the first count value of the hardware counter when the data request event is triggered, and the second timestamp is the second count value of the hardware counter when the data response event is triggered; The difference between the second count value and the first count value is calculated as the data transmission delay.

5. The method for real-time performance detection of an on-chip system according to claim 4, characterized in that, The method for detecting the on-chip bus triggering a data request event includes: detecting that a valid handshake has occurred on the read address channel of the on-chip bus, and that the request transaction identifier is a read address identifier; The method for detecting a triggered data response event includes: detecting a valid handshake on the read data channel of the on-chip bus, and the response transaction identifier being a read response identifier.

6. A task scheduling method for an on-chip system, characterized in that, include: The actual transmission bandwidth of the peripheral interface controller is obtained by using the on-chip system performance real-time detection method as described in any one of claims 1 to 5. Compare the actual transmission bandwidth with the benchmark bandwidth; If the difference between the actual transmission bandwidth and the benchmark bandwidth is greater than a preset first threshold, then an I / O intensive service will be added to the operating system. If the difference between the actual transmission bandwidth and the benchmark bandwidth is less than or equal to the first threshold, then a computationally intensive service is added to the operating system.

7. A task scheduling method for an on-chip system, characterized in that, include: The data transmission delay is obtained by using the on-chip system performance real-time detection method as described in any one of claims 1 to 5; Compare the data transmission latency with the benchmark latency; If the data transmission delay is greater than the benchmark test delay, and the difference between the data transmission delay and the benchmark test delay reaches a preset second threshold, then the access services to the devices connected to the peripheral interface controller are reduced.

8. A system-on-a-chip, characterized in that, include: On-chip bus; Peripheral interface controller; And a hardware-based monitoring module located between the on-chip bus and the peripheral interface controller; The monitoring module is configured to perform the following operations: Within a preset time window, monitor the transmission status of the on-chip bus; Based on the transmission status, the number of valid data interaction events is counted and stored in a register for the external operating system to read and determine the actual transmission bandwidth of the peripheral interface controller. When a data request event is detected by the on-chip bus, the current first timestamp and the corresponding request transaction identifier are recorded; When a data response event is detected and the obtained response transaction identifier matches the request transaction identifier, the current second timestamp is recorded; The first timestamp and the second timestamp are stored in a register so that the external operating system can read them and determine the data transmission delay.

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