General ip core supporting biss-c protocol and communication method

Abstract

This invention discloses a general-purpose IP core and communication method supporting the BISS-C protocol. The IP core includes an input terminal, a data processing module, and an output terminal. The input terminal provides a reference clock and receives serial input data under the BISS-C protocol, and indicates reset, data output length, data read, CRC check, and clock output signal delay. The data processing module responds to instructions from the control unit and parses the serial input data using the reference clock. The output terminal outputs the parsed data in parallel, synchronizes the data transmission of the serial input data, and indicates the status of the data parsing process. The technical solution of this invention not only efficiently completes the functions of the BISS-C protocol but can also be used on various types of FPGAs.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to a general-purpose IP core and communication method that supports the BISS-C protocol. Background Technology

[0002] To meet the real-time communication requirements of absolute position sensors in high-precision, high-dynamic motion control systems, BISS-C was developed. BISS-C is a fully digital, open-source synchronous serial communication protocol primarily used to establish a reliable, high-speed data link between BISS-C master devices and BISS-C slave devices (absolute position sensors, such as linear scales and encoders). The operation of the point-to-point connected BISS-C master and slave devices relies mainly on clock and data signals, and data exchange is achieved through a unique frame structure.

[0003] In the embedded systems field, all operations of an FPGA, such as protocol state machines, CRC calculations, and data shifting, can be executed synchronously and in parallel, with response times in the nanosecond range. This is crucial for BISS-C slave devices that require high-speed, real-time position feedback. Different FPGA models from different manufacturers vary, and IP cores using features specific to a particular FPGA model can only run on that specific FPGA, significantly reducing the versatility of the IP cores.

[0004] For the point-to-point connection between BISS-C master and BISS-C slave devices in the BISS-C protocol, designing a general-purpose IP core based on FPGA is particularly important. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a general IP core and communication method that supports the BISS-C protocol.

[0006] In a first aspect, the present invention provides a general-purpose IP core supporting the BISS-C protocol, comprising:

[0007] Input terminal, data processing module, and output terminal;

[0008] The input terminal includes: a clock unit, a reset unit, a configuration unit, a control unit, a serial input unit, a verification enable unit, and a delay control unit; wherein, the clock unit is used to provide a reference clock for the IP core operation; the reset unit is used to initialize the internal state of the IP core; the configuration unit is used to configure the output length of the position data; the control unit is used to instruct the data processing unit to read the position data when a data read request is triggered; the serial input unit is used to receive serial input data under the BISS-C protocol; the verification enable unit is used to instruct the CRC verification module to perform data verification when the CRC verification function is triggered; and the delay control unit is used to control the delay of the clock output signal and adjust the phase relationship between the clock output signal and the serial input data;

[0009] The data processing module is used to respond to the instructions of the control unit and parse the serial input data with a reference clock; the data processing module includes a position data reading state machine and a CRC check module; wherein, the position data reading state machine is used to parse the position data from the serial input data according to the timing requirements of the BISS-C protocol; the CRC check module is used to respond to the instructions of the check enable unit and perform data check on the position data.

[0010] The output terminal includes an output unit, a valid indicator unit, a synchronization clock unit, an error indicator unit, and a warning indicator unit; wherein, the output unit is used to output the parsing result of the data processing unit; the valid indicator unit is used to indicate that the data parsed by the data processing unit is valid; the synchronization clock unit is used to synchronize the data transmission of serial input data under the BISS-C protocol; the error indicator unit is used to indicate that there is an error in the parsing process of the data processing unit; and the warning indicator unit is used to indicate that there is an anomaly in the parsing process of the data processing unit.

[0011] Furthermore, while the location data reading state machine parses the location data, the CRC check module performs data verification on the location data; the CRC check module uses a polynomial... Perform a 6-bit CRC check, where X represents the bit of the position data.

[0012] Furthermore, the reference clock in the IP core is divided by 8 to obtain the clock output signal in the IP core; the IP core indicates the clock model to the BISS-C slave device through the clock output signal, and receives the position data of the BISS-C slave device through serial input data.

[0013] Furthermore, the initial state of the location data reading state machine is an idle state;

[0014] When a data read request is triggered, the control signal is pulled high by a reference clock, and the position data read state machine enters the read request state from the idle state and waits for the confirmation signal from the BISS-C slave device.

[0015] Furthermore, when an acknowledgment signal is received from the BISS-C slave device, the location data reading state machine changes from the read request state to the wait-to-start state and waits for the start signal from the BISS-C slave device.

[0016] When the start signal from the BISS-C slave device is received, the position data reading state machine changes from the waiting start state to the receiving initial bit state and waits for the key bit signal from the BISS-C slave device.

[0017] When the key bit signal from the BISS-C slave device is received, the position data reading state machine enters the position data receiving state from the initial bit receiving state and begins to parse the position data from the serial input data.

[0018] Furthermore, if the CRC check fails or the parsing process of the data processing unit is incorrect, the output unit outputs a specific piece of data.

[0019] If the CRC check is correct and the data processing unit's parsing process is error-free, the output unit outputs the position data.

[0020] Furthermore, after the output unit outputs a specific piece of data or outputs position data, the position data reading state machine enters an idle state.

[0021] Secondly, the present invention provides a communication method between a master device and a slave device equipped with a general-purpose IP core, comprising:

[0022] After the BISS-C master device and the BISS-C slave device establish a point-to-point connection, the BISS-C master device starts the location data reading state machine in the general IP core and receives the location data of the BISS-C slave device through serial input data.

[0023] Furthermore, the initial state of the location data reading state machine is the idle state; and it sequentially enters the reading request state, the waiting start state, the receiving initial bit state, the receiving location data state, the receiving error data state, the receiving warning data state, the receiving verification data state, the verification state, and the output state.

[0024] When a data read request is triggered, the location data read state machine enters the read request state from the idle state; when an acknowledgment signal is received from the BISS-C slave device, the location data read state machine enters the waiting start state from the read request state; when a start signal is received from the BISS-C slave device, the location data read state machine enters the receive initial bit state from the waiting start state; when a key bit signal is received from the BISS-C slave device, the location data read state machine enters the receive location data state from the receive initial bit state.

[0025] Furthermore, when the location data is received, the location data reading state machine transitions from the location data receiving state to the error data receiving state; when a 1-bit error status data is received, the location data reading state machine transitions from the error data receiving state to the warning data receiving state; when a 1-bit warning status data is received, the location data reading state machine transitions from the warning data receiving state to the check data receiving state; when a 6-bit CRC check data is received, the location data reading state machine transitions from the check data receiving state to the verification state; and when data verification or error status determination is completed, the location data reading state machine transitions from the verification state to the output state.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] The technical solution of this invention proposes a general-purpose IP core that supports the BISS-C protocol. The input terminal provides a reference clock and receives serial input data under the BISS-C protocol. The data processing module responds to the control unit's instructions and parses the serial input data using the reference clock. The output terminal outputs the parsed data in parallel. This solution provides all the functions of a BISS-C master device to an FPGA without using any proprietary functional modules or IP cores built into the FPGA, and is suitable for various types of FPGAs. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only preferred embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A schematic diagram of the structure of a general-purpose IP core supporting the BISS-C protocol is provided for an embodiment of the present invention;

[0030] Figure 2This is a schematic diagram of the connection between a BISS-C master device and a BISS-C slave device provided in an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram illustrating the communication process between a BISS-C master device and a BISS-C slave device, provided as an embodiment of the present invention. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] Figure 1 A schematic diagram of a general-purpose IP core supporting the BISS-C protocol is provided for an embodiment of the present invention, as shown below. Figure 1 As shown, this general-purpose IP core specifically includes an input terminal, a data processing module, and an output terminal. Furthermore, this general-purpose IP core is implemented using Verilog, without using any vendor-specific IP cores or primitives, and can be adapted to the vast majority of FPGAs.

[0034] The input terminals include a clock unit, a reset unit, a configuration unit, a control unit, a serial input unit, a verification enable unit, and a delay control unit. The clock unit provides the reference clock for the IP core's operation; the reset unit initializes the internal state of the IP core; the configuration unit configures the output length of the position data; the control unit instructs the data processing unit to read the position data when a data read request is triggered; the serial input unit receives serial input data under the BISS-C protocol; the verification enable unit instructs the CRC verification module to perform data verification when the CRC verification function is triggered; and the delay control unit controls the delay of the clock output signal, adjusting the phase relationship between the clock output signal and the serial input data.

[0035] It should be noted that the clock unit provides the reference clock CLK for the IP core's operation, serving as the main operating clock for the IP core's internal state machine, data sampling, and logic operations. The reset unit resets the IP core upon receiving a high-level reset signal RST, clearing the buffer and restoring the default configuration. The configuration unit receives the input configuration signal Resolution_Bits, which contains the bit width parameter of the position data, determining the output length of the position data (e.g., 24 bits or 32 bits), and is a crucial configuration for parsing serial input data. Upon receiving the position data read control signal Request, the control unit instructs the data processing unit to read the position data. The serial input unit receives the serial input data SL under the BISS-C protocol. This serial input data is the carrier of the core position data and requires bit-by-bit sampling in conjunction with the reference clock. The verification enable unit receives the verification enable signal CRC_Check_En, which indicates whether the CRC verification function is enabled. A high-level valid verification enable signal instructs the CRC verification module to perform data verification on the received data; a low-level signal skips the verification and directly outputs the data. The delay control unit receives the clock configuration signal Shift_MA_Clk, which contains information to adjust the phase of the clock output signal MA and the serial input data SL. By adjusting the clock configuration signal Shift_MA_Clk, the timing requirements of different external devices can be adapted. The default value of the clock configuration signal Shift_MA_Clk is 0, which means that no delay processing is performed.

[0036] The data processing module responds to instructions from the control unit and parses the serial input data using a reference clock. The data processing module includes a position data reading state machine and a CRC check module; the position data reading state machine parses position data from the serial input data according to the timing requirements of the BISS-C protocol; the CRC check module responds to instructions from the check enable unit and performs data verification on the position data.

[0037] It should be noted that the data processing module is the core of the IP core, responsible for parsing, verifying, and managing the status of serial input data. It includes two core sub-modules: the position data reading state machine and the CRC check module. The position data reading state machine is the control core of the data processing module. Based on the reference clock CLK and the control signal Request, it completes the serial data sampling, frame synchronization, and data bit extraction in stages according to the timing requirements of the BISS-C protocol. The CRC check module, controlled by the check enable signal CRC_Check_En, performs CRC redundancy checks on the read position data frames. If the check passes, the received data is considered valid, triggering the valid indication signal Position_Data_Valid; if the check fails, the data is considered incorrect, triggering the error status signal Error, and the erroneous data is discarded.

[0038] The output terminal includes an output unit, a valid indicator unit, a synchronization clock unit, an error indicator unit, and a warning indicator unit. The output unit outputs the parsing results from the data processing unit; the valid indicator unit indicates that the parsed data is valid; the synchronization clock unit synchronizes the data transmission of serial input data under the BISS-C protocol; the error indicator unit indicates an error in the parsing process of the data processing unit; and the warning indicator unit indicates an anomaly in the parsing process of the data processing unit.

[0039] It should be noted that the parallel output unit is the core output of the IP core, used to output the parsed result Position_Data from the data processing unit, and the output bit width is configured by the Resolution_Bits signal. The validity indicator unit uses the Position_Data_Valid signal to indicate that the data parsed by the data processing unit is valid. The synchronization clock unit is responsible for carrying the synchronization clock output signal MA under the BISS-C protocol, i.e., synchronizing the serial input data transmission of external devices. The phase between the clock output signal MA and the serial input data SL can be adjusted by the clock configuration signal Shift_MA_Clk. The error indicator unit uses the Error status signal to indicate data read or CRC check failure (such as frame format error, checksum mismatch), requiring external system intervention. The warning indicator unit uses the Warning status signal to indicate non-fatal anomalies (such as data read timeout, invalid request signal), reminding external systems to pay attention to the link status, but does not affect data output.

[0040] The entire IP core's operation is as follows: The external system sends a control signal Request, along with configuration signals Resolution_Bits and CRC_Check_En; the state machine responds to the request, sampling the serial input data SL bit by bit under the drive of the reference clock Clk; after sampling, the CRC check module CRC_Unit verifies the data (when enabled); after data verification, the parsing result Position_Data is output. If the parsing result is correct, the valid indication signal Position_Data_Valid is pulled high; if the parsing result is incorrect, the error status signal Error is pulled high; throughout the process, the external device is synchronized via the clock output signal MA, and link anomalies are reported via the warning status signal Warning.

[0041] Furthermore, while the location data reading state machine parses the location data, the CRC check module performs data verification on the location data; the CRC check module uses a polynomial... Perform a 6-bit CRC check, where X represents the bit of the position data.

[0042] The 6-bit CRC check is implemented using a serial data method, performing a 6-bit CRC check calculation for each bit of input data.

[0043] Furthermore, the reference clock in the IP core is divided by 8 to obtain the clock output signal in the IP core; the IP core indicates the clock model to the BISS-C slave device through the clock output signal, and receives the position data of the BISS-C slave device through serial input data.

[0044] Furthermore, the initial state of the position data reading state machine is the idle state, and in the idle state, both the serial input data and the clock output signal are set to high level;

[0045] When a data read request is triggered, the control signal is pulled high by a reference clock, the position data read state machine changes from the idle state to the read request state, and waits for the BISS-C slave device's confirmation signal.

[0046] Furthermore, when an acknowledgment signal is received from the BISS-C slave device, the location data reading state machine changes from the read request state to the wait-to-start state and waits for the start signal from the BISS-C slave device.

[0047] When the start signal from the BISS-C slave device is received, the position data reading state machine changes from the waiting start state to the receiving initial bit state and waits for the key bit signal from the BISS-C slave device.

[0048] When the critical bit signal from the BISS-C slave device is received, the position data reading state machine changes from the initial bit receiving state to the position data receiving state and begins to parse the position data from the serial input data.

[0049] Furthermore, if the CRC check fails or the data processing unit parses incorrectly, the output unit outputs a specific piece of data; if the CRC check is correct and the data processing unit parses correctly, the output unit outputs position data.

[0050] At this point, the FPGA uses a general-purpose IP core that supports the BISS-C protocol to obtain the location data of the BISS-C slave device and completes the interaction process with the BISS-C slave device.

[0051] Furthermore, after the output unit outputs a specific piece of data or outputs position data, the position data reading state machine enters an idle state.

[0052] For example, the reference clock CLK in the input is 40MHz, which serves as the operating clock for the IP core. After being divided by 8, it is sent to the synchronization clock unit to output a 5MHz clock output signal MA. When the control signal Request in the input is pulled high for one CLK cycle, the position data reading state machine is started, enabling the synchronization clock unit to output the 5MHz clock output signal MA, and begins reading position data from the serial input data SL. By default, CRC verification is performed. After reading the position data and status data, a 6-bit CRC check is performed.

[0053] If the CRC check fails or the status data indicates that the received data is incorrect, a specific piece of data, Position_Data, will be output to indicate that the data is incorrect. If the CRC check is correct and the status data indicates that the received data is correct, Position_Data containing the position data will be output. Once the CRC check is successful, the system enters the data output state, and Position_Data_Valid is set high, indicating that Position_Data is valid and readable. After data output, the position data reading state machine enters the IDLE state and waits for the next control signal, Request.

[0054] In summary, the technical solution presented in this invention proposes a general-purpose IP core supporting the BISS-C protocol. The input terminal provides a reference clock and receives serial input data under the BISS-C protocol. The data processing module responds to the control unit's instructions and parses the serial input data using the reference clock. The output terminal outputs the parsed data in parallel. This general-purpose IP core not only efficiently performs the functions of the BISS-C protocol but also allows for a single design and use on various types of FPGAs. Furthermore, it ensures system reliability and consistency.

[0055] Figure 2 This is a schematic diagram illustrating the connection structure between a BISS-C master device and a BISS-C slave device according to an embodiment of the present invention, as shown below. Figure 2 As shown, the FPGA acts as the BISS-C master device. The general-purpose IP core outputs a single-ended clock signal MA, which is converted into a differential signal by the FPGA and then connected to the BISS-C slave device. Similarly, the differential serial input data SL transmitted from the BISS-C slave device is converted into single-ended serial input data SL by the FPGA and then fed into the IP core. Furthermore, when establishing a point-to-point connection between the BISS-C master and slave devices, the SLI pin of the BISS-C slave device must be grounded.

[0056] On the other hand, embodiments of the present invention also provide a communication method between a master device and a slave device equipped with a general-purpose IP core. Figure 3 This is a schematic diagram illustrating the communication process between a BISS-C master device and a BISS-C slave device according to an embodiment of the present invention, combined with... Figure 3 The method specifically includes:

[0057] Once a point-to-point connection is established between the BISS-C master device and the BISS-C slave device, the BISS-C master device starts the location data reading state machine in the general IP core and receives the location data from the BISS-C slave device through serial input data.

[0058] The initial state of the position data reading state machine is the idle state. At this time, the clock output signal MA=1 and the serial input data SL=1. Then, it sequentially enters the read request state, the wait start state, the receive initial bit state, the receive position data state, the receive error data state, the receive warning data state, the receive check data state, the check state, and the output state.

[0059] When a data read request is triggered, the reference clock cycle is pulled high, and the position data read state machine enters the read request state from the idle state. At this time, the clock output signal MA is a 5MHz clock, and in this state, it begins to wait for the acknowledgment signal ASK (SL=0).

[0060] When the BISS-C slave device receives an acknowledgment signal, the location data reading state machine changes from the read request state to the wait-to-start state; and in this state, it begins to wait for the start signal Start (SL=1).

[0061] When the start signal from the BISS-C slave device is received, the position data reading state machine changes from the waiting start state to the receive initial bit state; and in this state, it begins to wait for the key bit signal CDS (SL=0).

[0062] When the key bit signal from the BISS-C slave device is received, the position data reading state machine enters the position data receiving state from the initial bit receiving state. At this time, it begins to receive position data through serial input data SL.

[0063] When the location data has been received, the location data reading state machine changes from the location data receiving state to the error data receiving state; at this time, it begins to receive error status data.

[0064] When one bit of error status data has been received, the position data reading state machine changes from the error data receiving state to the warning data receiving state; at this time, it begins to receive warning status data.

[0065] When the 1-bit warning status data has been received, the position data reading state machine changes from the warning data receiving state to the verification data receiving state; at this time, it begins to receive 6-bit CRC check data.

[0066] When the 6-bit CRC check data is received, the position data reading state machine enters the verification state from the receiving check data state. At this time, the CRC check is checked for correctness and the Error state is judged. If the CRC check is wrong, or the data is wrong (Error=0), a special value is assigned to the parsing result Position_Data to indicate that the data is abnormal.

[0067] When data verification or error status determination is completed, the position data reading state machine transitions from the verification state to the output state. At this time, the validity indicator signal Position_Data_Valid goes high, and the parsed result Position_Data is output as valid.

[0068] After the Position_Data parsing result is output, the state machine enters an idle state, waiting for the Request control signal for the next round of position data reading requests.

[0069] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A general-purpose IP core supporting the BISS-C protocol, characterized in that, include: Input terminal, data processing module, and output terminal; The input terminal includes: a clock unit, a reset unit, a configuration unit, a control unit, a serial input unit, a verification enable unit, and a delay control unit; wherein, the clock unit is used to provide a reference clock for the IP core operation; the reset unit is used to initialize the internal state of the IP core; the configuration unit is used to configure the output length of the position data; the control unit is used to instruct the data processing unit to read the position data when a data read request is triggered; the serial input unit is used to receive serial input data under the BISS-C protocol; the verification enable unit is used to instruct the CRC verification module to perform data verification when the CRC verification function is triggered; and the delay control unit is used to control the delay of the clock output signal and adjust the phase relationship between the clock output signal and the serial input data; The data processing module is used to respond to the instructions of the control unit and parse the serial input data with a reference clock; the data processing module includes a position data reading state machine and a CRC check module; wherein, the position data reading state machine is used to parse the position data from the serial input data according to the timing requirements of the BISS-C protocol; the CRC check module is used to respond to the instructions of the check enable unit and perform data check on the position data. The output terminal includes an output unit, a valid indicator unit, a synchronization clock unit, an error indicator unit, and a warning indicator unit; wherein, the output unit is used to output the parsing result of the data processing unit; the valid indicator unit is used to indicate that the data parsed by the data processing unit is valid; the synchronization clock unit is used to synchronize the data transmission of serial input data under the BISS-C protocol; the error indicator unit is used to indicate that there is an error in the parsing process of the data processing unit; and the warning indicator unit is used to indicate that there is an anomaly in the parsing process of the data processing unit.

2. The general-purpose IP core according to claim 1, characterized in that, While the location data reading state machine parses the location data, the CRC check module performs data verification on the location data; the CRC check module uses a polynomial... Perform a 6-bit CRC check, where X represents the bit of the position data.

3. The general-purpose IP core according to claim 1, characterized in that, The reference clock in the IP core is divided by 8 to obtain the clock output signal in the IP core; the IP core indicates the clock model to the BISS-C slave device through the clock output signal, and receives the position data of the BISS-C slave device through serial input data.

4. The general-purpose IP core according to claim 1, characterized in that, The initial state of the location data reading state machine is an idle state; When a data read request is triggered, the control signal is pulled high by a reference clock, and the position data read state machine enters the read request state from the idle state and waits for the confirmation signal from the BISS-C slave device.

5. The general-purpose IP core according to claim 4, characterized in that, Also includes: When an acknowledgment signal is received from the BISS-C slave device, the location data reading state machine changes from the read request state to the wait-to-start state and waits for the start signal from the BISS-C slave device. When the start signal from the BISS-C slave device is received, the position data reading state machine changes from the waiting start state to the receiving initial bit state and waits for the key bit signal from the BISS-C slave device. When the key bit signal from the BISS-C slave device is received, the position data reading state machine enters the position data receiving state from the initial bit receiving state and begins to parse the position data from the serial input data.

6. The general-purpose IP core according to claim 1, characterized in that, Also includes: If the CRC check fails or the data processing unit parses incorrectly, the output unit outputs a specific piece of data. If the CRC check is correct and the data processing unit's parsing process is error-free, the output unit outputs the position data.

7. The general-purpose IP core according to claim 6, characterized in that, After the output unit outputs a specific piece of data or outputs position data, the position data reading state machine enters an idle state.

8. A communication method between a master device and a slave device equipped with a general-purpose IP core as described in any one of claims 1-7, characterized in that, include: After the BISS-C master device and the BISS-C slave device establish a point-to-point connection, the BISS-C master device starts the location data reading state machine in the general IP core and receives the location data of the BISS-C slave device through serial input data.

9. The communication method according to claim 8, characterized in that, The initial state of the location data reading state machine is the idle state; and it sequentially enters the reading request state, the waiting start state, the receiving initial bit state, the receiving location data state, the receiving error data state, the receiving warning data state, the receiving verification data state, the verification state, and the output state. When a data read request is triggered, the location data read state machine enters the read request state from the idle state; when an acknowledgment signal is received from the BISS-C slave device, the location data read state machine enters the waiting start state from the read request state; when a start signal is received from the BISS-C slave device, the location data read state machine enters the receive initial bit state from the waiting start state; when a key bit signal is received from the BISS-C slave device, the location data read state machine enters the receive location data state from the receive initial bit state.

10. The communication method according to claim 9, characterized in that, Also includes: When the location data is received, the location data reading state machine changes from the location data receiving state to the error data receiving state. When one bit of error status data has been received, the position data reading state machine changes from the error data receiving state to the warning data receiving state. When one bit of warning status data has been received, the location data reading state machine changes from the warning data receiving state to the verification data receiving state. When the 6-bit CRC check data has been received, the position data reading state machine enters the check state from the check data receiving state. When data verification or error status determination is completed, the location data reading state machine changes from the verification state to the output state.

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