Processor transient execution vulnerability triggering method based on loop exit prediction mechanism
By training the predictor to exit the loop and utilizing cache side-channel technology, the performance loss and data leakage caused by processor misprediction in long iterative loops are solved, and a secure attack and defense method for obtaining sensitive data within the transient execution window is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HARBIN INST OF TECH
- Filing Date
- 2026-02-24
- Publication Date
- 2026-06-02
Smart Images
Figure CN122133154A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for triggering processor transient execution vulnerabilities based on a loop exit prediction mechanism, and belongs to the field of computer science. Background Technology
[0002] Modern mainstream branch prediction algorithms (such as TAGE, Perceptron, or GShare) primarily rely on the Global History Register (GHR) to capture the contextual dependencies of the instruction flow. For short loops, these history-based predictors typically exhibit good prediction accuracy. However, when faced with loops with long iterations, traditional predictors suffer from a severe "history saturation" problem. When the number of loop iterations exceeds the history length that the GHR can cover, the history register becomes filled with bit patterns representing "jumps." Based on this strong history pattern, the predictor predicts with extremely high confidence that the next branch will still be a jump. Therefore, when the loop reaches its termination condition and needs to exit, general-purpose predictors are highly prone to misprediction. This inevitable "loop exit misprediction" causes processor pipeline swirl, resulting not only in a performance loss of hundreds of clock cycles but also in wasted power due to speculating on incorrect execution paths. Summary of the Invention
[0003] This invention aims to solve the technical problem that the performance optimization mechanism of the loop exit predictor can be maliciously trained, forming a new type of processor transient execution vulnerability that leads to the leakage of sensitive kernel data. It proposes a processor transient execution vulnerability triggering method based on the loop exit predictor mechanism.
[0004] The technical solution of the present invention:
[0005] A method for triggering a processor transient execution vulnerability based on a loop exit prediction mechanism includes the following steps:
[0006] S1. Detect whether a loop exit predictor exists in the target processor; S2. Based on the detection results, construct attacker branch training code, and train the loop exit predictor by repeatedly executing loop code of a specific length, so that the loop exit predictor can predict exiting the loop after running to the specific loop length. S3. Trigger the victim to execute loop code containing boundary checks, wherein the actual iteration length of the victim loop code is greater than the specified iteration length; S4. When the victim loop executes to the specified loop length, due to the training result of the attacker's training code, the loop exit predictor predicts the loop exit in advance, forming a transient execution window;
[0007] S5. A memory access behavior is generated within the transient execution window, and the memory access behavior leaves a trace in the processor cache;
[0008] S6. Use cache side-channel technology to detect the traces left in the cache by the memory access behavior, thereby recovering the victim's sensitive data.
[0009] Specifically, step S1 includes:
[0010] S11. Construct loop code with a length of 64 to 1024 iterations; S12. Execute the loop code and monitor the rollback signal of the processor reorder buffer; S13. Determine whether the processor has a loop exit prediction mechanism based on the regularity of the rollback signal.
[0011] Specifically, the step of constructing attacker branch training code based on the detection results further includes the step of determining key parameters of the loop exit predictor: by constructing loop instruction structures with different instruction addresses, the upper and lower bounds of the loop length that the loop exit predictor can accommodate are determined in reverse by changing the loop length; by changing the loop instruction address, the label addressing rule of the loop exit predictor is determined in reverse by using address collision; by successively increasing the number of times loops of the same length are repeatedly executed at the same address, the minimum number of times required for the training confidence of the loop exit predictor is tested; the specific loop length is set according to the upper bound of the loop length, the label addressing rule, and the minimum number of times required for the training confidence.
[0012] Specifically, the training of the loop exit predictor includes: training the total number of iterations recorded in the loop exit predictor to the specific loop length set by the attacker by repeatedly executing loop code of a specific length; and making the iteration confidence counter of the loop exit predictor reach a high confidence threshold by repeatedly executing the same length of loop code at the same address.
[0013] Specifically, the transient execution window includes:
[0014] The loop exit predictor detects that the current pipeline count value is equal to the learned specific loop length; the loop exit predictor generates a high-priority signal and issues a loop exit prediction signal.
[0015] Specifically, the memory access behavior includes:
[0016] Within the transient execution window, the processor generates a transient out-of-bounds access based on an offset, which is the difference between a specific loop length set by the attacker and the actual loop length of the victim; the out-of-bounds access points to a cache line in the victim's address space containing private data.
[0017] Specifically, the processor is a RISC-V architecture processor, and the loop exit predictor is a dedicated hardware structure independent of the general branch predictor, including a label field, an iteration confidence counter, a current pipeline count field, and a total number of iterations field.
[0018] The beneficial effects of this invention are:
[0019] By precisely controlling the loop length trained by the attacker, the loop exit predictor can be forced to exit prematurely, bypassing boundary checks and accessing arbitrary memory locations within the transient execution window, thereby obtaining protected secret data. Combined with cache side-channel technology, secret data accessed during transient execution can be effectively recovered. This invention provides a new attack surface and defense perspective for processor microarchitecture security. Attached Figure Description
[0020] Figure 1 A schematic diagram of a general cyclic prediction optimization mechanism analysis method;
[0021] Figure 2 This diagram illustrates the triggering mechanism of a processor transient execution vulnerability based on a loop exit prediction mechanism. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0023] Example 1:
[0024] This embodiment provides a general analysis method for loop exit predictors on RISC-V processors, used to determine key parameters of the loop exit predictor of the processor under test.
[0025] like Figure 1 As shown, the method includes:
[0026] The upper and lower bounds s_cnt of the loop length that the loop exit predictor can accommodate are constructed by reversing loops of different lengths. Then, the addressing rule tag of the loop exit predictor is reversed by changing the loop instruction address. The minimum number of iterations iter required to achieve the training confidence of the loop exit predictor is tested by successively increasing the number of repetitions of loops of the same length at the same address.
[0027] Example 2:
[0028] This embodiment provides a method for triggering a processor transient execution vulnerability based on a loop exit prediction mechanism. The attack process mainly includes two stages: the attacker training stage and the triggering stage.
[0029] Step 1: Detect the loop exit prediction mechanism on the victim's processor platform
[0030] By constructing a repetitive loop code with a length of 64-1024, and detecting the rollback signal of the reorder buffer (RoB) on the corresponding platform, it is determined whether there is a corresponding loop exit prediction mechanism.
[0031] Step 2: Construct the attacker branch training code
[0032] Receive the detection results from step one and construct appropriate attacker branch training code based on those results. Train the loop exit predictor by repeatedly executing loop code of a specific length, so that it always predicts a loop exit after running to a specific loop length.
[0033] By controlling code execution, the attacker can make the target loop multiple times, thereby training the total number of iterations s_cnt in the LOOP table to a specific value atk_len set by the attacker.
[0034] Step 3: Trigger victim execution and create a transient execution window
[0035] After the attacker's branch training code in step two is completed, the attacker triggers the victim's execution. The victim contains a corresponding loop code pattern, and the boundary check conditions of the victim's loop code contain private data related to the victim's secret. The actual iteration length v_len of the victim's loop is greater than the specific loop length atk_len trained by the attacker, i.e., atk_len < v_len.
[0036] The attacker triggers the victim to execute a specific code snippet. When the victim's loop reaches a certain loop length `atk_len`, the loop exit predictor incorrectly predicts that the loop will exit prematurely due to the training results of the attacker's code. This misprediction causes the processor to enter a speculative execution state, constituting a transient execution window.
[0037] Within this transient execution window, the processor bypasses incomplete boundary checks, resulting in transient out-of-bounds access based on the offset atk_len - v_len. By finely controlling the value of atk_len, an attacker can bypass boundary checks and access arbitrary memory locations within the transient execution window, i.e., access protected, specific secret data.
[0038] Step 4: Caching side-channel leaked sensitive data
[0039] The aforementioned memory access behavior leaves traces in the processor cache. After the victim finishes executing the attack, the attacker retrieves the addresses corresponding to the traces left by the attacker through a cache side-channel, thereby inferring the victim's private data information.
[0040] Specifically, attackers can use side-channel techniques (such as Flush+Reload) to recover secret data accessed during transient execution.
Claims
1. A method for triggering a processor transient execution vulnerability based on a loop exit prediction mechanism, characterized in that, Includes the following steps: S1. Detect whether a loop exit predictor exists in the target processor; S2. Based on the detection results, construct attacker branch training code, and train the loop exit predictor by repeatedly executing loop code of a specific length, so that the loop exit predictor can predict exiting the loop after running to the specific loop length. S3. Trigger the victim to execute loop code containing boundary checks, wherein the actual iteration length of the victim loop code is greater than the specified iteration length; S4. When the victim loop executes to the specified loop length, due to the training result of the attacker's training code, the loop exit predictor predicts the loop exit in advance, forming a transient execution window; S5. A memory access behavior is generated within the transient execution window, and the memory access behavior leaves a trace in the processor cache; S6. Use cache side-channel technology to detect the traces left in the cache by the memory access behavior, thereby recovering the victim's sensitive data.
2. The processor transient execution vulnerability triggering method based on loop exit prediction mechanism according to claim 1, characterized in that, Step S1 includes: S11. Construct loop code with a length of 64 to 1024 iterations; S12. Execute the loop code and monitor the rollback signal of the processor reorder buffer; S13. Determine whether the processor has a loop exit prediction mechanism based on the regularity of the rollback signal.
3. The processor transient execution vulnerability triggering method based on loop exit prediction mechanism according to claim 1, characterized in that, The step of constructing attacker branch training code based on detection results also includes the step of determining key parameters for loop exiting the predictor: By constructing loop instruction structures with different instruction addresses, the upper and lower bounds of the loop exit predictor's loop length are determined in reverse by changing the loop length; by changing the loop instruction address, the label addressing rule of the loop exit predictor is determined in reverse by address collision; by successively increasing the number of times loops of the same length are repeatedly executed at the same address, the minimum number of times required for the training confidence of the loop exit predictor is tested; the specific loop length is set according to the upper bound of the loop length, the label addressing rule, and the minimum number of times required for training confidence.
4. The processor transient execution vulnerability triggering method based on loop exit prediction mechanism according to claim 1, characterized in that, The training of the loop exit predictor includes: training the total number of iterations recorded in the loop exit predictor to the specific loop length set by the attacker by repeatedly executing loop code of a specific length; and making the iteration confidence counter of the loop exit predictor reach a high confidence threshold by repeatedly executing the same length of loop code at the same address.
5. The method according to claim 1, characterized in that, The transient execution window comprises: The loop exit predictor detects that the current pipeline count value is equal to the learned specific loop length; the loop exit predictor generates a high-priority signal and issues a loop exit prediction signal.
6. The method according to claim 1, characterized in that, The memory access behavior includes: Within the transient execution window, the processor generates a transient out-of-bounds access based on an offset, which is the difference between a specific loop length set by the attacker and the actual loop length of the victim; the out-of-bounds access points to a cache line in the victim's address space containing private data.
7. The method according to claim 1, characterized in that, The processor is a RISC-V architecture processor, and the loop exit predictor is a dedicated hardware structure independent of the general branch predictor, which includes a label field, an iteration confidence counter, a current pipeline count field, and a total number of iterations field.