Graph structure generation method based on memory computing accelerator and memory computing accelerator

Abstract

This application relates to the field of data processing technology, and discloses a graph structure generation method and a memory computing accelerator based on a memory computing accelerator. The graph structure generation method based on the memory computing accelerator includes: a node generation module calculating the hidden state of the current node and sending it to an edge probability generation module; the edge probability generation module outputting a probability vector based on the hidden state and sending it to a Bernoulli sampling module; the Bernoulli sampling module outputting a decision vector based on the probability vector and sending it to an edge storage module; and the edge storage module receiving the decision vectors corresponding to all nodes and generating a target graph structure based on the decision vectors corresponding to all nodes. This invention can reduce computational complexity, reduce data movement, save storage space, and improve energy efficiency, thereby improving the graph structure generation effect.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a graph structure generation method and a memory computing accelerator based on a memory computing accelerator. Background Technology

[0002] Graph structures are core data models for representing complex relationships between entities, with applications spanning molecular design, materials discovery, bioinformatics, and social network analysis. However, efficiently generating large-scale, sparse graph structures in real-world scenarios remains a significant challenge. While traditional software-based deep generative models have made significant progress in this task, their inherent computational and energy efficiency bottlenecks limit their application potential in resource-constrained or real-time-critical environments.

[0003] Currently, the hardware implementation of mainstream depth map generation models faces the following challenges: First, models based on Variational Auto-Encoders (VAEs), such as GraphVAE, need to decode the entire adjacency matrix containing N nodes at once, resulting in a computational complexity as high as O(N). 2 As the graph size increases, this complexity increases quadratically, leading to huge overhead in computation, memory, and bandwidth. Secondly, while models based on Generative Adversarial Networks (GANs), such as GraphGAN, avoid the computational complexity of full-graph decoding, their training process is generally unstable and suffers from pattern collapse, causing convergence control and reliability issues in the hardware implementation. Furthermore, Transformer models based on self-attention mechanisms and Diffusion models based on probabilistic diffusion also face scalability problems. Transformer models require significant resources to construct and store N×N self-attention matrices, while diffusion models require numerous iterations for noise reduction, both resulting in extremely high latency and high buffer resource consumption.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] The main purpose of this application is to provide a graph structure generation method and a memory computing accelerator based on a memory computing accelerator, which aims to solve the problem that the graph structure generation effect is poor due to the high computational and storage complexity, poor training stability and high number of iterations in the traditional graph generation model in the prior art.

[0006] The first aspect of this application provides a graph structure generation method based on a memory computing accelerator. The graph structure generation method is applied to a memory computing accelerator, which includes a node generation module, an edge probability generation module, a Bernoulli sampling module, and an edge storage module. The graph structure generation method based on the memory computing accelerator includes: The node generation module calculates the hidden state of the current node and sends it to the edge probability generation module; The edge probability generation module outputs a probability vector based on the hidden state and sends it to the Bernoulli sampling module; The Bernoulli sampling module outputs a decision vector based on the probability vector and sends it to the edge storage module; The edge storage module receives the decision vectors corresponding to all nodes and generates the target graph structure based on the decision vectors corresponding to all nodes.

[0007] Optionally, in one embodiment of this application, the graph structure generation method based on a memory computing accelerator further includes: The control logic module generates graph generation instructions and obtains the current node status according to the graph generation instructions; The control logic module generates node calculation instructions based on the current node state and sends them to the node calculation module; The control logic module generates an edge probability calculation instruction based on the hidden state and sends it to the edge probability generation module; The control logic module generates a sampling instruction based on the probability vector and sends it to the Bernoulli sampling module; The control logic module generates a storage instruction based on the decision vector and sends it to the edge storage module.

[0008] Optionally, in one embodiment of this application, calculating the hidden state of the current node state specifically includes: Receive the current input vector and the previous cell state vector, and obtain the concatenation vector based on the current input vector and the previous cell state vector; The splicing vector is input into the ReRAM cross switch array to obtain input projection data and peephole gating data; The hidden state of the current cell state and the current node state is calculated based on the input projection data and the peephole gating data.

[0009] Optionally, in one embodiment of this application, the step of outputting a probability vector based on the hidden state specifically includes: Based on the hidden state, output the corresponding analog current data on each of the multiple bit lines; Based on the simulated current data corresponding to each of the multiple bit lines, output a probability vector showing that there are edge connections between the new node and multiple candidate nodes.

[0010] Optionally, in one embodiment of this application, the step of outputting a decision vector based on the probability vector specifically includes: Generate multiple random numbers; Based on the multiple random numbers and the multiple elements corresponding to the probability vector, multiple output results are obtained; A decision vector is formed based on the multiple output results.

[0011] Optionally, in one embodiment of this application, generating the target graph structure based on the decision vectors corresponding to all nodes specifically includes: For each decision vector, the target position of the decision vector in the sparse adjacency matrix is ​​determined according to the breadth-first search order; The target graph structure is obtained based on the target positions corresponding to each of the decision vectors.

[0012] Optionally, in one embodiment of this application, the step of generating the target graph structure based on the decision vectors corresponding to all nodes further includes: Sparse data is obtained from the edge storage module, and the sparse data is shifted and aligned to obtain valid data; Calculate the zero-bit data, and merge the valid data and the zero-bit data to output the complete adjacency matrix rows.

[0013] The second aspect of this application also provides a memory computing accelerator for a graph structure generation method based on a memory computing accelerator according to any one of the above solutions, wherein the memory computing accelerator includes a node generation module, an edge probability generation module, a Bernoulli sampling module, and an edge storage module. The node generation module is connected to the edge probability generation module, the edge probability generation module is connected to the Bernoulli sampling module, and the Bernoulli sampling module is connected to the edge storage module. The node generation module is used to calculate the hidden state of the current node and send it to the edge probability generation module; the edge probability generation module is used to output a probability vector based on the hidden state and send it to the Bernoulli sampling module; the Bernoulli sampling module is used to output a decision vector based on the probability vector and send it to the edge storage module; the edge storage module is used to receive the decision vectors corresponding to all nodes and generate the target graph structure based on the decision vectors corresponding to all nodes.

[0014] Optionally, in one embodiment of this application, the memory computing accelerator further includes a control logic module, which is connected to the node generation module, the edge probability generation module, the Bernoulli sampling module, and the edge storage module, respectively. The control logic module is used to coordinate the timing of the node generation module, the edge probability generation module, the Bernoulli sampling module, and the edge storage module.

[0015] Optionally, in one embodiment of this application, the memory computing accelerator further includes a matrix reconstruction module, which is connected to the edge storage module and the control logic module respectively; The matrix reconstruction module is used to output the complete adjacency matrix rows.

[0016] Beneficial Effects: This application provides a graph structure generation method and a memory computing accelerator based on a memory computing accelerator. This invention deeply integrates an autoregressive generation process with a ReRAM memory computing architecture. The node generation module (first ReRAM array) receives the current input and the previous cell state, performs SRU calculation in parallel through a single read operation, and outputs the hidden state of the current node. The edge probability generation module (second ReRAM array, physically reusable with the first array) inputs the hidden state into a 2-layer MLP and outputs a connection probability vector between the new node and the previous M candidate nodes. The Bernoulli sampling module uses LFSR to generate random numbers, compares them in parallel with the probability vectors, and outputs the binary decision vectors of all candidate edges within one clock cycle. The edge storage module (1T1R ReRAM array) writes the decision vectors as a partial adjacency matrix in BFS order, repeating the above steps until a complete graph structure with a predetermined number of nodes N is generated. This reduces computational complexity, reduces data movement, saves storage space, and improves energy efficiency, thereby improving the graph structure generation effect. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the data path of the memory computing accelerator in this application; Figure 2 This is a flowchart of a preferred embodiment of the graph structure generation method based on a memory computing accelerator according to this application; Figure 3This is a schematic diagram of projection weight mapping in a preferred embodiment of the graph structure generation method based on a memory computing accelerator in this application; Figure 4 This is a schematic diagram illustrating the edge writing and adjacency matrix reading process in a preferred embodiment of the graph structure generation method based on a memory computing accelerator in this application. Figure 5 This is a schematic diagram of the pipeline timing of the crossbar switch array and the process of time multiplexing multiple graphs in the pipeline, which is a preferred embodiment of the graph structure generation method based on the memory computing accelerator of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and effects of this application clearer and more explicit, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only possible technical implementations of this application and not all possible implementations. Based on the embodiments in this application, those skilled in the art can obtain other embodiments without creative effort, and these embodiments are also within the protection scope of this application.

[0020] First, let's introduce the terms used in the embodiments of this application: Memristor / ReRAM: Resistive Random Access Memory, a novel type of non-volatile memory, whose resistance value can be changed by applying an electrical pulse (high resistance represents 0, low resistance represents 1). Its role in this invention: Not only a storage unit, but also a computing unit. Utilizing Ohm's law and Kirchhoff's laws, when an input voltage is applied to the ReRAM cross-array, the output current is naturally the sum of the product of the "input vector" and the "stored weight matrix," achieving "in-memory computing," fundamentally avoiding the energy consumption and latency associated with data transfer between the processor and memory in traditional architectures.

[0021] Cross-switch array: A two-dimensional grid structure in which ReRAM memory cells are arranged at the intersections of row lines (word lines) and column lines (bit lines), with each intersection being a memory cell. Its role in this invention: It is the physical basis for performing analog domain vector-matrix multiplication; the input vector is applied as a voltage to each row, and current flows out along each column; the magnitude of the column current represents the calculation result; the first and second ReRAM cross-switch arrays map the weights of SRU and MLP, respectively.

[0022] 1T1R structure: This refers to a ReRAM memory cell consisting of a transistor and a memristor connected in series. "1T" is used for gating to prevent read / write crosstalk; "1R" is used for data storage. Its role in this invention: Used in edge storage modules. Compared to simple cross-arrays, this structure offers better controllability and reliability, making it suitable as a graph data storage medium requiring frequent and precise programming and reading.

[0023] Simple Recurrent Unit (SRU): A simplified version of the recurrent neural network unit. Compared to LSTM or GRU, SRU simplifies the core recurrent computation by moving most of the complex computations (such as interactions between gating nodes) forward, making it more suitable for parallelization. Its role in this invention: The core algorithm of the node generation module. Due to its simple computation graph, it can be mapped very efficiently onto a ReRAM array (especially through block diagonal matrix mapping), achieving single-cycle parallel computation, perfectly meeting the "hardware-friendly" requirement of memory computing.

[0024] Autoregressive generation: A sequence generation paradigm that predicts and generates the next element based on a portion of the already generated sequence. Its role in this invention: It refers to the graph generation process, generating nodes one by one and determining the connections between each new node and all previous nodes. Utilizing the sparsity of the graph (new nodes are only connected to some existing nodes), it avoids generating the entire dense matrix at once, as is done with VAEs.

[0025] Gating weights and the peephole: In a recurrent cell, "gating" controls the retention and forgetting of information; "peephole" refers to the fact that the generation of the gating signal not only depends on the current input and the hidden state of the previous time step, but also on the cell state of the previous time step. Its role in this invention: This is a computational term in the SRU. By mapping the gating weights to a block diagonal matrix and coordinating them with the concatenated input vector, the peephole computation can be completed simultaneously and in parallel on the ReRAM array with the conventional input projection computation.

[0026] In contrast, autoregressive generative models based on Recurrent Neural Networks (RNNs), such as GraphRNN, employ a sequential "generate-decision" workflow. This involves generating nodes one by one and determining the connections between each new node and previous nodes sequentially. This approach naturally leverages the sparsity of graphs, avoiding the overall O(N) time complexity. 2 ) operation. However, this process was implemented by Feng. When running on a von Neumann computer architecture, frequent, small-batch matrix-vector computation requests are generated, resulting in continuous background data movement between computing units and memory. This dynamic and sparse node and edge generation process is incompatible with the fixed computing mode designed for static data flow in traditional hardware, thus generating additional control overhead and data movement energy consumption.

[0027] In recent years, in-memory computing (IMC) architectures have significantly reduced data movement by integrating computational functions within memory, providing a viable solution for accelerating machine learning workloads. Related research has demonstrated the potential of IMC in graph neural network inference, generative adversarial network training, and Transformer model acceleration. However, due to the irregular and dynamically evolving nature of graph generation processes, static data flows cannot be predefined, and existing IMC platforms cannot effectively handle graph structure generation tasks. Therefore, there is an urgent need in this field for an innovative hardware acceleration solution that can overcome the computational bottlenecks of existing deep graph generation models and fully leverage the high energy efficiency of IMC to support efficient and scalable graph structure generation processes.

[0028] It is worth noting that this application addresses the pain points of traditional in-memory computation graph generation through the following dedicated mechanisms: First, operator fusion mapping: the gate weights and peephole weights of the SRU are fused into the same ReRAM array through a diagonal matrix mapping, completing complex computations in a single read operation. Second, parallel sampling: single-cycle parallel Bernoulli sampling is implemented using digital logic circuits, replacing the inefficient serial cyclic sampling in software. Third, sliding window storage: utilizing BFS characteristics, the N×N sparse adjacency matrix storage is compressed into an N×M regular dense storage, solving the problem of dynamic sparse writing. Fourth, pipeline scheduling: time-division pipelines in the digital / analog domains mask the latency caused by irregular control.

[0029] Scalability comes from three levels: First, parameter scalability: N (maximum number of nodes) and M (maximum number of previous nodes / candidate window) are configurable; Second, storage / bandwidth scalability: N×M windowed sparse adjacency storage, which expands linearly with M rather than N²; Third, computational resource scalability: cross arrays can be expanded through multi-array parallel / tiling; control logic supports pipelines and multi-graph polling to maintain high utilization.

[0030] like Figure 1As shown, the memory computing accelerator described in the preferred embodiment of this application is an autoregressive graph structure generation accelerator architecture based on memristors (ReRAM). The purpose of this invention is to combine a ReRAM memory computing array with dedicated digital computing circuits, and through algorithm-hardware co-optimization, overcome the data movement bottleneck and computational irregularities caused by dynamic sparsity in graph generation tasks. This improves the efficiency of operations such as serialized node and edge generation, in-situ probabilistic sampling, and sparse adjacency storage, thereby maintaining the quality of graph structure generation while significantly improving the energy efficiency of graph structure generation.

[0031] Understandably, the algorithm layer employs SRU and BFS sorting strategies suitable for hardware streaming processing. The hardware layer customizes a diagonal weight mapping to fit the SRU algorithm and a bucket shifter to adapt to the reconstruction of BFS data. This design, which specifically customizes the hardware storage format and computational data flow for specific algorithm characteristics, is known as co-optimization. In this application, parallel probabilistic sampling is implemented using a hardware LFSR and comparators; the sparse graph structure is stored using BFS ordering and a ReRAM dense array, eliminating the need for complex sparse index overhead; and the time-dependent computation of SRU is integrated using an in-memory computation array.

[0032] See Figure 1 The memory computing accelerator provided in this application embodiment is used to implement a graph structure generation method based on a memory computing accelerator. The memory computing accelerator includes a node generation module, an edge probability generation module, a Bernoulli sampling module, and an edge storage module; The node generation module is connected to the edge probability generation module, the edge probability generation module is connected to the Bernoulli sampling module, and the Bernoulli sampling module is connected to the edge storage module. The node generation module is used to calculate the hidden state of the current node and send it to the edge probability generation module; the edge probability generation module is used to output a probability vector based on the hidden state and send it to the Bernoulli sampling module; the Bernoulli sampling module is used to output a decision vector based on the probability vector and send it to the edge storage module; the edge storage module is used to receive the decision vectors corresponding to all nodes and generate the target graph structure based on the decision vectors corresponding to all nodes.

[0033] In one embodiment of this application, the memory computing accelerator further includes a control logic module, which is connected to the node generation module, the edge probability generation module, the Bernoulli sampling module, and the edge storage module, respectively. The control logic module is used to coordinate the timing of the node generation module, the edge probability generation module, the Bernoulli sampling module, and the edge storage module.

[0034] Specifically, the node generation module includes a first ReRAM cross-switch array, and the node generation module is configured to store the weights of simple cyclic units (SRUs) and perform vector-matrix multiplication operations to generate the hidden state of the node based on the input sequence; The edge probability generation module includes a second ReRAM cross switch array. The edge probability generation module is configured to receive the hidden state of the node and output a probability vector that there are edge connections between the new node and multiple candidate nodes. The Bernoulli sampling module, including digital logic circuits, is configured to be coupled with the edge probability generation module to sample the probability vectors of edge connections in parallel and generate the corresponding binary edge decision vectors. The edge storage module includes a 1T1R ReRAM cell array, and the edge storage module is configured to store the binary edge decision vectors in breadth-first search (BFS) order and form a partial adjacency matrix of the graph; The control logic module, including a central controller and a state machine, is configured to coordinate the timing and control of the node generation module, edge probability generation module, Bernoulli sampling module, and edge storage module to successfully execute the autoregressive graph generation process.

[0035] In this embodiment of the application, the weights of the SRU in the node generation module include input projection weights W and W'. f W r and gating weight W c Among them, the gating weight W c The data is mapped into the first ReRAM crossbar switch array in the form of a block diagonal matrix, so that the calculation of the peephole term of the gate switch is completed by performing a single read operation on the first ReRAM crossbar switch array.

[0036] In this embodiment, the first ReRAM cross switch array is configured to simultaneously receive the current input vector and the previous cell state vector, concatenate the current input vector and the previous cell state vector into a new input vector, and compute the input projection and peephole term of the SRU in parallel through a single operation.

[0037] In this embodiment, the Bernoulli sampling module includes structures such as a linear feedback shift register (LFSR), an sigmoid activation function unit, and a comparator, and performs parallel sampling operations on all candidate edge probabilities in the probability vector within a single clock cycle.

[0038] In this embodiment, the output of the edge probability generation module (MLP) is usually an unnormalized numerical value (Logits), which must first be mapped to the [0,1] interval by the sigmoid activation function to become a "probability value" before it can be compared with the random number generated by LFSR.

[0039] In this embodiment of the application, the edge storage module only stores a portion of the columns of the adjacency matrix of the graph structure. The width of the portion of the columns is determined by a predetermined maximum number of previous nodes, which is less than the maximum number of nodes in the graph.

[0040] In this embodiment, the first ReRAM cross switch array and the second ReRAM cross switch array are physically the same ReRAM cross switch array. The node generation module and the edge probability generation module are time-division multiplexed through the control logic module when using the ReRAM cross switch array.

[0041] In this embodiment, the control logic module pipelines the operations of multiple SRU layers, ensuring that the crossbar switch array operation performed in one layer coincides with the digital logic operation performed in the previous layer. The control logic module uses a polling method to switch between multiple graph structure generation sequences with similar order to maintain pipeline saturation and achieve multi-graph concurrency generation.

[0042] In one embodiment of this application, the memory computing accelerator further includes a matrix reconstruction module, which is connected to the edge storage module and the control logic module respectively; The matrix reconstruction module is used to output the complete adjacency matrix rows.

[0043] In this embodiment of the application, the accelerator further includes a matrix reconstruction module, which includes: A cylindrical shifter is configured to shift a portion of data read from the edge storage module by node index, wherein the number of bits in the portion of data is the maximum number of previous nodes; A zero generator is configured to generate multiple zeros, the number of which is the maximum number of nodes in the graph minus the maximum number of previous nodes. A multiplexer array is configured to merge shifted portions of data with multiple zero bits to output a complete adjacency matrix row, the number of bits in the adjacency matrix row being equal to the maximum number of nodes in the graph.

[0044] This invention simplifies the loop unit by utilizing a hardware-compatible SRU, fuses the SRU weights using a ReRAM crossbar switch array, and generates the adjacency matrix using BFS sequence. This enables the in-memory computation graph structure generation accelerator to reduce computational complexity, significantly reduce storage and computational overhead, and improve the utilization rate of the ReRAM array. It provides an ideal high-speed and high-energy-efficiency solution for large-scale graphics processing tasks.

[0045] The technical solutions of this application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0046] The graph structure generation method based on a memory computing accelerator described in the preferred embodiment of this application, such as... Figure 2 As shown, the graph structure generation method based on a memory computing accelerator includes the following steps: In step S101, the node generation module calculates the hidden state of the current node and sends it to the edge probability generation module.

[0047] In this application, computational complexity is reduced by using a hardware-compatible SRU and the weights of the entire SRU are fused onto a ReRAM array, effectively reducing storage footprint and computational overhead. This accelerator is a system integrating multiple modules, with its main workflow being: node generation – edge probability generation – edge sampling – edge writing, which is executed cyclically until a complete graph structure is generated. The entire process is centrally scheduled by the control logic module. It is understandable that the Simple Recurrent Unit (SRU) is a lightweight recurrent neural network variant optimized for parallelization acceleration, eliminating most temporal dependencies while maintaining LSTM-level performance. GraphRNN's autoregressive mechanism generates a new node at each time step and determines the connections (edges) between this new node and existing nodes.

[0048] Step S101 specifically includes: receiving the current input vector and the previous cell state vector, and obtaining a splicing vector based on the current input vector and the previous cell state vector; inputting the splicing vector into the ReRAM cross switch array to obtain input projection data and peephole gating data; and calculating the hidden state of the current cell state and the current node state based on the input projection data and the peephole gating data.

[0049] Specifically, the node generation module includes a first ReRAM cross-connected switch array for storing the weights of Simple Recurrent Units (SRUs) and performing vector-matrix multiplication operations to generate the hidden states of nodes based on the input sequence. The node generation module is the computational core for performing sequential node generation and mainly includes the following functions: SRU weight mapping: Reference Figure 3 Project the input weights W and W' of the SRU. f W r Mapped in a dense layout onto different rows of the first ReRAM crossbar switch array, and the gating weight W is applied. c (W) fc and Wrc The input x is mapped to the first ReRAM cross-switch array in the form of a block diagonal matrix; where W is the input projection weight, used to process the input x. t W f The Forget Gate Weight determines how much of the old state is retained; W r To reset the gate weights, it determines how much new input to use; W c Peephole weight, also known as gate weight, is a unique structure of SRUs that directly applies the cell state c{t-1} to the gate; W fc and W rc The weight of the forget gate, W rc It is W c Reset gate weights.

[0050] Computational Fusion: To enable parallel computing operations on the accelerator, the input vector of the node generation module is designed to be the current input vector x. t (correspond Figure 1 The left side inputs Node(k) from the data stream (i.e., the node feature vector input at the current time) and the previous cell state vector c. {t-1} The concatenated vector [x] of the state feedback from the previous time step t c {t-1} ]( Figure 1 The input data stream actually includes the current input Node(k) and the state feedback of the previous time step. During hardware execution, these two parts of data are concatenated and sent to the word line (WL) of the ReRAM array. When the concatenated vector is input into the first ReRAM crossbar switch array, since the gating weight is mapped to a block diagonal matrix, the first ReRAM crossbar switch array completes the calculation of the input projection and the peephole term in parallel in a single read operation and directly sums and outputs it in the analog domain. Digital post-processing: Reference Figure 3 The analog current signal output from the first ReRAM cross-connect array is converted into a digital signal by an 8-bit analog-to-digital converter (ADC) and then sent to the subsequent digital computing unit to perform the element-wise operations required in the SRU formula. Finally, the hidden state h of the current node (referring to the k-th node generated in the current time step) is output. t and the updated cell state c t . Figure 3 This illustrates the in-memory mapping scheme for the SRU operator: On the left, the input vector x t and the cell state c at the previous moment {t-1}They are spliced ​​together. In the middle, a ReRAM array stores the weights, where W, W... f W r Dense storage, while W c (Peeping hole weights) are sparsely stored below in a block-diagonal format. The operation, through a single VMM (vector-matrix multiplication) operation, simultaneously computes U. xt The terms with Wc⊙c{t-1}. On the right, after the simulation result is converted by the ADC, the remaining nonlinear activation (Sigmoid) and element-wise multiplication and addition are completed by digital circuits (SFU / Multipliers).

[0051] In step S102, the edge probability generation module outputs a probability vector based on the hidden state and sends it to the Bernoulli sampling module.

[0052] Step S102 specifically includes: outputting the analog current data corresponding to each of the multiple bit lines according to the hidden state; and outputting the probability vector that there are edge connections between the new node and multiple candidate nodes according to the analog current data corresponding to each of the multiple bit lines.

[0053] Specifically, the edge probability generation module consists of a second ReRAM cross-switch array, which stores the weights of a multilayer perceptron (MLP) with a layer count of 2 (not limited to this). The second ReRAM cross-switch array stores the hidden state h output by the node generation module. k As input, it outputs a probability vector θ of length equal to the maximum number of previous nodes. k The element θ in the vector k [i] represents the probability that the new node (generated by the SRU node generation module at the current time step in the autoregressive process) is connected to the i-th candidate node. It can be understood that for graph-structured data (edge ​​storage module): this is achieved by setting a maximum number of previous nodes (M), utilizing the BFS property to reduce the storage complexity of the full graph adjacency matrix from O(N²) to linear O(N×M). Candidate nodes are selected from previous nodes, but not randomly. Instead, based on the BFS (Breadth-First Search) order, the M logically closest previous nodes to the current node (i.e., nodes within the window defined by the maximum number of previous nodes) are selected to leverage the locality of graph structure and reduce computational dimensionality.

[0054] In actual setup, to save chip area, the second ReRAM cross switch array and the first ReRAM cross switch array are physically the same ReRAM cross switch array. Through time-division multiplexing of control logic, the first ReRAM cross switch array and the second ReRAM cross switch array are called respectively to execute node generation and edge probability generation tasks in sequence.

[0055] In step S103, the Bernoulli sampling module outputs a decision vector based on the probability vector and sends it to the edge storage module.

[0056] Step S103 specifically includes: generating multiple random numbers; obtaining multiple output results based on the multiple random numbers and multiple elements corresponding to the probability vector; and forming a decision vector based on the multiple output results.

[0057] Specifically, the Bernoulli sampling module consists of digital logic circuits that convert probability vectors into concrete edge decisions. The Bernoulli sampling module performs this operation primarily in the following ways: Random number generation: Integrate a linear feedback shift register (LFSR) and use the LFSR to generate pseudo-random numbers; Probability Comparison: An integrated comparator compares the pseudo-random number generated by the LFSR with the element θ in the probability vector output by the edge probability generation module. k [i] Compare in parallel; Parallel Output: The comparator outputs the binary edge decision vectors of all candidate edges in one clock cycle, thereby achieving high-speed, low-latency edge generation. A candidate edge is defined in the autoregressive generation process: when the k-th new node is generated, the algorithm stipulates that it can only connect to the M nodes that were just generated before it (i.e., previous nodes). These M potential new-node-old-node relationships constitute the candidate edge. The binary edge decision vector represents the final determined connection relationship (graph topology) between the current new node and those M previous nodes.

[0058] In step S104, the edge storage module receives the decision vectors corresponding to all nodes and generates the target graph structure based on the decision vectors corresponding to all nodes.

[0059] Step S104 specifically includes: for each decision vector, determining the target position of the decision vector in the sparse adjacency matrix according to the breadth-first search order; and obtaining the target graph structure based on the target positions corresponding to all the decision vectors.

[0060] Specifically, the edge storage module is responsible for storing the graph structure being generated. (See reference...) Figure 4 The edge storage module consists of a 1T1R ReRAM cell array. It sequentially stores the binary edge decision vectors using breadth-first search (BFS) of the graph, and forms and stores a partial adjacency matrix of the graph. The width (number of columns) of the partial adjacency matrix is ​​determined by a predetermined maximum number of previous nodes M. Based on the value of M and the maximum number of nodes N in the graph, the storage requirement of the edge storage module will be O(N). 2The computational cost is significantly reduced to O(N*M). It is important to note that the value of M is based on the BFS sorting characteristics of the graph. In most real-world graphs, long-distance connections are extremely rare under BFS order. If M is chosen too small, a very small number of long-distance edges will be lost (resulting in a slight decrease in accuracy). However, in return, the storage space and computational cost are reduced from quadratic to linear, and the hardware energy efficiency is greatly improved. This is a worthwhile engineering trade-off.

[0061] Figure 4 This demonstrates edge storage and reconstruction. The top left corner shows the diagonal strip storage method of the adjacency matrix (only the blue part is stored), and the top right corner shows the circuit implementation: During writing, the controller selects the word line WL and writes a row of M data in parallel through the bit line BL; during reading, the read M bits of data are shifted according to the current node index k by the Barrel Shifter below, and then zeroed out by the Zero Generator, finally restoring the complete N-dimensional adjacency matrix row vector. SL means: SourceLine, which is the common line connecting the transistor sources in the 1T1R structure, used to form a current loop. In 1T1R, T stands for Transistor, used to control the selection of R devices, i.e., resistive random access memory (ReRAM). This application uses BFS to determine an ordered node sequence, and according to the node order, determines the row of each node's binary edge decision vector in the adjacency matrix.

[0062] Reference Figure 4 When generating node k, the control logic module drives the corresponding bit line BL. k And simultaneously apply the edge decision vectors corresponding to the aforementioned partial adjacency matrix to word lines WL1 to WL M The data is written in parallel via programmed pulses.

[0063] Step S104 is followed by the following steps: obtaining sparse data from the edge storage module and shifting and aligning the sparse data to obtain valid data; calculating zero-bit data and merging the valid data and the zero-bit data to output a complete adjacency matrix row.

[0064] Specifically, refer to Figure 3 The matrix reconstruction module works when it is necessary to read the complete adjacent rows (a row in the adjacency matrix), and mainly includes: The barrel shifter reads M bits of data from the edge storage module and shifts and aligns the read data according to the current node index k. It can be understood that this is a cyclic shift or logical shift operation because the stored position is relative (relative to the first M bits of k), while restoring the complete matrix requires the absolute position (position in 1 to N). The barrel shifter moves these M bits to the column positions from kM to k-1.

[0065] The zero-bit generator produces NM zero bits simultaneously; The multiplexer array combines the shifted M-bit data with the NM zero bits within one clock cycle to output a complete N-bit adjacency matrix row. This operation enables fast conversion between sparse storage and a complete matrix view.

[0066] In one possible implementation, the graph structure generation method further includes the following steps: the control logic module generates a graph generation instruction and obtains the current node state according to the graph generation instruction; the control logic module generates a node calculation instruction based on the current node state and sends it to the node calculation module; the control logic module generates an edge probability calculation instruction based on the hidden state and sends it to the edge probability generation module; the control logic module generates a sampling instruction based on the probability vector and sends it to the Bernoulli sampling module; the control logic module generates a storage instruction based on the decision vector and sends it to the edge storage module.

[0067] Specifically, the control logic module consists of a central controller and a state mechanism. Its main function is to coordinate the timing and control of the node generation module, edge probability generation module, Bernoulli sampling module, and edge storage module to successfully execute the autoregressive graph generation process. (Refer to...) Figure 4 The operating modes of the control logic module include: Pipeline mode scheduling: Figure 5 (a) in the diagram is the pipeline timing diagram of the crossbar switch array. The control logic module schedules the operations of multiple SRU layers in a pipelined manner. When the i-th layer is performing a crossbar array read operation, the (i-1)-th layer is performing its digital operation phase. The operations performed by the i-th and (i-1)-th layers overlap in time, maximizing hardware utilization. The operation of each layer is broken down into ReRAM array computation time (Txbar) and digital circuit processing time (Tdig). When the L2-th layer is performing analog calculations using the ReRAM array, the data of the L1-th layer is undergoing post-processing (activation, sampling, etc.) in the digital circuit. In this way, hardware resources (array and logic circuit) work in overlapping time, eliminating waiting bubbles and improving throughput.

[0068] Multiple images concurrently: Figure 5 (b) describes the process of time-multiplexing multiple graphs in the pipeline. The control logic module switches between the generation contexts of multiple graphs in a polling manner. When a layer of a graph completes its computation and enters the next stage, the controller immediately allocates computing resources to the next graph, ensuring that the pipeline is always saturated. This mode enables concurrent generation of multiple graphs, significantly improving the overall throughput of the in-memory computing accelerator pipeline. When a write wait (Twrite) or long-delay operation is encountered during the generation of graph A, the controller immediately switches contexts and uses idle computing resources to process the generation steps of graph B. Similar to the hyper-threading technology of CPUs, multitasking fills the pipeline gaps, ensuring that the ReRAM array is always in a working state and not idle. Figure 5 In (b), Txbar is the time required for the crossbar array to perform analog calculations; Tdig is the time required for the digital circuit to perform activation, sampling, and other operations; Twrite is the time to write the generated edge to ReRAM (which is usually slower); and II is the pipeline-level delay.

[0069] The specific implementation of this application will be described below with reference to a specific application scenario.

[0070] S1. Process the current node state through the node generation module and generate the hidden state of the current node; In the node generation module processing step, the concatenated vector of the current input vector and the previous cell state vector is input to the first ReRAM cross switch array, and the input projection of the SRU and the calculation of the peephole item are completed in a single operation.

[0071] S2. The hidden state of the current node is processed by the edge probability generation module, and a connection probability vector between the new node and the multiple candidate nodes is generated, wherein the number of candidate nodes is equal to the maximum number of previous nodes; S3. Perform parallel Bernoulli sampling on the probability vector of the edge connection through the Bernoulli sampling module to obtain the binary edge decision vector; S4. Write the binary edge decision vector into the edge storage module in BFS order; S5. Repeat the above steps until a graph structure with a predetermined number of nodes is generated, wherein the number of nodes in the graph structure is equal to the maximum number of nodes in the graph; S6. After the graph structure is generated, when it is necessary to read the complete adjacency matrix, perform the matrix reconstruction step, specifically as follows: Read the partial columns from the edge storage module; The bucket shifter is used to perform shift and alignment operations on the partial columns based on the node index; The zero-bit generator is used to generate the plurality of zero bits; The multiplexer is used to merge the shifted column data with the zero bits and output the complete adjacency matrix rows.

[0072] Understandably, each operation targets a single node k, reconstructing the k-th row of the matrix. Only after all nodes have been processed, and the combined output rows, constitute the complete matrix.

[0073] The graph structure generation method based on the memory computing accelerator provided in this application is applied to the aforementioned memory computing accelerator, thereby possessing all the beneficial effects of the aforementioned memory computing accelerator, which will not be elaborated further here.

[0074] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0075] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0076] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0077] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable storage medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable storage medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable storage medium could be paper or other suitable media on which the program can be printed, since the program can be obtained electronically by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0078] It should be understood that the various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0079] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0080] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0081] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

[0082] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A graph structure generation method based on a memory computing accelerator, characterized in that, Applied to a memory computing accelerator, the memory computing accelerator includes a node generation module, an edge probability generation module, a Bernoulli sampling module, and an edge storage module. The graph structure generation method based on the memory computing accelerator includes: The node generation module calculates the hidden state of the current node and sends it to the edge probability generation module; The edge probability generation module outputs a probability vector based on the hidden state and sends it to the Bernoulli sampling module; The Bernoulli sampling module outputs a decision vector based on the probability vector and sends it to the edge storage module; The edge storage module receives the decision vectors corresponding to all nodes and generates the target graph structure based on the decision vectors corresponding to all nodes.

2. The graph structure generation method based on a memory computing accelerator according to claim 1, characterized in that, The graph structure generation method based on memory computing accelerators also includes: The control logic module generates graph generation instructions and obtains the current node status according to the graph generation instructions; The control logic module generates node calculation instructions based on the current node state and sends them to the node calculation module; The control logic module generates an edge probability calculation instruction based on the hidden state and sends it to the edge probability generation module; The control logic module generates a sampling instruction based on the probability vector and sends it to the Bernoulli sampling module; The control logic module generates a storage instruction based on the decision vector and sends it to the edge storage module.

3. The graph structure generation method based on a memory computing accelerator according to claim 2, characterized in that, The calculation of the hidden state of the current node specifically includes: Receive the current input vector and the previous cell state vector, and obtain the concatenation vector based on the current input vector and the previous cell state vector; The splicing vector is input into the ReRAM cross switch array to obtain input projection data and peephole gating data; The hidden state of the current cell state and the current node state is calculated based on the input projection data and the peephole gating data.

4. The graph structure generation method based on a memory computing accelerator according to claim 3, characterized in that, The step of outputting a probability vector based on the hidden state specifically includes: Based on the hidden state, output the corresponding analog current data on each of the multiple bit lines; Based on the simulated current data corresponding to each of the multiple bit lines, output a probability vector showing that there are edge connections between the new node and multiple candidate nodes.

5. The graph structure generation method based on a memory computing accelerator according to claim 4, characterized in that, The step of outputting a decision vector based on the probability vector specifically includes: Generate multiple random numbers; Based on the multiple random numbers and the multiple elements corresponding to the probability vector, multiple output results are obtained; A decision vector is formed based on the multiple output results.

6. The graph structure generation method based on a memory computing accelerator according to claim 5, characterized in that, The step of generating the target graph structure based on the decision vectors corresponding to all nodes specifically includes: For each decision vector, the target position of the decision vector in the sparse adjacency matrix is ​​determined according to the breadth-first search order; The target graph structure is obtained based on the target positions corresponding to each of the decision vectors.

7. The graph structure generation method based on a memory computing accelerator according to any one of claims 1-5, characterized in that, The process of generating the target graph structure based on the decision vectors corresponding to all nodes further includes: Sparse data is obtained from the edge storage module, and the sparse data is shifted and aligned to obtain valid data; Calculate the zero-bit data, and merge the valid data and the zero-bit data to output the complete adjacency matrix rows.

8. A memory computing accelerator based on the graph structure generation method of any one of claims 1 to 5, characterized in that, The in-memory computing accelerator includes a node generation module, an edge probability generation module, a Bernoulli sampling module, and an edge storage module. The node generation module is connected to the edge probability generation module, the edge probability generation module is connected to the Bernoulli sampling module, and the Bernoulli sampling module is connected to the edge storage module. The node generation module is used to calculate the hidden state of the current node and send it to the edge probability generation module; the edge probability generation module is used to output a probability vector based on the hidden state and send it to the Bernoulli sampling module; the Bernoulli sampling module is used to output a decision vector based on the probability vector and send it to the edge storage module; the edge storage module is used to receive the decision vectors corresponding to all nodes and generate the target graph structure based on the decision vectors corresponding to all nodes.

9. The memory computing accelerator according to claim 8, characterized in that, The memory computing accelerator also includes a control logic module, which is connected to the node generation module, the edge probability generation module, the Bernoulli sampling module, and the edge storage module. The control logic module is used to coordinate the timing of the node generation module, the edge probability generation module, the Bernoulli sampling module, and the edge storage module.

10. The memory computing accelerator according to claim 9, characterized in that, The memory computing accelerator also includes a matrix reconstruction module, which is connected to the edge storage module and the control logic module respectively. The matrix reconstruction module is used to output the complete adjacency matrix rows.

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