Data storage device and chip

Abstract

This application relates to a data storage device and a chip. The data storage device includes: a filtering module and multiple storage modules; each storage module includes at least one storage unit, and the storage unit includes a latch; the input terminal of the filtering module is used to receive operation data, and the output terminal of the filtering module is connected to each storage module; the operation data is used to perform data operations on the data storage device; the filtering module is used to determine a target storage module among the multiple storage modules based on the operation data, and input the operation data to the target storage module so that the target storage module can access data according to the operation data. Using this device can reduce the area and power consumption of the storage device.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to a data storage device and chip. Background Technology

[0002] As chip logic scales increase, chip performance becomes a growing concern. Chips contain various functional modules, and rationally designing the physical attributes of each module can help improve chip performance. For example, the memory module, used for data caching, can benefit from improvements in its area and power consumption by reducing these physical attributes, thus meeting the miniaturization requirements of electronic devices.

[0003] In related technologies, storage modules are typically implemented using SRAM (Static Random Access Memory) or registers. However, storage modules built using SRAM or registers may not meet the chip's actual requirements for storage module area and power consumption, affecting chip performance. Therefore, reducing the area and power consumption of storage modules has become an urgent technical problem to be solved. Summary of the Invention

[0004] Therefore, it is necessary to provide a data storage device and chip that can reduce the area and power consumption of the storage module to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a data storage device, which includes a filtering module and a plurality of storage modules; each storage module includes at least one storage unit, and each storage unit includes a latch; the input end of the filtering module is used to receive operation data, and the output end of the filtering module is connected to each storage module.

[0006] The filtering module is used to determine the target storage module among multiple storage modules based on the operation data, and input the operation data into the target storage module so that the target storage module can access and retrieve data based on the operation data.

[0007] In one embodiment, the operation data further includes address information, and the storage module is also used to determine a target storage unit in at least one storage unit based on the address information.

[0008] The target storage unit is used to receive operation data and perform data access based on the operation data.

[0009] In one embodiment, the operation data further includes data information, read enable information, write enable information, mask information, and control information; the target storage unit includes at least one latch, a second AND gate, a third AND gate, a fourth AND gate, and a fifth AND gate;

[0010] The input of the second AND gate is used to receive write enable information, mask information and control information, and the output of the second AND gate is connected to the write enable port of each latch.

[0011] The input of the third AND gate is used to receive write enable information, mask information, and the inverse of control information. The output of the third AND gate is connected to the write mask port of each latch.

[0012] The input of the fourth AND gate is used to receive read enable information and control information, and the output of the fourth AND gate is connected to the read enable port of each latch.

[0013] The input of the fifth AND gate is used to receive read enable information and control information, and the output of the fifth AND gate is connected to the read mask port of each latch.

[0014] The data information is connected to the data ports of each latch.

[0015] In one embodiment, the filtering module is further configured to input operation data to the target storage module so that the target storage module can read data based on the operation data.

[0016] In one embodiment, the data storage device further includes an output module, wherein the output terminal of each storage module is connected to the input terminal of the output module;

[0017] The storage module is used to output target data to the output module based on the operation data when it is identified as the target storage module;

[0018] The output module is used to receive target data and output the target data.

[0019] In one embodiment, the output module includes a data selector; the input of the data selector is connected to the output of each storage module.

[0020] The data selector is used to receive the output data from each storage module and output the target data according to the target data output by the target storage module.

[0021] In one embodiment, the operation data includes data information, and the data storage device further includes a matching module and an output module that correspond one-to-one with each storage module. The input end of the matching module is connected to the storage module, and the output end of the matching module is connected to the output module.

[0022] The storage module is also used to perform data matching between the operation data and the data stored in the storage module, and output the bit data matching result. The bit data matching result is used to indicate the matching result of each bit of the data information with the data stored in the storage module.

[0023] The matching module is used to output the address matching result to the output module based on the bit data matching result. The address matching result is used to indicate the matching result of the data information at each address in the storage module.

[0024] In one embodiment, the operation data further includes search enable information and mask information. The matching module includes a first OR gate, a first AND gate, and a first logic unit. The input of the first OR gate is used to receive the bit data matching result and mask information output by the storage module. The input of the first AND gate is connected to the output of the first OR gate. The input of the first AND gate is also used to receive search enable information. The output of the first AND gate is connected to the input of the first logic unit. The output of the first logic unit is connected to the output module.

[0025] In one embodiment, the first OR gate is used to filter the bit data matching results according to the mask information and output the first candidate bit data matching result;

[0026] The first AND gate is used to filter the matching results of the first candidate position data based on the search enable information and output the matching results of the second candidate position data.

[0027] The first logic unit is used to perform a bitwise AND operation on the matching result of the second candidate bit data and output the address matching result.

[0028] In one embodiment, the output module includes a second OR gate; the input of the second OR gate is connected to the output of each matching module.

[0029] The second OR gate is used to output the storage device matching result based on the address matching results output by each matching module. The storage device matching result is used to characterize the matching result of data information in the storage device.

[0030] In one embodiment, the operation data further includes address information, and the storage module is also used to determine a target storage unit in at least one storage unit based on the address information.

[0031] The target storage unit is used to receive operation data and perform data operations based on the operation data.

[0032] In one embodiment, the operation data further includes data information, read enable information, write enable information, mask information, and control information; the target storage unit includes at least one latch, a second AND gate, a third AND gate, a fourth AND gate, and a fifth AND gate;

[0033] The input of the second AND gate is used to receive write enable information, mask information and control information, and the output of the second AND gate is connected to the write enable port of each latch.

[0034] The input of the third AND gate is used to receive write enable information, mask information, and the inverse of control information. The output of the third AND gate is connected to the write mask port of each latch.

[0035] The input of the fourth AND gate is used to receive read enable information and control information, and the output of the fourth AND gate is connected to the read enable port of each latch.

[0036] The input of the fifth AND gate is used to receive read enable information and control information, and the output of the fifth AND gate is connected to the read mask port of each latch.

[0037] The data information is connected to the data ports of each latch.

[0038] In one embodiment, the latch includes a first storage sub-unit, a second storage sub-unit, a sixth AND gate, a seventh AND gate, and a third OR gate;

[0039] The first input terminal of the first storage sub-unit is a write enable port, and the second input terminal is a data port; the output terminal of the first storage sub-unit is connected to the first input terminal of the sixth AND gate;

[0040] The first input terminal of the second storage sub-unit is a data port, the second input terminal is a write mask port, and the output terminal of the second storage sub-unit is connected to the first input terminal of the seventh AND gate.

[0041] The second input of the sixth AND gate is the read enable port, and the output of the sixth AND gate is connected to the first input of the third OR gate.

[0042] The second input of the seventh AND gate is the mask reading port, and the output of the seventh AND gate is connected to the second input of the third OR gate.

[0043] The third OR gate is used to output the data stored in the latch during the data reading process.

[0044] In one embodiment, the latch further includes a selection module; a first input terminal of the selection module is connected to the output terminal of the first storage sub-unit, a second input terminal of the selection module is connected to the output terminal of the second storage sub-unit, and a third input terminal of the selection module is a data port;

[0045] The selection module is used to output the data matching results of the latch during the data search process.

[0046] In one embodiment, the filtering module is further configured to input operation data to the target storage module so that the target storage module stores data according to the operation data.

[0047] In one embodiment, the latch includes a first storage sub-unit;

[0048] The first input terminal of the first storage sub-unit is a write enable port, and the second input terminal is a data port; the first storage sub-unit is used to write data information from the data port into the first storage sub-unit when the write enable port is active.

[0049] Secondly, this application also provides a chip including any of the data storage devices described in the first aspect above.

[0050] This application provides a data storage device and chip. The data storage device includes a filtering module and multiple storage modules. Each storage module includes at least one storage unit, and each storage unit includes a latch. The input of the filtering module is used to receive operation data, and the output of the filtering module is connected to each storage module. The filtering module is used to determine a target storage module among the multiple storage modules based on the operation data, and input the operation data to the target storage module so that the target storage module can access data based on the operation data. By using latches to form storage units, multiple storage units to form storage modules, and multiple storage modules to form a storage device, the storage device can be divided into blocks for storage addresses. During data access, the target storage module that the data needs to access can be filtered according to the address, and only the target storage module needs to be accessed, without accessing other storage modules, thereby reducing the power consumption of the storage device. Furthermore, under the same chip process conditions, the area of ​​a latch is smaller than the area of ​​a register, and the storage device constructed with latches can reduce the area of ​​the storage device. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the data storage device in one embodiment;

[0053] Figure 2 This is a schematic diagram of the storage unit structure in another embodiment;

[0054] Figure 3 This is a schematic diagram of the data storage device in another embodiment;

[0055] Figure 4 This is a schematic diagram of the data storage device in another embodiment;

[0056] Figure 5 This is a schematic diagram of the matching module in another embodiment;

[0057] Figure 6 This is a schematic diagram of the latch structure in another embodiment;

[0058] Figure 7 This is a schematic diagram of the data storage device in another embodiment;

[0059] Figure 8 This is a schematic diagram of the data storage device in another embodiment.

[0060] Explanation of reference numerals in the attached figures:

[0061] 10: Filtering module;

[0062] 20: Storage module;

[0063] 30: Output module;

[0064] 40: Matching module;

[0065] 21: Storage unit;

[0066] 31: Data selector;

[0067] 32: Second OR gate;

[0068] 41: First OR gate;

[0069] 42: The first gate;

[0070] 43: First logic unit;

[0071] 211: Latch;

[0072] 212: The second AND gate;

[0073] 213: The Third and the Gate;

[0074] 214: The Fourth AND Gate;

[0075] 215: The Fifth Gate;

[0076] 2111: First storage sub-unit;

[0077] 2112: Second storage sub-unit;

[0078] 2113: The Sixth Gate;

[0079] 2114: The Seventh Gate;

[0080] 2115: Third OR gate;

[0081] 2116: Select module. Detailed Implementation

[0082] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0083] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The term "comprising" and any variations thereof in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion. In the description of embodiments of this application, "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. References to "embodiment" herein mean that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0084] The memory module of a chip is a functional module used for data caching. Reducing the area and power consumption of the memory module can help improve chip performance and meet the miniaturization requirements of electronic devices.

[0085] In related technologies, there are generally two ways to implement memory modules. One is to directly purchase existing SRAM. However, this method increases the cost of the chip, and the size of readily available SRAM is fixed, which may not meet the design requirements of the actual chip. Furthermore, SRAM does not support fast search functionality. The second method is to build the memory module using registers. However, this method consumes a large number of registers, and the large area of ​​the registers leads to a larger memory module area, affecting chip performance. Therefore, reducing the area and power consumption of the memory module has become an urgent technical problem to be solved.

[0086] Based on this, the data storage device and chip provided in this application embodiment use latches to form storage units, multiple storage units to form storage modules, and multiple storage modules to form a storage device. This allows for the storage device to be divided into blocks for storage addresses using multiple storage modules. During data storage, the target storage module that the data needs to access can be selected based on its address, allowing access only to the target storage module and eliminating the need to access other storage modules, thereby reducing the power consumption of the storage device. Furthermore, under the same chip manufacturing process, the area of ​​a latch is smaller than that of a register, thus reducing the overall area of ​​the storage device.

[0087] like Figure 1 As shown, this application embodiment provides a data storage device, which includes a filtering module 10 and at least one storage module 20; the storage module includes at least one storage unit 21, and the storage unit 21 includes a latch 211; the input terminal of the filtering module 10 is used to receive operation data, and the output terminal of the filtering module 10 is connected to each storage module 20; the operation data is used to perform data operations on the data storage device; the filtering module 10 is used to determine a target storage module among the multiple storage modules 20 according to the operation data, and input the operation data to the target storage module so that the target storage module can perform data access according to the operation data.

[0088] In this embodiment, the data storage device can be a hardware structure applied in a system-on-a-chip (SoC) for data storage, data retrieval, and data searching. To reduce the power consumption of the data storage device, it can be divided into multiple storage modules 20. Each storage module 20 can store data within a specific address range. During data operations, only the storage module corresponding to the operation address needs to be accessed, without needing to access the entire data storage device, thereby reducing the power consumption of the data storage device. Each storage module 20 includes at least one storage unit 21, and each storage unit 21 includes a latch 211. A latch is a basic digital circuit element that can be used to store one bit of binary data. By constructing multiple latches 211, a multi-bit storage unit 21 can be built, enabling the storage of multiple bits of data. Optionally, the capacity of the data storage device can be determined based on the amount of data to be stored during chip design. The data storage device can be divided into multiple storage modules 20 based on storage addresses. The number of storage modules 20 can be reasonably divided according to the capacity of the data storage device. With a fixed capacity of the data storage device, the fewer the storage modules 20, the more storage addresses each storage module 20 corresponds to, and the smaller the improvement in power consumption of the data storage device. Conversely, the more storage modules 20, the more storage addresses each storage module 20 corresponds to, and the greater the improvement in power consumption of the data storage device. However, the complexity of the data storage device is also higher. Therefore, the data storage device can be divided into multiple storage modules 20 according to the actual chip design requirements, balancing chip power consumption and design complexity.

[0089] For example, when the filtering module 10 determines the target storage module to be operated on when operating the data storage device, the input terminal of the filtering module 10 receives operation data. Optionally, the operation data may include address information and data information. The address information is the address of the data operation, such as the address of data storage or data retrieval. The data information may be the data to be stored or the data to be searched during the data search process. The filtering module 10 may be a register. By decoding the address information in the operation data, it determines which storage module 20 the address to be operated on belongs to, and that storage module 20 is the target storage module. Optionally, a strobe signal can be set for each storage module 20. When a storage module 20 is determined to be the target storage module, the strobe signal corresponding to the target storage module is set to a high level, and the operation data is output to the target storage module. The strobe signals corresponding to other storage modules 20 are set to a low level, and the operation data is not output.

[0090] After receiving the operation data, the target storage module performs data access operations based on the received operation data. The operation data may also include read / write enable information, mask information, and control information. Based on the address information, read / write enable information, mask information, and control information in the operation data, the module writes the data information from the operation data into the target storage module. The mask information allows for bit-by-bit masking of the written data; if the mask value at a corresponding position is 1, no data is written. This effectively controls the repeated writing of the same data to the same address.

[0091] In the above embodiments, latches constitute storage units, multiple storage units constitute storage modules, and multiple storage modules constitute a storage device. This allows for the segmentation of storage addresses within the storage device using multiple storage modules. During data access, the target storage module to be accessed can be selected based on the address, allowing access only to the target storage module and eliminating the need to access other storage modules, thereby reducing the power consumption of the storage device. Furthermore, under the same chip manufacturing process, the area of ​​a latch is smaller than that of a register. The latch 211 has advantages such as simple structure, small area, fast read / write speed, and the ability to maintain the stored state. The storage device constructed using latches can reduce the area of ​​the storage device.

[0092] In one embodiment, the operation data further includes address information, and the storage module 20 is further configured to determine a target storage unit in at least one storage unit 21 based on the address information; the target storage unit is configured to receive the operation data and perform data access based on the operation data.

[0093] Optionally, the storage module 20 includes multiple storage addresses, each of which can consist of one or more storage units. When a storage address consists of multiple storage units, the storage module 20 determines the address to be used for data operations based on the address information. In this case, all storage units at that address are target storage units. These target storage units receive the operation data and perform data operations based on it, including data storage, data retrieval, and data search.

[0094] In embodiments of this application, the operation data further includes data information, read enable information, write enable information, mask information, and control information; such as Figure 2 As shown, the target storage unit includes at least one latch 211, a second AND gate 212, a third AND gate 213, a fourth AND gate 214, and a fifth AND gate 215. The input of the second AND gate 212 is used to receive write enable information, mask information, and control information, and the output of the second AND gate 212 is connected to the write enable port of each latch 211. The input of the third AND gate 213 is used to receive the inverse information of the write enable information, mask information, and control information, and the output of the third AND gate 213 is connected to the write mask port of each latch 211. The input of the fourth AND gate 214 is used to receive read enable information and control information, and the output of the fourth AND gate 214 is connected to the read enable port of each latch 211. The input of the fifth AND gate 215 is used to receive read enable information and control information, and the output of the fifth AND gate 215 is connected to the read mask port of each latch 211. The data information is connected to the data port of each latch 211.

[0095] One latch 211 can store one bit of data. The target storage unit can encapsulate multiple latches 211 to achieve the storage and retrieval of multiple bits of data. Optionally, the number of encapsulated latches can be selected according to the actual design requirements. For example, in this application... Figure 2 As shown, taking a target storage unit consisting of 4 latches as an example, the target storage unit can realize the reading, writing, and searching of 4 bits of data. The write enable information is the Wen signal, the mask information Mask[3:0] is a 4-bit array, the control information is the Dsel signal used to control how data is written to latch 211, the read enable signal is the Ren signal, and the data information Data_in[3:0] is a 4-bit array, with each bit corresponding to one latch 211.

[0096] The Wen signal, mask information, and Dsel signal are ANDed through the second AND gate 212, and the result is output to the write enable port of each latch 211. The Wen signal, mask information, and Dsel signal are inverted and ANDed through the third AND gate 213, and the result is output to the write mask port of each latch 211. The Ren signal and Dsel signal are ANDed through the fourth AND gate 214, and the result is output to the read enable port of each latch 211. The Ren signal and Dsel signal are ANDed through the fifth AND gate 215, and the result is output to the read mask port of each latch 211. Data_in[3:0] is connected to the data port of each latch 211. The target storage unit performs data operations according to the above operation data and outputs the corresponding data. For example, when reading data, the target data read is output through Data_Out[3:0], and when searching data, the search matching result of each bit is output through Key_Match[3:0].

[0097] In the embodiments of this application, the filtering module 10 is further configured to input operation data into the target storage module so that the target storage module can read data according to the operation data.

[0098] In the embodiments of this application, such as Figure 3 As shown, the device also includes an output module 30, with the output terminals of each storage module 20 connected to the input terminals of the output module 30; the storage module 20 is used to output target data to the output module 30 according to the operation data when it is determined to be the target storage module; the output module 30 is used to receive the target data and output the target data.

[0099] In this embodiment, when the data storage device is used in a data reading scenario, the target data is the data read from the storage module 20. At this time, the address information in the operation data is the address to be read. The target storage module is determined according to the address information, and the target data corresponding to the address information in the target storage module is read according to the address information, read / write enable information, mask information and control information. The target data is output to the output module 30. The output module 30 is connected to the data output terminal of each storage module 20 to obtain the target data and output it to other functional modules on the chip that performs data reading.

[0100] The output module 30 includes a data selector 31; the input terminal of the data selector 31 is connected to the output terminal of each storage module 20; the data selector 31 is used to receive the output data of each storage module 20 and output the target data according to the target data output by the target storage module.

[0101] Data selector 31 is a multiplexer used to select one signal from multiple input signals and output it. That is, it selects one output data from the output data of multiple storage modules 20. Since only the strobe signal corresponding to the target storage module is high, the target data is output. Other storage modules 20 are not selected for access, so the output data is 0. Therefore, data selector 31 selects the target data output by the target storage module for output.

[0102] Alternatively, the output module 30 may include an OR gate circuit, which performs an OR operation on the output data of multiple storage modules 20 and outputs the result of the OR operation as the target data.

[0103] In the above embodiments, data reading operations can be performed based on the operation data. By determining the target storage module, only the target storage module is accessed during the data reading process. Then, the output data of each storage module 20 is selected by the data selector 31 and the target data is output, which can effectively reduce the power consumption of the storage module.

[0104] In one embodiment, the data storage device can implement a fast search function, and the data to be operated on includes data information, such as... Figure 4 As shown, the device also includes a matching module 40 and an output module 30 corresponding to each storage module 20. The input terminal of the matching module 40 is connected to the storage module 20, and the output terminal of the matching module 40 is connected to the output module 30. The storage module 20 is also used to perform data matching based on the operation data and the data stored in the storage module 20, and output bit data matching results. The bit data matching results are used to indicate the matching result of each bit of the data information with the data stored in the storage module 20. The matching module 40 is used to output address matching results to the output module 30 based on the bit data matching results. The address matching results are used to indicate the matching result of the data information at each address in the storage module 20.

[0105] The quick search function enables a rapid search within the data storage device based on the input operation data, which includes data information such as the data to be searched. It determines whether the data storage device contains the data to be searched and outputs the storage location information of the data to be searched. Optionally, when the data storage device contains multiple data to be searched, it can also output the storage location information corresponding to each data to be searched.

[0106] For example, a fast data search function is implemented through the matching module 40. The output of each storage module 20 is connected to the input of a matching module 40. During the data search process, the data information of the operation data is the data to be searched. The operation data also includes search enable information, mask information, and control information. According to the operation data, the storage module 20 matches the data to be searched with the data stored in the storage module 20 and outputs the matching result of each bit of data at each address, i.e., the bit data matching result. The matching module 40 filters the bit data matching results according to the search enable information and mask information, masking out bits that do not need to be of interest. Then, it performs a bitwise AND operation on the matching results of all bits of data at each address to obtain the matching result of each address. The matching result of each address of the storage module 20 is then output to the output module 30 so that the matching result can be output through the output module 30.

[0107] Alternatively, the operation data can also include address information, allowing you to search whether the data to be searched is located at a specified address.

[0108] In embodiments of this application, the operation data also includes search enable information and mask information; please refer to [reference needed]. Figure 5 The matching module 40 includes a first OR gate 41, a first AND gate 42, and a first logic unit 43. The input of the first OR gate 41 is used to receive the bit data matching result and mask information output by the storage module 20. The input of the first AND gate 42 is connected to the output of the first OR gate 41. The input of the first AND gate 42 is also used to receive search enable information. The output of the first AND gate 42 is connected to the input of the first logic unit 43. The output of the first logic unit 43 is connected to the output module 30.

[0109] The first OR gate 41 is used to filter the bit data matching results according to the mask information and output the first candidate bit data matching result; the first AND gate 42 is used to filter the first candidate bit data matching results according to the search enable information and output the second candidate bit data matching result; the first logic unit 43 is used to perform a bitwise AND operation on the second candidate bit data matching result and output the address matching result.

[0110] Optionally, the search enable information may include a first search enable flag (CMP) and a second search enable flag (VBE). The first search enable flag (CMP) indicates whether the upper-layer system has enabled the search function. Search results are output only when CMP is valid; otherwise, the output search results are invalid. The second search enable flag (VBE) enables search by address. Each address of each storage module corresponds to a VBE value. When the VBE value is valid, the data at that address is compared during the search to determine a matching result; when the VBE value is invalid, the data at that address is not compared during the search. The mask information is used to determine whether each bit of data at each address is compared during the data search. When the mask information is valid, the data at that bit needs to be compared during the search; when the mask information is invalid, the data at that bit does not need to be compared, and the matching result for that bit is directly output as a high level.

[0111] The storage module 20 outputs the bit data matching result for each bit of each address in the storage module 20 based on the operation data. The data matching result can be represented by a two-dimensional array, where the rows of the two-dimensional array represent each address in the storage module 20, and the columns of the two-dimensional array represent each bit corresponding to each address. It can be understood that the mask information is also a corresponding two-dimensional array. The mask information and the bit data matching result are ORed by the first OR gate 41 to output the first candidate bit data matching result. The first candidate bit data matching result is used to characterize the bit data matching result of all bits that need to be considered during the data search process. Further, the first candidate bit data matching result is ANDed with the first search enable flag CMP and the second search enable flag VBE by the first AND gate 42 to determine which addresses need to be searched and compared, and the second candidate bit data matching result is output. Finally, the second candidate bit data matching result is bitwise ANDed with each address by the first logic unit 43 to determine the matching result corresponding to each address, which is output as the address matching result. The address matching result is a one-dimensional array, and the number of elements in the array is related to the number of addresses that can be stored in the storage module 20.

[0112] In the above embodiments, data can be quickly searched through a data storage device. The scope of the search can be determined through mask information and search enable information, and the address can be specified for searching through address information, resulting in higher search efficiency and flexibility.

[0113] In the embodiments of this application, please continue to refer to Figure 3The output module 30 includes a second OR gate 32; the input terminal of the second OR gate 32 is connected to the output terminal of each matching module 40; the second OR gate 32 is used to output the storage device matching result according to the address matching result output by each matching module 40, and the storage device matching result is used to characterize the matching result of data information in the storage device.

[0114] The address matching results output by each matching module 40 can be directly output by the output module 30. The address matching results are a one-dimensional array used to represent the matching results of each address in the data storage device. The storage location of the data to be searched in the data storage device can be determined based on the address matching results.

[0115] Alternatively, the address matching results output by each matching module 40 can be bitwise ORed by the second OR gate 32 to obtain a one-bit search result. If the result is high, it means that the data to be searched has been found in the data storage device. If the result is low, it means that the data to be searched has not been found in the data storage device. In this way, it is possible to determine more quickly whether the data storage device has found the data to be searched.

[0116] In the above embodiments, the data storage device can output the search results for each address in the data storage device, or it can output a single bit to indicate whether the entire data storage device has found a matching result for the data to be searched.

[0117] In one embodiment, the latch 211 constituting the above-described storage unit 21 has the following structure: Figure 6 As shown, the latch includes a first storage sub-unit 2111, a second storage sub-unit 2112, a sixth AND gate 2113, a seventh AND gate 2114, and a third OR gate 2115. The first input of the first storage sub-unit 2111 is a write enable port, and the second input is a data port. The output of the first storage sub-unit 2111 is connected to the first input of the sixth AND gate 2113. The first input of the second storage sub-unit 2112 is a data port, and the second input is a write mask port. The output of the second storage sub-unit 2112 is connected to the first input of the seventh AND gate 2114. The second input of the sixth AND gate 2113 is a read enable port, and the output of the sixth AND gate 2113 is connected to the first input of the third OR gate 2115. The second input of the seventh AND gate 2114 is a read mask port, and the output of the seventh AND gate 2114 is connected to the second input of the third OR gate 2115. The third OR gate 2115 is used to output the data stored in the latch during the data reading process.

[0118] In this configuration, the first storage sub-unit 2111 can be a D_Latch, and the second storage sub-unit 2112 can be an M_Latch. The D_Latch and M_Latch can latch the input data to the output under the control of the input data. For example... Figure 6 As shown, the first input of D_Latch is the write enable port Wen_Data, which is... Figure 2 The output of the second AND gate 212 in the D_Latch is connected to the data port Data_in, which is used to receive data information from the operation data. The first input of the M_Latch is the data port Data_in, which is used to receive data information from the operation data. The second input of the M_Latch is the write mask port Wen_Mask, which is connected to the output of the second AND gate 212 in the D_Latch. Figure 2 The output of the third AND gate 213 in the array is connected. During data storage, if Wen_Data of D_Latch is valid (e.g., Wen_Data = 1), the data in Data_in is stored in D_Latch; if Wen_Mask is valid, the data in Data_in is stored in M_Latch. Figure 2 As can be seen, Wen_Data and Wen_Mask are determined by the control signal Dsel, that is, Dsel can control whether data is written to D_Latch or M_Latch.

[0119] The second input of the sixth AND gate 2113 is the read enable port Ren_Data. Ren_Data and the output of D_Latch are ANDed through the sixth AND gate 2113, and the result is output to the third OR gate 2115. The second input of the seventh AND gate 2114 is the read mask port Ren_Mask. Ren_Mask and the output of M_Latch are ANDed through the seventh AND gate 2114, and the result is output to the third OR gate 2115. During data reading, if Ren_Data is valid, the data stored in D_Latch is output as R_Data. If Ren_Mask is valid, the data stored in M_Latch is output as R_Data.

[0120] In one embodiment, please refer to... Figure 6 The latch 211 also includes a selection module 2116; the first input terminal of the selection module 2116 is connected to the output terminal of the first storage subunit 2111, the second input terminal of the selection module 2116 is connected to the output terminal of the second storage subunit 2112, and the third input terminal of the selection module 2116 is a data port; the selection module 2116 is used to output the data matching result of the latch 211 during the data search process.

[0121] During the data search process, the selection module 2116 matches the input output values ​​of D_Latch and M_Latch with the data information to determine the data matching result. The truth table for the search process is shown below, where X can be 0 or 1. The latch 211 can obtain the data matching result in real time, but only outputs the data matching result when the search enable signal is active.

[0122] Table 1 Truth Table for Data Search Process

[0123]

[0124] In embodiments of this application, the filtering module 10 is further configured to input operation data into the target storage module so that the target storage module stores data according to the operation data.

[0125] Please continue to refer to the following: Figure 6 When the target storage module stores data according to the operation data, the latch includes a first storage sub-unit 2111; the first input terminal of the first storage sub-unit 2111 is a write enable port, and the second input terminal is a data port; the first storage sub-unit 2111 is used to write the data information of the data port into the first storage sub-unit 2111 when the write enable port is valid.

[0126] As described in the above embodiments, the first storage sub-unit 2111 can be a D_Latch, and during data storage, such as... Figure 6 As shown, the first input of D_Latch is the write enable port Wen_Data, which is... Figure 2 The output of the second AND gate 212 in the D_Latch is connected, and the second input of the D_Latch is the data port Data_in, which is used to receive data information from the operation data. During data storage, if Wen_Data of the D_Latch is valid, such as when Wen_Data is 1, the data in Data_in is stored into the D_Latch for data storage.

[0127] In the embodiments of this application, such as Figure 7 and Figure 8 The diagram shown is an overall structural block diagram of the data storage device provided in this application embodiment. The description uses an example of a data storage device with a capacity of 512x144 bits, divided into 8 storage modules 20. Due to space limitations, the data storage device is divided into two parts. Figure 7 For the connection of the filtering module 10 and the storage module 20, Figure 8The connection between the storage module 20, the matching module 40, and the output module 30 is provided. It is understood that the size of the data storage device and the number of storage modules 20 can be expanded based on this architecture according to specific needs, and this embodiment does not impose any limitations in this regard.

[0128] First, the input operation data is divided into eight segments by the filtering module 10, that is, the 512-depth storage address is divided into eight equal segments, each segment controlling a 64-depth storage address, forming a storage module 20. A 1-bit Bank_Sel signal is generated for each storage module 20. During data read and write operations, the filtering module 10 first decodes the externally input address information to determine which storage module 20 it belongs to. This storage module 20 is the target storage module. Then, the filtering module 10 internally controls the read and write enable of the target storage module by enabling the Bank_Sel signal of the target storage module, that is, outputting operation data to the target storage module. Only the operation data of the target storage module is valid; the operation data of other unaccessed storage modules 20 is invalid. Similarly, during data reading, only the Rdata output by the target storage module is valid data, while the Rdata output by other unselected storage modules 20 is always 0. Finally, the final target data is output by ORing the eight segments of output Rdata. In this way, by using address segmentation to control the read / write enable, address, and data signals in the operation data of the storage module, it is ensured that the read / write enable, address, and data signals in the operation data of the target storage module with a successful address match will be toggled, thereby reducing module power consumption.

[0129] During the data search process, firstly, using the second search enable flag VBE and the address signal, a 1-bit VBE is written into a 512-bit wide control register according to the address. That is, each address corresponds to a VBE value. The data search process will only compare the stored data corresponding to the address when the VBE corresponding to the address is high; when the VBE corresponding to the address is low, the data search process will not compare the stored data corresponding to the address. Then, the search process is started by using the upper-layer first search enable flag CMP. Each storage module 20 will output 64 144-bit Key_Match signals. Based on the matching module 40 and the mask information, each 144-bit Key_Match signal is judged to determine whether a comparison is needed. If the value of the corresponding bit in the mask information is low, the Key_Match corresponding to that bit will be directly output as high, that bit does not need to be compared. Then, a bitwise AND operation is performed on the 144-bit Key_Match corresponding to the address where VBE is high. A 1-bit address matching result is output for each address. If the address matching result is high, it indicates that the 144-bit data stored at that address is the data to be searched. Depending on the depth of the data storage device, the address matching result includes a 512-bit result value, as shown in QHR[511:0] in the figure. Simultaneously, to more quickly determine whether the data storage device has found the data to be searched, the 512-bit result value of the address matching data can be bitwise ORed to obtain the storage device matching result QHIT. If the storage device matching result is high, it indicates that at least one piece of data to be searched has been found. Optionally, QHIT can be output through the REG register. This allows for rapid output of the matching search result within one clock cycle during the search process.

[0130] In the above embodiments, latches are used to form storage units, storage units are used to form storage modules, and multiple storage modules are used to form a data storage device, which can reduce the area and power consumption of the data storage device. A comparison of the area of ​​a certain domestic process is shown in Table 2 below. It can be seen that the area of ​​a data storage device constructed using latches is smaller than the area of ​​a data storage device constructed using registers. A comparison of power consumption with and without segmented data storage modules is shown in Table 3. It can be seen that segmenting the data storage device can reduce its power consumption.

[0131] Table 2 Comparison of storage device area composed of different storage units

[0132]

[0133] Table 3. Power consumption comparison between segmented and non-segmented data storage devices.

[0134]

[0135] Embodiments of this application also provide a chip including any of the data storage devices described in the above embodiments. By integrating the aforementioned data storage device, CPU, and input / output interfaces, the chip can be applied to electronic devices, such as smartphones and tablets, to achieve a high-performance, miniaturized, and low-power integrated solution.

[0136] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0137] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data storage device, characterized in that, The data storage device includes a filtering module and multiple storage modules; each storage module includes at least one storage unit, and each storage unit includes a latch; the input terminal of the filtering module is used to receive operation data, and the output terminal of the filtering module is connected to each of the storage modules. The filtering module is used to determine the target storage module among the multiple storage modules based on the operation data, and input the operation data into the target storage module so that the target storage module can perform data access based on the operation data.

2. The data storage device according to claim 1, characterized in that, The operation data also includes address information, and the storage module is further configured to determine a target storage unit in the at least one storage unit based on the address information; The target storage unit is used to receive the operation data and perform data access based on the operation data.

3. The data storage device according to claim 2, characterized in that, The operation data also includes data information, read enable information, write enable information, mask information, and control information; the target storage unit includes at least one latch, a second AND gate, a third AND gate, a fourth AND gate, and a fifth AND gate; The input of the second AND gate is used to receive the write enable information, the mask information, and the control information, and the output of the second AND gate is connected to the write enable port of each of the latches; The input of the third AND gate is used to receive the write enable information, the mask information, and the inverse information of the control information; the output of the third AND gate is connected to the write mask port of each latch. The input terminal of the fourth AND gate is used to receive the read enable information and the control information, and the output terminal of the fourth AND gate is connected to the read enable port of each latch. The input terminal of the fifth AND gate is used to receive the read enable information and the control information, and the output terminal of the fifth AND gate is connected to the read mask port of each latch. The data information is connected to the data ports of each latch.

4. The data storage device according to claim 3, characterized in that, The filtering module is also used to input the operation data into the target storage module so that the target storage module can read data according to the operation data.

5. The data storage device according to claim 4, characterized in that, The data storage device further includes an output module, and the output terminal of each storage module is connected to the input terminal of the output module; The storage module is configured to output target data to the output module based on the operation data when it is determined to be the target storage module; The output module is used to receive the target data and output the target data.

6. The data storage device according to claim 5, characterized in that, The output module includes a data selector; the input terminal of the data selector is connected to the output terminal of each of the storage modules. The data selector is used to receive the output data of each of the storage modules and output the target data according to the target data output by the target storage module.

7. The data storage device according to claim 4, characterized in that, The operation data includes data information, and the data storage device further includes a matching module and an output module that correspond one-to-one with each of the storage modules. The input end of the matching module is connected to the storage module, and the output end of the matching module is connected to the output module. The storage module is further configured to perform data matching between the operation data and the data stored in the storage module, and output a bit data matching result. The bit data matching result is used to indicate the matching result of each bit of the data information with the data stored in the storage module. The matching module is used to output an address matching result to the output module based on the bit data matching result, and the address matching result is used to indicate the matching result of the data information at each address in the storage module.

8. The data storage device according to claim 7, characterized in that, The operation data also includes search enable information and mask information. The matching module includes a first OR gate, a first AND gate, and a first logic unit. The input of the first OR gate is used to receive the bit data matching result output by the storage module and the mask information. The input of the first AND gate is connected to the output of the first OR gate. The input of the first AND gate is also used to receive the search enable information. The output of the first AND gate is connected to the input of the first logic unit. The output of the first logic unit is connected to the output module.

9. The data storage device according to claim 8, characterized in that, The first OR gate is used to filter the bit data matching results according to the mask information and output the first candidate bit data matching result; The first AND gate is used to filter the matching result of the first candidate bit data according to the search enable information and output the matching result of the second candidate bit data. The first logic unit is used to perform a bitwise AND operation on the second candidate bit data matching result and output the address matching result.

10. The data storage device according to claim 9, characterized in that, The output module includes a second OR gate; the input of the second OR gate is connected to the output of each of the matching modules. The second OR gate is used to output a storage device matching result based on the address matching result output by each of the matching modules, wherein the storage device matching result is used to characterize the matching result of the data information in the storage device.

11. The data storage device according to claim 4, characterized in that, The latch includes a first storage sub-unit, a second storage sub-unit, a sixth AND gate, a seventh AND gate, and a third OR gate; The first input terminal of the first storage sub-unit is the write enable port, and the second input terminal is the data port; the output terminal of the first storage sub-unit is connected to the first input terminal of the sixth AND gate. The first input terminal of the second storage sub-unit is the data port, the second input terminal is the write mask port, and the output terminal of the second storage sub-unit is connected to the first input terminal of the seventh AND gate; The second input terminal of the sixth AND gate is the read enable port, and the output terminal of the sixth AND gate is connected to the first input terminal of the third OR gate; The second input terminal of the seventh AND gate is the read mask port, and the output terminal of the seventh AND gate is connected to the second input terminal of the third OR gate; The third OR gate is used to output the data stored in the latch during the data reading process.

12. The data storage device according to claim 11, characterized in that, The latch further includes a selection module; the first input terminal of the selection module is connected to the output terminal of the first storage sub-unit, the second input terminal of the selection module is connected to the output terminal of the second storage sub-unit, and the third input terminal of the selection module is the data port; The selection module is used to output the data matching result of the latch during the data search process.

13. The data storage device according to claim 3, characterized in that, The filtering module is also used to input the operation data into the target storage module so that the target storage module stores data according to the operation data.

14. The data storage device according to claim 13, characterized in that, The latch includes a first storage sub-unit; The first input terminal of the first storage sub-unit is the write enable port, and the second input terminal is the data port; the first storage sub-unit is used to write the data information of the data port into the first storage sub-unit when the write enable port is valid.

15. A chip, characterized in that, Includes the data storage device described in any one of claims 1 to 14.

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