An on-chip integrated vertical inductor structure, transformer and application circuit

Abstract

This invention relates to an on-chip integrated vertical inductor structure, transformer, and application circuit, belonging to the field of inductor design. It comprises a vertically wound inductor formed by sequentially connecting a first winding structure, a second winding structure, and a third winding structure. The vertically wound inductor is perpendicular to the XOY plane. Signal input and output feed structures are provided on the first winding structure. The first and third winding structures employ a multilayer metal structure silicon-based process. The signal input and output feed structures are located in the middle metal Mn layer and Mn-1 layer of the first winding structure. The second winding structure connects the Mn layer and Mn-1 layer of both the first and third winding structures. This invention utilizes vertical three-dimensional winding, employing vias and metal traces in a multilayer metal process to vertically connect and form the inductor, further reducing the inductor area in the XY direction, achieving miniaturization and reducing chip cost.

Description

Technical Field

[0001] This invention relates to the field of inductor design, and more particularly to an on-chip integrated vertical inductor structure, transformer, and application circuit. Background Technology

[0002] Inductors are crucial components in modern integrated circuit design, particularly in RF, millimeter-wave, high-speed digital, and power management fields. Using off-chip discrete inductors occupies valuable PCB area, increases assembly complexity and cost, and limits system miniaturization. Integrating inductors directly into the silicon chip or package substrate eliminates dependence on external components, enabling true system-on-a-chip (SoC). This primarily addresses the urgent need for high-frequency, miniaturized, highly integrated, and high-performance electronic systems, driving the realization of smaller, faster, smarter, and more reliable electronic products. Inductors and transformers are extensively used in phased-array radar and wireless communication chips, often occupying more than 50% of the chip area. Therefore, miniaturizing inductors is key to reducing chip area and cost. Furthermore, to reduce chip area, modules and links are often placed close together, leading to increased coupling between inductors. This reduces isolation between modules, links, and channels, and severe signal crosstalk can degrade chip performance or even cause malfunction. Therefore, resolving inductor coupling issues is crucial for system miniaturization.

[0003] like Figure 1 and Figure 2 As shown, the inductor model provided by traditional on-chip integrated inductors is usually formed by winding top-layer metal traces on a two-dimensional XY plane. Furthermore, traditional on-chip integrated circuits are usually composed of one or two layers of metal and metal vias connecting the two layers. Their area is much larger than that of transistors, making them one of the most space-consuming components in the system. Moreover, foundries usually charge for chips based on the area calculated in the XY direction when manufacturing chips, which is very disadvantageous for chips that use planar wire-wound inductors and transformers over a large area. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide an on-chip integrated vertical inductor structure, transformer and application circuit, thereby solving the deficiencies of the prior art.

[0005] The objective of this invention is achieved through the following technical solution: an on-chip integrated vertical inductor structure, comprising a vertically wound inductor formed by sequentially connecting a first winding structure, a second winding structure, and a third winding structure, wherein the vertically wound inductor is perpendicular to the XOY plane, and a signal input and output feeder structure is provided on the first winding structure.

[0006] The first and third winding structures are manufactured using a multilayer metal structure silicon-based process. The signal input and output feed structures are located in the metal Mn layer and Mn-1 layer of the first winding structure. The second winding structure is connected to the metal Mn layer and Mn-1 layer of the first and third winding structures, respectively.

[0007] The first winding structure is wound into a coil through the vias between the metal Mn layer and Mtop layer and the vias between the metal M1 layer and Mn-1 layer, thereby connecting the feed structure and the second winding structure. The third winding structure is wound into a coil through the vias between the metal M1 layer and Mtop layer and is connected to the first winding structure through the second winding structure.

[0008] The second winding structure connects the Mn layer metal in the first winding structure with the Mn-1 layer metal in the third winding structure. The second winding structure also connects the Mn-1 layer metal in the first winding structure with the Mn layer metal in the third winding structure. When current flows through the first winding structure and the third winding structure, the magnetic flux passes through the XOZ plane of the coil. According to the principle of electromagnetic induction, the magnetic flux directions of the first winding structure and the third winding structure are opposite, thereby achieving magnetic coupling cancellation to the outside, reducing coupling to other inductors or devices, and reducing signal crosstalk.

[0009] The linewidths of the signal input and output feeder structures are W1 and W4, respectively, and the line length is L1 for both. The linewidths of the Mtop and M1 layers of the first winding structure are W2 and W5, respectively, and the line length is L2 for both. The linewidths of the Mtop and M1 layers of the third winding structure are W3 and W6, respectively, and the line length is L3 for both. The width of the second winding structure is W7, and the length is L4. The inductance value is adjusted by adjusting W1, W2, W3, W4, W5, W6, L1, L2, L3, and L4.

[0010] An on-chip integrated vertical winding transformer includes two vertical inductor structures, which are placed parallel to each other in the Y direction, and the feed structures of the two vertical inductor structures are located on different sides.

[0011] The interval between the two vertical inductor structures is S1, and the centers of the second winding structures of the two vertical inductor structures are not on the same straight line, and the interval between the centers in the X direction is S2. The self-inductance LP of the primary coil and the self-inductance LS of the secondary coil of the transformer can be adjusted by adjusting the parameters of the two vertical inductor structures, and the coupling coefficient km of the transformer can be adjusted by adjusting S1 and S2.

[0012] An application circuit based on an on-chip integrated vertical inductor structure is disclosed. The application circuit includes a common-source cascode amplifier. A vertical inductor structure is added between the common-source stage and the common-gate stage of the common-source cascode amplifier. The vertical inductor structure generates magnetic flux in opposite directions, achieving magnetic coupling cancellation. Furthermore, the magnetic flux generated by each winding is physically orthogonal to the magnetic flux generated by the planar inductor, thereby achieving low coupling.

[0013] An application circuit based on on-chip integrated vertical winding transformer matching, the application circuit includes an amplifier structure, the amplifier structure including a vertical winding transformer connected to the input and output terminals of the amplifier respectively.

[0014] The present invention has the following advantages: an on-chip integrated vertical inductor structure, transformer and application circuit, compared with the traditional planar inductor solution, adopts vertical three-dimensional winding to form an inductor by vertically connecting vias and metal traces in multilayer metal processing, further reducing the area of ​​the inductor in the XY direction, realizing miniaturization and reducing chip cost, and can realize mutual closed loop of magnetic flux between adjacent coils, thereby reducing electromagnetic coupling to other inductors or devices and reducing signal crosstalk. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a traditional planar multi-turn wire-wound inductor.

[0016] Figure 2 This is a schematic diagram of a traditional planar figure-eight wire-wound inductor.

[0017] Figure 3 This is a cross-sectional view of silicon-based processes.

[0018] Figure 4 This is a three-dimensional structural diagram of the vertical wire-wound inductor structure of the present invention.

[0019] Figure 5 This is a schematic diagram of an embodiment of the vertical wire-wound inductor structure of the present invention.

[0020] Figure 6 This is an application structure diagram of the vertical wire-wound inductor structure of the present invention.

[0021] Figure 7 This is a schematic diagram illustrating the magnetic flux analysis of the vertical wound inductor structure of the present invention.

[0022] Figure 8 This is a schematic diagram of the common-source cascode amplifier structure based on an on-chip vertical winding transformer according to the present invention.

[0023] Figure 9 This is a circuit diagram of the amplifier based on on-chip vertical winding transformer matching according to the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of this application provided below with reference to the accompanying drawings is not intended to limit the scope of protection of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. The present invention will be further described below with reference to the accompanying drawings.

[0025] One embodiment of the present invention is based on, for example Figure 3 The paper presents an on-chip vertical wire-wound inductor structure based on multilayer metal processing. For inductors with the same inductance, the area can be reduced by more than 65%, which helps to reduce chip costs. In addition, while reducing the inductor area, it can further reduce the coupling between the inductor and the planar inductor compared with the traditional figure-eight inductor, which greatly reduces crosstalk and improves system performance.

[0026] like Figure 4 As shown, it includes a signal input / output feeder structure. Vertically, it includes and sequentially connects a first winding structure, a second winding structure, and a third winding structure to form a vertical wire-wound inductor. The entire structure is manufactured using a silicon-based process with a multilayer metal structure. The middle metal Mn layer and Mn-1 layer serve as the input and output of the feeder structure, respectively. The first winding structure is wound into a coil through vias between the metal Mn layer and Mtop layer and between the M1 layer and Mn-1 layer, and connects the feeder structure and the second winding structure. The third winding structure is wound into a coil through vias between the metal M1 layer and Mtop layer, and connects to the first winding structure through the second winding structure.

[0027] Furthermore, such as Figure 5 As shown, in this scheme, to reduce external electromagnetic coupling, the following specific winding method is used: the second winding structure connects the Mn layer metal in the first winding structure with the Mn-1 layer metal in the third winding structure, and the second winding structure also connects the Mn-1 layer metal in the first winding structure with the Mn layer metal in the third winding structure. The principle analysis is as follows: when current flows through the first and third winding structures, the magnetic flux will pass through the XOZ plane of the coil. According to the principle of electromagnetic induction, the magnetic flux in the two winding structures is in opposite directions, achieving magnetic coupling cancellation externally, thereby reducing coupling to other inductors or devices and reducing signal crosstalk.

[0028] like Figure 6As shown, the feeder structure is located on layers Mn and Mn-1, with linewidths of W1 and W4, and a line length of L1 for both. The first winding structure is wound into a coil via vias between metal layers Mn and Mtop, and between M1 and Mn-1. The linewidths on layers Mtop and M1 are W2 and W5, respectively, with a line length of L2 for both. The third winding structure is wound into a coil via vias between metal layers M1 and Mtop. The linewidths on layers Mtop and M1 are W3 and W6, respectively, with a line length of L3 for both. The second winding structure has a width of W7, typically determined by the number of vertical vias, and a length of L4. The desired inductance value can be obtained by adjusting these parameters.

[0029] To help those skilled in the art better understand the application of the silicon-based millimeter-wave transformer design proposed in this invention, the following example of a 6-layer metal silicon-based vertical wire-wound inductor operating in the 1GHz-30GHz frequency band will be used for further explanation.

[0030] A vertically wound inductor is designed using a silicon-based process. This process has six metal layers, with AP as the top layer. The second-to-top metal, TM2, is selected as the Mn layer metal of the vertically wound inductor of this invention, TM1 as the Mn-1 metal, and the lower metal layers M1-M3 as the winding connection structure. Figure 7 As shown. The metal trace widths W1-W6 are all 3µm, W7 is 6µm, the feed line length L1 is 12µm, the winding lengths L2 and L3 are 54.5µm, and L4 is 21µm. Modeling and simulation were performed using AnsysMaxwell electromagnetic simulation software. The area of ​​the vertical winding inductor is approximately 744µm. 2 And through Z parameters and formulas The calculated inductance value is approximately 100 pH, where L is the inductance value, f represents the frequency, Im(·) represents the operation of taking the imaginary part of the "·", and Z11, Z12, Z21, and Z22 are the matrix parameters of the two-port network Z-parameter matrix. Additionally, a conventional on-chip planar figure-eight inductor with the same inductance value is designed as a comparison reference, such as... Figure 2 As shown, TM1 and TM2 are used as winding metals, the metal trace width W1 is 3um for all traces, the feed line spacing S1 is 3um, the winding lengths L1 to L5 are 20um, 10.5um, 30um, 30um, and 30um respectively, the winding line spacing S2 is 2um, and the vertical winding inductor area is approximately 2370um. 2 .

[0031] To compare electromagnetic coupling performance, both the traditional figure-eight inductor and the vertical wound inductor structure of this invention were placed within the same planar wound inductor. Modeling and simulation were performed using the electromagnetic simulation software Ansys Maxwell, and the Z-parameters and formulas were used to analyze the results. Calculate the coupling coefficient km between the two inductors and perform simulation. The value is used to evaluate the isolation performance between inductors, where Gmax represents the maximum available gain, S21 represents the forward transmission coefficient, S12 represents the reverse transmission coefficient, Z11, Z12, Z21, and Z22 are the matrix parameters of the Z-parameter matrix of the two-port network, and k... f This represents the network stability coefficient.

[0032] The overall performance comparison is summarized in Table 1 below. Compared with the traditional two-dimensional figure-eight inductor, the area of ​​this invention is reduced by more than 65%, the coupling coefficient (km) with the unidirectional inductor is reduced by more than 70%, and the isolation between inductors is improved by more than 20dB. In summary, it can be seen that the vertical wire-wound inductor structure of this invention has achieved significant improvements in terms of area and signal isolation performance.

[0033] Table 1. Comparison of the implementation effects of the embodiments of the present invention and traditional wire-wound inductors Comparison items Traditional wire-wound inductors This invention winding method Planar winding Vertical winding area <![CDATA[2370 um 2 ]]> <![CDATA[744 um 2 ]]> Coupling coefficient km 14m@15G 2.5m@15G Inductor isolation -21dB@15G -44dB@15G

[0034] like Figure 8 As shown, another embodiment of the present invention relates to an on-chip vertically wound transformer structure, which is formed by placing two vertically wound inductors parallel to each other in the Y direction in the first embodiment, with the input and output ports placed back to back, the inductors spaced S1 apart in the Y direction, and the centers of the two second winding structures spaced S2 apart in the X direction. Adjustment... Figure 8 The parameters shown can adjust the self-inductance LP of the primary and secondary coils and the self-inductance LS of the secondary coil of the transformer. Adjusting S1 and S2 can adjust the transformer coupling coefficient km.

[0035] Another embodiment of the present invention relates to an application circuit based on an on-chip vertical wire-wound inductor structure. The application circuit includes a Cascode amplifier, which uses an on-chip vertical wire-wound inductor to realize the peaking inductor. The on-chip vertical wire-wound inductor is disposed between the common source stage and the common gate stage of the Cascode amplifier. The vertical wire-wound structure generates magnetic flux in opposite directions, achieving magnetic coupling cancellation. Moreover, the magnetic flux generated by each set of wires is physically orthogonal to the magnetic flux generated by the planar inductor, which can achieve low coupling. Therefore, the peaking inductor can be embedded in the secondary coil of the input matching transformer, introducing a peaking inductor to improve circuit performance without consuming additional area.

[0036] like Figure 9 As shown, another embodiment of the present invention relates to an application circuit based on on-chip vertical winding transformer matching. The application circuit includes an amplifier structure, which uses two sets of vertical winding inductor structures to realize the placement of the vertical transformer at the input (RFIN) and output (RFOUT) terminals of the amplifier structure for amplifier circuit matching design.

[0037] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and improvements, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. An on-chip integrated vertical inductor structure, characterized in that: It includes a vertically wound inductor formed by connecting a first winding structure, a second winding structure and a third winding structure in sequence. The vertically wound inductor is perpendicular to the XOY plane. A feeder structure for signal input and output is provided on the first winding structure. The first and third winding structures are manufactured using a multilayer metal structure silicon-based process. The signal input and output feed structures are located in the metal Mn layer and Mn-1 layer of the first winding structure. The second winding structure is connected to the metal Mn layer and Mn-1 layer of the first and third winding structures, respectively.

2. The on-chip integrated vertical inductor structure according to claim 1, characterized in that: The first winding structure is wound into a coil through the vias between the metal Mn layer and Mtop layer and the vias between the metal M1 layer and Mn-1 layer, thereby connecting the feed structure and the second winding structure. The third winding structure is wound into a coil through the vias between the metal M1 layer and Mtop layer and is connected to the first winding structure through the second winding structure.

3. The on-chip integrated vertical inductor structure according to claim 1, characterized in that: The second winding structure connects the Mn layer metal in the first winding structure with the Mn-1 layer metal in the third winding structure. The second winding structure also connects the Mn-1 layer metal in the first winding structure with the Mn layer metal in the third winding structure. When current flows through the first winding structure and the third winding structure, the magnetic flux passes through the XOZ plane of the coil. According to the principle of electromagnetic induction, the magnetic flux directions of the first winding structure and the third winding structure are opposite, thereby achieving magnetic coupling cancellation to the outside, reducing coupling to other inductors or devices, and reducing signal crosstalk.

4. The on-chip integrated vertical inductor structure according to claim 1, characterized in that: The linewidths of the signal input and output feeder structures are W1 and W4, respectively, and the line lengths are both L1; the linewidths of the Mtop layer and M1 layer metal of the first winding structure are W2 and W5, respectively, and the line lengths are both L2. The linewidths of the Mtop and M1 layers of the third winding structure are W3 and W6, respectively, and the line lengths are both L3. The width of the second winding structure is W7 and the length is L4; the inductance value can be adjusted by adjusting W1, W2, W3, W4, W5, W6, L1, L2, L3 and L4.

5. An on-chip integrated vertical winding transformer, characterized in that: The transformer includes two vertical inductor structures as described in any one of claims 1-4, the two vertical inductor structures are placed parallel to each other in the Y direction, and the feeder structures of the two vertical inductor structures are located on different sides.

6. The on-chip integrated vertical winding transformer according to claim 5, characterized in that: The interval between the two vertical inductor structures is S1, and the centers of the second winding structures of the two vertical inductor structures are not on the same straight line, and the interval between the centers in the X direction is S2. The self-inductance LP of the primary coil and the self-inductance LS of the secondary coil of the transformer can be adjusted by adjusting the parameters of the two vertical inductor structures, and the coupling coefficient km of the transformer can be adjusted by adjusting S1 and S2.

7. An application circuit based on an on-chip integrated vertical inductor structure, characterized in that: The application circuit includes a common-source cascode amplifier. A vertical inductor structure as described in any one of claims 1-4 is added between the common-source stage and the common-gate stage of the common-source cascode amplifier. The vertical inductor structure generates magnetic flux in opposite directions, achieving magnetic coupling cancellation. Furthermore, the magnetic flux generated by each set of windings is physically orthogonal to the magnetic flux generated by the planar inductor, thereby achieving low coupling.

8. An application circuit based on on-chip integrated vertical winding transformer matching, characterized in that: The application circuit includes an amplifier structure, wherein a vertically wound transformer as described in claim 5 or 6 is connected to the input and output terminals of the amplifier, respectively.

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