A chamber liner, chamber kit, and semiconductor apparatus

Abstract

This application discloses a cavity liner, a cavity assembly, and a semiconductor device for improving the quality of semiconductor processes. The application provides a cavity liner made entirely of silicon or silicides other than metal silicides. The cavity liner is placed inside a semiconductor device, which may include etching equipment. Because the cavity liner is entirely made of silicon or silicides other than metal silicides, no plating is applied, thus avoiding the problem of plating peeling off due to high-power bombardment. Furthermore, the inventors have noted that semiconductor processes are typically very sensitive to metal elements. This application utilizes silicon or silicides other than metal silicides as the entire material of the cavity liner, thus preventing the formation of metal elements even when bombarded by high-power plasma, thereby improving the quality of the semiconductor process.

Description

Technical Field

[0001] This application relates to the field of semiconductor etching technology, specifically to a cavity liner, a cavity kit, and a semiconductor device. Background Technology

[0002] During plasma etching, plasma is formed in the cavity liner, which is typically made of aluminum alloy with a yttrium oxide coating. As semiconductor etching requires larger aspect ratios, the radio frequency power of the plasma is gradually increasing. Under the bombardment of high-power plasma, the yttrium oxide coating may peel off, thus affecting the plasma etching effect and reducing the quality of the semiconductor process. Summary of the Invention

[0003] This application discloses a cavity liner, a cavity kit, and a semiconductor device for improving the quality of semiconductor processes.

[0004] On one hand, this application provides a cavity liner, the entire material of which is silicon or a silicide other than metal silicide; the cavity liner includes a top wall and a bottom wall disposed opposite to each other, and a side wall connecting the top wall and the bottom wall, the top wall enclosing to form a first opening, the first opening being a gas inlet; the bottom wall enclosing to form a second opening.

[0005] The cavity liner provided in this application is for placement inside a semiconductor device, which may include etching equipment. Since the entire material of the cavity liner is silicon or a silicide other than metal silicides, no plating is used, thus fundamentally avoiding the problem of plating peeling off due to high-power bombardment. Furthermore, the inventors have noted that semiconductor processes are typically very sensitive to metal elements; excessive metal elements can significantly affect the quality of the semiconductor process. For example, the peeling off of yttrium oxide plating can lead to excessive yttrium levels. This application utilizes silicon or a silicide other than metal silicides as the entire material of the cavity liner, thus preventing the presence of metal elements even under high-power plasma bombardment, thereby improving the quality of the semiconductor process.

[0006] In some embodiments, the cavity lining material is silicon or silicon carbide.

[0007] In plasma etching processes, when the cavity lining is made of silicon or silicon carbide, it has good corrosion resistance. Moreover, silicon and silicon carbide are relatively inexpensive, which helps to reduce costs.

[0008] In one possible implementation, the bulk resistivity of the cavity liner material is <100 Ω·cm. This configuration improves the overall conductivity of the cavity liner, facilitating the formation of radio frequency pathways through the cavity liner and providing a foundation for semiconductor processes.

[0009] In one possible implementation, the cavity liner is integrally molded. This improves the integral continuity of the cavity liner, avoiding the problem of poor continuity at joints compared to spliced ​​cavity liners, thus improving the overall conductivity of the cavity liner and consequently enhancing the performance of semiconductor processes. Furthermore, it effectively reduces the number of components and their interconnections, lowering the complexity of engineering implementation.

[0010] In one possible implementation, a plurality of through grooves are provided on the bottom wall, the through grooves penetrating the bottom wall in the thickness direction, and the ratio of the depth of the through groove to the width of the through groove opening is greater than or equal to 2.5.

[0011] Because the through-slot penetrates the bottom wall in the thickness direction, it can connect the reaction space with the process chamber of the semiconductor equipment. Furthermore, since the ratio of the depth of the through-slot to the width of the through-slot opening is greater than or equal to 2.5, the plasma can be annihilated within the through-slot (for example, the plasma gradually dissipates as it collides with the inner wall of the through-slot during its passage), preventing the plasma from leaking from the reaction space into the process chamber and avoiding damage to other components within the process chamber.

[0012] On the other hand, this application also provides a chamber kit, which includes, for example, a chamber liner and a grounding element as described in any of the above embodiments. The grounding element is connected to the chamber liner.

[0013] In one possible implementation, the grounding component includes a first connecting portion, a deformable portion, and a second connecting portion. The deformable portion connects the first and second connecting portions. The first connecting portion connects to the cavity liner, and the second connecting portion connects to the grounding platform. The deformable portion deforms according to the distance between the first and second connecting portions. The cavity liner may be simultaneously subjected to pressure from a rigid component (e.g., a heating element and a top cover) located above it and a grounding component located below it. If a rigid grounding component is used, since both the components above and below the cavity liner are rigid, an inappropriate distance between the components above the cavity liner and the grounding component below (e.g., less than the height of the cavity liner) can easily affect the stress safety of the cavity liner, leading to liner breakage. This application uses a flexible grounding component with a deformable portion, which helps ensure the stress safety of the cavity liner. Furthermore, using a flexible grounding component also helps to compensate for the fit gaps between the cavity liner, the grounding component, and the top cover, thereby avoiding the problem of loose connection between the cavity liner and the grounding component.

[0014] In one possible implementation, the deformable part is curved or bent in the vertical direction, which facilitates deformation of the deformable part in the vertical direction.

[0015] In another aspect, this application provides a semiconductor device including a cavity liner and a chuck. The cavity liner is, for example, the cavity liner described in any of the above embodiments. The cavity liner includes a top wall and a bottom wall disposed opposite each other, and a side wall connecting the top wall and the bottom wall. The top wall encloses to form a first opening, which is a gas inlet. The bottom wall encloses to form a second opening. The chuck is located inside the second opening, and the chuck and the cavity liner enclose to form a reaction space.

[0016] The semiconductor device provided in this application may include etching equipment. An internal cavity liner is placed within the semiconductor device. Since the entire material of the cavity liner is silicon or a silicide other than metal silicides, no plating is applied, thus fundamentally avoiding the problem of plating peeling off due to high-power bombardment. Furthermore, the inventors have noted that semiconductor processes are typically very sensitive to metal elements; excessive metal elements can significantly affect the quality of the semiconductor process. For example, the peeling off of yttrium oxide plating can lead to excessive yttrium levels. This application utilizes silicon or a silicide other than metal silicides as the entire material of the cavity liner, thereby preventing the formation of metal elements even under high-power plasma bombardment and improving the quality of the semiconductor process.

[0017] In one possible implementation, a wafer transfer port is provided on the sidewall; the semiconductor device includes a switch board and a moving mechanism, the switch board is located on the side of the wafer transfer port away from the reaction space, the moving mechanism is connected to the switch board, and the moving mechanism is used to drive the switch board to cover or expose the wafer transfer port.

[0018] With the above configuration, when the moving mechanism drives the switch board to expose the wafer transfer port, the wafer can enter the reaction space through the transfer port. When the moving mechanism drives the switch board to cover the wafer transfer port, the switch board can block the transfer port, preventing plasma from leaking from the reaction space into the process chamber through the transfer port, thus avoiding damage to other components in the process chamber.

[0019] In one possible implementation, the switchboard includes a silicon plate made of silicon or a silicide other than a metal silicide, wherein when the switchboard covers the wafer transfer port, the orthographic projection of the wafer transfer port onto the silicon plate is located inside the silicon plate.

[0020] With the above settings, the part of the switch board corresponding to the chip transfer port is made of silicon or silicide other than metal silicide, rather than a material with yttrium oxide coating. This can avoid the presence of metal elements during semiconductor processing, improve the quality of semiconductor processing, and at the same time, allow the switch board to seal the chip transfer port during the process, preventing plasma from leaking out of the reaction space.

[0021] In one possible implementation, the switch board further includes a receiving frame surrounding the silicon substrate, with a portion of the silicon substrate exposed by the receiving frame; a moving mechanism is connected to the receiving frame, and when the moving mechanism drives the switch board to a position that covers the wafer transfer port, the exposed portion of the silicon substrate covers the wafer transfer port.

[0022] With the above configuration, the moving mechanism is connected to the receiving frame and indirectly connected to the silicon plate set on the receiving frame, thus avoiding direct connection between the moving mechanism and the silicon plate, which could damage the silicon plate.

[0023] In one possible implementation, the switch board further includes a buffer pad that fills the space between the receiving frame and the silicon plate. This helps to prevent the silicon plate from shaking during lifting and lowering, and also helps to prevent the silicon plate from colliding with the receiving frame or other components and breaking.

[0024] In one possible implementation, the semiconductor device includes a cavity wall and a grounding element. The cavity wall encloses a process chamber, and an inner liner of the process chamber is located inside the process chamber. The grounding element connects the inner liner of the cavity and the cavity wall so that a radio frequency path can be formed within the process chamber.

[0025] In one possible implementation, the cavity wall includes a grounding platform, and a grounding element is located between the grounding platform and the bottom wall; the grounding element is arranged around the chuck, with one end of the grounding element connected to the bottom wall and the other end of the grounding element connected to the grounding platform.

[0026] In one possible implementation, the grounding element includes a first connecting portion, a deformable portion, and a second connecting portion. The deformable portion connects the first and second connecting portions. The first connecting portion is connected to the cavity liner, and the second connecting portion is connected to the grounding platform. The deformable portion is used to deform according to the distance between the first and second connecting portions. The cavity liner may be simultaneously subjected to pressure from a rigid component (e.g., a heating element and a top cover) located above it and a grounding element located below it. If a rigid grounding element is used, since both the components above and below the cavity liner are rigid, if the distance between the components above the cavity liner and the grounding element below is inappropriate (e.g., less than the height of the cavity liner), it can easily affect the stress safety of the cavity liner, causing it to crack. This application uses a flexible grounding element with a deformable portion, which is beneficial for ensuring the stress safety of the cavity liner. It should be understood that silicon cavity liners are generally more brittle than aluminum alloy liners and are more prone to damage under excessive stress or deformation. Therefore, using a flexible grounding element is particularly useful for silicon cavity liners. In addition, the use of flexible grounding components helps to compensate for the gaps between the cavity liner, the grounding component, and the top cover, thereby avoiding the problem of loose connection between the cavity liner and the grounding component.

[0027] In one possible implementation, the deformable part is curved or bent in the vertical direction, which facilitates deformation of the deformable part in the vertical direction.

[0028] In one possible implementation, the semiconductor device further includes a radio frequency (RF) generator connected to a chuck via a conductive cable or structural component. The RF generator emits radio frequency energy into the reaction space via the chuck, which is used to convert the gas located in the reaction space into plasma.

[0029] In one possible implementation, an exhaust device is provided on the cavity wall to exhaust the gas inside the process cavity.

[0030] With the above setup, before the plasma etching process begins, the exhaust equipment can evacuate the process chamber and reaction space of the semiconductor equipment to a vacuum or ultra-vacuum, so as to minimize the presence of unnecessary residual gas molecules in the reaction space, thereby increasing the concentration of plasma input into the reaction space.

[0031] Meanwhile, during the plasma etching process, the byproducts formed after the silicon material is etched into the cavity liner can be transformed into gaseous compounds through process means, and the exhaust equipment is also used to remove the gaseous compounds (unlike the aluminum alloy cavity liner, yttrium oxide and other coatings cannot be transformed into gaseous compounds); thus reducing the number of contaminant particles in the cavity liner and improving the effect of plasma etching.

[0032] In one possible implementation, the semiconductor device further includes a gas equalization disk and a temperature control device. The gas equalization disk is located inside the first opening, and the temperature control device is located on the side of the gas equalization disk away from the reaction space. Gas enters the reaction space through the temperature control device and the gas equalization disk.

[0033] With the above setup, the process gas is evenly distributed in the reaction space via the gas distribution plate, which facilitates the uniform distribution of plasma in the reaction space; the process gas first passes through the temperature control device to adjust its temperature and then enters the reaction space via the gas distribution plate, so that the plasma entering the reaction space has an initial temperature. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the internal structure of the semiconductor device in the embodiments of this application; Figure 2 This is a schematic diagram of the cavity liner in an embodiment of this application; Figure 3 This is a schematic diagram illustrating the relative positions of a switch board and a transmission port in one embodiment of this application. Figure 1 ; Figure 4 This is a schematic diagram illustrating the relative positions of a switch board and a transmission port in one embodiment of this application. Figure 2 ; Figure 5 This is a schematic diagram showing the relative positions of another switch board and the transfer port in an embodiment of this application. Figure 1 ; Figure 6 This is a schematic diagram showing the relative positions of another switch board and the transfer port in an embodiment of this application. Figure 2 ; Figure 7 This is a schematic diagram of the grounding element in an embodiment of this application.

[0036] Explanation of reference numerals in the attached figures: 100 - Semiconductor equipment; 10-Cavity wall; 11-Side cavity wall; 12-Bottom cavity wall; 13-Top cover; 14-Grounding platform; 01-Process chamber; 20-Cavity liner; 201-Reaction space; 21-Top wall; 210-First opening; 22-Bottom wall; 220-Second opening; 221-Through groove; 23-Side wall; 230-Plate transfer port; 31-Chuck; 32-RF generator; 33-Gas equalization plate; 40 - Temperature control device; 41 - Heating plate; 42 - Water cooling plate; 43 - Heating element; 50 - Exhaust equipment; 51 - Molecular pump; 52 - Pressure control valve; 60-Switchboard; 61-Silicon plate; 62-Receiving frame; 63-Buffer pad; 70 - Moving mechanism; 80 - Grounding component; 81 - First connecting part; 82 - Second connecting part; 83 - Deformation part; 801 - First groove; 802 - Second groove; 90 - Insulating component; 91 - First insulating component; 92 - Second insulating component. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.

[0039] Furthermore, in the embodiments of this application, directional terms such as "up," "down," "left," "right," "horizontal," and "vertical" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0040] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0041] It should be noted that, in the description of the embodiments of this application, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection or an integral connection; they can also refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; or they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0042] Reference Figure 1 This application provides a semiconductor device 100, which includes a plasma etching apparatus. The plasma etching apparatus uses capacitive coupling to transfer radio frequency energy to a process gas, causing it to ionize and form plasma, i.e., capacitively coupled plasma (CCP). Then, the plasma selectively removes certain materials from the wafer, including polysilicon gate etching, contact / via etching, trench etching, and dielectric layer removal; thereby forming logic chips (CPU, GPU, ASIC, etc.) or memory chips (DRAM, 3D NAND Flash, etc.).

[0043] The semiconductor device 100 is used to connect with other systems such as a gas supply system, an exhaust system, a temperature control system, and a wafer handling system. The gas supply system provides high-purity process gases (CF4, Cl2, C2F8, etc.) to the semiconductor device 100; the exhaust system removes waste gases from inside the semiconductor device 100 or creates a vacuum environment inside the semiconductor device 100; the temperature control system adjusts the initial temperature of the process gases; and the wafer handling system moves wafers into or out of the semiconductor device 100.

[0044] The semiconductor device 100 provided in this application embodiment includes a cavity wall 10, which includes a side cavity wall 11, a bottom cavity wall 12, and a top cover 13. The side cavity wall 11 and the bottom cavity wall 12 can be an integral structure, and the top cover 13 can be detachably connected to the side cavity wall 11. The side cavity wall 11, the bottom cavity wall 12, and the top cover 13 enclose a process chamber 01. The semiconductor device 100 also includes a cavity liner 20 and a chuck 31. The cavity liner 20 and the chuck 31 are both disposed in the process chamber 01. The entire material of the cavity liner 20 is silicon or silicide excluding metal silicides. The cavity liner 20 includes a top wall 21 and a bottom wall 22 disposed opposite to each other, and a side wall 23 connecting the top wall 21 and the bottom wall 22. The top wall 21 encloses a first opening 210, which is used to connect to a gas supply system and serves as an inlet for process gas. The bottom wall 22 encloses a second opening 220. The internal space of the chamber liner 20 (i.e., the space between the top wall 21 and the bottom wall 22) is the reaction space 201, which is, for example, a plasma reaction space for carrying out plasma reactions. In some embodiments, the chuck 31 is located within the second opening 220, and the chuck 31 and the chamber liner 20 can be considered to enclose and form the reaction space 201.

[0045] The cavity wall 10 of the semiconductor device 100 is provided with a transport opening (not shown in the figure) for wafer transport, which is used to connect to a wafer transport system. The side wall 23 of the cavity liner 20 is provided with a wafer transfer port 230, which corresponds to the transport opening on the cavity wall 10 of the semiconductor device 100, allowing the wafer transport system to move to or from the reaction space 201 through the transport opening and the wafer transfer port 230. The upper surface of the chuck 31 is used to hold the wafer.

[0046] The semiconductor device 100 also includes a radio frequency (RF) generator 32, which is connected to a chuck 31 via a conductive cable or structural component. The RF generator 32 emits radio frequency energy into the reaction space 201 through the chuck 31. This RF energy is used to convert the gas within the reaction space 201 into plasma. For example, the RF generator 32 is connected to the chuck 31 via a conductive cable. The RF energy is an electromagnetic wave. With the chuck 31 as the lower electrode and the top wall 21 of the cavity liner 20 as the upper electrode, the electromagnetic wave creates an alternating electric field between the chuck 31 and the top wall 21 of the cavity liner 20. This causes electrons to oscillate in the electric field and gain energy. When the electron energy is sufficiently high, it collides with neutral gas molecules of the process gas input into the reaction space 201, ionizing them and generating new electrons and ions. Ultimately, this transforms the neutral process gas into conductive plasma. The resulting plasma etches the wafer located on the chuck 31.

[0047] In some embodiments, the cavity liner in the semiconductor device 100 is made of aluminum alloy, and a yttrium oxide coating is deposited on the inner wall of the aluminum alloy cavity liner. However, as semiconductor etching requires a larger aspect ratio, the radio frequency power of the plasma generation gradually increases. Under the bombardment of high-power plasma, the yttrium oxide coating may detach, thus affecting the plasma etching effect and reducing the quality of the semiconductor process. Furthermore, semiconductor processes are generally very sensitive to metal elements; if the metal element content exceeds the standard, it will greatly affect the quality of the semiconductor process. The detachment of the yttrium oxide coating will lead to an excess of yttrium.

[0048] In the semiconductor device 100 provided in this application, the cavity liner 20 located in the semiconductor device 100 is made of silicon. Specifically, all materials of the cavity liner 20 are silicon or silicides other than metal silicides. On the one hand, no plating layer is provided in the cavity liner, thus fundamentally avoiding the problem of plating layer falling off due to high-power bombardment. On the other hand, this application uses silicon or silicides other than metal silicides as all materials of the cavity liner, so that even if bombarded by high-power plasma, metal elements can be avoided, which can improve the quality of semiconductor processing.

[0049] For example, the cavity liner material is silicon (e.g., monocrystalline silicon, polycrystalline silicon), silicon carbide, silicon dioxide, etc. Among these, in plasma etching processes, when the cavity liner is made of silicon or silicon carbide, it has good corrosion resistance, and silicon and silicon carbide are relatively inexpensive, which helps to reduce costs.

[0050] In some embodiments, the bulk resistivity of the cavity liner 20 material is <100 Ω·cm. This configuration improves the overall conductivity of the cavity liner 20, facilitating the formation of radio frequency pathways through the cavity liner and providing a foundation for semiconductor processes.

[0051] In some embodiments, the cavity liner 20 is integrally formed, for example, by integral machining (e.g., grinding). Integral forming improves the continuity of the cavity liner 20, avoiding the problem of poor continuity at joints compared to spliced ​​cavity liners, thus improving the overall conductivity of the cavity liner 20 and consequently enhancing the performance of semiconductor processes. Furthermore, it effectively reduces the number of parts in the cavity liner 20 and their interconnections, lowering the difficulty of engineering implementation.

[0052] In some embodiments, an exhaust device 50 is provided on the cavity wall 10. The exhaust device 50 is used to connect to an exhaust system and to discharge gas from the process chamber 01. For example, the exhaust device 50 is provided on the bottom cavity wall 12, which has an interface. The exhaust device 50 may include a molecular pump 51 and a pressure control valve 52. The molecular pump 51 is connected to the interface through the pressure control valve 52.

[0053] Reference Figure 1 and Figure 2 In the above embodiment, a plurality of through slots 221 are formed on the bottom wall 22 of the cavity liner 20. The through slots 221 penetrate the bottom wall 22 in the thickness direction to connect the reaction space 201 and the process chamber 01 of the semiconductor device 100. The ratio of the depth of the through slot 221 to the width of the slot opening is greater than or equal to a preset threshold (e.g., 2.5). With the above configuration, the through slots 221 can realize the connection between the reaction space 201 and the process chamber 01 of the semiconductor device 100. Since the ratio of the depth of the through slot 221 to the width of the through slot opening is greater than or equal to 2.5, the plasma can be annihilated in the through slot 221 (e.g., the plasma gradually dissipates by colliding with the inner wall of the through slot 221 during the process of passing through the through slot 221), thus avoiding the leakage of plasma from the reaction space 201 to the process chamber 01 as much as possible, so as to avoid damage to other components in the process chamber 01. The channel 221 can be set in the part of the bottom wall 22 near the side wall 23, so that the channel 221 is as far away from the central region of the reaction space 201 as possible, thereby reducing the amount of plasma entering the channel 221.

[0054] With the above setup, before the plasma etching process begins, the exhaust device 50 can evacuate the process chamber 01 and reaction space 201 of the semiconductor device 100 to a vacuum or ultravacuum, minimizing unnecessary residual gas molecules in the reaction space 201 to increase the concentration of plasma input into the reaction space 201. During the plasma etching process, the molecular pump 51 operates continuously, and the pressure in the reaction space 201 can be maintained at the required process level by adjusting the opening of the pressure control valve 52. Furthermore, volatile and gaseous byproducts generated during the plasma etching process can be discharged from the reaction space 201, preventing their accumulation and avoiding interference with the plasma etching process.

[0055] In some embodiments, such as Figure 1 and Figure 2 As shown, a plurality of through slots 221 are evenly and closely distributed circumferentially on the bottom wall 22 of the cavity liner 20, for example, in the form of louvers. In some embodiments, the surface of the cavity liner 20 may be provided with one or more holes (e.g., a first opening 210 and a second opening 220) for connecting the cavity liner 20 and other components.

[0056] In some embodiments, the semiconductor device 100 includes a switch plate 60 and a moving mechanism 70. Both the switch plate 60 and the moving mechanism 70 are disposed within the process chamber 01 of the semiconductor device 100. The switch plate 60 is located on the side of the wafer transfer port 230 facing away from the reaction space 201. The moving mechanism 70 may be located below the switch plate 60 and is connected to the switch plate 60. The moving mechanism 70 is used to drive the switch plate 60 to cover or expose the wafer transfer port 230. The moving mechanism 70 may include a drive motor or a drive piston. With this configuration, when the moving mechanism 70 drives the switch plate 60 to expose the wafer transfer port 230, the wafer can enter the reaction space 201 through the wafer transfer port 230. When the moving mechanism 70 drives the switch plate 60 to cover the wafer transfer port 230, the switch plate 60 can block the wafer transfer port 230, preventing plasma from leaking from the reaction space 201 into the process chamber 01 through the wafer transfer port 230, thus avoiding damage to other components within the process chamber 01.

[0057] In one implementation of the above embodiments, refer to Figure 1 , Figure 3 and Figure 4 , Figure 3 exist Figure 1 The observation direction is from top to bottom. Figure 4 exist Figure 1The observation direction is from right to left. The switch plate 60 includes a silicon plate 61. The material of the silicon plate 61 is silicon or a silicide other than metal silicides, rather than a material with a yttrium oxide coating. This avoids the presence of metal elements during semiconductor processing and improves the quality of the semiconductor process. Simultaneously, when the switch plate 60 covers the wafer transfer port 230, the orthogonal projection of the wafer transfer port 230 onto the silicon plate 61 is located inside the silicon plate 61, and the moving mechanism 70 is directly connected to the silicon plate 61. Through this arrangement, the silicon switch plate 60 can be prevented from being etched by plasma, thus sealing the wafer transfer port 230 during the process and preventing plasma leakage from the reaction space 201.

[0058] In another implementation of the above embodiments, refer to Figure 1 , Figure 5 and Figure 6 , Figure 5 exist Figure 1 The observation direction is from top to bottom. Figure 6 exist Figure 1 The observation direction is from right to left. The switch plate 60 includes a silicon plate 61 and a receiving frame 62. The receiving frame 62 surrounds the silicon plate 61 and exposes a portion of the silicon plate 61. The silicon plate 61 is located on the side of the receiving frame 62 facing the wafer transfer port 230. When the moving mechanism 70 drives the switch plate 60 to move to the position that covers the wafer transfer port 230, the exposed portion of the silicon plate 61 covers the wafer transfer port 230. Similarly, the size of the silicon plate 61 is larger than the size of the wafer transfer port 230. The orthographic projection of the wafer transfer port 230 on the silicon plate 61 is located inside the silicon plate 61. This can also prevent the silicon switch plate 60 from being etched by plasma, so that the switch plate 60 can block the wafer transfer port 230 during the process and prevent plasma from leaking out of the reaction space 201.

[0059] Furthermore, the moving mechanism 70 is connected to the receiving frame 62 and indirectly connected to the silicon plate 61 disposed on the receiving frame 62, avoiding direct contact between the moving mechanism 70 and the silicon plate 61, which could damage the silicon plate 61. The receiving frame 62 can be made of aluminum alloy, and the silicon plate 61 is embedded within it. The switch plate 60 also includes a buffer pad 63, which fills the space between the silicon plate 61 and the receiving frame 62. The buffer pad 63 is made of flexible material, preventing direct contact between the silicon plate 61 and the receiving frame 62, thus preventing the silicon plate 61 from shaking during lifting and lowering, and also preventing the silicon plate 61 from colliding with the receiving frame 62 or other components and breaking.

[0060] In some embodiments, continue to refer to Figure 1The semiconductor device 100 also includes a chamber assembly comprising the aforementioned chamber liner 20 and a grounding element 80. The grounding element 80 is located within the process chamber 01 and connects the outer surface of the chamber liner 20 to the chamber wall 10, thereby forming a radio frequency path within the process chamber 01. Exemplarily, the chamber wall 10 further includes a grounding platform 14, which is parallel to the bottom chamber wall 12 and connected to the side chamber wall 11. The grounding platform 14 is located on the side of the bottom wall 22 of the chamber liner 20 facing away from the top wall 21. The grounding element 80 is located between the grounding platform 14 and the chamber liner 20. One end of the grounding element 80 is connected to the bottom wall 22 of the chamber liner 20, and the other end is connected to the side of the grounding platform 14 facing the chamber liner 20. The grounding element 80 is arranged around the chuck 31 in a vertical direction so that it can uniformly provide support to the chamber liner 20 in the vertical direction.

[0061] In some embodiments, refer to Figure 1 and Figure 7 The grounding member 80 includes a first connecting portion 81, a second connecting portion 82, and a deformation portion 83. The deformation portion 83 connects the first connecting portion 81 and the second connecting portion 82. The first connecting portion 81 is connected to the cavity liner 20, and the second connecting portion 82 is connected to the grounding platform 14. The deformation portion 83 is used to deform according to the distance between the first connecting portion 81 and the second connecting portion 82. In some embodiments, the cavity liner 20 may be simultaneously subjected to pressure from a rigid component located above it (e.g., a heating element and a top cover) and a grounding member 80 located below it. If a rigid grounding member 80 is used, since both the components located above and below the cavity liner 20 are rigid components, if the distance between the components above the cavity liner 20 and the grounding member 80 below is inappropriate (e.g., less than the height of the cavity liner 20), it can easily affect the stress safety of the cavity liner 20, causing the cavity liner 20 to crack. This application uses a flexible grounding member 80 with a deformation portion 83, which is beneficial to ensuring the stress safety of the cavity liner 20. It should be understood that silicon cavity liners are generally more brittle than aluminum alloy liner materials and are more prone to damage under excessive stress or deformation. Therefore, the use of flexible grounding components is particularly useful for silicon cavity liners. Furthermore, the flexible grounding component 80 helps to compensate for the fit gaps between the cavity liner 20, chuck 31, grounding component 80, and top cover 13, thereby avoiding the problem of loose connections between the cavity liner 20 and the grounding component 80. The deformable part 83 also prevents the entire grounding component 80 from being pulled apart or cracked during deformation.

[0062] For example, the deformable part 83 has a plurality of first grooves 801 on the side facing the chuck 31, and the grounding member 80 has a plurality of second grooves 802 on the side away from the chuck 31. For example, the number of first grooves 801 is greater than or equal to 2, and the number of second grooves 802 is greater than or equal to 2. In the direction in which the top wall 21 and the bottom wall 22 are arranged opposite each other in the cavity liner 20, that is, in the vertical direction, the plurality of first grooves 801 and the plurality of second grooves 802 are alternately spaced. A portion of a first groove 801 is located within two adjacent second grooves 802, and a portion of a second groove is located between two adjacent first grooves 801, so that the deformable part 83 is curved or bent in the arrangement direction of the first connecting part 81 and the second connecting part 82 (that is, in the vertical direction), which facilitates the deformation of the grounding member 80 in the vertical direction. At the same time, the curved or bent deformable part 83 can reduce the heat transfer efficiency of the entire grounding member 80, thereby reducing the heat transferred from the cavity liner 20 to the grounding platform 14 or other components through the grounding member 80.

[0063] In the above embodiments, the grounding component 80 is made of aluminum alloy. The surfaces of the grounding component 80 that contact the cavity liner 20 and the surfaces of the grounding component 80 that contact the grounding platform 14 may be provided with a nickel plating layer or a pure aluminum layer to improve the conductivity of the grounding component 80. Other surfaces of the grounding component 80 may also be provided with a nickel plating layer, a pure aluminum layer, an oxide layer, etc. In embodiments where other surfaces of the grounding component 80 are provided with an oxide layer, the service life of the grounding component 80 can be improved.

[0064] In some embodiments, the semiconductor device 100 further includes an insulating element 90, a portion of which is located between the chuck 31 and the grounding platform 14, and another portion of which is located between the chuck 31 and the grounding element 80. The insulating element 90 may include a first insulating element 91 and a second insulating element 92, which are independent of each other. The first insulating element 91 is located between the chuck 31 and the grounding platform 14, and the second insulating element 92 is located between the chuck 31 and the grounding element 80. Through this arrangement, insulation can be achieved between the chuck 31 and the grounding platform 14, and also between the chuck 31 and the grounding element 80, thereby forming a radio frequency path within the process chamber 01.

[0065] In some embodiments, continue to refer to Figure 1 The semiconductor device 100 also includes a gas equalization disk 33, which is located inside the first opening 210. The gas equalization disk 33 is used to connect to the gas supply system. The gas equalization disk 33 is provided with multiple channels, which form multiple gas supply ports evenly arranged on the side of the gas equalization disk 33 facing the reaction space 201. The process gas is evenly distributed in the reaction space 201 through the multiple gas supply ports of the gas equalization disk 33, which facilitates the uniform distribution of plasma in the reaction space 201.

[0066] In some embodiments, the semiconductor device 100 further includes a temperature control device 40, which is located on the side of the gas distribution plate 33 away from the reaction space 201. In embodiments where the gas distribution plate 33 is connected to the gas supply system, the temperature control device 40 is located between the gas distribution plate 33 and the gas supply system. The process gas first passes through the temperature control device 40 to adjust its temperature and then passes through the gas distribution plate 33 to enter the reaction space 201, so that the plasma entering the reaction space 201 has an initial temperature.

[0067] In the above embodiment, the temperature control device 40 includes a heating plate 41 and a water-cooling plate 42, which are arranged on one side in the direction of process gas input. The heating plate 41 is located between the water-cooling plate 42 and the gas distribution plate 33, and the water-cooling plate 42 covers the heating plate 41 and the upper cover 13 of the semiconductor device 100. The heating plate 41 is used to heat the process gas, and the water-cooling plate 42 is used to cool the process gas and also to prevent heat leakage from the inside of the semiconductor device 100.

[0068] In the above embodiments, the temperature control device 40 further includes a heating element 43, which is disposed adjacent to the inner lining 20 of the cavity and is used to heat the inner lining 20 of the cavity. For example, the heating element 43 is annular, and the heating element 43 and the heating plate 41 are disposed on the same side of the inner lining 20 of the cavity, with the annular heating element 43 surrounding the heating plate 41.

[0069] The foregoing preferred embodiments have further illustrated the objectives, technical solutions, and advantages of the present invention. It should be understood that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A cavity liner, characterized in that, The entire material of the cavity lining is silicon or silicides other than metal silicides; The cavity liner includes a top wall and a bottom wall disposed opposite to each other, and a side wall connecting the top wall and the bottom wall. The top wall encloses a first opening, which is a gas inlet. The bottom wall encloses a second opening.

2. The cavity liner according to claim 1, characterized in that, The material of the cavity lining is silicon or silicon carbide.

3. The cavity liner according to claim 1 or 2, characterized in that, The volume resistivity of the material lining the cavity is <100Ω·cm.

4. The cavity liner according to any one of claims 1 to 3, characterized in that, The cavity liner is integrally molded.

5. The cavity liner according to any one of claims 1-4, characterized in that, The bottom wall has multiple through grooves that penetrate the bottom wall in the thickness direction; the ratio of the depth of the through groove to the width of the through groove opening is greater than or equal to 2.

5.

6. A chamber kit, characterized in that, include: The cavity liner as described in any one of claims 1-5; as well as A grounding element, which is connected to the cavity liner as described in any one of claims 1-5.

7. The chamber assembly according to claim 6, characterized in that, The grounding component includes a first connecting part, a deformable part, and a second connecting part. The deformable part connects the first connecting part and the second connecting part. The first connecting part is connected to the cavity liner, and the second connecting part is used to connect to the grounding platform. The deformable part is used to deform according to the distance between the first connecting part and the second connecting part.

8. The chamber assembly according to claim 7, characterized in that, The deformable part is curved or bent in the vertical direction.

9. A semiconductor device, characterized in that, Includes the chamber liner as described in any one of claims 1-5; and A chuck is located within the second opening, and the chuck and the chamber liner enclose a reaction space.

10. The semiconductor device according to claim 9, characterized in that, The semiconductor device further includes a cavity wall and a grounding element. The cavity wall encloses a process chamber, and the cavity liner is located inside the process chamber. The grounding element connects the cavity liner and the cavity wall.

11. The semiconductor device according to claim 10, characterized in that, The cavity wall includes a grounding platform, and the grounding component includes a first connecting part, a deformable part, and a second connecting part. The deformable part connects the first connecting part and the second connecting part. The first connecting part is connected to the cavity lining, and the second connecting part is connected to the grounding platform. The deformable part is used to deform according to the distance between the first connecting part and the second connecting part.

12. The semiconductor device according to claim 11, characterized in that, The deformable part is curved or bent in the vertical direction.

13. The semiconductor device according to any one of claims 9-12, characterized in that, A wafer transfer port is provided on the side wall; the semiconductor device also includes a switch board and a moving mechanism. The switch board is located on the side of the wafer transfer port away from the reaction space. The moving mechanism is connected to the switch board and is used to drive the switch board to cover or expose the wafer transfer port.

14. The semiconductor device according to claim 13, characterized in that, The switch board includes a silicon plate, the material of which is silicon or a silicide other than metal silicide. When the switch board covers the wafer transfer port, the orthogonal projection of the wafer transfer port onto the silicon plate is located inside the silicon plate.

15. The semiconductor device according to claim 13 or 14, characterized in that, The switch board further includes a receiving frame that surrounds the silicon substrate and exposes a portion of the silicon substrate. The moving mechanism is connected to the receiving frame, and when the moving mechanism drives the switch board to move to a position that covers the wafer transfer port, the exposed portion of the silicon substrate covers the wafer transfer port.

16. The semiconductor device according to any one of claims 13-15, characterized in that, The switchboard also includes a buffer pad that fills the space between the receiving frame and the silicon plate.

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