A charging pile and a control method thereof

Abstract

The application discloses a charging pile and a control method thereof, relates to the technical field of direct-current charging, and the charging pile comprises a three-phase parallel resonant converter, a controller and a relay control circuit, the three-phase parallel resonant converter is connected with the controller and the relay control circuit respectively, the three-phase parallel resonant converter comprises three-phase independent and same-structure conversion units, each-phase conversion unit comprises an input rectifier bridge, a resonant circuit, an isolation transformer and a rectifier circuit which are connected in sequence, the resonant circuit comprises a choke coil, a switch tube, a shunt capacitor, a resonant capacitor and a resonant coil, the rectifier circuit comprises a rectifier capacitor, a diode, a filter capacitor, a first filter coil and a second filter coil, the controller is used for performing soft start control on output voltage and output current in a starting stage, controlling the series-parallel connection state of the relay control circuit, and performing input side and output side regulation and control and driving wave control in a running stage. The application has the effects of high power density, small volume and simple control.

Description

Technical Field

[0001] This application relates to the field of DC charging technology, and in particular to a charging pile and its control method. Background Technology

[0002] In traditional power electronic converters, especially in high-power applications, the converters typically employ a multi-stage topology, such as a combination of a PFC (Power Factor Correction) stage and a DC-DC conversion stage. This multi-stage structure suffers from drawbacks such as large system size, high control complexity, and significant efficiency losses, which does not meet the requirements of many current applications, such as electric vehicle charging and distributed generation. Therefore, there is an urgent need to provide a converter with high power density, small size, and simple control. Summary of the Invention

[0003] In view of the above-mentioned defects or deficiencies in the related technologies, the purpose of this application is to provide a charging pile and its control method, which can construct a three-phase parallel resonant converter based on the Class E topology, and has the effects of high power density, small size and simple control.

[0004] To achieve the above objectives, this application provides the following solution:

[0005] In a first aspect, this application provides a charging pile, which includes a three-phase parallel resonant converter, a controller, and a relay control circuit. The three-phase parallel resonant converter is connected to the controller and the relay control circuit respectively. The three-phase parallel resonant converter includes three independent and identically structured conversion units. Each conversion unit includes an input rectifier bridge, a resonant circuit, an isolation transformer, and a rectifier circuit connected in sequence. The resonant circuit includes a choke coil, a switching transistor, a shunt capacitor, a resonant capacitor, and a resonant coil. The rectifier circuit includes a rectifier capacitor, a diode, a filter capacitor, a first filter coil, and a second filter coil. The controller is used to: initialize parameters and perform soft-start control of the output voltage and output current of the outer loop within a preset range during the startup phase, and to perform series-parallel switching control of the relay control circuit; and to perform input-side and output-side regulation and drive wave generation control during the operation phase. The input side includes the input rectifier bridge, the resonant circuit, and the primary circuit of the transformer. The output side includes the secondary circuit of the isolation transformer, the rectifier circuit, and a load connected to the rectifier circuit.

[0006] Optionally, the input rectifier bridges of the three-phase conversion units are respectively connected to the three-phase input voltages. The output terminal of each phase input rectifier bridge is connected to one end of the corresponding choke coil, and the other end of the choke coil is connected to the drain of the switching transistor, one end of the shunt capacitor, and one end of the resonant capacitor, respectively. The source of the switching transistor is grounded, the other end of the shunt capacitor is grounded, the other end of the resonant capacitor is connected to one end of the resonant coil, and the other end of the resonant coil is connected to the primary winding of the isolation transformer.

[0007] Optionally, the secondary windings of the isolation transformer are respectively connected to the corresponding rectifier circuits. In each phase rectifier circuit, the two ends of the secondary winding are respectively connected to the two ends of the rectifier capacitor and the anode of the diode. The cathode of the diode passes through the first filter coil and the second filter coil in sequence and is connected in parallel with the filter capacitor to form the output terminal.

[0008] Optionally, the input rectifier bridge is a bridge rectifier circuit composed of four diodes. Its AC input terminal is connected to the three-phase input voltage, and its DC output terminal is connected to the drain of the switching transistor. Half-wave control is achieved through the combination of the rectifier bridge and the switching transistor, so that the positive and negative half-cycle currents flow through the same switching transistor. The secondary windings of the isolation transformer are connected in series or in parallel through relays or switching circuits. When the output voltage needs to be widened, the output voltage amplitude is adjusted by switching the connection mode of the dual windings.

[0009] Optionally, the resonant circuit parameters of each phase conversion unit are consistent, including the inductance value of the choke coil, the capacitance value of the resonant capacitor, the inductance value of the resonant coil, and the model parameters of the switching transistor, so as to ensure the consistency of the three-phase output current.

[0010] Secondly, this application provides a control method for a charging pile. The controller described above is the execution subject of the method. The method includes: in the startup phase, initializing parameters and performing soft-start control on the output voltage and output current of the outer loop within a preset range, and performing series-parallel switching control on the relay control circuit; in the operation phase, performing input-side and output-side regulation and drive wave generation control; the input side includes the input rectifier bridge, resonant circuit, and primary circuit of the transformer; the output side includes the secondary circuit of the isolation transformer, rectifier circuit, and load connected to the rectifier circuit.

[0011] Optionally, the soft-start control of the output voltage and output current of the outer loop within the preset range includes: controlling the soft start of the output voltage by: if the output voltage setpoint is less than the preset output voltage value, increasing the output voltage setpoint by a preset soft-start growth rate; if the output voltage setpoint is greater than the preset output voltage value, decreasing the output voltage setpoint by a preset soft-start decay rate; simultaneously determining whether the output voltage setpoint exceeds the voltage safety value, and if it does, forcibly decreasing it by an emergency decay rate to limit the output voltage setpoint between the minimum and maximum allowable output voltage values; controlling the soft start of the output current by: if the output current setpoint is less than the preset output current value, increasing the output current setpoint by a preset soft-start growth rate; if the output current setpoint is greater than the preset output current value, decreasing the output current setpoint by a preset soft-start decay rate; simultaneously determining whether the output current setpoint exceeds the current safety value, and if it does, forcibly decreasing it by an emergency decay rate to limit the output current setpoint between the minimum and maximum allowable output current values.

[0012] Optionally, the series-parallel switching control of the relay control circuit includes: in each cycle, real-time acquisition of the output voltage sample value, and execution of switching logic based on the series-parallel flag bit, wherein the series-parallel flag bit is 0 or 1; the series-parallel flag bit being 0 indicates that the output voltage is in a parallel state; the series-parallel flag bit being 1 indicates that the output voltage is in a series state; the switching logic includes: in the parallel state, if the output voltage sample value is greater than or equal to a first series-parallel switching threshold, timing is started; if the timing duration is greater than or equal to a preset switching timing threshold, the series-parallel flag bit is set to 1; otherwise, the parallel state is maintained; in the series state, if the output voltage sample value is less than or equal to a second series-parallel switching threshold, timing is started; if the timing duration is greater than or equal to a preset switching timing threshold, the series-parallel flag bit is set to 0; otherwise, it is determined whether the output voltage setpoint is less than or equal to the second series-parallel switching threshold; if so, the series-parallel flag bit is set to 0; otherwise, the series state is maintained.

[0013] Optionally, the execution of input-side and output-side control includes: real-time acquisition of the output voltage and output current of the outer loop to obtain output voltage sample values ​​and output current sample values; calculation of the error between the output voltage sample value and the output voltage setpoint, and performing PI algorithm calculation on the voltage error to obtain the PI voltage output value of the voltage outer loop; simultaneously calculating the error between the output current sample value and the output current setpoint, and performing PI algorithm calculation on the current error to obtain the PI current output value of the current outer loop; comparing the magnitudes of the PI voltage output value and the PI current output value, and taking the smaller value as the final output value of the outer loop; real-time acquisition of the input voltage and input current sample values ​​of the three-phase converter unit; extraction of the input voltage phase of the corresponding phase based on the input voltage of the three-phase converter unit; multiplying the input voltage phase of the corresponding phase of the three-phase converter unit with the final output value of the outer loop to obtain the input current setpoint of the corresponding phase; calculating the error between the input current setpoint of the corresponding phase of the three-phase converter unit and the input current sample value, and performing PI algorithm calculation on the current error to obtain the PI output value of the current inner loop of the corresponding phase.

[0014] Optionally, the drive waveform control includes: if the PI output value of the current inner loop of the corresponding phase of the three-phase converter unit is greater than the PFM frequency modulation threshold, then PFM modulation is used, the fixed duty cycle is a preset constant duty cycle, and the frequency changes in the opposite direction to the PI output value; if the PI output value of the current inner loop of the corresponding phase of the three-phase converter unit is less than or equal to the PFM frequency modulation threshold and greater than the PWM frequency modulation threshold, then PWM modulation is used, the fixed frequency is a preset constant frequency, and the duty cycle changes in the positive direction to the PI output value; if the PI output value of the current inner loop of the corresponding phase of the three-phase converter unit is less than or equal to the PWM frequency modulation threshold, then the waveform blocking stage is entered, the duty cycle drive quantity is set to 0, and the switching transistor of the corresponding phase is controlled to be turned off.

[0015] Optionally, the method further includes: when the sampled output voltage value is greater than the given output voltage value and the sampled input current value is less than the given input current value, the outer current loop is saturated, and the PI voltage output value is used as the control reference to operate in constant voltage mode; when the sampled input current value is greater than the given input current value and the sampled output voltage value is less than the given output voltage value, the outer voltage loop is saturated, and the PI current output value is used as the control reference to operate in constant current mode.

[0016] According to the specific embodiments provided in this application, the following technical effects are disclosed:

[0017] This application provides a charging pile and its control method. A three-phase parallel resonant converter is constructed using a Class E topology. During startup, soft-start control of the output voltage and current of the outer loop can, to some extent, prevent sudden changes in output voltage / current that could damage the load (such as the battery) or hardware. By controlling the series-parallel switching of the relay control circuit, the output range can be broadened to adapt to different load voltage requirements without hardware replacement. During operation, by executing input-side and output-side regulation and drive wave generation control, the on / off timing of the switching transistors of the three-phase parallel resonant converter can be precisely adjusted, achieving zero-voltage conduction under all operating conditions. This effectively matches the resonant frequency, reduces switching losses, and improves energy conversion efficiency. Furthermore, the Class E topology three-phase parallel resonant converter used in this application requires no additional filtering or complex topology, has fewer components, is smaller than traditional multi-stage converters, and has a wider output range suitable for high power density scenarios. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of the structure of a three-phase parallel resonant converter for a charging pile provided in one embodiment of this application;

[0020] Figure 2 A flowchart illustrating a control method for a charging pile according to an embodiment of this application;

[0021] Figure 3 A schematic diagram of the series-parallel switching process provided in an embodiment of this application;

[0022] Figure 4 A flowchart of soft-start control of output voltage and output current provided in an embodiment of this application;

[0023] Figure 5 A schematic diagram of the inner and outer loop control, dual-loop competition control, and half-wave control provided in an embodiment of this application;

[0024] Figure 6 A diagram showing the effective values ​​of the three output currents provided in one embodiment of this application;

[0025] Figure 7 This is a schematic flowchart of a drive wave generation control provided in an embodiment of this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] In one exemplary embodiment, the charging pile provided in this application includes a three-phase parallel resonant converter, a controller, and a relay control circuit, wherein the three-phase parallel resonant converter is connected to the controller and the relay control circuit respectively; as Figure 1 As shown, the three-phase parallel resonant converter includes three independent and identically structured conversion units. Specifically, the three-phase conversion units are A-phase conversion unit 10, B-phase conversion unit 20, and C-phase conversion unit 30. A-phase conversion unit 10 includes an input rectifier bridge BRG1, a resonant circuit 10, an isolation transformer Tr1, and an A-phase rectifier circuit connected in sequence. The resonant circuit 10 includes a choke coil Lp1, a switching transistor MOS1, a shunt capacitor Cs1, a resonant capacitor Cr1, and a resonant coil Lr1. The A-phase rectifier circuit includes rectifier capacitors Cr2 and Cr3, diodes D1 and D2, filter capacitors Cd1 and Cd2, a first filter coil Ls1, and a second filter coil Ls2. The B-phase conversion unit 20 includes an input rectifier bridge BRG2, a resonant circuit 20, an isolation transformer Tr2, and a B-phase rectifier circuit connected in sequence. The resonant circuit 20 includes a choke coil Lp2, a switching transistor MOS2, a shunt capacitor Cs2, a resonant capacitor Cr4, and a resonant coil Lr2. The B-phase rectifier circuit includes rectifier capacitors Cr5 and Cr6, diodes D3 and D4, filter capacitors Cd3 and Cd4, a first filter coil Ls3, and a second filter coil Ls4. The C-phase conversion unit 30 includes an input rectifier bridge BRG3, a resonant circuit 30, an isolation transformer Tr3, and a C-phase rectifier circuit connected in sequence. The resonant circuit 30 includes a choke coil Lp3, a switching transistor MOS3, a shunt capacitor Cs3, a resonant capacitor Cr7, and a resonant coil Lr3. The C-phase rectifier circuit includes rectifier capacitors Cr8 and Cr9, diodes D5 and D6, filter capacitors Cd5 and Cd6, a first filter coil Ls5, and a second filter coil Ls6. The relay control circuit 40 includes relay S1, relay S2 and relay S3.

[0029] In this three-phase converter unit, each phase's input rectifier bridge and switching transistors combine to form a half-wave control circuit, replacing the traditional dual-switching transistor control structure. The secondary side of each phase isolation transformer employs a dual-winding design. The controller is used for: initializing parameters and performing soft-start control of the output voltage and current of the outer loop within a preset range during startup; and executing input-side and output-side regulation and drive wave generation control during operation. The input side includes the input rectifier bridge, resonant circuit, and the primary circuit of the transformer. The output side includes the secondary circuit of the isolation transformer, rectifier circuit, and load connected to the rectifier circuit. It also performs series-parallel switching control of the relay control circuit.

[0030] It should be noted that this application involves a PI algorithm when performing input-side and output-side control. The PI algorithm, short for Proportional-Integral (PI) control algorithm, is the most classic and commonly used closed-loop control algorithm in the field of automatic control. Its core function is to output a precise control quantity through dual calculation of current deviation and historical deviation, allowing the system to quickly and stably approach the target value (without steady-state error). The output of the PI algorithm is composed of the superposition of a "proportional term (P)" and an "integral term (I)". For example, the PI algorithm quickly converges the error (P term) and eliminates the steady-state error (I term), ensuring that the turn-on / turn-off time of the switching transistor is precisely matched with the resonant frequency, ensuring that the switching transistor is turned on only when the voltage drops to 0, achieving ZVS under all operating conditions and reducing switching losses.

[0031] In one specific embodiment, each phase input rectifier bridge of the three-phase converter unit is connected to the input voltage of the corresponding phase. The output terminal of each phase input rectifier bridge is connected to one end of the corresponding choke coil. The other end of the choke coil is connected to the drain of the switching transistor, one end of the shunt capacitor, and one end of the resonant capacitor. The source of the switching transistor is grounded, the other end of the shunt capacitor is grounded, and the other end of the resonant capacitor is connected to one end of the resonant coil. The other end of the resonant coil is connected to the primary winding of the isolation transformer. The secondary windings of the isolation transformer are connected to the corresponding rectifier circuits. In each phase rectifier circuit, the two ends of the secondary winding are connected to the two ends of the rectifier capacitor and the anode of the diode. The cathode of the diode is connected in parallel with the filter capacitor after passing through the first filter coil and the second filter coil to form the output terminal.

[0032] It should be noted that the resonant circuit parameters of each phase conversion unit are consistent, including the inductance value of the choke coil, the capacitance value of the resonant capacitor, the inductance value of the resonant coil, and the model parameters of the switching transistor, to ensure the consistency of the three-phase output current.

[0033] In one specific implementation, each phase input rectifier bridge is a bridge rectifier circuit composed of four diodes. Its AC input terminal is connected to the three-phase input voltage, and its DC output terminal is connected to the drain of the switching transistor. Half-wave control is achieved through the combination of the rectifier bridge and the switching transistor, so that the positive and negative half-cycle currents flow through the same switching transistor. The secondary windings of the isolation transformer are connected in series or in parallel through relays or switching circuits. When the output voltage needs to be widened, the output voltage amplitude is adjusted by switching the connection mode of the dual windings.

[0034] It should be noted that the secondary windings of the isolation transformer are connected in either series or parallel mode. The filter capacitors in each phase rectifier circuit are electrolytic capacitors. The first and second filter coils form a π-type filter structure to filter out high-frequency ripple in the output voltage, ensuring its stability.

[0035] This application constructs a three-phase parallel resonant converter using a Class E topology. During startup, soft-start control of the output voltage and current of the outer loop can, to some extent, prevent sudden changes in output voltage / current from damaging the load (such as the battery) or hardware. By controlling the series-parallel switching of the relay control circuit, the output range can be widened to adapt to different load voltage requirements without replacing hardware. During operation, by executing input-side and output-side regulation and drive wave generation control, the on / off timing of the switching transistors of the three-phase parallel resonant converter can be precisely adjusted, achieving zero-voltage conduction under all operating conditions. This effectively matches the resonant frequency, reduces switching losses, and improves energy conversion efficiency. Furthermore, the Class E topology three-phase parallel resonant converter used in this application requires no additional filtering or complex topology, has fewer components, is smaller in size than traditional multi-stage converters, and has a wider output range to adapt to high power density scenarios.

[0036] Based on the same inventive concept, this application also provides a control method for a charging pile applied to the controller in the above embodiments. The solution provided by this method is similar to the solution described in the charging pile above, and will not be repeated here.

[0037] In one exemplary embodiment, such as Figure 2 As shown, a control method for a charging pile is provided. The control method for the charging pile includes the following steps S201 to S202, specifically:

[0038] Step S201: During the startup phase, the parameters are initialized and the output voltage and output current of the outer loop are soft-started within a preset range.

[0039] Step S202: During the operation phase, input-side and output-side regulation and drive wave generation control are performed; the input side includes the input rectifier bridge, resonant circuit, and primary circuit of the transformer; the output side includes the secondary circuit of the isolation transformer, rectifier circuit, and load connected to the rectifier circuit; and series-parallel switching control of the relay control circuit is performed.

[0040] In this embodiment, within each control cycle, the charging pile, the power grid, and the load (such as a vehicle) form inner and outer loops. These loops include an outer loop and an inner loop. The controlled object in the outer loop is... Figure 1 The output voltage across the load RL and the output current through the load RL; sampling points are: Figure 1 At the output of the rectifier circuit, the output voltage sample value Vout and the output current sample value Iout are obtained. The goal of the outer loop control is to make the rectifier diode (such as...) Figure 1 Diodes D1 to D6), filter capacitors (such as...) Figure 1 The output voltage / current of the filter capacitors (Cd1 to Cd6) conforms to the preset values. The control logic of the outer loop control is as follows: by collecting the output voltage sample value Vout and the output current sample value Iout, the output voltage sample value Vout is compared with the output voltage setpoint Vout_ref, and the output current sample value Iout is compared with the output current setpoint Iout_ref, the error is calculated, and the PI voltage output value Pvout and the PI current output value Piout of the current outer loop are obtained by the PI algorithm. Then, the smaller value is taken as the final output value of the outer loop through "dual-loop competition".

[0041] The control object of the inner loop is Figure 1 The current flowing through L1 / L2 / L3 is sampled at the following points: Figure 1 Between the three-phase inputs L1 / L2 / L3 on the left side and the resonant circuit, the input current sampling values ​​of the A-phase conversion unit, the B-phase conversion unit, and the C-phase conversion unit are obtained. To avoid redundancy, in the following embodiments of this application, the input current sampling value of the A-phase conversion unit will be simply referred to as the A-phase input current sampling value, the input current sampling value of the B-phase conversion unit will be simply referred to as the B-phase input current sampling value, and the input current sampling value of the C-phase conversion unit will be simply referred to as the C-phase input current sampling value. Correspondingly, a certain device of a certain phase conversion unit will be simply referred to as a certain phase + device.

[0042] The goal of inner-loop control is to adjust the resonant state of the resonant circuit by controlling the on / off frequency and duty cycle of the switching transistors, thereby stabilizing the input current and ensuring its phase follows the input voltage to improve power quality. Simultaneously, it aims to balance the current in the three-phase converter units, i.e., automatic current sharing. The control logic of inner-loop control is as follows: based on the product of the final output value of the outer loop and the phase of the input voltage of the corresponding phase of the three-phase converter unit, the input current setpoint value for the corresponding phase of the three-phase converter unit is obtained. This is equivalent to dividing the inner loop into A-phase current inner loop, B-phase current inner loop, and C-phase current inner loop. Based on the energy requirements of the A-phase, B-phase, and C-phase current inner loops, combined with the phase of the grid input voltage, the current required by each phase converter unit is determined. Then, based on the error between the input current setpoint value and the sampled input current value of the corresponding phase of the three-phase converter unit, a three-phase independent PI algorithm outputs a control quantity to drive the switching transistors MOS1 to MOS3 to switch on and off, i.e., controlling the switching transistors to use PWM modulation / PFM modulation.

[0043] It should be noted that in the embodiments of this application, the outer loop control, inner loop control, and power topology are combined to form a closed loop, and the energy flow is... Figure 1 The path in the signal flow is: power grid (L1-L3) → inner loop (resonant circuit + switching transistor) → isolation transformer → outer loop (rectifier circuit) → load RL; the signal flow is... Figure 1 The path is as follows: load-side sampling (outer loop) → dual-loop competition → generating the final output value of the outer loop (the reference value of the inner loop) → input-side sampling (inner loop) → PI algorithm adjustment → driving the switching transistor → adjusting the energy flow → load-side sampling (outer loop) → loop.

[0044] The following describes the signal flow of this embodiment using the charging pile's startup and operation phases as examples. It is understood that during the charging pile startup phase, parameters are initialized. Specifically, fixed reference parameters and PI algorithm parameters are loaded, the output voltage setpoint Vout_ref and output current setpoint Iout_ref are initialized to 0, the series-parallel flag is set to 0 by default (corresponding to parallel output status), and the fault alarm flag is initialized to "no fault". The fixed reference parameters include the output voltage preset value Vout_RefSet, the output current preset value Iout_RefSet, the voltage safety value, the current safety value, the minimum allowable output voltage value Vout_Min, the maximum allowable output voltage value Vout_Max, the minimum allowable output current value Iout_Min, the maximum allowable output current value Iout_Max, the first series-parallel switching threshold Value1, the second series-parallel switching threshold Value2, the PWM frequency modulation threshold value, the PFM frequency modulation threshold value, and the preset switching timing threshold. The PI algorithm parameters include voltage loop proportional coefficient Kp_v, voltage loop integral coefficient Ki_v, current loop proportional coefficient Kp_i, and current loop integral coefficient Ki_i, where the voltage loop proportional coefficient Kp_v, voltage loop integral coefficient Ki_v, and current loop integral coefficient Kp_i and Ki_i are preset fixed values.

[0045] It should be noted that the fixed reference parameters in this application embodiment are based on actual production, and this application embodiment does not impose specific limitations.

[0046] Subsequently, soft-start control is implemented for the output voltage / output current. Specifically, the soft-start control for the output voltage includes: if the output voltage setpoint Vout_ref is less than the output voltage preset value Vout_RefSet, the output voltage setpoint Vout_ref is incremented by a preset soft-start increment rate; if the output voltage setpoint Vout_ref is greater than the output voltage preset value Vout_RefSet, the output voltage setpoint Vout_ref is decremented by a preset soft-start decay rate; simultaneously, it is determined whether the output voltage setpoint Vout_ref exceeds the voltage safety value. If it does, it is forcibly decremented by an emergency decay rate to limit the output voltage setpoint Vout_ref to between the minimum allowable output voltage value Vout_Min and the maximum allowable output voltage value Vout_Max.

[0047] Controlling the soft start of the output current includes: if the output current setpoint Iout_ref is less than the output current preset value Iout_RefSet, the output current setpoint Iout_ref is incremented by a preset soft start increment rate; if the output current setpoint Iout_ref is greater than the output current preset value Iout_RefSet, the output current setpoint Iout_ref is decremented by a preset soft start decay rate; simultaneously, it is determined whether the output current setpoint Iout_ref exceeds the current safety value. If it does, it is forcibly decremented by an emergency decay rate, limiting the output current setpoint Iout_ref to between the minimum allowable output current value Iout_Min and the maximum allowable output current value Iout_Max.

[0048] Combination Figure 3 Understandably, when performing soft-start control on the output voltage / output current, it is determined whether the output voltage setpoint Vout_Ref is less than the output voltage preset value Vout_RefSet. If so, the output voltage setpoint Vout_ref is slowly increased; otherwise, the output voltage setpoint Vout_ref is slowly decreased until the output voltage setpoint Vout_ref is the same as the output voltage preset value Vout_RefSet. Finally, the output voltage setpoint Vout_ref is limited to between the minimum allowable output voltage value Vout_Min and the maximum allowable output voltage value Vout_Max.

[0049] Determine whether the output current setpoint Iout_ref is less than the output current preset value Iout_RefSet. If so, slowly increase the output current setpoint Iout_ref; otherwise, slowly decrease the output current setpoint Iout_ref until it is the same as the output current preset value Iout_RefSet. Finally, limit the output current setpoint Iout_ref to between the minimum allowable output current value Iout_Min and the maximum allowable output current value Iout_Max.

[0050] It should be noted that the preset soft start growth rate in this application embodiment is subject to actual application and is not limited in this application embodiment.

[0051] And the series-parallel switching control of the relay control circuit, specifically including:

[0052] In each cycle, the output voltage sample value Vout is acquired in real time, and the switching logic is executed based on the series-parallel flag bit, where the series-parallel flag bit is 0 or 1; a series-parallel flag bit of 0 indicates that the output voltage is in parallel state; a series-parallel flag bit of 1 indicates that the output voltage is in series state.

[0053] The switching logic includes: In parallel mode, if the output voltage sample value Vout is greater than or equal to the first parallel switching threshold Value1, timing is started. If the timing duration is greater than or equal to the preset switching timing threshold, the parallel flag is set to 1; otherwise, the parallel mode is maintained. In series mode, if the output voltage sample value Vout is less than or equal to the second parallel switching threshold Value2, timing is started. If the timing duration is greater than or equal to the preset switching timing threshold, the parallel flag is set to 0; otherwise, it is determined whether the output voltage setpoint Vout_ref is less than or equal to the second parallel switching threshold Value2. If it is, the parallel flag is set to 0; otherwise, the series mode is maintained.

[0054] Combination Figure 4 Understandably, during series-parallel switching control, the relay control circuit defaults to parallel mode. In parallel mode, it checks whether the output voltage sample value Vout is greater than or equal to the first series-parallel switching threshold Value1. If so, it switches to series mode; otherwise, it remains in parallel mode. In series mode, it checks whether the output voltage sample value Vout is less than or equal to the second series-parallel switching threshold Value2. If so, it switches to parallel mode; otherwise, it checks again whether the output voltage setpoint Vout_ref is less than or equal to the second series-parallel switching threshold Value2. If so, it switches to parallel mode; otherwise, it remains in series mode.

[0055] It should be noted that in this embodiment, the startup phase ends and switches to the running phase when all of the following conditions are met simultaneously; otherwise, the startup phase control continues. That is, 1. The output voltage setpoint Vout_ref satisfies: |Vout_ref - VoutRefSet| ≤ preset steady-state voltage threshold, and this state lasts for ≥ preset steady-state holding period; 2. The output current setpoint Iout_ref satisfies: |Iout_ref - Iout_RefSet| ≤ preset steady-state current threshold, and this state lasts for ≥ preset steady-state holding period; 3. The output voltage setpoint Vout_ref is between the minimum allowable output voltage Vout_Min and the maximum allowable output voltage Vout_Max, and the output current setpoint Iout_ref is between the minimum allowable output current Iout_Min and the maximum allowable output current Iout_Max, and no safety threshold alarm is triggered; 4. The series-parallel flag bit is stable, such as no switching occurring for three consecutive control cycles.

[0056] During the operation phase, this includes executing input-side and output-side regulation as well as driving wave generation control, specifically,

[0057] The input-side and output-side control includes: real-time acquisition of the output voltage and output current of the outer loop to obtain the output voltage sample value Vout and the output current sample value Iout; calculation of the error between the output voltage sample value Vout and the output voltage setpoint Vout_ref, and performing PI algorithm calculation on the voltage error to obtain the PI voltage output value of the voltage outer loop; simultaneously calculating the error between the output current sample value Iout and the output current setpoint Iout_ref, and performing PI algorithm calculation on the current error to obtain the PI current output value of the current outer loop; comparing the magnitudes of the PI voltage output value and the PI current output value, and taking the smaller value as the final output value of the outer loop;

[0058] The input voltage and input current sampling values ​​of the three-phase converter unit are collected in real time; the input voltage phase of the corresponding phase is extracted based on the input voltage of the three-phase converter unit; the input voltage phase of the corresponding phase of the three-phase converter unit is multiplied by the final output value of the outer loop to obtain the input current setpoint of the corresponding phase;

[0059] Calculate the error between the input current setpoint and the input current sample value of the corresponding phase of the three-phase converter unit, and use the PI algorithm to calculate the current error to obtain the PI output value of the current inner loop of the corresponding phase.

[0060] Combination Figure 5 Understandably, the outer loop control uses dual-loop competition, while the inner loop control uses half-wave control. In the outer loop control, the output voltage sampling value Vout and the output current sampling value Iout of the outer loop are first determined. The output voltage sampling value Vout is obtained by the soft-start control of the output voltage of the voltage outer loop, and the output current sampling value Iout is obtained by the soft-start control of the output current of the current outer loop.

[0061] Next, the error between the output voltage sample value Vout and the output voltage setpoint Vout_ref is calculated to obtain the voltage error. A PI algorithm is then applied to the voltage error to obtain the PI voltage output value of the outer voltage loop. Simultaneously, the error between the output current sample value Iout and the output current setpoint Iout_ref is calculated to obtain the current error. A PI algorithm is then applied to the current error to obtain the PI current output value of the outer current loop. The transfer function of the PI algorithm Gs_pi(VdcLoopErr) is Kp + Ki / s, where Kp is the proportional coefficient, Ki is the integral coefficient, and s is the input parameter for the PI closed-loop control. The PI voltage output value and the PI current output value are compared, and the smaller value is used as the final output value of the outer loop, while the larger value remains unchanged and is not controlled.

[0062] In the inner loop control, taking the A-phase current inner loop as an example, the input current sampling value of the A-phase current inner loop is determined by the final output value of the outer loop control and the input voltage of the A-phase current inner loop. The final output value of the outer loop determines the amplitude of the input current sampling value, and the input voltage determines the phase of the input voltage of the A-phase current inner loop. The input current setpoint of the A-phase current inner loop is obtained by multiplying the final output value of the outer loop by the input voltage phase. Then, the error between the input current setpoint and the input current sampling value of the A-phase current inner loop is calculated, and the PI algorithm is used to calculate the PI output value of the A-phase current inner loop. The control logic of the B-phase and C-phase current inner loops is the same as that of the A-phase current inner loop, and will not be described again in this embodiment.

[0063] It should be noted that, in this embodiment, the input voltage phases of the A-phase current inner loop, the B-phase current inner loop, and the C-phase current inner loop all use absolute values, thus converting the sine wave into a swirl wave. Furthermore, the input current sampling values ​​of the A-phase current inner loop, the B-phase current inner loop, and the C-phase current inner loop, after passing through the corresponding phase rectifier bridges, are all converted from sine waves to swirl waves.

[0064] Furthermore, the inner loop control, after half-wave control, ensures consistent positive and negative half-cycle waveform generation, simplifying the subsequent drive waveform generation algorithm. The outer loop control stabilizes the output voltage and current at the required levels by real-time acquisition of output voltage and current, thereby controlling the output power. The inner loop control adjusts the power factor by having the input current of the corresponding phase follow the fluctuations of the input voltage of the corresponding phase. Since the amplitude of the input current setpoint for each phase is determined by the final output value of the outer loop, the input current setpoints of the three-phase current inner loop are equal after the three-phase current inner loop stabilizes. When the input current setpoints of the three-phase current inner loop are equal, the PI output values ​​of the three-phase current inner loop are also equal because the turns ratio of the resonant transformer is the same, thus achieving automatic current sharing.

[0065] The simulation examines the impact of hardware parameters at their maximum absolute error on the PI output value. Specifically, it modifies the resonant inductance of the three-phase converter unit to 0.8, 1, and 1.2 times the original set parameters, and observes the changes in the resonant secondary current of the three-phase converter unit. The results are as follows: Figure 6 As shown, after outer loop control and inner loop control, PI output values ​​Value11, Value12, and Value13 are obtained respectively. Among them, the magnitudes of PI output values ​​Value11, Value12, and Value13 are almost equal, realizing the automatic current sharing function.

[0066] The drive waveform control includes: if the PI output value of the corresponding phase's current inner loop of the three-phase converter unit is greater than the PFM frequency modulation threshold, then PFM modulation is used, with a fixed duty cycle of a preset constant duty cycle D_Fix, and the frequency changes inversely with the PI output value (e.g., the larger the output value, the smaller the frequency); if the PI output value of the corresponding phase's current inner loop of the three-phase converter unit is greater than or equal to the PFM frequency modulation threshold and greater than the PWM frequency modulation threshold, then PWM modulation is used, with a fixed frequency of a preset constant frequency f_Fix, and the duty cycle changes in the positive direction with the PI output value (e.g., the larger the output value, the larger the duty cycle); if the PI output value of the corresponding phase's current inner loop of the three-phase converter unit is less than or equal to the PWM frequency modulation threshold, then the waveform blocking stage is entered, the duty cycle drive is set to 0, and the switching transistors of the corresponding phase (e.g., ...) are controlled. Figure 1 The MOS1 / MOS2 / MOS3 in the circuit are disconnected.

[0067] Combination Figure 7 Taking the A-phase current inner loop as an example, the A-phase switch is controlled based on the PI output value of the A-phase current inner loop. It is determined whether the PI output value is greater than the PFM modulation threshold. If so, the A-phase switch is modulated using PFM modulation, with a fixed drive duty cycle D_Fix, and the switch's on / off state is controlled by adjusting the drive frequency. Otherwise, it is determined whether the PI output value is greater than the PWM modulation threshold. If so, the A-phase switch is modulated using PWM modulation, with a fixed drive frequency f_Fix, and the switch's on / off state is controlled by adjusting the drive duty cycle. Otherwise, the A-phase switch is modulated using a waveform blocking mode, with a fixed drive frequency at its maximum value and a fixed drive duty cycle of 0. The control logic for the B-phase and C-phase switches is the same as that for the A-phase switch, and will not be repeated in this embodiment.

[0068] It should be noted that the wave blocking mode in this application is that the duty cycle drive quantity of all switching transistors is set to 0. The wave blocking mode is the fault state of the charging pile in this application embodiment. The fault triggering conditions of this application include: real-time monitoring of the following states during the operation phase, if any condition is met, it is determined to be a fault, a fault alarm flag is set as "fault", and wave blocking is immediately executed, that is:

[0069] 1. Output voltage sample value Vout > voltage safety value or output voltage sample value Vout < output voltage minimum allowable value Vout_Min, and the duration is ≥ preset fault judgment period; 2. Output current sample value Iout > current safety value or output current sample value Iout < output current minimum allowable value Iout_Min, and the duration is ≥ preset fault judgment period; 3. The maximum difference of the input current sample value of the three-phase conversion unit > three-phase current imbalance threshold, and the duration is ≥ preset fault judgment period; the switching transistor temperature sample value > switching transistor over-temperature threshold; 4. The series-parallel flag bit switches 2 or more times within 1 control cycle (state jitter fault).

[0070] In other embodiments, after a fault occurs, the method further includes: maintaining the fault alarm flag, recording the fault type and operating parameters at the time of occurrence (such as the output voltage sample value Vout, the output current sample value Iout, the input current sample value of the three-phase converter unit, and the switching transistor temperature); resetting the output voltage setpoint Vout_ref and the output current setpoint Iout_ref to 0, and restoring the series-parallel flag to the default value 0 (parallel state); clearing the original steady-state determination result, re-entering the startup phase, and executing soft-start control and phase switching determination; if the same type of fault is triggered three times consecutively after restarting, locking the three-phase parallel resonant converter, stopping the waveform generation and maintaining the fault alarm, requiring manual reset before restarting.

[0071] In addition, the method may also include: when the output voltage sample value Vout is greater than the output voltage setpoint Vout_ref and the input current sample value is less than the input current setpoint, the outer current loop is saturated, and the PI voltage output value is used as the control reference to operate in constant voltage mode; when the input current sample value is greater than the input current setpoint and the output voltage sample value Vout is less than the output voltage setpoint Vout_ref, the outer voltage loop is saturated, and the PI current output value is used as the control reference to operate in constant current mode.

[0072] In implementing this method, in terms of hardware cost, traditional converters use two switches to control the positive and negative half-cycles separately. The three-phase parallel resonant converter provided in this application uses a combination of a rectifier bridge and a switch to control the circuit, reducing hardware costs. In terms of software control, the control method is changed from separate control of the positive and negative half-cycles to half-wave control, simplifying the software control algorithm. Furthermore, due to the characteristics of Class E, the traditional structure using two switches leads to inconsistent current magnitudes flowing through the switches during the positive and negative half-cycles, resulting in uneven temperature distribution between the two switches, with one switch having a higher temperature than the other. However, the embodiment of this application uses a single switch in conjunction with a rectifier bridge, ensuring that the current always flows through the same switch, avoiding temperature differences caused by changes in current direction, thereby effectively reducing the average operating temperature of the switch. In addition, the transformer secondary side adopts a dual-winding structure, which can widen the output voltage adjustment range and improve the circuit's adaptability and output flexibility. This design not only optimizes thermal management but also enhances the circuit's output capability and stability.

[0073] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A charging pile, characterized in that, The charging pile includes a three-phase parallel resonant converter, a controller, and a relay control circuit. The three-phase parallel resonant converter is connected to the controller and the relay control circuit, respectively. The three-phase parallel resonant converter includes three independent and identical conversion units; each conversion unit includes an input rectifier bridge, a resonant circuit, an isolation transformer, and a rectifier circuit connected in sequence; the resonant circuit includes a choke coil, a switching transistor, a shunt capacitor, a resonant capacitor, and a resonant coil; the rectifier circuit includes a rectifier capacitor, a diode, a filter capacitor, a first filter coil, and a second filter coil. The controller is used for: during the startup phase, initializing parameters and performing soft-start control of the output voltage and output current of the outer loop within a preset range, as well as performing series-parallel switching control of the relay control circuit; during the operation phase, performing input-side and output-side regulation and drive wave generation control; the input side includes the input rectifier bridge, resonant circuit, and primary circuit of the transformer; the output side includes the secondary circuit of the isolation transformer, rectifier circuit, and load connected to the rectifier circuit; The series-parallel switching control of the relay control circuit includes: Within each cycle, the output voltage sample value is acquired in real time, and switching logic is executed based on the series-parallel flag bit, wherein the series-parallel flag bit is 0 or 1; the series-parallel flag bit being 0 indicates that the output voltage is in parallel state; the series-parallel flag bit being 1 indicates that the output voltage is in series state. The switching logic includes: in parallel mode, if the output voltage sample value is greater than or equal to the first parallel switching threshold, timing is started; if the timing duration is greater than or equal to the preset switching timing threshold, the parallel flag is set to 1; otherwise, the parallel mode is maintained. In series mode, if the output voltage sample value is less than or equal to the second parallel switching threshold, timing is started; if the timing duration is greater than or equal to the preset switching timing threshold, the parallel flag is set to 0; otherwise, it is determined whether the output voltage setpoint is less than or equal to the second parallel switching threshold. If it is, the parallel flag is set to 0; otherwise, the series mode is maintained. The output voltage setpoint is a parameter dynamically set by the controller according to the preset output voltage value. The preset output voltage value is a pre-set fixed reference parameter.

2. The charging pile according to claim 1, characterized in that, The input rectifier bridges of the three-phase conversion unit are respectively connected to the three-phase input voltages. The output terminal of each phase input rectifier bridge is connected to one end of the corresponding choke coil, and the other end of the choke coil is connected to the drain of the switching transistor, one end of the shunt capacitor, and one end of the resonant capacitor. The source of the switching transistor is grounded, the other end of the shunt capacitor is grounded, the other end of the resonant capacitor is connected to one end of the resonant coil, and the other end of the resonant coil is connected to the primary winding of the isolation transformer. The secondary windings of the isolation transformer are respectively connected to the corresponding rectifier circuits. In each phase rectifier circuit, the two ends of the secondary winding are respectively connected to the two ends of the rectifier capacitor and the anode of the diode. The cathode of the diode passes through the first filter coil and the second filter coil in sequence and is connected in parallel with the filter capacitor to form the output terminal.

3. The charging pile according to claim 2, characterized in that, The input rectifier bridge is a bridge rectifier circuit composed of four diodes. Its AC input terminal is connected to the three-phase input voltage, and its DC output terminal is connected to the drain of the switching transistor. Half-wave control is achieved through the combination of the rectifier bridge and the switching transistor, so that the positive and negative half-cycle currents flow through the same switching transistor. The secondary windings of the isolation transformer are connected in series or in parallel through relays or switching circuits. When the output voltage needs to be widened, the output voltage amplitude is adjusted by switching the connection mode of the dual windings.

4. The charging pile according to claim 3, characterized in that, The resonant circuit parameters of each phase conversion unit are consistent, including the inductance value of the choke coil, the capacitance value of the resonant capacitor, the inductance value of the resonant coil, and the model parameters of the switching transistor, to ensure the consistency of the three-phase output current.

5. A control method for a charging pile, wherein the executing entity of the method is the controller described in claims 1-4, characterized in that, The method includes: During the startup phase, the parameters are initialized and soft-start control is performed on the output voltage and output current of the outer loop within the preset range, as well as series-parallel switching control is performed on the relay control circuit. During operation, input-side and output-side regulation and drive wave generation control are performed; the input side includes the input rectifier bridge, resonant circuit, and primary circuit of the transformer; the output side includes the secondary circuit of the isolation transformer, rectifier circuit, and load connected to the rectifier circuit; wherein, the series-parallel switching control of the relay control circuit includes: Within each cycle, the output voltage sample value is acquired in real time, and switching logic is executed based on the series-parallel flag bit, wherein the series-parallel flag bit is 0 or 1; the series-parallel flag bit being 0 indicates that the output voltage is in parallel state; the series-parallel flag bit being 1 indicates that the output voltage is in series state. The switching logic includes: in parallel mode, if the output voltage sample value is greater than or equal to the first parallel switching threshold, timing is started; if the timing duration is greater than or equal to the preset switching timing threshold, the parallel flag is set to 1; otherwise, the parallel mode is maintained. In series mode, if the output voltage sample value is less than or equal to the second parallel switching threshold, timing is started; if the timing duration is greater than or equal to the preset switching timing threshold, the parallel flag is set to 0; otherwise, it is determined whether the output voltage setpoint is less than or equal to the second parallel switching threshold. If it is, the parallel flag is set to 0; otherwise, the series mode is maintained. The output voltage setpoint is a parameter dynamically set by the controller according to the preset output voltage value. The preset output voltage value is a pre-set fixed reference parameter.

6. The control method for a charging pile according to claim 5, characterized in that, The preset range includes soft-start control of the output voltage and output current of the outer loop, including: Controlling the soft start of the output voltage includes: if the output voltage setpoint is less than the output voltage preset value, automatically increasing the output voltage setpoint at a preset soft start growth rate; if the output voltage setpoint is greater than the output voltage preset value, automatically decreasing the output voltage setpoint at a preset soft start decay rate; simultaneously determining whether the output voltage setpoint exceeds the voltage safety value, and if it does, forcibly decreasing it at an emergency decay rate to limit the output voltage setpoint between the minimum and maximum allowable output voltage values; Controlling the soft start of the output current includes: if the output current setpoint is less than the output current preset value, the output current setpoint is automatically increased according to the preset soft start growth rate; if the output current setpoint is greater than the output current preset value, the output current setpoint is automatically decreased according to the preset soft start decay rate; simultaneously, it is determined whether the output current setpoint exceeds the current safety value, and if it does, it is forcibly decreased according to the emergency decay rate, limiting the output current setpoint to between the minimum allowable output current value and the maximum allowable output current value.

7. The control method for a charging pile according to claim 5, characterized in that, The execution of input-side and output-side control includes: The output voltage and output current of the outer loop are acquired in real time to obtain the output voltage sample value and output current sample value; the error between the output voltage sample value and the output voltage setpoint is calculated, and the voltage error is calculated using a PI algorithm to obtain the PI voltage output value of the voltage outer loop; at the same time, the error between the output current sample value and the output current setpoint is calculated, and the current error is calculated using a PI algorithm to obtain the PI current output value of the current outer loop; the magnitudes of the PI voltage output value and the PI current output value are compared, and the smaller value is taken as the final output value of the outer loop; The input voltage and input current sampling values ​​of the three-phase converter unit are collected in real time; the input voltage phase of the corresponding phase is extracted based on the input voltage of the three-phase converter unit; the input voltage phase of the corresponding phase of the three-phase converter unit is multiplied by the final output value of the outer loop to obtain the input current setpoint of the corresponding phase; Calculate the error between the input current setpoint and the input current sample value of the corresponding phase of the three-phase conversion unit, and perform PI algorithm calculation on the current error to obtain the PI output value of the current inner loop of the corresponding phase.

8. The control method for a charging pile according to claim 7, characterized in that, The drive wave generation control includes: If the PI output value of the corresponding phase current inner loop of the three-phase conversion unit is greater than the PFM frequency modulation threshold, then PFM modulation is used, with the fixed duty cycle being a preset constant duty cycle, and the frequency changing inversely to the PI output value. If the PI output value of the corresponding phase current inner loop of the three-phase conversion unit is less than or equal to the PFM frequency modulation threshold value and greater than the PWM frequency modulation threshold value, then PWM modulation is adopted, the fixed frequency is the preset constant frequency, and the duty cycle changes in a positive direction with the PI output value. If the PI output value of the current inner loop of the corresponding phase of the three-phase converter unit is less than or equal to the PWM frequency modulation threshold value, then the phase enters the blocking stage, the duty cycle drive quantity is set to 0, and the corresponding phase switch is turned off.

9. The control method for a charging pile according to claim 8, characterized in that, The method further includes: when the output voltage sample value is greater than the output voltage setpoint and the input current sample value is less than the input current setpoint, the outer current loop is saturated, and the PI voltage output value is used as the control reference to operate in constant voltage mode; when the input current sample value is greater than the input current setpoint and the output voltage sample value is less than the output voltage setpoint, the outer voltage loop is saturated, and the PI current output value is used as the control reference to operate in constant current mode.

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