A multi-path multi-phase step-down DC circuit, a circuit architecture, an electronic device, and a control method of a multi-path multi-phase step-down DC circuit

Abstract

This application provides a multi-channel, multi-phase buck DC circuit, circuit architecture, electronic equipment, and a control method for the multi-channel, multi-phase buck DC circuit. Each power supply is equipped with a corresponding adjustment unit. The adjustment unit has configuration pins, and the adjustment units are electrically connected to each other. Each adjustment unit is configured to determine its identity based on the voltage applied to the configuration pin, identifying one adjustment unit as the active unit and the others as passive units. The active unit is configured to generate and output a first control signal. The passive units are configured to determine the phase control start point of their corresponding power supply, thereby enabling at least two power supplies to achieve phase interleaving under a unified time base. This multi-channel, multi-phase buck DC circuit has the effects of reducing the rate of change of current and voltage, reducing electromagnetic interference radiation, reducing the amplitude of power supply ripple at the input terminal, and enhancing the robustness and electromagnetic compatibility of the system.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a multi-channel multi-phase step-down DC circuit, circuit architecture, electronic equipment, and control method for the multi-channel multi-phase step-down DC circuit. Background Technology

[0002] As chip design processes and hardware performance requirements continue to improve, the power supply needs of graphics cards and AI accelerator cards are rapidly evolving in multiple directions. A single graphics card or AI accelerator card typically has multiple power supplies to meet the power requirements of different functional modules within the chip.

[0003] In related technologies, for high-current single-channel power supplies, a multi-phase (multi-phase parallel step-down) design is typically used. This involves connecting multiple phases in parallel to achieve the same power supply capacity of several hundred amperes as a single channel, while each phase can provide tens of amperes. Multi-phase power supplies usually employ phase-interleaved control, which reduces input and output voltage ripple. Under the same input and output ripple voltage requirements, the input capacitor capacity can be reduced, and global phase interleaving offers significant advantages in reducing system electromagnetic interference.

[0004] However, existing multi-phase step-down DC circuits may have scenarios where different phases of different power supplies are switched synchronously. This will worsen the voltage ripple of the local input power supply, increase electromagnetic interference radiation, and also cause the current change rate and voltage change rate of the local power supply loop to increase interference to other surrounding lines, thereby reducing the robustness of the system. Summary of the Invention

[0005] To reduce the rate of change of current and voltage in the circuit, decrease the amplitude of power supply ripple at the input terminal, reduce electromagnetic interference radiation, and enhance the robustness and electromagnetic compatibility of the system, this application provides a multi-channel multi-phase buck DC circuit, a circuit architecture, electronic equipment, and a control method for the multi-channel multi-phase buck DC circuit.

[0006] According to a first aspect of the embodiments of this application, a multi-channel multi-phase step-down DC circuit is provided, the multi-channel multi-phase step-down DC circuit including at least two power supplies; Each of the power supplies is provided with a corresponding adjustment unit; the adjustment unit has a configuration pin, which is configured to receive an externally applied voltage, and the adjustment units are electrically connected to each other; In at least two of the power supplies, the regulating unit is configured to determine one of the regulating units as an active unit and the other regulating units as passive units based on the voltage applied to its configured pin. The active unit is configured to generate and output a first control signal based on the voltage applied to its corresponding configuration pin; the passive unit is configured to respond to the first control signal and determine the phase control start point with respect to the corresponding power supply based on the voltage on its configuration pin, so as to generate a second control signal for controlling its corresponding power supply on the time base of the first control signal, thereby enabling the at least two power supplies to achieve phase interleaving under a unified time base.

[0007] In some embodiments of this disclosure, the adjustment unit includes: The comparison module has its input terminal electrically connected to the configuration pin. The comparison module is configured to compare the voltage applied to the configuration pin with a preset voltage and generate and output an identity confirmation signal.

[0008] In some embodiments of this disclosure, the comparison module includes: The comparator has a first input terminal, a second input terminal, and a third input terminal; The first input terminal is electrically connected to the configuration pin. The second input terminal is electrically connected to an external power supply voltage terminal and is configured to provide an operating voltage to the comparator; The third input terminal is configured to apply a preset voltage to the comparator; The comparator is configured to compare the voltage on the configuration pin with the preset voltage and generate and output an identity verification signal.

[0009] In some embodiments of this disclosure, the adjustment unit further includes: A frequency control module, the control terminal of which is electrically connected to the output terminal of the comparison module, is configured to generate a clock with a controllable frequency. The system includes a channel selection module and a counting module. The channel selection module has a first port and is configured to have a first mode in the active unit and a second mode in the slave unit. In the first mode, the channel selection module is configured to load a clock provided by the frequency control module onto the first port to form a first control signal. In the second mode, the first port receives the input first control signal and provides the first control signal to the counting module. An analog-to-digital conversion module is electrically connected to the counting module. In the second mode, the counting module is electrically connected to the channel selection module. In the second mode, the counting module counts based on the first control signal loaded on the channel selection module and outputs a configuration result when the count value reaches a preset value.

[0010] In some embodiments of this disclosure, the frequency control module includes: A voltage-controlled oscillator with a tuning terminal and a clock output terminal; The tuning terminal is electrically connected to the configuration pin and is configured to receive the voltage on the configuration pin; The clock output terminal is configured such that, in the first mode, the clock signal generated by the clock output terminal is output from the first port via the channel selection module as the first control signal.

[0011] In some embodiments of this disclosure, the comparator is configured such that when the voltage of the configuration pin is greater than a preset voltage, the identity verification signal output by the comparator is used to determine that the current adjustment unit is an active unit; When the voltage of the configuration pin is not greater than the preset voltage, the identification signal output by the comparator is used to determine that the current adjustment unit is a slave unit.

[0012] In some embodiments of this disclosure, the preset voltage is half the voltage at the power supply voltage terminal.

[0013] In some embodiments of this disclosure, the regulating unit further includes a voltage regulation module; The voltage regulation module has a first terminal and a second terminal; the first terminal is electrically connected to the external power supply voltage terminal; the second terminal is electrically connected to the configuration pin and is configured to adjust the voltage value provided by the configuration pin to the input terminal of the comparison module.

[0014] In some embodiments of this disclosure, the voltage regulation module includes a first resistor and a second resistor; One end of the first resistor is electrically connected to the external power supply voltage terminal, and the other end of the first resistor is electrically connected to one end of the second resistor to form a voltage divider node; The other end of the second resistor is electrically connected to the ground terminal; The configured pins are electrically connected to the voltage divider node.

[0015] According to a second aspect of the embodiments of this application, a circuit architecture is provided, the circuit architecture including the aforementioned multi-channel multiphase buck DC circuit.

[0016] According to a third aspect of the embodiments of this application, an electronic device is provided, including the circuit architecture as described in claim 12, and / or including the multi-channel multiphase buck DC circuit as described in any one of claims 1 to 11.

[0017] According to a fourth aspect of the embodiments of this application, a control method for a multi-channel multiphase step-down DC circuit is provided, wherein the multi-channel multiphase step-down DC current includes: At least two power supplies; each power supply is provided with a corresponding adjustment unit; the adjustment unit has a configuration pin, which is configured to receive an externally applied voltage; and the adjustment units are electrically connected to each other. The control method includes: The adjustment unit determines one of the adjustment units as the active unit and the remaining adjustment units as the passive units based on the voltage applied on the configuration pin. The active unit generates and outputs a first control signal based on the voltage applied to its corresponding configuration pin; The slave unit responds to the first control signal and determines the phase control start point of its corresponding power supply based on the voltage on its configured pin, so as to generate a second control signal for controlling the corresponding power supply on the time base of the first control signal, thereby enabling the at least two power supplies to achieve phase interleaving under a unified time base. The technical solution provided by the embodiments of this application may include the following beneficial effects: In this embodiment, during the circuit configuration phase, an external voltage is applied to the configuration pins of the adjustment units of each power supply. Each adjustment unit reads and determines its identity based on the applied voltage, automatically identifying one as the active unit and the rest as passive units, and establishing a unified time base under the electrical connection relationship. The active unit generates and outputs a first control signal based on the voltage on its configuration pin, serving as the global time base signal. The passive units receive the first control signal and determine the phase control start point of their respective channels based on the voltage on their own configuration pins, generating a second control signal on the unified time base to drive the power stage of their respective power supply. Thus, at least two power supplies achieve phase-interleaved operation under the unified time base, avoiding phase drift and disordered superposition. This configuration establishes a unified time base and implements phase interleaving among multiple power supplies, which avoids overlapping and superimposed switching edges of each channel. This effectively reduces the current and voltage change rates of the common input node, reduces input or output ripple, suppresses electromagnetic interference radiation, and weakens coupling to surrounding lines. Under the premise of meeting the same ripple index, the configuration of input capacitors and filtering devices can be reduced. At the same time, master-slave determination and phase arrangement are completed by configuring pins. The structure is simple to implement and easy to expand. Overall, it enhances the robustness and electromagnetic compatibility margin of the system, and is suitable for multi-channel high-current power supply scenarios such as graphics cards and artificial intelligence accelerator cards to support higher power consumption and higher performance nodes.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this application, illustrate embodiments consistent with this application and, together with the application, serve to explain the principles of this application.

[0020] Figure 1 This is a schematic diagram of a multi-channel, multi-phase step-down DC circuit in related technologies.

[0021] Figure 2 This is a timing diagram of a multi-channel, multi-phase step-down DC circuit in related technologies.

[0022] Figure 3 This is a schematic diagram of the multi-channel, multi-phase step-down DC circuit in this application.

[0023] Figure 4 This is a timing diagram of the multi-channel, multi-phase step-down DC circuit in this application.

[0024] Figure 5 This is a schematic diagram showing that the regulating unit is defined as the active unit in this application.

[0025] Figure 6 This is a schematic diagram showing that the adjustment unit is defined as the driven unit in this application.

[0026] Explanation of reference numerals in the attached figures: 1. Power supply; 2. Adjustment unit; 21. Active unit; 22. Slave unit; 23. Comparison module; 231. Comparator; 2311. First input terminal; 2312. Second input terminal; 2313. Third input terminal; 24. Frequency control module; 241. Voltage-controlled oscillator; 25. Analog-to-digital conversion module; 26. Channel selection module; 261. First port; 27. Counting module; 28. Voltage control module; 281. First resistor; 282. Second resistor; 3. First adjustment unit; 4. Second adjustment unit; 5. Configuration pin; 6. Modulation unit; Q1. High-side switching transistor; Q2. Low-side switching transistor; CM. Drive unit; L. Inductor; C. Capacitor; V1. First output voltage; V2. Second output voltage; Vin. Voltage loading terminal. Detailed Implementation

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0028] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0029] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0030] In related technologies, with the continuous improvement of chip design processes and hardware performance requirements, the demand for power supplies (Power 1) for graphics cards and AI accelerator cards is rapidly developing. A single graphics card or AI accelerator card typically has multiple power supplies (Power 1) to meet the power supply needs of different functional modules of the chip. For a single high-current power supply (Power 1), the current can reach hundreds of amperes. Considering the heat dissipation limits of the power supply solution and the efficiency optimization of the entire power supply board, a multi-phase parallel connection is usually used for a single power supply (Power 1), so that each phase can handle tens of amperes, thereby achieving a single-channel power supply capacity of hundreds of amperes. However, this method can lead to scenarios where different sub-power supplies in different power supplies (Power 1) switch synchronously. This will worsen the voltage ripple of the local input power supply (Power 1), increase electromagnetic interference radiation, and also cause a larger rate of change of current and voltage in the local power supply loop (Power 1), increasing interference to other surrounding lines and thus reducing the robustness of the system.

[0031] Figure 1 A schematic diagram of a multi-channel, multi-phase buck DC-DC converter circuit in the related art is shown. Figure 2 A timing diagram of a multi-channel, multi-phase buck DC-DC converter circuit in the related art is shown. See also... Figure 1 and Figure 2The circuit includes a modulation unit 6 to manage one power supply 1 output. This power supply 1 consists of multiple sub-branch circuits with phase interleaving within the rail, including phases 1 to 1 (N>1). The modulation unit 6 performs phase arrangement for this rail; therefore, when other independent power supply 1 channels are configured simultaneously, rising or falling edges may occur at the same time between each channel, causing multiple phase current pulses at the common input terminal to be instantaneously superimposed. Under the influence of the input distributed inductance L and the parasitic parameters of the traces, the superposition further amplifies the input voltage ripple and increases the peak electromagnetic interference at the switching fundamental frequency and its harmonics. Equivalently, the rate of change of input current and voltage increases, exacerbating coupling interference to adjacent lines, thereby reducing the electromagnetic compatibility margin and overall robustness of the system.

[0032] Based on this, this application provides a multi-channel, multi-phase buck DC circuit, a circuit architecture and electronic equipment including the circuit, and a corresponding control method for the multi-channel, multi-phase buck DC circuit. The multi-channel, multi-phase buck DC circuit provided in this application, by establishing a unified time base and implementing phase interleaving among multiple power supplies 1, can reduce the rate of change of current and voltage at the input of the global power supply 1, reduce the amplitude of the power supply ripple at the input, and suppress electromagnetic interference radiation, thereby improving the robustness and electromagnetic compatibility of the system. Correspondingly, the circuit architecture, electronic equipment, and control method also have the aforementioned technical effects when implementing the technical solution of this application.

[0033] The following is a detailed introduction to the multi-channel, multi-phase step-down DC circuit: Figure 3 A circuit diagram of the multi-channel, multi-phase step-down DC circuit of this application is shown. See also... Figure 3 The multi-phase step-down DC circuit includes at least two power supplies 1; each power supply 1 is provided with a corresponding adjustment unit 2; the adjustment unit 2 has a configuration pin 5, which is configured to receive an externally applied voltage, and the adjustment units 2 are electrically connected to each other; in the at least two power supplies 1, each adjustment unit 2 is configured to determine its identity based on the voltage applied to its configuration pin 5, identifying one adjustment unit 2 as an active unit 21 and the other adjustment units 2 as passive units 22; wherein, the active unit 21 is configured to generate and output a first control signal according to the voltage applied to its corresponding configuration pin 5; the passive unit 22 is configured to respond to the first control signal and determine the phase control start point of its corresponding power supply 1 according to the voltage on its configuration pin 5, so as to generate a second control signal for controlling the corresponding power supply 1 on the time base of the first control signal, thereby enabling the at least two power supplies 1 to achieve phase interleaving under a unified time base.

[0034] In this embodiment, each power supply 1 corresponds to an adjustment unit 2 that receives an applied voltage on its configuration pin 5. Each adjustment unit 2 reads its local configuration voltage and performs local identification according to a preset determination rule, thereby identifying a unique active unit 21 among at least two power supplies 1, with the rest being passive units 22. The active unit 21 generates and outputs a first control signal based on the voltage on its configuration pin 5. This signal is distributed to each passive unit 22 as a global time base signal, thus forming a unified timing reference for the system. After receiving the first control signal, each passive unit 22 determines its phase control start point for its corresponding power supply 1 based on the voltage on its own configuration pin 5; this phase control start point is equivalent to a delay or phase value relative to the first control signal. Subsequently, the passive unit 22 generates a second control signal for driving its power stage based on the determined phase start point, using the time base of the first control signal. The active unit 21 and each slave unit 22 control the switching action of the corresponding power supply 1 using their output second control signals. All channels use the first control signal as a unified time base and are sequentially staggered according to their respective determined phase start points, so that at least two power supplies 1 can achieve phase-interleaved operation under a unified time base. In this way, when the frequency is adjusted or the load changes, each channel still remains synchronized with the first control signal, the phase relationship remains stable, and the multi-channel multi-phase coordinated operation is completed.

[0035] It should be noted that, in order to clarify the phase relationship, this embodiment defines the phase control start point of the active unit 21 corresponding to the power supply 1 as the global phase reference point. Specifically, taking the reference time t0 of the first control signal (e.g., its effective edge time) as the reference point P0, the phase control start point of the active unit 21 corresponding to the power supply 1 satisfies: P0=t0, which is equivalent to a delay of 0 or a phase of 0° relative to the first control signal.

[0036] After receiving the first control signal, each slave unit 22 determines the phase offset of its corresponding power supply 1 based on the voltage on its own configuration pin 5, and determines the phase control start point accordingly. Specifically, for any slave unit 22 corresponding to a power supply 1, its phase control start point Pi and reference point P0 satisfy the following relative relationship: Pi = P0 + Δti; where Δti is a preset delay relative to reference point P0. Equivalently, this can be expressed as Δti = (Δφi / 360°)T, where Δφi is a preset phase offset relative to reference point P0, and T is the global period corresponding to the first control signal. Subsequently, the slave unit 22 generates a second control signal at time Pi on the time base of the first control signal to drive the power level of its own power supply 1, thereby making the switching action of the corresponding power supply 1 phase-interleaved with the power supply 1 corresponding to the active unit 21 under a unified time base. The active unit 21 and each slave unit 22 use their output second control signal to control the switching action of the corresponding power supply 1. When frequency adjustment or load change causes the period T to change, the Δti or Δφi of each slave unit 22 remains unchanged relative to the reference point P0 or is updated according to a preset rule, so that the cross-channel phase relationship remains stable and the multi-channel multi-phase collaborative work is completed.

[0037] Furthermore, for example, when there are two power supplies 1, it is preferable to operate the two power supplies 1 with 180° phase interleaving; in this case, the phase control starting point of the active unit 21 corresponding to power supply 1 is P0=t0 (0°), and the phase control starting point of the driven unit 22 corresponding to power supply 1 is P1=t0+T / 2 (180°), that is, Δt1=T / 2, Δφ1=180°. When the system contains three power supplies 1, it is preferable to operate the three power supplies 1 with 120° equally spaced phase interleaving; in this case, the phase control starting point of the active unit 21 corresponding to power supply 1 is P0=t0 (0°), the phase control starting point of the first driven unit 22 corresponding to power supply 1 is P1=t0+T / 3 (120°), and the phase control starting point of the second driven unit 22 corresponding to power supply 1 is P2=t0+2T / 3 (240°), that is, Δt1=T / 3, Δt2=2T / 3. Figure 3 The example illustrates a multi-phase, multi-channel buck DC circuit that includes at least two power supplies (see [link]). Figure 3 Each power supply 1 consists of multiple parallel sub-power supplies. Each sub-power supply serves as a multi-phase power branch of power supply 1 and corresponds to its own phase, jointly supplying power to the corresponding load.

[0038] Taking two power supplies 1 as an example, one power supply 1 corresponds to the first regulating unit 32, and the other power supply 1 corresponds to the second regulating unit 42. Each sub-power supply includes a voltage conversion branch, which includes at least a high-side switching transistor Q1, a low-side switching transistor Q2, and its driving unit CM: the upper end of the high-side switching transistor Q1 is connected to the voltage loading terminal Vin, the lower end of the low-side switching transistor Q2 is connected to ground, the adjacent ends of the two form a common switching node and are electrically connected to one end of the inductor L, the other end of the inductor L is connected to the output terminal, the output terminal is connected in parallel with a capacitor C and electrically connected to the load; the input side of each voltage conversion branch is connected in parallel to the same input bus, and its gate is controlled by its respective driving unit CM. The control terminal of the driving unit CM is electrically connected to the phase control output of the corresponding regulating unit 2. After the adjustment unit 2 completes the identity verification, if the first adjustment unit 32 is determined to be the active unit 21, the clock of the frequency control module 24 is loaded to the first port 261 through the channel selection module 26 to form a first control signal, which is distributed to each phase of its corresponding power supply 1 as a unified time base, and provided to the second adjustment unit 42 when needed; if the second adjustment unit 42 is determined to be the passive unit 22, the first control signal is received by the channel selection module 26 as a time base, and the counting module 27 determines the phase starting point of each phase according to the counting threshold obtained by analog-to-digital conversion based on the level of its configuration pin 5, generates a second control signal and distributes it to each power branch of this power supply 1, so that this power supply 1 operates with a preset phase misalignment under a unified time base; the parallel voltage transformation branches in the same phase share the corresponding control pulse to be synchronously turned on and off, so that the current formed by each branch through its respective inductor L is superimposed at the common output terminal, and filtered by capacitor C to obtain a stable DC output voltage; the two adjustment units 2 can realize role interchange through the configuration pin 5 settings.

[0039] Figure 4 A timing diagram of the multi-channel, multi-phase buck DC circuit of this application is shown. See also... Figure 4 The first output voltage V1 is managed by the first regulating unit 32, including the first phase to the Nth phase (N>1); the second output voltage V2 is managed by the second regulating unit 42, including the first phase to the Mth phase (M>1). Unlike related technologies, the two sets of regulating units 2 achieve cross-track phase arrangement through a unified time base: the active unit 21 in the first mode outputs the first control signal as a global synchronization reference; the slave unit 22 in the second mode receives the first control signal through the channel selection module 26, and determines the phase control start point of the corresponding power supply 1 based on the voltage on its configuration pin 5, and generates a second control signal for controlling this channel on this time base, so that at least two power supplies 1 achieve phase interleaving under a unified time base. Figure 4As can be seen from the time axis, the phase pulses within the first output voltage V1 and the second output voltage V2 are interleaved at equal intervals or according to a preset pattern within the global cycle, avoiding the occurrence of rising or falling edges of different power supply rails at the same time, thereby reducing the superposition of instantaneous phase currents at the common input terminal. Accordingly, under the same load conditions, the peak value of the instantaneous input current can be reduced and the peak value of electromagnetic interference at the switching fundamental frequency and its harmonics can be suppressed. Equivalently, the rate of change of input current and the rate of change of voltage decrease, the coupling interference to adjacent lines is reduced, and the electromagnetic compatibility margin and robustness of the system are improved.

[0040] More specifically, Figure 4 The timing diagram of the multi-channel, multi-phase buck DC circuit of this application is shown. It should be noted that... Figure 4 This is merely a specific example for ease of understanding and does not constitute a limitation on the phase arrangement method of this application. See also Figure 4 The first output voltage V1 is managed by the first regulating unit 32 and includes the first phase to the Nth phase (N>1); the second output voltage V2 is managed by the second regulating unit 42 and includes the first phase to the Mth phase (M>1). Unlike related technologies, the two sets of regulating units 2 achieve cross-track phase arrangement through a unified time base: the active unit 21 in the first mode outputs the first control signal as a global synchronization reference; the slave unit 22 in the second mode receives the first control signal through the channel selection module 26 and determines the phase control start point of the corresponding power supply 1 based on the voltage on its configuration pin 5, and generates a second control signal for controlling this channel on this time base, so that at least two power supplies 1 achieve phase interleaving under a unified time base.

[0041] In a preferred embodiment of this application, the phase-interleaved arrangement preferably satisfies the following rules: a global period T and a reference time t0 (e.g., the effective edge time of the first control signal) are defined by the first control signal, and the phase control start point of the active unit 21 corresponding to the power supply 1 is defined as the reference phase start point P0, such that P0 = t0 (equivalent to 0 delay or 0° phase); the phase control start point Pi of each slave unit 22 corresponding to the power supply 1 has a preset relative offset Δti or Δφi relative to P0, where Pi = P0 + Δti, and Δti and Δφi satisfy Δti = (Δφi / 360°)T.

[0042] Preferably, the phase control start points corresponding to the N phases of the first output voltage V1 and the M phases of the second output voltage V2 are distributed as evenly as possible and staggered across rails within a period T: on the one hand, all (N+M) phase control start points are distributed at equal intervals on the time axis to increase the minimum time interval between any two start points; on the other hand, it is preferable to make the phase control start points from the first output voltage V1 and the second output voltage V2 alternate as much as possible on the time axis, thereby avoiding the occurrence of rising or falling edges on different power supply rails at the same time, or significantly reducing their probability. When N and M are not equal, making strict one-to-one alternation impossible, it is preferable to first ensure that the phase control start points from the first output voltage V1 and the second output voltage V2 are staggered as much as possible, and then disperse the remaining phase control start points within the period T according to the principle of "maximizing the minimum interval", or determine them by a preset phase table / preset mapping relationship.

[0043] For example, in Figure 4 In the example shown, both the first output voltage V1 and the second output voltage V2 are four-phase (N = M = 4). This allows for the phase control starting points within one cycle T to be evenly distributed. Preferably, the four phases of the first output voltage V1 and the four phases of the second output voltage V2 alternate on the time axis (e.g., the interval between adjacent starting points is approximately T / 8), thereby forming a cross-track phase interleaving deployment within the global cycle. This reduces the superposition of instantaneous phase currents at the common input terminal. In some embodiments, the multi-channel multi-phase buck DC circuit may include N power supplies, where N is greater than or equal to 2.

[0044] It should be noted that those skilled in the art can determine the specific value of N based on the load scale and power consumption requirements. For example, a multi-channel multiphase step-down DC circuit may include two, three, or more than three channels, which does not constitute a limitation on this application.

[0045] Furthermore, each power supply 1 consists of multiple sub-power supplies connected in parallel. Each sub-power supply serves as a multi-phase power branch of power supply 1 and corresponds to its respective phase, used to jointly supply power to the corresponding load. This application does not limit the number of sub-power supplies in each power supply.

[0046] In some embodiments of this disclosure, see Figure 5 , Figure 6 The adjustment unit 2 includes a comparison module 23; the input terminal of the comparison module 23 is electrically connected to the configuration pin 5, and the comparison module 23 is configured to compare the voltage applied on the configuration pin 5 with a preset voltage and generate and output an identity confirmation signal.

[0047] Specifically, after the power supply 1 is powered on, the configuration pin 5 applies voltage to the comparison module 23. The comparison module 23 compares the voltage on the configuration pin 5 with the preset voltage, and generates and outputs an identity confirmation signal accordingly: when the voltage is higher than the preset voltage, it is determined to be the active unit 21, and when the voltage is lower than or equal to the preset voltage, it is determined to be the passive unit 22.

[0048] In some implementations, the identity determination result can be latched to maintain identity stability. This setting ensures that the identity of the adjustment unit 2 is maintained once determined, avoiding frequent switching caused by jitter near the threshold, ensuring continuous and stable unified time base, and preventing multiple adjustment units 2 from competing for master control simultaneously, thus preventing competition. The start-up and shutdown sequence is predictable, making it easier to meet system-level timing constraints. Phase does not change abruptly and synchronization is not lost, reducing instantaneous input current jumps and the resulting electromagnetic interference peaks. The master-slave boundary is clear, facilitating fault isolation and diagnosis, and reducing the complexity of control logic and software.

[0049] It is understood that in other embodiments, the identity of the adjustment unit 2 can be dynamically adjusted according to stages or operating conditions, that is, the adjustment unit 2 can present different identities at different stages, and this disclosure does not limit this. Such a setting can adaptively adjust the identity according to conditions such as light load, heavy load, temperature rise or power limitation to optimize efficiency and temperature rise; realize rapid master-slave switching when an anomaly is detected to improve availability and robustness; reconfigure the allocation of phase and unified time base as needed, taking into account phase resource balance and electromagnetic compatibility optimization; take turns controlling the master among multiple power supplies 1 according to priority to distribute the aging of components and thermal load; and facilitate factory debugging and field maintenance, and complete system reconfiguration without modifying the hardware.

[0050] In this embodiment, see Figure 5 , Figure 6 The comparison module 23 includes a comparator 231; the comparator 231 has a first input terminal 2311, a second input terminal 2312, and a third input terminal 2313; wherein, the first input terminal 2311 is electrically connected to the configuration pin 5; the second input terminal 2312 is electrically connected to an external power supply voltage terminal and is configured to provide an operating voltage to the comparator 231; the third input terminal 2313 is configured to load a preset voltage into the comparator 231; the comparator 231 is configured to compare the voltage on the configuration pin 5 with the preset voltage, generate and output an identity verification signal.

[0051] Specifically, after power supply 1 is powered on, the external power supply terminal supplies power to comparator 231, and the second input terminal 2312 receives the external power supply voltage; the configuration pin 5 loads the voltage to the first input terminal 2311; the preset voltage is loaded to comparator 231 through the third input terminal 2313 as a reference threshold; within the determination time window, comparator 231 compares the voltage of the first input terminal 2311 with the preset voltage of the third input terminal 2313, and generates an identity verification signal at the output terminal to verify the identity of the adjustment unit 2.

[0052] More specifically, when the voltage of the configuration pin 5 is greater than the preset voltage, the identification confirmation signal output by the comparator 231 determines that the current adjustment unit 2 is the active unit 21; when the voltage of the configuration pin 5 is not greater than the preset voltage, the identification confirmation signal output by the comparator 231 determines that the current adjustment unit 2 is the passive unit 22.

[0053] In some embodiments of this disclosure, the preset voltage is half of the voltage applied to the power supply voltage terminal.

[0054] It should be noted that the "supply voltage" referred to in this disclosure refers to the voltage provided by an external supply voltage terminal and electrically connected to the second input terminal 2312 of the comparator 231. Furthermore, the voltage applied to the supply voltage terminal serves as an external input power supply and is not generated internally by the comparator 231.

[0055] In some embodiments of this disclosure, see Figure 5 , Figure 6 The adjustment unit 2 also includes a frequency control module 24; the control terminal of the frequency control module 24 is electrically connected to the output terminal of the comparison module 23, and the frequency control module 24 is configured to generate a clock with a controllable frequency.

[0056] As an example, a voltage-controlled oscillator 241 has a tuning terminal and a clock output terminal; the tuning terminal is electrically connected to a configuration pin 5 and is configured to receive the voltage on the configuration pin 5; the clock output terminal is configured such that, in a first mode, the clock signal generated by the clock output terminal is output from the first port 261 as a first control signal via the channel selection module 26.

[0057] Specifically, the comparison module 23 first outputs an identity verification signal based on the voltage of configuration pin 5 to indicate the first mode or the second mode. When in the first mode, the frequency control module 24 is enabled, and the tuning terminal of the voltage-controlled oscillator 241 directly receives the voltage of configuration pin 5 and sets the oscillation frequency accordingly. Its clock output is sent to the first port 261 via the channel selection module 26 to form the first control signal, which is used as a unified time base for distribution. When in the second mode, the frequency control module 24 is turned off or stops oscillating, and the channel selection module 26 selects the first control signal input externally as a local synchronization reference. Under the optional dynamic identity strategy, the output change of the comparison module 23 will synchronously switch the enable state of the oscillator and the channel selection path to ensure that the unified time base is always generated and distributed by the current active unit 21.

[0058] In some embodiments of this disclosure, see Figure 5 , Figure 6 The adjustment unit 2 also includes an analog-to-digital converter (ADC) module 25. The input terminal of the ADC module 25 is electrically connected to the configuration pin 5. The ADC module 25 is configured to convert the voltage applied to the configuration pin 5 into a digital signal. In this embodiment, the ADC module 25 quantizes the analog voltage on the configuration pin 5 into a digital quantity, which is used by the adjustment unit 2 for parameter setting and operating condition identification. Firstly, it is used to generate the counting threshold and bias quantity required for phase arrangement, guiding the slave unit 22 to determine the starting point of each phase under a unified time base, realizing phase interleaving across power supply 1. Secondly, it can serve as an input source for multiple programmable parameters, such as nominal switching frequency, number of participating phases, current limiting threshold, soft-start slope, etc., completing factory calibration and field debugging without increasing the communication interface. Thirdly, it works with the comparison module 23 to provide digital evidence for threshold judgment, and identifies and backs down anomalies such as open circuit, short circuit, and over-limit, improving the reliability and maintainability of the system.

[0059] In some embodiments of this disclosure, see Figure 5 , Figure 6 The adjustment unit 2 further includes a channel selection module 26 and a counting module 27. The channel selection module 26 has a first port 261 and is configured to have a first mode in the active unit 21 and a second mode in the driven unit 22. In the first mode, the channel selection module 26 is configured to load the clock provided by the frequency control module 24 onto the first port 261 to form a first control signal. In the second mode, the first port 261 receives the input first control signal and provides the first control signal to the counting module 27. The counting module 27 is electrically connected to the analog-to-digital conversion module 25 and is electrically connected to the channel selection module 26 in the second mode. In the second mode, the counting module 27 counts based on the first control signal loaded on the channel selection module 26 and outputs the configuration result when the count value reaches a preset value.

[0060] Understandably, when the adjustment unit 2 is determined to be the active unit 21, the channel selection module 26 is in the first mode, loads the clock of the frequency control module 24 to the first port 261 and outputs the first control signal as the unified time base of this power supply 1; when the adjustment unit 2 is determined to be the passive unit 22, the channel selection module 26 is in the second mode, so that the first port 261 receives the first control signal and sends it to the counting module 27. The counting module 27 determines the phase starting point according to the threshold given by the analog-to-digital conversion module 25 and generates a second control signal for driving this power supply 1.

[0061] Specifically, after power supply 1 is powered on and identity verification is completed, channel selection module 26 enters the corresponding mode accordingly: when in the first mode (active unit 21), channel selection module 26 selects the clock of frequency control module 24 as the signal source, loads the clock to the first port 261 to form the first control signal and distributes it externally, and at the same time closes the counting path or keeps the counting module 27 idle; when in the second mode (slave unit 22), the first port 261 receives the first control signal input from the outside, and channel selection module 26 sends it to counting module 27. Counting module 27 simultaneously receives the digital setting value from analog-to-digital conversion module 25 as the preset counting threshold, counts according to the preset edge under a unified time base, and outputs the configuration result and latches it when the count value reaches the preset threshold. This is used to indicate the phase interleaving start point of this channel and trigger the local generation of the second control signal.

[0062] In some implementations, in the event of mode (first mode and second mode) switching or abnormal reset, the channel selection module 26 can disconnect the original path and then establish a new path, and the counting module 27 can be reset to zero and recounted to ensure the determinism and stability of the loading process.

[0063] In some embodiments of this disclosure, see Figure 5 , Figure 6 The adjustment unit 2 also includes a voltage regulation module 28; the voltage regulation module 28 has a first terminal and a second terminal; the first terminal is electrically connected to an external power supply voltage terminal; the second terminal is electrically connected to a configuration pin 5 and is configured to adjust the voltage value provided by the configuration pin 5 to the input terminal of the comparison module 23.

[0064] Specifically, the first end of the voltage regulation module 28 is electrically connected to the external power supply voltage terminal, and applies a settable potential to the configuration pin 5 through its output terminal. By adjusting the voltage of the configuration pin 5 to be higher than the preset voltage, the comparison module 23 outputs an "active" identity confirmation, thereby determining the corresponding adjustment unit 2 as the active unit 21; when the voltage of the configuration pin 5 is adjusted to be no higher than the preset voltage, it is determined to be the passive unit 22.

[0065] It should be noted that the above settings can be completed once during the power-on phase, or can be reset during operation according to the strategy.

[0066] As an example, see Figure 5 , Figure 6 The voltage regulation module 28 includes a first resistor 281 and a second resistor 282; one end of the first resistor 281 is electrically connected to the external power supply voltage terminal, and the other end of the first resistor 281 is electrically connected to one end of the second resistor 282 to form a voltage divider node; the other end of the second resistor 282 is electrically connected to the ground terminal; and the configuration pin 5 is electrically connected to the voltage divider node.

[0067] Specifically, the voltage divider control module 28 is composed of a first resistor 281 and a second resistor 282, and the configuration pin 5 is connected to the voltage divider node; when a certain adjustment unit 2 needs to be designated as the active unit 21, the resistance ratio is selected so that the voltage of the configuration pin 5 is higher than the preset voltage; when it needs to be designated as the passive unit 22, the resistance ratio is selected so that the voltage of the configuration pin 5 is not higher than the preset voltage.

[0068] In some embodiments of this disclosure, the regulating unit 2 can be identified as the active unit 21 by applying a potential higher than half the supply voltage to the configuration pin 5. For example, the voltage source applied to the configuration pin 5 can be a programmable digital-to-analog converter, a buffered reference source, or an adjustable regulated output. The comparison module 23 outputs an "active" identity confirmation accordingly; correspondingly, the channel to be designated as the slave unit 22 provides a potential to the configuration pin 5 that is no higher than half the supply voltage.

[0069] Optionally, soft start and overvoltage protection can be configured in this application to ensure that the judgment process is stable and reliable.

[0070] The following is a detailed description of the operation of power supply 1 in the first mode: See Figure 5In the first mode, after power supply 1 is powered on, comparison module 23 starts working. The first input terminal 2311 of comparator 231 is electrically connected to configuration pin 5 to receive configuration voltage, the second input terminal 2312 is electrically connected to external power supply voltage terminal to receive external voltage, and the third input terminal 2313 loads a preset voltage as a comparison threshold. The preset voltage is half of the power supply voltage. If a certain adjustment unit 2 needs to be designated as active unit 21, the resistance values ​​of the first resistor 281 and the second resistor 282 can be adjusted so that the voltage loaded onto comparator 231 at configuration pin 5 is higher than the threshold, or a DC voltage greater than the threshold can be directly applied to configuration pin 5. When comparator 231 determines that the voltage at configuration pin 5 is greater than the preset voltage, it outputs a high-level identity confirmation signal, determines that the adjustment unit 2 is active unit 21, and drives channel selection module 26 to switch to the left path, so that the clock output by frequency control module 24 is loaded onto the first port 261 of channel selection module 26 to form the first control signal.

[0071] See Figure 6 In the second mode, after power supply 1 is powered on, comparison module 23 starts to work: the first input terminal 2311 of comparator 231 receives the voltage of configuration pin 5, the second input terminal 2312 is electrically connected to the external power supply voltage terminal to receive the external voltage, and the third input terminal 2313 loads a preset voltage to set the comparison threshold; when comparator 231 determines that the voltage of configuration pin 5 is less than or equal to the preset voltage, it outputs a low-level identity confirmation signal to confirm that the adjustment unit 2 is the slave unit 22, and drives the channel selection module 26 to switch to the right path, so that the external first control signal is loaded to the counting module 27 as a timing reference. To meet the phase interleaving requirements of multiple slave power supplies and different operating frequencies, the external level of pin 5 is configured as a phase setting quantity, which is sampled by the analog-to-digital converter and converted into a counting threshold. The counting module 27 accumulates according to the set rhythm after being reset at the reference edge of each first control signal. When the count value reaches the counting threshold, it outputs a set signal to determine the phase starting point of this power supply, and triggers the driver stage to generate a second control signal to drive the corresponding power supply 1 to work, thereby forming a phase interleaving with the power supply 1 corresponding to the active unit 21. By setting different counting thresholds for different slave units 22, uniform or on-demand phase misalignment can be achieved.

[0072] It should be noted that, in Figure 5 In the diagram, the dashed arrows indicate the formation of the first control signal and the direction of loading; Figure 6 In the diagram, the dashed arrow indicates the direction of the first control signal being applied.

[0073] This application also provides a circuit architecture including a multi-channel, multi-phase buck DC circuit. This circuit architecture establishes unified synchronization and implements overall phase interleaving for the multiple multi-channel, multi-phase power supplies 1, enabling staggered operation of switches on different power supply 1 rails. This significantly reduces global input voltage ripple, and under the same input ripple performance, reduces the number of input capacitors C, saving board space and material costs. Simultaneously, it reduces simultaneous switching events across power supply 1 rails, improves electromagnetic interference radiation characteristics at fixed frequencies and their harmonics, and enhances electromagnetic compatibility and system robustness. Furthermore, it makes the energy of the switching-related current and voltage change rates more uniform in the spectrum and spatial distribution within the printed circuit board, reducing coupling interference to high-speed signals and sensitive low-speed signals, and increasing signal integrity and design margin.

[0074] This application also provides an electronic device, which includes a circuit architecture with multiple multi-phase buck DC circuits or an electronic device including multiple multi-phase buck DC circuits. This electronic device can achieve synchronization of multiple multi-phase power supplies 1, reduce input voltage ripple, and reduce the number of input capacitors C under the same ripple performance, thereby saving design space and material costs; through global phase interleaving, it reduces the situation where different power supply 1 channels switch at the same time, improving the radiation characteristics of electromagnetic interference; phase interleaving also makes the energy of the current change rate and voltage change rate related to the power supply 1 more uniformly distributed within the printed circuit board, which is beneficial to the stable operation of high-speed signals and sensitive low-speed signals, providing more sufficient design margin.

[0075] The applicable scenarios for this electronic device include at least multi-rail power supply for data centers and high-performance computing platforms, especially the core power supply 1 and peripheral power supply 1 for discrete graphics cards and artificial intelligence accelerator cards; collaborative power supply for industrial automation and robotic systems, including the main control board, tool head board, and adapter board of 3D printing equipment; domain controller and sensor fusion power supply 1 for automotive electronics; power supply 1 systems for communication and edge computing devices, including base stations, switching equipment, storage devices, and edge servers; and medical imaging and precision measurement instruments sensitive to electrical noise; it is also suitable for consumer and portable terminals such as laptops, tablets, augmented reality devices, and virtual reality devices to improve battery life under light loads and reduce heat generation.

[0076] It should be noted that the electronic equipment provided in this application can also be used in other devices and systems that have requirements for multi-rail power supply, low ripple and high electromagnetic compatibility. All equivalent substitutions or modifications based on this technical solution are within the protection scope of this application, and will not be elaborated here.

[0077] This application also provides a control method for a multi-channel, multi-phase step-down DC circuit. The multi-channel, multi-phase step-down DC circuit includes: at least two power supplies; each power supply is equipped with a corresponding regulating unit; the regulating unit has a configuration pin configured to receive an externally applied voltage; and the regulating units are electrically connected to each other; the control method includes: Based on the voltage applied to the configuration pin, the adjustment unit determines one of the adjustment units as the active unit and the rest as the passive units; The active unit generates and outputs the first control signal based on the voltage applied to its corresponding configuration pin; The slave unit responds to the first control signal and determines the phase control start point of its corresponding power supply based on the voltage on its configuration pin. It then generates a second control signal to control the corresponding power supply on the time base of the first control signal, thereby enabling phase interleaving of at least two power supplies under a unified time base. Specifically, configuration pin 5 applies voltage to the adjustment unit 2 of the corresponding power supply 1. The adjustment unit 2 compares the voltage applied to configuration pin 5 with a preset voltage to determine the identity of the power supply 1. The adjustment unit 2 corresponding to one power supply 1 is identified as the active unit 21, and the adjustment units 2 corresponding to the other power supplies 1 (excluding the active unit 21) are identified as slave units 22. The active unit 21 generates and outputs the first control signal, and the slave unit 22 receives the first control signal. The slave unit 22 generates a second control signal based on the first control signal to drive its corresponding power supply 1.

[0078] Furthermore, the adjustment unit 2 determines its identity by comparing the voltage of the configuration pin 5 with a preset voltage. Specifically, two methods can be used: First, the direct setting method: a DC voltage higher than the preset voltage is applied externally to the configuration pin 5, or the voltage is divided by the first resistor 281 and the second resistor 282 to make the potential of the configuration pin 5 greater than the preset voltage. The comparator 231 outputs a high level, and the adjustment unit 2 is determined to be the active unit 21; if the configuration potential is not greater than the preset voltage, it remains a slave unit. Second, the controlled adjustment method: under the action of the voltage regulation module 28, programmable pull-up or pull-down branches are selectively connected, the equivalent resistance values ​​of the first resistor 281 and the second resistor 282 are adjusted, or the reference network is switched, so that the potential of the configuration pin 5 is biased relative to the preset voltage as needed; when the configuration potential is adjusted to be greater than the preset voltage, the comparator 231 outputs a high level and latches it as the active unit 21; when the configuration potential is adjusted to be less than the preset voltage, it remains a slave unit 22. To avoid jitter near the threshold, voltage hysteresis and hold time can be set, and other channels can be prevented from becoming active when active unit 21 already exists, so as to achieve arbitration.

[0079] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the application and practice of the invention described herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not claimed herein. The application and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0080] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0081] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A multi-channel, multi-phase step-down DC circuit, characterized in that: The multi-channel multiphase step-down DC circuit includes at least two power supplies; Each of the power supplies is provided with a corresponding adjustment unit; the adjustment unit has a configuration pin, which is configured to receive an externally applied voltage, and the adjustment units are electrically connected to each other; In at least two of the power supplies, the regulating unit is configured to determine one of the regulating units as an active unit and the other regulating units as passive units based on the voltage applied on the configuration pin. The active unit is configured to generate and output a first control signal based on the voltage applied to its corresponding configuration pin; the passive unit is configured to respond to the first control signal and determine the phase control start point of its corresponding power supply based on the voltage on its configuration pin, so as to generate a second control signal for controlling the corresponding power supply on the time base of the first control signal, thereby enabling the at least two power supplies to achieve phase interleaving under a unified time base.

2. The multi-channel, multi-phase step-down DC circuit according to claim 1, characterized in that: The adjustment unit includes: The comparison module has its input terminal electrically connected to the configuration pin. The comparison module is configured to compare the voltage applied to the configuration pin with a preset voltage to generate and output an identity confirmation signal.

3. The multi-channel, multi-phase step-down DC circuit according to claim 2, characterized in that: The comparison module includes: The comparator has a first input terminal, a second input terminal, and a third input terminal; The first input terminal is electrically connected to the configuration pin. The second input terminal is electrically connected to an external power supply voltage terminal and is configured to provide an operating voltage to the comparator; The third input terminal is configured to apply a preset voltage to the comparator; The comparator is configured to compare the voltage on the configuration pin with the preset voltage to generate and output an identity verification signal.

4. The multi-channel, multi-phase step-down DC circuit according to claim 2, characterized in that: The adjustment unit further includes: A frequency control module, the control terminal of which is electrically connected to the output terminal of the comparison module, is configured to generate a clock with a controllable frequency. The system includes a channel selection module and a counting module. The channel selection module has a first port and is configured to have a first mode in the active unit and a second mode in the slave unit. In the first mode, the channel selection module is configured to load a clock provided by the frequency control module onto the first port to form a first control signal. In the second mode, the first port receives the input first control signal and provides the first control signal to the counting module. An analog-to-digital conversion module is electrically connected to the counting module. In the second mode, the counting module is electrically connected to the channel selection module. In the second mode, the counting module counts based on the first control signal loaded on the channel selection module and outputs a configuration result when the count value reaches a preset value.

5. The multi-channel, multi-phase step-down DC circuit according to claim 4, characterized in that: The frequency control module includes: A voltage-controlled oscillator with a tuning terminal and a clock output terminal; The tuning terminal is electrically connected to the configuration pin and is configured to receive the voltage on the configuration pin; The clock output terminal is configured such that, in the first mode, the clock signal generated by the clock output terminal is output from the first port via the channel selection module as the first control signal.

6. The multi-channel, multi-phase step-down DC circuit according to claim 3, characterized in that: The comparator is configured such that when the voltage of the configuration pin is greater than a preset voltage, the comparator outputs an authentication signal to determine that the current adjustment unit is an active unit; and when the voltage of the configuration pin is not greater than the preset voltage, the comparator outputs an authentication signal to determine that the current adjustment unit is a passive unit.

7. The multi-channel, multi-phase step-down DC circuit according to claim 3, characterized in that: The preset voltage is half the voltage on the external power supply voltage terminal.

8. The multi-channel, multi-phase step-down DC circuit according to claim 2, characterized in that: The regulating unit also includes a voltage regulation module; The voltage regulation module has a first terminal and a second terminal; the first terminal is electrically connected to the external power supply voltage terminal; the second terminal is electrically connected to the configuration pin and is configured to adjust the voltage value provided by the configuration pin to the input terminal of the comparison module.

9. The multi-channel, multi-phase step-down DC circuit according to claim 8, characterized in that: The voltage regulation module includes a first resistor and a second resistor; One end of the first resistor is electrically connected to the external power supply voltage terminal, and the other end of the first resistor is electrically connected to one end of the second resistor to form a voltage divider node; The other end of the second resistor is electrically connected to the ground terminal; The configured pins are electrically connected to the voltage divider node.

10. A circuit architecture, characterized in that: Includes the multi-channel multiphase step-down DC circuit as described in any one of claims 1 to 9.

11. An electronic device, characterized in that: It includes the circuit architecture as described in claim 10, and / or includes the multi-channel multiphase buck DC circuit as described in any one of claims 1 to 9.

12. A control method for a multi-channel, multi-phase step-down DC circuit, wherein the multi-channel, multi-phase step-down DC circuit comprises: At least two power supplies; each power supply is provided with a corresponding adjustment unit; the adjustment unit has a configuration pin, which is configured to receive an externally applied voltage; Furthermore, all the aforementioned adjustment units are electrically connected; The control method is characterized by: The adjustment unit determines one of the adjustment units as the active unit and the remaining adjustment units as the passive units based on the voltage applied on the configuration pin. The active unit generates and outputs a first control signal based on the voltage applied to its corresponding configuration pin; The slave unit responds to the first control signal and determines the phase control start point of its corresponding power supply based on the voltage on its configuration pin, so as to generate a second control signal for controlling the corresponding power supply on the time base of the first control signal, thereby enabling the at least two power supplies to achieve phase interleaving under a unified time base.

Images