Drive frequency control circuit and energy storage power supply
By combining sampling, comparison, filtering, and control circuits, the driving frequency of the power transistor is adjusted to match the resonant frequency of the LLC resonant circuit, thus solving the frequency error problem caused by the transformer leakage inductance acting as the resonant inductor. This achieves zero-voltage turn-on and zero-current turn-off, reducing power transistor losses.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN FEIYOUQUE NEW ENERGY TECH CO LTD
- Filing Date
- 2026-02-02
- Publication Date
- 2026-06-02
AI Technical Summary
In the existing technology, the leakage inductance of the transformer is used as the resonant inductor, which leads to a large error in the resonant frequency and makes it impossible to achieve zero-voltage turn-on and zero-current turn-off of the power transistor, resulting in high power transistor losses.
By combining sampling circuits, comparison circuits, AND gate circuits, filtering circuits, and control circuits, the driving frequency of the power transistor is adjusted to match the resonant frequency of the LLC resonant circuit, thereby achieving zero-voltage turn-on and zero-current turn-off.
This effectively reduces power transistor losses and improves power conversion efficiency.
Smart Images
Figure CN122137201A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of energy storage power technology, and in particular to a drive frequency control circuit and an energy storage power supply. Background Technology
[0002] In energy storage power supplies, LLC resonant circuits are often used to improve power conversion efficiency, achieving zero-voltage turn-on (ZVS) and zero-current turn-off (ZCS) of the power transistors to reduce power transistor losses. LLC refers to the magnetizing inductance, resonant inductance, and resonant capacitor of the transformer. To reduce costs, the resonant inductor is usually integrated into the transformer, thus reducing the number of components by one.
[0003] To integrate a resonant inductor onto a transformer, there are typically two implementation schemes: The first method involves adding another magnetic column to the transformer core to generate a resonant inductor. The inductance is then adjusted by grinding the air gap between the columns in the core.
[0004] The second method is to directly use the leakage inductance of the transformer as the resonant inductor. This method is low-cost and commonly used in open-loop resonant circuits. However, because the leakage inductance of the transformer is very small, typically only a few μH to tens of μH, the accuracy is also greater than 10%. Especially in open-loop resonant LLC circuits, zero-voltage turn-on (ZVS) and zero-current turn-off (ZCS) can only be achieved when the switching frequency of the power transistor is equal to the true resonant frequency.
[0005] In practical applications, using the leakage inductance of a transformer as the resonant inductor can easily lead to a large error in the resonant frequency. This makes it impossible to accurately obtain the resonant frequency, resulting in a mismatch between the switching frequency of the power transistor and the resonant frequency. Consequently, it is impossible to achieve zero-voltage turn-on (ZVS) and zero-current turn-off (ZCS) of the power transistor, leading to high power transistor losses. Summary of the Invention
[0006] This application provides a drive frequency control circuit and an energy storage power supply, which can adjust the drive frequency of the power transistor to match the resonant frequency of the LLC resonant circuit, enabling the power transistor to achieve zero voltage turn-on (ZVS) and zero current turn-off (ZCS), thereby reducing the power transistor's losses.
[0007] This application provides a drive frequency control circuit applied to a power conversion circuit. The power conversion circuit includes an input side and an output side, which are coupled to each other via a transformer. The input side includes a power transistor. The drive frequency control circuit includes: A sampling circuit is used to connect to the output side and the power transistor to sample the current of the output side and obtain the corresponding sampling voltage, as well as to obtain the driving voltage of the power transistor; A comparison circuit, connected to the sampling circuit, is used to compare the sampled voltage with a reference voltage and output a comparison signal; An AND gate circuit, connected to the sampling circuit and the comparison circuit, is used to output an AND signal based on the driving voltage and the comparison signal; A filter circuit, connected to the AND gate circuit, is used to convert the AND signal into a DC voltage; A control circuit, connected to the filter circuit, is used to calculate the target drive frequency based on the DC voltage and adjust the drive frequency of the power transistor to the target drive frequency.
[0008] In some embodiments, the control circuit calculates the target driving frequency according to the following formula: Where fsw is the target driving frequency, VCC is the power supply voltage of the AND gate circuit, Vadc is the amplitude of the DC voltage, T is the period of the AND signal, and t(die) is the dead time of the driving signal of the power transistor.
[0009] In some embodiments, the sampling circuit includes: The first sampling branch is used to connect to the output side to sample the current of the output side and obtain the corresponding sampling voltage; The second sampling branch is used to connect to the driving terminal of the power transistor to obtain the driving voltage of the power transistor; A charging branch is connected between the first sampling branch and the second sampling branch. The charging branch includes an energy storage element, and the driving voltage is also used to charge the energy storage element.
[0010] In some embodiments, the first sampling branch includes: A current transformer includes a primary winding and a secondary winding coupled to each other, wherein the primary winding is connected in series on the output side; The anode of the first diode is connected to the secondary winding; A first sampling resistor, the first end of which is connected to the cathode of the first diode and used to output the sampling voltage, and the second end of which is grounded.
[0011] In some embodiments, the second sampling branch includes a second sampling resistor, the first end of which is used to connect to the driving terminal of the power transistor, and the second end of which is used to output the driving voltage.
[0012] In some embodiments, the charging branch includes a second diode and a first capacitor, the anode of the second diode is connected to the second terminal of the second sampling resistor, the cathode of the second diode is connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is connected to the first terminal of the first sampling resistor.
[0013] In some embodiments, the comparison circuit includes a comparator, the non-inverting input of which is connected to the sampling circuit for inputting the sampling voltage, the inverting input of which is grounded, and the output of which is used to output the comparison signal.
[0014] In some embodiments, the comparison module further includes a current-limiting resistor, the first end of which is connected to the output of the comparator, and the second end of which is used to output the comparison signal.
[0015] In some embodiments, the filtering circuit includes a first RC filtering circuit and a second RC filtering circuit; The first RC filter circuit includes a first resistor and a second capacitor. The first end of the first resistor is connected to the output terminal of the AND gate circuit, the second end of the first resistor is connected to the first end of the second capacitor, and the second end of the second capacitor is grounded. The second RC filter circuit includes a second resistor and a third capacitor. The first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is connected to the first end of the third capacitor and is used to output the DC voltage. The second end of the third capacitor is grounded.
[0016] This application also provides an energy storage power supply, including the drive frequency control circuit of any of the above embodiments.
[0017] The drive frequency control circuit of this application embodiment obtains the sampling voltage V1 on the output side and the drive voltage v-gs of the power transistor through a sampling circuit. The sampling voltage V1 is compared by a comparison circuit and a comparison signal V2 is output. For example, a zero-crossing comparison is performed to determine the zero-crossing point of the output current. An AND gate circuit outputs an AND signal V3 of the PWM waveform based on the drive voltage V1 and the comparison signal. The AND signal of the PWM waveform is then converted into a DC voltage Vadc by a filter circuit. Finally, the control circuit calculates the target drive frequency fsw based on the DC voltage Vadc and adjusts the drive frequency of the power transistor to the target drive frequency fsw. This allows the drive frequency of the power transistor to be adjusted to match the resonant frequency of the LLC resonant circuit, enabling the power transistor to achieve zero-voltage turn-on (ZVS) and zero-current turn-off (ZCS), thereby reducing the power transistor's losses. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of the power conversion circuit according to an embodiment of this application.
[0020] Figure 2 This is a schematic diagram of the power conversion circuit sampling the output current in an embodiment of this application.
[0021] Figure 3 This is a schematic diagram of the drive frequency control circuit according to an embodiment of this application.
[0022] Figure 4 This is a timing diagram of the driving voltage and output current of the power transistor in an embodiment of this application. Detailed Implementation
[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0024] This application provides a driving frequency control circuit for use in a power conversion circuit. The power conversion circuit can be used in an energy storage power supply to convert the voltage of the energy storage power supply and output it.
[0025] refer to Figure 1 , Figure 1 This is a schematic diagram of the power conversion circuit according to an embodiment of this application. The power conversion circuit includes an input side and an output side, which are coupled to each other through a transformer T1. The input side is used to input power, and after voltage conversion by the transformer T1, the output side outputs power to the load. The power conversion circuit can be an LLC resonant circuit. Figure 1 In the middle, L M L represents the magnetizing inductance of transformer T1. r C represents the resonant inductance. r i represents the resonant capacitor, and i-llc represents the output current.
[0026] The input side includes a power supply and power transistors. The power supply can be represented by capacitor C11, and can be, for example, a battery in an energy storage device or a photovoltaic cell. There can be multiple power transistors; for example, the input side can include four power transistors: S1, S2, S3, and S4. Power transistors S1, S2, S3, and S4 are all connected between the power supply C11 and the transformer T1. The power supply C11, power transistor S1, transformer T1, and power transistor S4 form one input loop, and the power supply C11, power transistor S3, transformer T1, and power transistor S2 form another input loop. For ease of description and explanation below, the specifications of power transistors S1, S2, S3, and S4 can be set to be the same, and the power transistors described below can refer to any one of power transistors S1, S2, S3, and S4.
[0027] The output side includes a rectifier circuit, which connects transformer T1 and the load, which can be represented as capacitor C12. The rectifier circuit includes multiple transistors, such as Q1, Q2, Q3, and Q4. Transistors Q1, Q2, Q3, and Q4 are all connected between transformer T1 and the load C12. Transformer T1, transistor Q1, load C12, and transistor Q4 form one power loop, while transformer T1, transistor Q2, load C12, and transistor Q3 form another power loop.
[0028] refer to Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of the power conversion circuit sampling the output current according to an embodiment of this application. Figure 3 This is a schematic diagram of the drive frequency control circuit according to an embodiment of this application. The drive frequency control circuit includes a sampling circuit 10, a comparison circuit 20, an AND gate circuit 30, a filter circuit 40, and a control circuit (not shown in the figure).
[0029] The sampling circuit 10 is connected to the output side of the power conversion circuit to sample the current i-llc on the output side and obtain the corresponding sampling voltage, which can be expressed as V1. In addition, the sampling circuit 10 is connected to the power transistor of the power conversion circuit (for example, any one of power transistors S1, S2, S3, and S4, and the same applies below, so it will not be described again). For example, it is connected to the driving terminal of the power transistor to obtain the driving voltage v-gs of the power transistor.
[0030] The comparator circuit 20 is connected to the sampling circuit 10 and is used to compare the sampled voltage V1 with the reference voltage, and output a comparison signal, which can be represented as V2. In practical applications, the reference voltage can be ground voltage, i.e., 0V voltage. The comparator circuit 20 performs a zero-crossing comparison on the sampled voltage V1 to determine the zero-crossing point of the output current i-llc.
[0031] AND gate 30 is connected to sampling circuit 10 and comparator circuit 20. It is used to input the driving voltage v-gs obtained by sampling circuit 10 and the comparison signal V2 output by comparator circuit 20, and outputs an AND signal based on driving voltage v-gs and comparison signal V2. The AND signal can be represented as V3. The AND signal V3 is the PWM wave.
[0032] The filter circuit 40 is connected to the AND gate circuit 30 and is used to filter the AND signal V3, converting the AND signal V3 of the PWM waveform into a DC voltage. The DC voltage can be represented as Vadc, which is the effective value of the voltage of the PWM wave (AND signal V3).
[0033] The control circuit is connected to the filter circuit 40. The control circuit receives the DC voltage Vadc output from the filter circuit 40, calculates the target drive frequency based on Vadc, and adjusts the drive frequency of the power transistor to the target drive frequency. In practical applications, the control circuit can be a controller for the power conversion circuit, such as a control chip.
[0034] The specific implementation of the embodiments of this application will be described in detail below.
[0035] In some embodiments, such as Figure 2 and Figure 3 As shown, the sampling circuit 10 includes a first sampling branch, a second sampling branch, and a charging branch.
[0036] The first sampling branch is connected to the output side of the power conversion circuit to sample the current i-llc at the output side and obtain the corresponding sampling voltage V1. In some embodiments, the first sampling branch includes a current transformer CT1, a first diode D1, and a first sampling resistor R1. The current transformer CT1 includes a primary winding and a secondary winding coupled to each other. The primary winding is connected in series with the output side of the power conversion circuit, such as... Figure 2 As shown. The primary winding carries the output current i-llc, which induces a corresponding current in the secondary winding. The anode of the first diode D1 is connected to the secondary winding of the current transformer CT1, for example, to one end of the secondary winding, while the other end of the secondary winding is grounded. The first terminal of the first sampling resistor R1 is connected to the cathode of the first diode D1 and is used to output the sampling voltage V1. The second terminal of the first sampling resistor R1 is grounded (i.e., connected to ground GND, as will be explained below). It is understood that the induced current generated by the current transformer through the output current i-llc flows back to ground through the first sampling resistor R1, thus generating a voltage across the first sampling resistor R1, which is the sampling voltage V1. This allows the current signal to be converted into a voltage signal V1 through the first sampling resistor R1.
[0037] The second sampling branch is used to connect to the drive terminal of the power transistor in the power conversion circuit to obtain the drive voltage v-gs of the power transistor. In some embodiments, the second sampling branch includes a second sampling resistor R2. The first terminal of the second sampling resistor R2 is connected to the drive terminal of the power transistor to obtain the drive voltage v-gs, and the second terminal of the second sampling resistor R2 is used to output the drive voltage v-gs. In practical applications, the drive voltage v-gs is either high or low (low level is 0V). A high level drives the power transistor to conduct, and a low level drives the power transistor to turn off.
[0038] A charging branch is connected between the first sampling branch and the second sampling branch. The charging branch includes an energy storage element. The driving voltage v-gs obtained from the second sampling branch is also used to charge the energy storage element. In some embodiments, the charging branch includes a second diode D2 and a first capacitor C1. The first capacitor C1 is the aforementioned energy storage element. The anode of the second diode D2 is connected to the second terminal of the second sampling resistor R2, the cathode of the second diode D2 is connected to the first terminal of the first capacitor C1, and the second terminal of the first capacitor C1 is connected to the first terminal of the first sampling resistor R1.
[0039] Understandably, in practical applications, when outputting a drive voltage v-gs to the drive terminal of the power transistor, the drive voltage v-gs will have a rising edge. During the rising edge, the voltage gradually increases and then reaches a stable voltage. When the drive voltage v-gs is at its rising edge, after being sampled by the second sampling resistor R2, it will charge the first capacitor C1, causing the first capacitor C1 to quickly obtain a voltage (i.e., a high level). When the drive voltage v-gs reaches a stable voltage, the first capacitor C1 will no longer continue to charge and will discharge through the ground resistor R2, releasing the voltage on the first capacitor C1.
[0040] Continue to refer to Figure 3 In some embodiments, the comparison circuit 20 includes a comparator U1A. The non-inverting input (+) of comparator U1A is connected to the sampling circuit 10, for example, to the first end of the first sampling resistor R1, and is used to input the sampling voltage V1. The inverting input (-) of comparator U1A is grounded; in this case, the ground level (0V) is the aforementioned reference voltage, therefore comparator U1A can be understood as a zero-crossing comparator. The output of comparator U1A is used to output the comparison signal V2. Furthermore, the positive power supply terminal v+ of comparator U1A is connected to the power supply VCC, and the negative power supply terminal v- is grounded.
[0041] Understandably, when the sampling voltage V1 is greater than the 0V reference voltage, the comparison signal V2 is high, which is the power supply voltage VCC. When the sampling voltage V1 is less than or equal to the 0V reference voltage, the comparison signal V2 is low, which is 0V.
[0042] In some embodiments, the comparison module 20 further includes a current-limiting resistor R3. The first terminal of the current-limiting resistor R3 is connected to the output terminal of the comparator U1A, and the second terminal of the current-limiting resistor R3 is used to output the aforementioned comparison signal V2. It is understood that the current-limiting resistor R3 can limit the magnitude of the output current, preventing a sudden large current from damaging subsequent devices (e.g., AND gate 30) or the output terminal of the comparator U1A.
[0043] In some embodiments, the AND gate circuit 30 includes an AND gate unit U2A. The first input terminal of the AND gate unit U2A is connected to the comparison module 20, for example, to the current-limiting resistor R3, and is used to input the comparison signal V2. The second input terminal of the AND gate unit U2A is connected to the sampling circuit 10, for example, to the second terminal of the second sampling resistor R2, and is used to input the driving voltage v-gs. The output terminal 1Y of the AND gate unit U2A is used to output the AND signal V3. Furthermore, the positive power supply terminal 1A of the AND gate unit U2A is connected to the power supply VCC, and the negative power supply terminal 1B is grounded.
[0044] Understandably, the AND signal V3 output by the AND gate unit U2A is high only when both the comparison signal V2 and the drive voltage v-gs are high; this high level corresponds to the power supply voltage VCC. When either the comparison signal V2 or the drive voltage v-gs is low, or both are low, the AND signal V3 is low (0V). Therefore, the AND signal V3 is a high-frequency alternating signal, i.e., a PWM wave.
[0045] In some embodiments, a resistor R4 is provided between the second input terminal of the AND gate unit U2A and the second sampling resistor R2. The resistor R4 can limit the current, thereby limiting the magnitude of the current and preventing excessive current from damaging subsequent devices (such as the AND gate unit U2A).
[0046] Continue to refer to Figure 3 In some embodiments, the filter circuit 40 includes a first RC filter circuit and a second RC filter circuit. The first RC filter circuit includes a first resistor R5 and a second capacitor C2. The first terminal of the first resistor R5 is connected to the output terminal of the AND gate circuit 3, for example, to the output terminal of the AND gate unit U2A. The second terminal of the first resistor R5 is connected to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 is grounded. The second RC filter circuit includes a second resistor R6 and a third capacitor C3. The first terminal of the second resistor R6 is connected to the second terminal of the first resistor R5. The second terminal of the second resistor R6 is connected to the first terminal of the third capacitor C3 and is used to output a DC voltage Vadc. The second terminal of the third capacitor C3 is grounded.
[0047] Understandably, in the example above, the filter circuit 40 is a second-order RC filter circuit. In practical applications, by adjusting the RC values (i.e., the resistance values of the first resistor R5 / the second resistor R6, and the capacitance values of the second capacitor C2 / the third capacitor C3), the RC cutoff frequency of the filter circuit 40 can be made much smaller than the driving frequency of the power transistor (i.e., the frequency of the driving voltage V-gs). In this way, the high-frequency AND signal V3 can be filtered into a DC signal Vadc, which is convenient for subsequent control circuits to sample and process.
[0048] The following is in conjunction with the appendix Figure 4 The working principle of the drive frequency control circuit in the embodiments of this application will be explained. Figure 4 This is a timing diagram showing the driving voltage and output current of the power transistor in an embodiment of this application. Figure 4 In this context, v-gs represents the drive voltage of the power transistor, and i-llc represents the current on the output side of the power conversion circuit.
[0049] It should be noted first that in practical applications, due to the Miller effect, there is a delay between the moment the power transistor's drive signal v-gs is emitted (the drive unit emits the drive signal v-gs to drive the power transistor) and the actual turn-on time of the power transistor. This delay time can be expressed as td(on). For each specific power transistor, its delay time td(on) is fixed and recorded in the device datasheet. Therefore, this delay time td(on) can be obtained by consulting the power transistor's device datasheet.
[0050] Figure 4 In the diagram, t1 represents the moment when the drive signal v-gs of the power transistor is emitted during the positive half-cycle. At this time, v-gs is at a high level, and since the power transistor is not actually turned on, the current i-llc is 0. t2 represents the moment when the power transistor is actually turned on during the positive half-cycle. At this time, the current i-llc begins to gradually increase, and then the current i-llc conforms to the sinusoidal waveform of the positive half-cycle. After reaching its maximum value, the current i-llc gradually decreases. t3 represents the moment when the resonant current of the LLC resonant circuit crosses zero during the positive half-cycle. At this time, v-gs is still at a high level, and the current i-llc decreases to 0. Subsequently, the current i-llc becomes negative (i.e., in the opposite direction). t4 represents the moment when the drive signal v-gs of the power transistor is turned off during the positive half-cycle. At this time, v-gs becomes low, and the current i-llc is negative. t5 represents the moment when the drive signal v-gs of the power transistor is emitted during the negative half-cycle.
[0051] The interval t2-t1 represents the aforementioned delay time td(on). During the t2-t1 interval, the drive signal v-gs begins to be emitted, and v-gs is at a high level. At this time, the power transistor is not yet actually turned on, and the current i-llc is 0. The drive signal v-gs has a rising edge at the beginning of its emission. During this rising edge, the gradually increasing drive signal v-gs charges the first capacitor C1, causing the sampling voltage V1 to quickly reach a high level. Once the drive signal v-gs reaches a stable voltage, the first capacitor C1 stops charging and discharges through the ground resistor R2. This discharge process continues until the power transistor is actually turned on, i.e., after time t2. Therefore, the sampling voltage V1 remains high throughout the t2-t1 interval. Consequently, during the t2-t1 interval, the comparison signal V2 is high, ensuring that the high-level output start point of the comparison signal V2 coincides with the high-level output start point of the drive signal v-gs. Since both the comparison signal V2 and the drive signal v-gs are at high levels, signal V3 is at a high level during the t2-t1 interval.
[0052] During the t3-t2 interval, the resonant inductor and resonant capacitor resonate, and the current i-llc gradually increases from 0A to its maximum value, then gradually decreases back to 0A, which is exactly half a cycle of LC resonance. Its waveform conforms to a sine wave with a positive half-cycle. The duration of t3-t2 can be expressed as 0.5*t(llc), where t(llc) represents the resonant period of LC resonance. During the t3-t2 interval, the current i-llc is greater than 0, and the corresponding sampling voltage V1 is also greater than 0 (i.e., high level). Therefore, the comparison signal V2 is also high level. In addition, the drive signal v-gs is high level, so the signal V3 is high level during the t3-t2 interval.
[0053] The interval t4-t3 is the time from the resonant current crossing zero to the power transistor's drive signal turning off during the positive half-cycle. This zero-crossing reversal time should be minimized in practical applications. During the t4-t3 interval, the current i-llc is less than 0 (i.e., the current i-llc is reversed). At this time, the first diode D1 is cut off, so the sampling voltage V1 is low (0V), and the comparison signal V2 is also low (0V). Therefore, the comparison signal V3 is low (0V) during the t4-t3 interval.
[0054] The interval t5-t4 represents the time between the power transistor's drive signal being turned off during the positive half-cycle and the drive signal being emitted during the negative half-cycle. This interval is the dead time of the drive signal v-gs, which can be expressed as t(die). During this time, the drive signal v-gs is at a low level (0V), the power transistor is off, the current i-llc is 0, the sampling voltage V1 is at a low level (0V), and the comparison signal V2 is also at a low level (0V). Therefore, during the t5-t4 interval, the signal V3 is at a low level (0V).
[0055] Therefore, in summary, within the t3-t1 interval, signal V3 is at a high level, which is the power supply voltage VCC; within the t5-t3 interval, signal V3 is at a low level (0V). Signal V3 is a high-frequency PWM wave, and the PWM wave mentioned below refers to signal V3.
[0056] Based on the above analysis, the LC resonant frequency fllc of the power conversion circuit is given by the following equation: In addition, the zero-crossing reverse time t4-t3 should be minimized as much as possible. When this zero-crossing reverse time is 0, the ideal power transistor drive frequency fsw is expressed by the following relationship: In practical applications, the delay time td(on) is not easy to measure. Based on the above analysis, td(on) + 0.5*t(llc) is the duration of t3-t1, which can be expressed as t(half), the time from the issuance of the power transistor's drive signal during the positive half-cycle to the zero-crossing of the resonant current. Therefore, the power transistor's drive frequency fsw can also be expressed as the following equation: On the other hand, the DC voltage Vadc (the effective voltage value of the PWM wave) output by the filter circuit can be sampled by the control circuit to obtain its effective voltage value (the effective voltage value can be expressed as Vadc). The duty cycle D of the PWM wave is the ratio of the effective value of the DC voltage Vadc to the power supply voltage VCC of the AND gate circuit. That is, the duty cycle D can be expressed as the following relationship: The resonant current i-llc comes from the drive control of the power transistor. Therefore, the period of the PWM wave (with the period of signal V3) is the same as the drive period T of the power transistor. Thus, combining Equation 4, we can obtain the following Equation 5: Combining relation three and relation five above, we can obtain the following relation six: In the above relation 6, fsw is the target driving frequency (i.e., the driving frequency that the power transistor needs to be adjusted to), VCC is the power supply voltage of AND gate circuit 30, Vadc is the amplitude of DC voltage Vadc output by filter circuit 40, T is the period of AND signal V3 output by AND gate circuit 30 (which is also the driving period of the power transistor), and t(die) is the dead time of the driving signal of the power transistor.
[0057] Therefore, the control circuit can calculate the target drive frequency fsw based on the above equation six. After obtaining the target drive frequency fsw, the control circuit can control the drive unit to adjust the drive frequency of the power transistor to the target drive frequency fsw.
[0058] The drive frequency control circuit of this application embodiment obtains the sampling voltage V1 on the output side and the drive voltage v-gs of the power transistor through a sampling circuit. The sampling voltage V1 is compared by a comparison circuit and a comparison signal V2 is output. For example, a zero-crossing comparison is performed to determine the zero-crossing point of the output current. An AND gate circuit outputs an AND signal V3 of the PWM waveform based on the drive voltage V1 and the comparison signal. The AND signal of the PWM waveform is then converted into a DC voltage Vadc by a filter circuit. Finally, the control circuit calculates the target drive frequency fsw based on the DC voltage Vadc and adjusts the drive frequency of the power transistor to the target drive frequency fsw. This allows the drive frequency of the power transistor to be adjusted to match the resonant frequency of the LLC resonant circuit, enabling the power transistor to achieve zero-voltage turn-on (ZVS) and zero-current turn-off (ZCS), thereby reducing the power transistor's losses.
[0059] This application also provides an energy storage power supply, which includes the drive frequency control circuit of any of the above embodiments.
[0060] In the description of this application, it should be understood that terms such as “first” and “second” are used only to distinguish similar objects and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.
[0061] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.
[0062] The driving frequency control circuit and energy storage power supply provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application, and the descriptions of the embodiments above are only for the purpose of helping to understand this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A driving frequency control circuit, characterized in that, This circuit is applied to a power conversion circuit, which includes an input side and an output side, wherein the input side and the output side are coupled to each other via a transformer. The input side includes a power transistor, and the drive frequency control circuit includes: A sampling circuit is used to connect to the output side and the power transistor to sample the current of the output side and obtain the corresponding sampling voltage, as well as to obtain the driving voltage of the power transistor; A comparison circuit, connected to the sampling circuit, is used to compare the sampled voltage with a reference voltage and output a comparison signal; An AND gate circuit, connected to the sampling circuit and the comparison circuit, is used to output an AND signal based on the driving voltage and the comparison signal; A filter circuit, connected to the AND gate circuit, is used to convert the AND signal into a DC voltage; A control circuit, connected to the filter circuit, is used to calculate the target drive frequency based on the DC voltage and adjust the drive frequency of the power transistor to the target drive frequency.
2. The driving frequency control circuit according to claim 1, characterized in that, The control circuit calculates the target driving frequency according to the following formula: Where fsw is the target driving frequency, VCC is the power supply voltage of the AND gate circuit, Vadc is the amplitude of the DC voltage, T is the period of the AND signal, and t(die) is the dead time of the driving signal of the power transistor.
3. The driving frequency control circuit according to claim 1, characterized in that, The sampling circuit includes: The first sampling branch is used to connect to the output side to sample the current of the output side and obtain the corresponding sampling voltage; The second sampling branch is used to connect to the driving terminal of the power transistor to obtain the driving voltage of the power transistor; A charging branch is connected between the first sampling branch and the second sampling branch. The charging branch includes an energy storage element, and the driving voltage is also used to charge the energy storage element.
4. The driving frequency control circuit according to claim 3, characterized in that, The first sampling branch includes: A current transformer includes a primary winding and a secondary winding coupled to each other, wherein the primary winding is connected in series on the output side; The anode of the first diode is connected to the secondary winding; A first sampling resistor, the first end of which is connected to the cathode of the first diode and used to output the sampling voltage, and the second end of which is grounded.
5. The driving frequency control circuit according to claim 4, characterized in that, The second sampling branch includes a second sampling resistor. The first end of the second sampling resistor is used to connect to the driving end of the power transistor, and the second end of the second sampling resistor is used to output the driving voltage.
6. The driving frequency control circuit according to claim 5, characterized in that, The charging branch includes a second diode and a first capacitor. The anode of the second diode is connected to the second terminal of the second sampling resistor, the cathode of the second diode is connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is connected to the first terminal of the first sampling resistor.
7. The driving frequency control circuit according to claim 1, characterized in that, The comparison circuit includes a comparator, the non-inverting input of which is connected to the sampling circuit for inputting the sampling voltage, the inverting input of which is grounded, and the output of which is used to output the comparison signal.
8. The driving frequency control circuit according to claim 7, characterized in that, The comparison module further includes a current-limiting resistor, the first end of which is connected to the output terminal of the comparator, and the second end of which is used to output the comparison signal.
9. The driving frequency control circuit according to claim 1, characterized in that, The filtering circuit includes a first RC filtering circuit and a second RC filtering circuit; The first RC filter circuit includes a first resistor and a second capacitor. The first end of the first resistor is connected to the output terminal of the AND gate circuit, the second end of the first resistor is connected to the first end of the second capacitor, and the second end of the second capacitor is grounded. The second RC filter circuit includes a second resistor and a third capacitor. The first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is connected to the first end of the third capacitor and is used to output the DC voltage. The second end of the third capacitor is grounded.
10. An energy storage power source, characterized in that, Includes the drive frequency control circuit as described in any one of claims 1 to 9.