A DCM mode constant frequency control method and system for a BUCK-BOOST converter
By monitoring the operating status in the BUCK-BOOST converter and switching to the constant frequency peak current control mode, the problem of increased output voltage ripple caused by frequency changes in DCM mode is solved, achieving the effects of constant frequency and low ripple.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU SILICON SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2026-03-06
- Publication Date
- 2026-06-02
Smart Images
Figure CN122137207A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of BUCK-BOOST converter operating mode control technology, and in particular to a DCM mode constant frequency control method and system for BUCK-BOOST converters. Background Technology
[0002] The four-switch BUCK-BOOST converter differs from traditional BUCK or BOOST circuits in that it smoothly transforms the input voltage into a stable output voltage, whether high or low. BUCK converters have two common operating modes: Continuous On-Cycle (CCM): The inductor current remains greater than zero throughout the entire switching cycle. This is the most common mode and is suitable for medium to high loads. Discontinuous On-Cycle (DCM): The inductor current drops to zero for a period before the end of the switching cycle and remains zero until the end of the cycle. DCM typically occurs under light load or no-load conditions.
[0003] COT (Cross-Track Current Sampling) is a hysteresis-based frequency converter control method. It determines when to start the next cycle by setting a fixed on-time of the upper transistor and comparing the inductor current at its valley point with the error amplifier output. For a COT-controlled BUCK-BOOST converter with valley current sampling, after entering DCM mode, due to excess energy, all power transistors will be turned off after a certain switching cycle, causing the inductor current to be zero for a period, waiting for the system to turn the upper transistor back on and restart the switching cycle. During this time, the frequency changes, failing to meet the system's constant frequency requirement. Furthermore, due to the frequency change, the output voltage ripple of the BUCK circuit will increase.
[0004] Therefore, a DCM mode constant frequency control method and system for BUCK-BOOST converter was developed to solve the above problems. Summary of the Invention
[0005] This invention proposes a constant frequency control method and system for DCM mode of BUCK-BOOST converter to solve the problem that the frequency of the existing COT valley current sampling control BUCK circuit changes in DCM mode, resulting in increased output voltage ripple.
[0006] The present invention achieves the above objectives through the following technical solutions: This invention provides a DCM mode constant frequency control method for a BUCK-BOOST converter, comprising: Obtain the mode switching signal for the BUCK-BOOST converter to enter DCM mode and BUCK mode; In response to a mode switching signal, a mode switching command is generated; In response to the mode switching command, the control mode of the BUCK-BOOST converter switching transistor is switched from valley current sampling control mode to constant frequency peak current control mode.
[0007] Furthermore, the mode switching signals for the BUCK-BOOST converter to enter DCM mode and BUCK mode are acquired, including: Monitor the operating status of the BUCK-BOOST converter; When the BUCK-BOOST converter control system is detected to enter DCM mode, a corresponding enable signal is generated, and the DCM signal is obtained. When the BUCK-BOOST converter control system detects that it has entered BUCK mode, a corresponding enable signal is generated, resulting in the BUCK_MOD signal.
[0008] Furthermore, in response to the mode switching signal, a mode switching command is generated, including: The DCM signal and the BUCK_MOD signal are passed through the first NAND gate to obtain the EN_N_DCM signal. The EN_N_DCM signal is then passed through the first inverter to obtain the EN_P_DCM signal. Obtain the enable signal of the upper transistor HS1 in the BUCK-BOOST converter to obtain the HG_BUCK signal; The HG_BUCK signal and the EN_N_DCM signal are passed through a second NAND gate and a second inverter to obtain the RESET_DCM signal; The HG_BUCK signal and the EN_P_DCM signal are passed through the third NAND gate and the third inverter to obtain the SET_DCM signal; The SET_DCM signal and the RESET_DCM signal are passed through a NOR gate and a fourth inverter to obtain the BUCK_DCM_N signal. Then, the BUCK_DCM_N signal is passed through a fifth inverter to obtain the BUCK_DCM signal.
[0009] Furthermore, in response to the mode switching command, the control mode of the BUCK-BOOST converter switching transistor is switched from the valley current sampling control mode to the constant frequency peak current control mode, including: The output signal PWM_OUT_TOFF of the PWM comparator for valley current sampling, the fixed clock CLK generated internally by the system in BUCK DCM mode, the output signal TON_TIMER of the constant on-time module for valley current sampling, and the output signal PWM_OUT_TON of the PWM comparator in peak current control mode are obtained. PWM_OUT_TOFF, CLK, and BUCK_DCM_N are used to obtain TON_BUCK through a two-to-one multiplexer. TON_TIMER, PWM_OUT_TON, and BUCK_DCM_N are used to obtain TOFF_BUCK through a two-to-one multiplexer. When TON_BUCK=1, the Buck high-side switch in the BUCK-BOOST converter is turned on and the Buck low-side switch is turned off. When TOFF_BUCK=1, the Buck high-side switch in the BUCK-BOOST converter is turned off and the Buck low-side switch is turned on. The inductor current decreases. When the system is operating in the BUCK mode of DCM, the Boost high-side switch and Boost low-side switch are kept off.
[0010] The present invention also provides a DCM mode constant frequency control system for a BUCK-BOOST converter, comprising: The acquisition module is used to acquire the mode switching signal of the BUCK-BOOST converter entering DCM mode and BUCK mode; The instruction module is used to generate a mode switching instruction in response to a mode switching signal; The switching module is used to switch the control mode of the BUCK-BOOST converter switching transistor from valley current sampling control mode to constant frequency peak current control mode in response to the mode switching command.
[0011] Furthermore, the acquisition module includes: The monitoring module is used to monitor the operating status of the BUCK-BOOST converter; The first generation module is used to generate a corresponding enable signal and obtain a DCM signal when the BUCK-BOOST converter control system is detected to enter DCM mode. The second generation module is used to generate a corresponding enable signal and obtain the BUCK_MOD signal when the BUCK-BOOST converter control system is detected to enter BUCK mode.
[0012] Furthermore, the instruction module includes a first instruction module and a second instruction module, wherein: The first instruction module includes: The first NAND gate is used to process the DCM signal and the BUCK_MOD signal to obtain the EN_N_DCM signal; The first inverter is used to process the EN_N_DCM signal to obtain the EN_P_DCM signal. The second instruction module includes: The first signal acquisition module is used to acquire the turn-on signal of the upper transistor HS1 in the BUCK-BOOST converter and obtain the HG_BUCK signal. The second NAND gate is used to process the HG_BUCK signal and the EN_N_DCM signal; The second inverter is used to process the output of the second NAND gate to obtain the RESET_DCM signal; A third NAND gate is used to process the HG_BUCK signal and the EN_P_DCM signal. The third inverter is used to process the output of the third NAND gate to obtain the SET_DCM signal; NOR gate, which is used to process the SET_DCM signal and the RESET_DCM signal; The fourth inverter is used to process the output of the NOR gate to obtain the BUCK_DCM_N signal; The fifth inverter is used to process the BUCK_DCM_N signal to obtain the BUCK_DCM signal.
[0013] Furthermore, the switching module includes: The second signal acquisition module is used to acquire the output signal PWM_OUT_TOFF of the PWM comparator for valley current sampling, the fixed clock CLK generated internally by the DCM mode system of BUCK, the output signal TON_TIMER of the constant on-time module for valley current sampling, and the output signal PWM_OUT_TON of the PWM comparator for peak current control mode. The first two-to-one logic gate is used to process PWM_OUT_TOFF, CLK and BUCK_DCM_N to obtain TON_BUCK; The second 2-to-1 logic gate is used to process TON_TIMER, PWM_OUT_TON and BUCK_DCM_N to obtain TOFF_BUCK; Specifically, when TON_BUCK=1, the Buck high-side switch in the BUCK-BOOST converter is turned on and the Buck low-side switch is turned off. When TOFF_BUCK=1, the Buck high-side switch in the BUCK-BOOST converter is turned off and the Buck low-side switch is turned on, the inductor current decreases, and when the system is operating in the BUCK mode of DCM, the Boost high-side switch and Boost low-side switch are kept off.
[0014] The beneficial effects of this invention are as follows: This invention proposes a DCM mode constant frequency control method and system for a BUCK-BOOST converter, which transforms the system into a peak current control mode. In this mode, the system frequency is determined by an internally generated fixed clock, thereby achieving a constant frequency effect. Furthermore, the peak value of the inductor current in each cycle decreases as the load decreases, ensuring energy utilization and thus reducing output voltage ripple. Attached Figure Description
[0015] Figure 1 This is a control logic diagram of the first instruction module in an embodiment of this application; Figure 2 This is the control logic diagram of the second instruction module in the embodiments of this application; Figure 3 This is the control logic diagram of the first two-to-one multiplexer in the embodiments of this application; Figure 4 This is the control logic diagram of the second two-to-one multiplexer in the embodiments of this application; Figure 5 This is a schematic diagram of the circuit structure of the Buck high-side switch in the open state in an embodiment of this application; Figure 6 This is a schematic diagram of the circuit structure of the Buck low-side switch in the on state in an embodiment of this application; Figure 7 A schematic diagram of the circuit structure of a BUCK-BOOST converter; Figure 8 This is a schematic diagram of the inductor current variation curve with load in a BUCK circuit under peak current control mode. Detailed Implementation
[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0017] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0018] Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.
[0019] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0020] This invention provides a DCM mode constant frequency control method for a BUCK-BOOST converter, comprising: Obtain the mode switching signal for the BUCK-BOOST converter to enter DCM mode and BUCK mode; In response to a mode switching signal, a mode switching command is generated; In response to the mode switching command, the control mode of the BUCK-BOOST converter switching transistor is switched from valley current sampling control mode to constant frequency peak current control mode.
[0021] Furthermore, the mode switching signals for the BUCK-BOOST converter to enter DCM mode and BUCK mode are acquired, including: Monitor the operating status of the BUCK-BOOST converter; When the BUCK-BOOST converter control system is detected to enter DCM mode, a corresponding enable signal is generated, and the DCM signal is obtained. When the BUCK-BOOST converter control system detects that it has entered BUCK mode, a corresponding enable signal is generated, resulting in the BUCK_MOD signal.
[0022] Furthermore, in response to the mode switching signal, a mode switching command is generated, including: The DCM signal and the BUCK_MOD signal are passed through the first NAND gate to obtain the EN_N_DCM signal. The EN_N_DCM signal is then passed through the first inverter to obtain the EN_P_DCM signal. Obtain the enable signal of the upper transistor HS1 in the BUCK-BOOST converter to obtain the HG_BUCK signal; The HG_BUCK signal and the EN_N_DCM signal are passed through a second NAND gate and a second inverter to obtain the RESET_DCM signal; The HG_BUCK signal and the EN_P_DCM signal are passed through the third NAND gate and the third inverter to obtain the SET_DCM signal; The SET_DCM signal and the RESET_DCM signal are passed through a NOR gate and a fourth inverter to obtain the BUCK_DCM_N signal. Then, the BUCK_DCM_N signal is passed through a fifth inverter to obtain the BUCK_DCM signal.
[0023] Furthermore, in response to the mode switching command, the control mode of the BUCK-BOOST converter switching transistor is switched from the valley current sampling control mode to the constant frequency peak current control mode, including: The output signal PWM_OUT_TOFF of the PWM comparator for valley current sampling, the fixed clock CLK generated internally by the system in BUCK DCM mode, the output signal TON_TIMER of the constant on-time module for valley current sampling, and the output signal PWM_OUT_TON of the PWM comparator in peak current control mode are obtained. PWM_OUT_TOFF, CLK, and BUCK_DCM_N are used to obtain TON_BUCK through a two-to-one multiplexer. TON_TIMER, PWM_OUT_TON, and BUCK_DCM_N are used to obtain TOFF_BUCK through a two-to-one multiplexer. When TON_BUCK=1, the Buck high-side switch in the BUCK-BOOST converter is turned on and the Buck low-side switch is turned off. When TOFF_BUCK=1, the Buck high-side switch in the BUCK-BOOST converter is turned off and the Buck low-side switch is turned on. The inductor current decreases. When the system is operating in the BUCK mode of DCM, the Boost high-side switch and Boost low-side switch are kept off.
[0024] The present invention also provides a DCM mode constant frequency control system for a BUCK-BOOST converter, comprising: The acquisition module is used to acquire the mode switching signal of the BUCK-BOOST converter entering DCM mode and BUCK mode; The instruction module is used to generate a mode switching instruction in response to a mode switching signal; The switching module is used to switch the control mode of the BUCK-BOOST converter switching transistor from valley current sampling control mode to constant frequency peak current control mode in response to the mode switching command.
[0025] Furthermore, the acquisition module includes: The monitoring module is used to monitor the operating status of the BUCK-BOOST converter; The first generation module is used to generate a corresponding enable signal and obtain a DCM signal when the BUCK-BOOST converter control system is detected to enter DCM mode. The second generation module is used to generate a corresponding enable signal and obtain the BUCK_MOD signal when the BUCK-BOOST converter control system is detected to enter BUCK mode.
[0026] Furthermore, the instruction module includes a first instruction module and a second instruction module, wherein: The first instruction module includes: The first NAND gate is used to process the DCM signal and the BUCK_MOD signal to obtain the EN_N_DCM signal; The first inverter is used to process the EN_N_DCM signal to obtain the EN_P_DCM signal. The second instruction module includes: The first signal acquisition module is used to acquire the turn-on signal of the upper transistor HS1 in the BUCK-BOOST converter and obtain the HG_BUCK signal. The second NAND gate is used to process the HG_BUCK signal and the EN_N_DCM signal; The second inverter is used to process the output of the second NAND gate to obtain the RESET_DCM signal; A third NAND gate is used to process the HG_BUCK signal and the EN_P_DCM signal. The third inverter is used to process the output of the third NAND gate to obtain the SET_DCM signal; NOR gate, which is used to process the SET_DCM signal and the RESET_DCM signal; The fourth inverter is used to process the output of the NOR gate to obtain the BUCK_DCM_N signal; The fifth inverter is used to process the BUCK_DCM_N signal to obtain the BUCK_DCM signal.
[0027] Furthermore, the switching module includes: The second signal acquisition module is used to acquire the output signal PWM_OUT_TOFF of the PWM comparator for valley current sampling, the fixed clock CLK generated internally by the DCM mode system of BUCK, the output signal TON_TIMER of the constant on-time module for valley current sampling, and the output signal PWM_OUT_TON of the PWM comparator for peak current control mode. The first two-to-one logic gate is used to process PWM_OUT_TOFF, CLK and BUCK_DCM_N to obtain TON_BUCK; The second 2-to-1 logic gate is used to process TON_TIMER, PWM_OUT_TON and BUCK_DCM_N to obtain TOFF_BUCK; Specifically, when TON_BUCK=1, the Buck high-side switch in the BUCK-BOOST converter is turned on and the Buck low-side switch is turned off. When TOFF_BUCK=1, the Buck high-side switch in the BUCK-BOOST converter is turned off and the Buck low-side switch is turned on, the inductor current decreases, and when the system is operating in the BUCK mode of DCM, the Boost high-side switch and Boost low-side switch are kept off.
[0028] like Figure 7 The diagram shows the circuit topology of a BUCK-BOOST converter, where HS2, LS2, HS1, and LS1 represent the Boost high-side switch, Boost low-side switch, Buck high-side switch, and Buck low-side switch, respectively. The BUCK-BOOST converter uses the existing structure. CL and RL are the output capacitor and output load resistor, respectively. When the system operates in BUCK's CCM mode, HS2 is always on and LS2 is always off. When TON_BUCK=1, LS1 is off and HG1 is on; when TON_BUCK=0, HS1 is off and LG1 is on. When the system operates in BUCK's DCM mode, HS2 and LS2 are always off. When TON_BUCK=1, LS1 is off and HG1 is on; when TON_BUCK=0, HS1 is off and LG1 is on.
[0029] like Figure 1-4 As shown, for the first instruction module, the processing procedure is as follows: the DCM signal and the BUCK_MOD signal are passed through a NAND gate and an inverter to obtain the EN_N_DCM signal and the EN_P_DCM signal, where the DCM signal is the enable signal for the system to enter the DCM mode, and the BUCK_MOD signal is the enable signal for the system to enter the BUCK mode.
[0030] For the second instruction module, the processing procedure is as follows: The HG_BUCK signal and the EN_N_DCM signal are processed by a NAND gate and an inverter to obtain the RESET_DCM signal. The HG_BUCK signal and the EN_P_DCM signal are processed by a NAND gate and an inverter to obtain the SET_DCM signal. The SET_DCM signal and the RESET_DCM signal are processed by a NOR gate and an inverter to obtain the BUCK_DCM_N and BUCK_DCM signals. Here, HG_BUCK is the enable signal for the upper transistor HS1. BUCK_DCM=1 indicates that the system has entered the BUCK DCM mode.
[0031] For the switching module, the processing procedure is as follows: PWM_OUT_TOFF, CLK, and BUCK_DCM_N are used to obtain TON_BUCK through a two-to-one multiplexer. TON_TIMER, PWM_OUT_TON, and BUCK_DCM_N are used to obtain TOFF_BUCK through a two-to-one multiplexer.
[0032] In this configuration, HG_BUCK, after being driven, serves as the enable signal for the upper transistor. PWM_OUT_TOFF is the output signal of the PWM comparator for valley current sampling, used to enable the upper transistor HS1 and disable the lower transistor LS1, causing the inductor current to rise. CLK is an internally generated fixed clock used to ensure a constant frequency in the peak current control mode. TON_TIMER is the output of the constant on-time module for valley current sampling, used to ensure a constant charging time for BUCK in each cycle. PWM_OUT_TON is the output signal of the PWM comparator for peak current control mode, used to disable the upper transistor HS1 and enable the lower transistor LS1, causing the inductor current to decrease. When TON_BUCK=1, the upper transistor HS1 is enabled and the lower transistor LS1 is disabled after being driven, causing the inductor current to rise. When TOFF_BUCK=1, the upper transistor HS1 is disabled and the lower transistor LS1 is enabled after being driven, causing the inductor current to decrease. When the system operates in DCM BUCK mode, transistors HS2 and LS2 are normally off.
[0033] Specific working principle: When the system operates in CCM mode, the load begins to decrease. When the inductor current valley value drops to near zero current, the system switches to DCM mode. At this time, DCM=1 and BUCK_MOD=1, EN_N_DCM=0, EN_P_DCM=1, RESET_DCM=0, waiting for the rising edge of the BUCK upper transistor to trigger. When HG_BUCK=1, SET_DCM=1, and the system enters BUCK_DCM mode, BUCK_DCM=1. After entering BUCK_DCM mode, the output of the two-to-one multiplexer module changes. TON_BUCK changes from PWM_OUT_TOFF to CLK, and TOFF_BUCK changes from TON_TIMER to PWM_OUT_TON. This completes the transition from COT valley current sampling control mode to peak current mode control mode. Simultaneously, This invention uses a novel logic control method to achieve the transition from DCM control mode in BUCK mode. The BUCK_DCM signal is used as the enable signal for the two-to-one module to switch the signal controlling the power transistor switch, thereby achieving the transition from COT valley current sampling control mode to peak current mode control mode in DCM mode, and realizing the purpose of constant frequency and low ripple.
[0034] Upon entering DCM, the system shuts down the alternating switches HS2, LS2, HS1, and LS1. The power transistors turned off at this time are equivalent to parasitic diodes, and their circuit topology is shown below. Figure 5 and Figure 6 As shown. Among them. Figure 5 HS1 is enabled. Figure 6 LS1 is enabled.
[0035] like Figure 8 As shown, as the load current L decreases, the peak inductor current decreases accordingly. When the inductor current drops to 0mA, SW2 starts to decrease from VOUT+0.7V. When VSW2=0V, the inductor current slope begins to rise. At this time, since the inductor current is negative, the voltage VSW2 will continue to drop to -0.7V. At this point, VSW1=0V, and the inductor current rising slope K is: ; The change in inductor current stops after the CLK clock is triggered, and a new cycle begins. Because of the presence of an internal fixed clock, the peak current mode is constant in DCM. Furthermore, because the peak inductor current decreases as the load decreases, the energy utilization rate is higher than that of COT valley current sampling, resulting in smaller output voltage ripple.
[0036] like Figure 8 As shown, IL_ON1 and IL_ON2 are the peak values of the inductor current, TSW1 is the CCM mode switching cycle (critical DCM mode), and IO1, represented by the black line, is the load current in CCM mode. The average inductor current equals the load current, so IL_ON1 = 2 * IO1. CCM is the COT mode, with the on-time of the upper transistor HG1 ton = K1 / RT * (VOUT / VIN) and the duty cycle D = VOUT / VIN, resulting in TSW1 = ton / D = K1 / RT. K1 is an internal system parameter, and RT is the resistor used to set the frequency. TSW2 is the DCM mode switching cycle, and IO2, represented by the red line, is the load current in CCM mode. The load current in CM mode is equal to the average inductor current over the TSW2 cycle. IL_ON2 is the peak inductor current in DCM mode, determined by the load current IO2. The smaller the load, the smaller the peak inductor current. Since the inductor current in DCM mode is negative for a portion of the time, the average inductor current over the TSW2 cycle is even smaller, resulting in system stability under a lower load current IO2. TSW2 is equal to the cycle of CLK, so TSW2 = K2 / RT, where K2 is an internal system parameter and RT is the resistor used to set the frequency. Setting K1 = K2 achieves TSW1 = TSW2, enabling constant frequency in both DCM and CCM modes.
[0037] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A constant frequency control method in DCM mode for a BUCK-BOOST converter, characterized in that, include: Obtain the mode switching signal for the BUCK-BOOST converter to enter DCM mode and BUCK mode; In response to a mode switching signal, a mode switching command is generated; In response to the mode switching command, the control mode of the BUCK-BOOST converter switching transistor is switched from valley current sampling control mode to constant frequency peak current control mode.
2. The DCM mode constant frequency control method for a BUCK-BOOST converter according to claim 1, characterized in that, Obtain the mode switching signals for the BUCK-BOOST converter to enter DCM mode and BUCK mode, including: Monitor the operating status of the BUCK-BOOST converter; When the BUCK-BOOST converter control system is detected to enter DCM mode, a corresponding enable signal is generated, and the DCM signal is obtained. When the BUCK-BOOST converter control system detects that it has entered BUCK mode, a corresponding enable signal is generated, resulting in the BUCK_MOD signal.
3. The DCM mode constant frequency control method for a BUCK-BOOST converter according to claim 2, characterized in that, In response to a mode switching signal, a mode switching command is generated, including: The DCM signal and the BUCK_MOD signal are passed through the first NAND gate to obtain the EN_N_DCM signal. The EN_N_DCM signal is then passed through the first inverter to obtain the EN_P_DCM signal. Obtain the enable signal of the upper transistor HS1 in the BUCK-BOOST converter to obtain the HG_BUCK signal; The HG_BUCK signal and the EN_N_DCM signal are passed through a second NAND gate and a second inverter to obtain the RESET_DCM signal; The HG_BUCK signal and the EN_P_DCM signal are passed through the third NAND gate and the third inverter to obtain the SET_DCM signal; The SET_DCM signal and the RESET_DCM signal are passed through a NOR gate and a fourth inverter to obtain the BUCK_DCM_N signal. Then, the BUCK_DCM_N signal is passed through a fifth inverter to obtain the BUCK_DCM signal.
4. The DCM mode constant frequency control method for a BUCK-BOOST converter according to claim 3, characterized in that, In response to a mode switching command, the control mode for the BUCK-BOOST converter switching transistors is switched from valley current sampling control mode to constant frequency peak current control mode, including: The output signal PWM_OUT_TOFF of the PWM comparator for valley current sampling, the fixed clock CLK generated internally by the system in BUCK DCM mode, the output signal TON_TIMER of the constant on-time module for valley current sampling, and the output signal PWM_OUT_TON of the PWM comparator in peak current control mode are obtained. PWM_OUT_TOFF, CLK, and BUCK_DCM_N are used to obtain TON_BUCK through a two-to-one multiplexer. TON_TIMER, PWM_OUT_TON, and BUCK_DCM_N are used to obtain TOFF_BUCK through a two-to-one multiplexer. When TON_BUCK=1, the Buck high-side switch in the BUCK-BOOST converter is turned on and the Buck low-side switch is turned off. When TOFF_BUCK=1, the Buck high-side switch in the BUCK-BOOST converter is turned off and the Buck low-side switch is turned on. The inductor current decreases. When the system is operating in the BUCK mode of DCM, the Boost high-side switch and Boost low-side switch are kept off.
5. A DCM mode constant frequency control system for a BUCK-BOOST converter, characterized in that, include: The acquisition module is used to acquire the mode switching signal of the BUCK-BOOST converter entering DCM mode and BUCK mode; The instruction module is used to generate a mode switching instruction in response to a mode switching signal; The switching module is used to switch the control mode of the BUCK-BOOST converter switching transistor from valley current sampling control mode to constant frequency peak current control mode in response to the mode switching command.
6. The DCM mode constant frequency control system for a BUCK-BOOST converter according to claim 5, characterized in that, The acquisition module includes: The monitoring module is used to monitor the operating status of the BUCK-BOOST converter; The first generation module is used to generate a corresponding enable signal and obtain a DCM signal when the BUCK-BOOST converter control system is detected to enter DCM mode. The second generation module is used to generate a corresponding enable signal and obtain the BUCK_MOD signal when the BUCK-BOOST converter control system is detected to enter BUCK mode.
7. The DCM mode constant frequency control system for a BUCK-BOOST converter according to claim 6, characterized in that, The instruction module includes a first instruction module and a second instruction module, wherein: The first instruction module includes: The first NAND gate is used to process the DCM signal and the BUCK_MOD signal to obtain the EN_N_DCM signal; The first inverter is used to process the EN_N_DCM signal to obtain the EN_P_DCM signal. The second instruction module includes: The first signal acquisition module is used to acquire the turn-on signal of the upper transistor HS1 in the BUCK-BOOST converter and obtain the HG_BUCK signal. The second NAND gate is used to process the HG_BUCK signal and the EN_N_DCM signal; The second inverter is used to process the output of the second NAND gate to obtain the RESET_DCM signal; A third NAND gate is used to process the HG_BUCK signal and the EN_P_DCM signal. The third inverter is used to process the output of the third NAND gate to obtain the SET_DCM signal; NOR gate, which is used to process the SET_DCM signal and the RESET_DCM signal; The fourth inverter is used to process the output of the NOR gate to obtain the BUCK_DCM_N signal; The fifth inverter is used to process the BUCK_DCM_N signal to obtain the BUCK_DCM signal.
8. The DCM mode constant frequency control system for a BUCK-BOOST converter according to claim 7, characterized in that, The switching module includes: The second signal acquisition module is used to acquire the output signal PWM_OUT_TOFF of the PWM comparator for valley current sampling, the fixed clock CLK generated internally by the DCM mode system of BUCK, the output signal TON_TIMER of the constant on-time module for valley current sampling, and the output signal PWM_OUT_TON of the PWM comparator for peak current control mode. The first two-to-one logic gate is used to process PWM_OUT_TOFF, CLK and BUCK_DCM_N to obtain TON_BUCK; The second 2-to-1 logic gate is used to process TON_TIMER, PWM_OUT_TON and BUCK_DCM_N to obtain TOFF_BUCK; Specifically, when TON_BUCK=1, the Buck high-side switch in the BUCK-BOOST converter is turned on and the Buck low-side switch is turned off. When TOFF_BUCK=1, the Buck high-side switch in the BUCK-BOOST converter is turned off and the Buck low-side switch is turned on, the inductor current decreases, and when the system is operating in the BUCK mode of DCM, the Boost high-side switch and Boost low-side switch are kept off.