Differential amplifier system

Abstract

A differential amplifier system is provided for receiving first and second input signals and generating first and second differential output signals. The system includes: a differential amplifier for receiving the first and second input signals, providing a first output current at a first current channel, and providing a second output current at a second current channel; a cascode stage for receiving the first and second output currents and generating the first and second differential output signals; and a detector for detecting when the first output current flowing through the first current channel satisfies the first condition, and / or detecting when the second output current flowing through the second current channel satisfies the second condition, wherein a current sink stage is configured to redirect at least a portion of the first and second output currents away from the cascode stage when the first output current satisfies the first condition, and / or redirect at least a portion of the first and second output currents away from the cascode stage when the second output current satisfies the second condition.

Description

Technical Field

[0001] This disclosure relates to a differential amplification system. Background Technology

[0002] Figure 1A This is a schematic diagram of a known differential amplifier system 100 (which may be referred to as a "differential amplifier"). During operation, the differential amplifier system 100 receives input signals In_p and In_n, and provides differential output signals Out_n and Out_p.

[0003] "Clipping" refers to the process of limiting the amplitude of the differential output signals Out_n and Out_p. Figure 1A The system demonstrates a known method for “clipping” the output of differential steps.

[0004] The differential amplifier system 100 includes a variable gain amplifier 102 and a peak detector 104. During operation, when the peak detector 104 detects an impending overload, it adjusts the gain of the variable gain amplifier 102. Specifically, when the output amplitudes of the differential output signals Out_n and Out_p exceed the desired maximum limit, the peak detector 104 reduces the gain of the variable gain amplifier 102, thereby reducing the output amplitude.

[0005] This technique can be very accurate and sensitive, but it is typically slow. Due to the slow speed, the output will exceed the specified clipping voltage until the loop stabilizes.

[0006] Figure 1B This is a schematic diagram of another known differential amplifier system 106, which includes diodes 108 and 110. Diodes 108 and 110 are used to limit the amplitude of the output signals Out_n and Out_p, thereby providing "clipping" using diodes.

[0007] If diodes were ideal, they would have fast and sharp behavior. However, practical diodes have an exponential response, so the limit is fast but not very sharp, and it can distort the signal as it approaches the limit, which is probably undesirable. Summary of the Invention

[0008] The aim is to provide an improved differential amplifier system for clipping output signals. Specifically, it is desired to provide an improved differential amplifier system that offers sharpness and / or speed during clipping.

[0009] According to a first aspect of this disclosure, a differential amplifier system is provided for receiving a first input signal and a second input signal, and for generating a first differential output signal and a second differential output signal. The differential amplifier system includes: a differential amplifier configured to receive the first input signal and the second input signal, provide a first output current at a first current channel, and provide a second output current at a second current channel; a cascode stage configured to receive the first output current and the second output current, and generate the first differential output signal and the second differential output signal; and a detector configured to detect when the first output current flowing through the first current channel satisfies a first condition, and / or detect when the second output current flowing through the second current channel satisfies a first condition. The second condition is satisfied; and the current sink stage is configured to redirect at least a portion of the first output current and at least a portion of the second output current away from the cascode stage when the first output current satisfies the first condition, and / or redirect at least a portion of the first output current and at least a portion of the second output current away from the cascode stage when the second output current satisfies the second condition, wherein the first output current satisfies the first condition when the first output current drops below the first threshold current value and / or rises above the first threshold current value, and the second output current satisfies the second condition when the second output current drops below the second threshold current value and / or rises above the second threshold current value.

[0010] Optionally, the differential amplifier includes: a first current source coupled to a first node; a first transistor including a first transistor first terminal configured to receive a first input signal, a first transistor second terminal coupled to a first current path, and a first transistor third terminal coupled to the first node; and a second transistor including a second transistor first terminal configured to receive a second input signal, a second transistor second terminal coupled to a second current path, and a second transistor third terminal coupled to the first node.

[0011] Optionally, the differential amplifier includes a first resistor and a second resistor, the third terminal of the first transistor is coupled to the first node via the first resistor, and the third terminal of the second transistor is coupled to the first node via the second resistor.

[0012] Optionally, the first transistor is a first bipolar transistor, the first terminal of the first transistor is the base terminal of the first transistor, the second terminal of the first transistor is the collector terminal of the first transistor, the third terminal of the first transistor is the emitter terminal of the first transistor, the second transistor is a second bipolar transistor, the first terminal of the second transistor is the base terminal of the first transistor, the second terminal of the second transistor is the collector terminal of the second transistor, and the third terminal of the second transistor is the emitter terminal of the second transistor.

[0013] Optionally, the common-source common-gate stage includes: a third bipolar transistor including a first terminal of the third transistor, a second terminal of the third transistor configured to provide a first differential output signal, and a third terminal of the third transistor coupled to a first current path; and a fourth bipolar transistor including a first terminal of the fourth transistor coupled to the first terminal of the third transistor, a second terminal of the fourth transistor configured to provide a second differential output signal, and a third terminal of the fourth transistor coupled to a second current path.

[0014] Optionally, the first terminal of the third transistor is the base terminal of the third transistor, the second terminal of the third transistor is the collector terminal of the third transistor, the third terminal of the third transistor is the emitter terminal of the third transistor, the first terminal of the fourth transistor is the base terminal of the fourth transistor, the second terminal of the fourth transistor is the collector terminal of the fourth transistor, and the third terminal of the fourth transistor is the emitter terminal of the fourth transistor.

[0015] Optionally, the detector includes a first detector input coupled to a first current channel to detect a first output current, and a second detector input coupled to a second current channel to detect a second output current.

[0016] Optionally, the detector is configured to activate the current sink stage to redirect at least a portion of the first output current and at least a portion of the second output current when the detector detects that the first condition has been met, and / or to activate the current sink stage to redirect at least a portion of the first output current and at least a portion of the second output current when the detector detects that the second condition has been met.

[0017] Optionally, the current absorber stage includes: a first absorber switch; a second absorber switch; and a current absorber coupled to a first current channel via the first absorber switch and coupled to a second current channel via the second absorber switch, wherein the detector is configured to: activate the first absorber switch and the second absorber switch when the detector detects that a first condition has been met, to redirect at least a portion of the first output current and at least a portion of the second output current, and / or activate the first absorber switch and the second absorber switch when the detector detects that a second condition has been met, to redirect at least a portion of the first output current and at least a portion of the second output current.

[0018] Optionally, the first absorption switch is a first absorption bipolar transistor, and the second absorption switch is a second bipolar transistor, wherein the detector is configured to activate the first absorption bipolar transistor by providing a first activation signal to the base terminal of the first absorption bipolar transistor, and / or the detector is configured to activate the second absorption bipolar transistor by providing a second activation signal to the base terminal of the second absorption bipolar transistor.

[0019] Optionally, the current sink includes a voltage source.

[0020] Optionally, the detector is configured to receive a reference voltage, a first threshold current value depending on the reference voltage, and / or a second threshold current value depending on the reference voltage.

[0021] Optionally, the differential amplifier system includes a reference voltage generator configured to generate a reference voltage.

[0022] Optionally, the reference voltage generator includes: a second current source coupled to a second node; a first reference generator bipolar transistor including a base terminal coupled to a common-source, common-gate stage and an emitter terminal coupled to the second node; and a second reference generator bipolar transistor including a base terminal coupled to a current sink stage and an emitter terminal coupled to the second node, wherein the reference voltage is provided at the second node.

[0023] Optionally, the detector includes a rectifier circuit comprising: a first rectifier input coupled to a first current channel; a second rectifier input coupled to a second current channel; a third rectifier input for receiving a reference voltage; a first rectifier output for providing a first activation signal to a current sink stage when the detector detects that a first condition has been met, to activate the current sink stage to redirect at least a portion of the first output current and at least a portion of the second output current; and / or a second rectifier output for providing a second activation signal to the current sink stage when the detector detects that a second condition has been met, to activate the current sink stage to redirect at least a portion of the first output current and at least a portion of the second output current.

[0024] Optionally, the rectifier circuit includes a first rectifier bipolar transistor, a second rectifier bipolar transistor, and a third rectifier bipolar transistor, wherein the first rectifier bipolar transistor includes a first rectifier input, the second rectifier bipolar transistor includes a second rectifier input, and the third rectifier bipolar transistor includes a third rectifier input.

[0025] Optionally, the detector includes a comparator.

[0026] Optionally, the cascode stage includes: a third bipolar transistor including a third transistor base terminal, a third transistor collector terminal configured to provide a first differential output signal, and a third transistor emitter terminal coupled to a first current channel; a fourth bipolar transistor including a fourth transistor base terminal coupled to a first terminal of the third transistor, a fourth transistor collector terminal configured to provide a second differential output signal, and a fourth transistor emitter terminal coupled to a second current channel; the current sink stage includes a first sink bipolar transistor, a second sink bipolar transistor, and a current sink coupled to the first current channel via a first sink switch and to the second current channel via a second sink switch, wherein the detector is configured to, when the detector detects that a first condition has been met, The current sink stage is activated by the following methods, thereby redirecting at least a portion of the first output current and at least a portion of the second output current: activating the first absorption bipolar transistor by providing a first activation signal to the base terminal of the first absorption bipolar transistor and activating the second absorption bipolar transistor by providing a first activation signal to the base terminal of the second absorption bipolar transistor, and / or, when the detector detects that a second condition has been met, activating the current sink stage by the following methods, thereby redirecting at least a portion of the first output current and at least a portion of the second output current: activating the first absorption bipolar transistor by providing a second activation signal to the base terminal of the first absorption bipolar transistor and activating the second absorption bipolar transistor by providing a second activation signal to the base terminal of the second absorption bipolar transistor.

[0027] Optionally, the differential amplifier system includes an output terminal coupled to the collector terminals of a third transistor, a fourth transistor, a first absorption bipolar transistor, and a second absorption bipolar transistor.

[0028] According to a second aspect of this disclosure, a method for providing a differential amplifier system is provided, the differential amplifier system being used to receive a first input signal and a second input signal, and to generate a first differential output signal and a second differential output signal, the method comprising: providing a differential amplifier configured to receive the first input signal and the second input signal, providing a first output current at a first current channel, and providing a second output current at a second current channel; providing a cascode stage configured to receive the first output current and the second output current, and to generate the first differential output signal and the second differential output signal; and providing a detector configured to detect when the first output current flowing through the first current channel satisfies a first condition, and / or detect the flow of the second current. The second output current of the channel satisfies a second condition; and a current sink stage is provided, the current sink stage being configured to redirect at least a portion of the first output current and at least a portion of the second output current away from the cascode stage when the first output current satisfies the first condition, and / or to redirect at least a portion of the first output current and at least a portion of the second output current away from the cascode stage when the second output current satisfies the second condition, wherein the first output current satisfies the first condition when the first output current drops below a first threshold current value and / or rises above a first threshold current value, and the second output current satisfies the second condition when the second output current drops below a second threshold current value and / or rises above a second threshold current value.

[0029] To be understood, the approach of the second aspect may include providing and / or using the features stated in the first aspect, and may be combined with other features described herein. Attached Figure Description

[0030] This disclosure is further described in detail below by way of example and with reference to the accompanying drawings, wherein:

[0031] Figure 1A This is a schematic diagram of a known differential amplifier system. Figure 1B This is a schematic diagram of yet another known differential amplifier system;

[0032] Figure 2A This is a schematic diagram of a differential amplification system according to a first embodiment of the present disclosure. Figure 2B This is a schematic diagram of a specific embodiment of the differential amplification system according to the second embodiment of the present disclosure;

[0033] Figure 3A This is a schematic diagram of yet another specific embodiment of the differential amplification system according to the third embodiment of this disclosure. Figure 3B yes Figure 3A Another schematic diagram of the differential amplifier system shown; and

[0034] Figure 4A This is a schematic diagram of yet another specific embodiment of the differential amplification system according to the fourth embodiment of this disclosure. Figure 4B This is a schematic diagram of a specific embodiment of the detector. Detailed Implementation

[0035] Figure 2A This is a schematic diagram of a differential amplifier system 200 according to a first embodiment of the present disclosure. During operation, the differential amplifier system 200 receives input signals In_p and In_n, and generates differential output signals Out_n and Out_p.

[0036] The differential amplifier system 200 includes a differential amplifier 202 configured to receive input signals In_p and In_n. The differential amplifier 202 is also configured to provide an output current Ia1 at current channel 204 and an output voltage Ia2 at current channel 206.

[0037] The differential amplifier system 200 also includes a cascode stage 208, which is configured to receive output currents Ia1 and Ia2 and generate differential output signals Out_n and Out_p.

[0038] The differential amplifier system 200 also includes a detector 210 and a current sink stage 212. The detector 210 is configured to detect when the output current Ia1 flowing through the current channel 204 satisfies a first condition. The detector 210 may be referred to as a "peak detector". The current sink stage 212 may include switches 214, 216 and a current sink 218.

[0039] The current sink stage 212 is configured to redirect at least a portion of the output current Ia1 and at least a portion of the output current Ia2 away from the cascode stage 208 when a first condition is met.

[0040] When the output current Ia1 drops below the first threshold current value, the first condition can be satisfied. Alternatively or additionally, when the output current Ia1 rises above the first threshold current value, the first condition can be satisfied.

[0041] Detector 210 can also be configured to detect when the output current Ia2 flowing through current channel 206 meets the second condition. The current sink stage can be configured to redirect at least a portion of the output current Ia1 and at least a portion of the output current Ia2 away from the cascode stage 208 when the second condition is met.

[0042] The second condition is satisfied when the output current Ia2 drops below the second threshold current value. Alternatively or additionally, the second condition is satisfied when the output current Ia2 rises above the second threshold current value.

[0043] Detector 210 may include an input 211a coupled to channel 204 to detect output current Ia1, and may include an input 211b coupled to channel 206 to detect output current Ia2. Detector 210 may be configured to activate current sink stage 212 to redirect at least a portion of output current Ia1 and at least a portion of second output current Ia2 when a first condition is met, and / or may be configured to activate current sink stage 212 to redirect at least a portion of first output current Ia1 and at least a portion of output current Ia2 when a second condition is met. Detector 210 may activate current sink stage 212 by controlling switch 214 and / or switch 216.

[0044] In summary, during operation, the inputs of the cascode stage 208 are sensed by detector 210. Detector 210 is coupled to the inputs of the cascode stage 208 to measure the current flowing to each input of the cascode stage 208. If detector 210 detects that the current in one channel of the input stage has dropped below a certain threshold, then a current sink path is activated. Therefore, current is directed to current sink 218 to prevent overload, or otherwise directed to the output of the cascode stage 208. Thus, embodiments of the differential amplifier system 200 provide a sharp and fast way to clip differential signals.

[0045] Figure 2B This is a schematic diagram of a specific embodiment of the differential amplification system 200 according to the second embodiment of the present disclosure.

[0046] In this embodiment, the differential amplifier 202 includes a current source 220 for providing current I1 and coupled to node N1.

[0047] The differential amplifier 202 also includes a transistor 222, which receives the input voltage In_p at terminal 224. The transistor 222 also includes a terminal 226 coupled to the current path 204 and a terminal 228 coupled to node N1.

[0048] The differential amplifier 202 also includes a transistor 230, which receives the input voltage In_n at terminal 232. The transistor 230 also includes a terminal 234 coupled to the current path 206 and a terminal 236 coupled to node N1.

[0049] In this embodiment, the differential amplifier 202 further includes resistors 238 and 240. Transistor 222 is coupled to node N1 via resistor 238, and transistor 230 is coupled to node N1 via resistor 240.

[0050] In this embodiment, transistors 222 and 230 are bipolar transistors. In this embodiment, transistor 222 receives the input voltage In_P at its base terminal, and transistor 230 receives the input voltage In_n at its base terminal. In this embodiment, terminals 226 and 234 are collector terminals, and terminals 228 and 236 are emitter terminals.

[0051] In this embodiment, the cascode stage 208 includes a bipolar transistor 242 having a terminal 244, a terminal 246 for providing a differential output signal Out_n, and a terminal 248 coupled to a current path 204. In this embodiment, terminal 244 is the base terminal, terminal 246 is the collector terminal, and terminal 248 is the emitter terminal.

[0052] In this embodiment, the cascode stage 208 further includes a bipolar transistor 250, which has a terminal 252, a terminal 254 for providing a differential output signal Out_p, and a terminal 256 coupled to the current path 206. In this embodiment, terminal 252 is the base terminal, terminal 254 is the collector terminal, and terminal 256 is the emitter terminal. The base terminals of transistors 242 and 250 can be coupled together.

[0053] Bipolar transistors 242 and 250 are referred to as bipolar junction transistors (BJTs). In this embodiment, since transistor 208 is topologically coupled with a common base, the use of a BJT transistor in the cascode stage 208 improves the speed of the cascode stage 208. In other embodiments, as will be understood by those skilled in the art, the cascode stage 208 can be implemented using a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0054] The voltage swing at the emitter of a common-base transistor is typically low, but the voltage swing increases exponentially as the emitter current decreases. Therefore, by detecting a low current at the emitter of one of the transistors 242 and 250 in the cascode stage 208, it can be determined that the signal swing at the output of the cascode stage 208 will be too high, thus causing an overload.

[0055] With known systems (such as) Figure 1A Compared to the presented system, the detector 210 of the embodiments of this disclosure does not change the gain of the amplifier to reduce the possibility of clipping. Instead, the detector 210 subtracts current from its output and uses the input of the cascode stage 208 as the trigger for this subtraction.

[0056] Figure 3A This is a schematic diagram of yet another specific embodiment of the differential amplification system 200 according to the third embodiment of the present disclosure.

[0057] In this embodiment, a specific embodiment of the current sink stage 212 is shown. Specifically, switches 214 and 216 are each bipolar transistors, which may be in a common-base arrangement, wherein their bases are coupled together. In yet another embodiment, as will be understood by those skilled in the art, each of switches 214 and 216 may be a MOSFET.

[0058] During operation, detector 210 can provide an activation signal to the base terminals of switches 214, 216 in response to the previously described conditions of satisfying necessary output currents Ia1, Ia2. In this embodiment, current absorber 218 includes a voltage source Vcc.

[0059] Switches 214 and 216, implemented by bipolar transistors, can be referred to as bipolar junction transistors (BJTs).

[0060] In summary, during operation, when detector 210 detects that the current on either of the two channels 204 and 206 has dropped below a certain threshold, it turns on the BJT transistors (switches 214 and 216) of the current sink stage 212. This, in turn, diverts a portion of the signal to the voltage source Vcc, thereby reducing the output amplitude of the differential output signals Out_n and Out_p. Therefore, a portion of the current (DC and RF) is shunted through the current sink 218.

[0061] Figure 3B yes Figure 3A Another schematic diagram of the differential amplifier system 200 is shown. The leftmost schematic diagram shows... Figure 3A The illustrated differential amplifier stage 200 is arranged as shown, and the rightmost schematic diagram shows the same differential amplifier stage 200 with an alternative schematic layout. The rightmost image is used to illustrate the structural similarity to the Gilbert unit. Structurally, there is similarity between the embodiments of this disclosure and the Gilbert unit. However, the Gilbert unit is used as a mixer, and therefore its function differs from the embodiments of this disclosure. Furthermore, the Gilbert unit does not include a peak detector such as detector 210.

[0062] Figure 4A This is a schematic diagram of yet another specific embodiment of the differential amplification system 200 according to the fourth embodiment of the present disclosure.

[0063] In this embodiment, detector 210 is configured to receive a reference voltage Ref. A first threshold current value used to evaluate a first condition may depend on the reference voltage Ref. A second threshold current value used to evaluate a second condition may depend on the reference voltage Ref.

[0064] The differential amplifier system 200 may include a reference voltage generator 400 for generating a reference voltage Ref.

[0065] The reference voltage generator 400 may include a current source 402 coupled to node N2 and bipolar transistors 404 and 406. In this embodiment, bipolar transistor 404 has a base terminal coupled to cascode stage 208 and an emitter terminal coupled to node N2. In this embodiment, bipolar transistor 406 has a base terminal coupled to current sink stage 212 and an emitter terminal coupled to node N2. During operation, a reference voltage Ref can be provided at node N2.

[0066] In another embodiment, the collector terminals of the common-source cascode stage 208 bipolar transistors 242, 250 can be coupled together and coupled to the collector terminals of the current sink stage 212 bipolar transistors 214, 216 to provide a single output terminal 405 for providing a single differential output signal.

[0067] Figure 4B This is a schematic diagram of a specific embodiment of detector 210 that can be used in any of the embodiments described herein, as understood by those skilled in the art. In this embodiment, detector 210 includes rectifier circuitry 408.

[0068] The rectifier circuit 408 includes an input 410 for coupling to current channel 204 and for receiving an input signal In_1 from current channel 204, the input signal In_1 depending on current Ia1. The rectifier circuit 408 also includes an input 412 for coupling to current channel 206 and for receiving an input signal In_2 from current channel 206, the input signal In_2 depending on current Ia2. The rectifier circuit 408 also includes an input 414 for receiving a reference voltage Ref. The rectifier circuit 408 also includes an output 416, the input 416 for, for example, in response to output current Ia1 satisfying a first condition, providing an activation signal Out_1 to current sink stage 212 to activate current sink stage 212, thereby redirecting the two output currents Ia1, Ia2 to current sink stage 218. The rectifier circuit 408 also includes an output 418 for providing an activation signal Out_2 to the current sink stage 212 to activate the current sink stage 212, for example, in response to the output current Ia2 satisfying a second condition, thereby redirecting the two output currents Ia1, Ia2 to the current sink stage 218.

[0069] The rectifier circuit 408 may include: a transistor Q1 including an input 410, a transistor Q2 including an input 412, and a transistor Q3 including an input 414.

[0070] The rectifier circuit 408 may also include a current source 416 and resistors 418, 420, and 422.

[0071] In yet another embodiment, detector 210 may include a comparator instead of rectifier circuit 408. However, rectifier circuit 408 offers the following advantages compared to a comparator:

[0072] a) It enables the voltage at the base of the transistor in the cascode stage 208 to be adjusted in contrast to the adjustment at the base of the transistor in the current sink stage 218.

[0073] b) Compared to using a conventional comparator, it has a smaller area, is faster, and has reduced complexity.

[0074] Preferably, the voltage reference Ref of detector 210 is highly accurate to set an appropriate clipping level and tolerate temperature and / or process variations. To achieve this, reference voltage generator 400 is coupled to cascode stage 208, current sink stage 212, and detector 210.

[0075] During operation, transistor 404 generates a diode voltage drop from the cascode base voltage. The reference voltage Ref then depends on the ratio between transistors 242, 250, and 404, and the ratio between the current I1 from current source 220 and the current I2 from current source 402. The reference voltage Ref stabilizes with temperature and process because transistor 404 mirrors transistors 242 and 250.

[0076] Transistor 406 takes over the settings of reference Ref during clipping operations. For example... Figure 4A As seen in the diagram, without the coupling of transistor 406, when detector 210 activates transistors 214 and 216, positive feedback will occur, which will ultimately cause all current to be directed to current sink 218 instead of cascode stage 208.

[0077] More specifically, when current is directed to the current sink Vcc, the voltage at the emitter of transistors 214, 216, 242, and 250 increases, which is equivalent to detector 210 detecting a lower current. Therefore, when clipping occurs, transistors 214 and 216 cause detector 210 to sense a larger overload, thereby adjusting the voltage at the base of transistors 214 and 212 in a way that directs more current to Vcc.

[0078] Through such Figure 4A The coupled transistor 406 shown increases the reference voltage Ref under overload conditions to compensate for the positive feedback mentioned above, thereby avoiding latch-up.

[0079] In summary, in embodiments of this disclosure, if the emitter current is less than a reference value, detector 210 activates a path that allows some current normally directed to the cascode stage 208 to be redirected away from the output (by directing it to the variable current sink 218). This, in turn, reduces the amplitude of the output, preventing overload.

[0080] In a specific embodiment, it should be understood that, due to the characteristics of the differential amplifier 202, a low current on the emitter of one common-base transistor may lead to a high current on the other common-base transistor. Therefore, in other embodiments, the detector 210 may be configured to detect a current exceeding a threshold on one of the channels and activate current sink operation associated with the current exceeding the threshold.

[0081] It should be understood that, in other embodiments, as will be understood by those skilled in the art, the bipolar junction transistors of the embodiments of this disclosure may alternatively be implemented using other transistor types, such as metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0082] In summary, the embodiments of this disclosure provide a sharper and faster differential signal clipping method compared to known systems.

[0083] Common reference numerals and variables among the figures indicate common features.

[0084] Various improvements and modifications may be made to the above text without departing from the scope of this disclosure.

Claims

1. A differential amplifier system for receiving a first input signal and a second input signal, and for generating a first differential output signal and a second differential output signal, the differential amplifier system comprising: The differential amplifier is configured as follows: Receive the first input signal and the second input signal; A first output current is provided at the first current path; and A second output current is provided at the second current channel; The common source and common gate stage is configured as follows: Receive the first output current and the second output current; and Generate the first differential output signal and the second differential output signal; The detector is configured as follows: Detect when the first output current flowing through the first current channel meets the first condition; and / or Detect when the second output current flowing through the second current channel meets the second condition; as well as The current sink stage is configured as follows: When the first output current satisfies the first condition, at least a portion of the first output current and at least a portion of the second output current are redirected away from the common source cascode stage; and / or When the second output current satisfies the second condition, at least a portion of the first output current and at least a portion of the second output current are redirected away from the common source cascode stage; wherein: When the first output current drops below the first threshold current value and / or rises above the first threshold current value, the first output current satisfies the first condition; and The second output current satisfies the second condition when the second output current drops below the second threshold current value and / or rises above the second threshold current value.

2. The differential amplifier system according to claim 1, wherein: The differential amplifier includes: The first current source is coupled to the first node; The first transistor includes: The first terminal of the first transistor is configured to receive the first input signal; The second terminal of the first transistor is coupled to the first current channel; The third terminal of the first transistor is coupled to the first node; and The second transistor includes: The first terminal of the second transistor is configured to receive the second input signal; The second terminal of the second transistor is coupled to the second current channel; The third terminal of the second transistor is coupled to the first node.

3. The differential amplifier system according to claim 2, wherein: The differential amplifier includes: A first resistor, the third terminal of which is coupled to the first node via the first resistor; and The second resistor, the third terminal of which is coupled to the first node via the second resistor.

4. The differential amplifier system according to claim 2, wherein: The first transistor is a first bipolar transistor; The first terminal of the first transistor is the base terminal of the first transistor; The second terminal of the first transistor is the collector terminal of the first transistor; The third terminal of the first transistor is the emitter terminal of the first transistor; The second transistor is a second bipolar transistor; The first terminal of the second transistor is the base terminal of the first transistor; The second terminal of the second transistor is the collector terminal of the second transistor; and The third terminal of the second transistor is the emitter terminal of the second transistor.

5. The differential amplifier system according to claim 1, wherein: The common source, common gate stage includes: The third bipolar transistor includes: The first terminal of the third transistor; The second terminal of the third transistor is configured to provide the first differential output signal; The third terminal of the third transistor is coupled to the first current channel; The fourth bipolar transistor includes: The first terminal of the fourth transistor is coupled to the first terminal of the third transistor; The second terminal of the fourth transistor is configured to provide the second differential output signal; and The third terminal of the fourth transistor is coupled to the second current channel.

6. The differential amplifier system according to claim 5, wherein: The first terminal of the third transistor is the base terminal of the third transistor; The second terminal of the third transistor is the collector terminal of the third transistor; The third terminal of the third transistor is the emitter terminal of the third transistor; The first terminal of the fourth transistor is the base terminal of the fourth transistor; The second terminal of the fourth transistor is the collector terminal of the fourth transistor; and The third terminal of the fourth transistor is the emitter terminal of the fourth transistor.

7. The differential amplifier system according to claim 1, wherein: The detector includes: A first detector input is coupled to the first current channel to detect the first output current; and The second detector input is coupled to the second current channel to detect the second output current.

8. The differential amplifier system according to claim 1, wherein: The detector is configured as follows: When the detector detects that the first condition has been met, the current sink stage is activated to redirect at least a portion of the first output current and at least a portion of the second output current; and / or When the detector detects that the second condition has been met, the current absorber stage is activated to redirect at least a portion of the first output current and at least a portion of the second output current.

9. The differential amplifier system according to claim 8, wherein the current sink stage comprises: First absorption switch; Second absorption switch; as well as A current absorber is coupled to the first current channel via the first absorber switch and to the second current channel via the second absorber switch; wherein: The detector is configured as follows: When the detector detects that the first condition has been met, it activates the first absorption switch and the second absorption switch to redirect at least a portion of the first output current and at least a portion of the second output current. and / or When the detector detects that the second condition has been met, it activates the first absorption switch and the second absorption switch to redirect at least a portion of the first output current and at least a portion of the second output current.

10. The differential amplifier system according to claim 9, wherein: The first absorption switch is a first absorption bipolar transistor; The second absorption switch is a second bipolar transistor; wherein: The detector is configured to activate the first absorption bipolar transistor by providing a first activation signal to the base terminal of the first absorption bipolar transistor; and / or The detector is configured to activate the second absorption bipolar transistor by providing a second activation signal to the base terminal of the second absorption bipolar transistor.

11. The differential amplifier system of claim 10, wherein the current sink comprises a voltage source.

12. The differential amplifier system according to claim 1, wherein: The detector is configured to receive a reference voltage; The first threshold current value depends on the reference voltage and / or the second threshold current value depends on the reference voltage.

13. The differential amplifier system of claim 12, further comprising a reference voltage generator configured to generate the reference voltage.

14. The differential amplifier system of claim 13, wherein the reference voltage generator comprises: The second current source is coupled to the second node; The first reference generator bipolar transistor includes a base terminal coupled to the common-source cascode stage and an emitter terminal coupled to the second node; The second reference generator bipolar transistor includes a base terminal coupled to the current sink stage and an emitter terminal coupled to the second node; wherein: The reference voltage is provided at the second node.

15. The differential amplification system according to claim 12, wherein the detector comprises: The rectifier circuit includes: The first rectifier input is coupled to the first current path; The second rectifier input is coupled to the second current path; The third rectifier input is used to receive the reference voltage; A first rectifier output is configured to provide a first activation signal to the current sink stage when the detector detects that the first condition has been met, thereby activating the current sink stage to redirect at least a portion of the first output current and at least a portion of the second output current; and / or The second rectifier output is used to provide a second activation signal to the current sink stage when the detector detects that the second condition has been met, so as to activate the current sink stage to redirect at least a portion of the first output current and at least a portion of the second output current.

16. The differential amplifier system of claim 15, wherein the rectifier circuit includes a first rectifier bipolar transistor, a second rectifier bipolar transistor, and a third rectifier bipolar transistor, wherein the first rectifier bipolar transistor includes a first rectifier input, the second rectifier bipolar transistor includes a second rectifier input, and the third rectifier bipolar transistor includes the third rectifier input.

17. The differential amplification system of claim 12, wherein the detector comprises a comparator.

18. The differential amplifier system according to claim 1, wherein: The common source, common gate stage includes: The third bipolar transistor includes: Third transistor base terminal; The collector terminal of the third transistor is configured to provide the first differential output signal; The third transistor emitter terminal is coupled to the first current channel; The fourth bipolar transistor includes: The base terminal of the fourth transistor is coupled to the first terminal of the third transistor; The fourth transistor collector terminal is configured to provide the second differential output signal; and The fourth transistor emitter terminal is coupled to the second current channel; The current absorber stage includes: First absorption bipolar transistor; The second absorption bipolar transistor; and A current absorber is coupled to the first current channel via the first absorber switch and to the second current channel via the second absorber switch; wherein: The detector is configured as follows: When the detector detects that the first condition has been met, the current absorber stage is activated by redirecting at least a portion of the first output current and at least a portion of the second output current by: activating the first absorber bipolar transistor by providing a first activation signal to the base terminal of the first absorber bipolar transistor, and activating the second absorber bipolar transistor by providing the first activation signal to the base terminal of the second absorber bipolar transistor; and / or When the detector detects that the second condition has been met, the current absorber stage is activated by redirecting at least a portion of the first output current and at least a portion of the second output current by providing a second activation signal to the base terminal of the first absorber bipolar transistor to activate the first absorber bipolar transistor, and by providing the second activation signal to the base terminal of the second absorber bipolar transistor to activate the second absorber bipolar transistor.

19. A method for providing a differential amplifier system, the differential amplifier system being configured to receive a first input signal and a second input signal, and to generate a first differential output signal and a second differential output signal, the method comprising: A differential amplifier is provided, the differential amplifier being configured to: Receive the first input signal and the second input signal; A first output current is provided at the first current path; as well as A second output current is provided at the second current channel; A common-source cascode stage is provided, wherein the common-source cascode stage is configured as follows: Receive the first output current and the second output current; as well as Generate the first differential output signal and the second differential output signal; Provide a detector, which is configured to: Detect when the first output current flowing through the first current channel meets the first condition; and / or Detect when the second output current flowing through the second current channel meets the second condition; as well as A current sink stage is provided, the current sink stage being configured to: When the first output current satisfies the first condition, at least a portion of the first output current and at least a portion of the second output current are redirected away from the common source cascode stage; and / or When the second output current satisfies the second condition, at least a portion of the first output current and at least a portion of the second output current are redirected away from the common source cascode stage; wherein: When the first output current drops below the first threshold current value and / or rises above the first threshold current value, the first output current satisfies the first condition; and The second output current satisfies the second condition when the second output current drops below the second threshold current value and / or rises above the second threshold current value.

Images