A wideband amplifier circuit with gain adjustment and die protection

Abstract

The application discloses a kind of wideband amplifier circuits with gain adjustable and with die protection function, belong to wideband amplifier field, based on Cascode structure design multiple cascade amplification units, by adjusting tube TB and RB1, RB2 Bias network is formed, cooperate D1, D2, D3 Zener diode, realize VDD bias voltage stability and die overvoltage protection.Adjusting specific node VG2 Voltage changes T2 in Cascode unit The degree of conduction of tube, realize amplifier gain flexible control.Input and output are constructed by microstrip transmission line Distribution architecture, signal is injected into amplification unit through input matching network, and the output is synthesized after amplification in output transmission line, and high-efficiency amplification of wideband signal is achieved.The application solves the gain adjustment limitation of traditional wideband amplifier and the problem of easy damage of die, and has high reliability and practicality in the field of radio frequency communication, radar detection and the like.

Description

Technical Field

[0001] This invention relates to the field of broadband amplifier technology, and more specifically to a broadband amplifier circuit that has gain adjustment function and can effectively protect the chip. Background Technology

[0002] Broadband amplifiers play a crucial role in modern communication and electronic systems, and their performance directly affects signal transmission quality and overall system efficiency. Currently, commercially available distributed broadband amplifiers based on Cascode structures suffer from several problems: firstly, limited gain adjustment methods make it difficult to meet the flexible signal amplification requirements of different application scenarios; secondly, the dies lack reliable protection measures under complex voltage and current conditions, making them susceptible to damage due to overvoltage, overcurrent, and other factors, thus reducing the amplifier's stability and lifespan. Therefore, developing a distributed broadband amplifier circuit based on a Cascode structure that can achieve both flexible gain adjustment and ensure the safe operation of the dies is of significant practical importance. Summary of the Invention

[0003] To address the aforementioned shortcomings in the prior art, this invention provides a broadband amplifier circuit that features gain adjustment and effectively protects the dies.

[0004] To achieve the above-mentioned objectives, the technical solution adopted by this invention is as follows:

[0005] A broadband amplifier circuit with adjustable gain and die protection includes an input matching network, a first gate-source feedback stacked amplification network, a second gate-source feedback stacked amplification network, a self-biased voltage divider network, and an output matching network.

[0006] The input terminal of the input matching network is the input terminal of the entire power amplifier, its first output terminal is connected to the input terminal of the first gate-source feedback stacked amplification network, and its second output terminal is connected to the input terminal of the second gate-source feedback stacked amplification network.

[0007] The output terminal of the output matching network is the output terminal of the entire power amplifier. Its first input terminal is connected to the output terminal of the first gate-source feedback stacked amplification network, and its second input terminal is connected to the output terminal of the second gate-source feedback stacked amplification network.

[0008] The self-biased voltage divider network is connected to the first gate-source feedback stacked amplification network, the second gate-source feedback stacked amplification network, and the output matching network, respectively.

[0009] The beneficial effects of this invention are: A gain-adjustable mechanism is established in the circuit with a specific voltage adjustment node VG2. By changing the voltage of this node, the operating state of the common gate transistor T2 in the Cascode amplifier unit can be adjusted. When the VG2 voltage varies within the range of -1.0V to +3V, the conduction level of T2 changes, thereby affecting the transconductance of the Cascode amplifier unit and achieving adjustment of the overall broadband amplifier gain. For example, when the VG2 voltage increases, T2 tends to conduct more, increasing the gain of the Cascode unit; when the VG2 voltage decreases, the gain decreases. Since the Cascode amplifier units are cascaded through microstrip transmission lines, the gain changes of individual units will cumulatively affect the overall amplifier gain, thus achieving flexible gain adjustment.

[0010] Furthermore, the input matching network includes a DC blocking capacitor C1, a microstrip line TL1, a microstrip line TL3, a first RC suppression circuit, and a microstrip line TL7 connected in series, with one end of the DC blocking capacitor C1 serving as the input terminal of the input matching network;

[0011] An open-circuit microstrip line TL2 is also connected to the connection node of microstrip line TL1 and microstrip line TL3.

[0012] The connection node between the first RC suppression circuit and the microstrip line TL7 is also connected to one end of the microstrip line TL4. The other end of the microstrip line TL4 is connected to one end of the resistor R3 and the second RC suppression circuit, respectively. The other end of the resistor R3 is connected to the low-voltage bias power supply V. g1 connect;

[0013] The other end of the microstrip line TL7 is connected to one end of the microstrip line TL6 and one end of the microstrip line TL5, respectively. The other end of the microstrip line TL6 is the first output terminal of the input matching network, and the other end of the microstrip line TL5 is the second output terminal of the input matching network.

[0014] The first RC suppression circuit includes a resistor R1 and a capacitor C2 connected in parallel, and the second RC suppression circuit includes a resistor R2 and a grounded capacitor C3 connected in series.

[0015] The beneficial effects of the above-mentioned further solutions are: The die protection mechanism, with clamping diodes D1, D2, and D3 playing a crucial protective role in the circuit. In a distributed circuit based on a Cascode structure, when an abnormal voltage occurs in the die of a Cascode amplifier unit during operation, especially when a negative bias occurs at the gate voltage, the clamping diodes quickly conduct, limiting the gate-drain / gate-source voltages of T1 and T2 within a safe range, preventing the die from being damaged by overvoltage, and effectively ensuring the safe operation of each stage of the die.

[0016] Furthermore, the first gate-source feedback stacked amplification network and the second gate-source feedback stacked amplification network have the same structure, both including a top-layer transistor, an intermediate-layer transistor, and a bottom-layer transistor stacked in a source-drain configuration.

[0017] The sources of the underlying transistors are all grounded, and their gates are the input terminals of the first gate-source feedback stacked amplification network or the second gate-source feedback stacked amplification network.

[0018] The gate of the intermediate layer transistor is connected to a self-biased voltage divider network and a gate compensation circuit, respectively, and its gate and source are connected by a series capacitor and a microstrip line.

[0019] The gate of the top-level transistor is connected to a self-biased voltage divider network and a gate compensation circuit, respectively. Its gate and source are connected by a series capacitor and a microstrip line. Its drain is the output terminal of the first gate-source feedback stacked amplification network or the second gate-source feedback stacked amplification network.

[0020] L-shaped matching stubs are connected between the drain of the bottom transistor and the source of the middle transistor, and between the drain of the middle transistor and the source of the top transistor.

[0021] The gate compensation circuit includes a gate stabilizing resistor and a compensation grounding capacitor connected in series. The L-type matching stub includes a microstrip line connected in series between the drain and source of two adjacent transistors and an open-circuit microstrip line connected in parallel between the microstrip line and the transistor drain.

[0022] The beneficial effects of the above-mentioned further scheme are: a bias stabilization mechanism, where the adjusting transistor TB, under the action of the bias network composed of RB1 and RB2, can stabilize the power supply bias (VDD) of the circuit. In the Cascode distributed circuit, since multiple amplification units are cascaded, when the current demand changes due to gain adjustment or external load changes, TB can maintain a stable output of VDD by adjusting its own conduction state, ensuring the stability of the operating point of each Cascode amplification unit and providing a guarantee for the reliable operation of the entire distributed amplifier.

[0023] Furthermore, the output matching network includes DC blocking capacitors C connected in series. 13 Microstrip line TL 32 Microstrip line TL 29 and microstrip lines TL 26 The DC blocking capacitor C 13 One end is the output end of the output matching network;

[0024] The microstrip line TL 32 and microstrip lines TL 29The connection node is also connected to an open-circuit microstrip line TL. 30 and open-circuit microstrip line TL 31 The microstrip line TL 29 and microstrip lines TL 26 The connection node is also connected to an open-circuit microstrip line TL. 27 and open-circuit microstrip line TL 28 The microstrip line TL 26 The other end is connected to the microstrip line TL. 22 One end, microstrip line TL 23 One end of the network and the self-biased voltage divider network are connected;

[0025] The microstrip line TL 22 The other end is connected to the microstrip line TL 20 One end is connected to the microstrip line TL 20 The other end is the first input of the output matching network, and the microstrip line TL 22 and microstrip lines TL 20 The connection node is also connected to the microstrip line TL 21 One end is connected to the microstrip line TL 21 The other end is connected to the third RC suppression circuit and the first high-voltage bias power supply V, respectively. d1 connect;

[0026] The microstrip line TL 23 The other end is connected to the microstrip line TL 24 One end is connected to the microstrip line TL 24 The other end is the second input of the output matching network, and the microstrip line TL 23 and microstrip lines TL 24 The connection node is also connected to the microstrip line TL 25 One end is connected to the microstrip line TL 25 The other end is connected to the fourth RC suppression circuit and the second high-voltage bias power supply V, respectively. d2 connect;

[0027] The third RC suppression circuit includes a series resistor R. 15 and grounding capacitor C 12 The fourth RC suppression circuit includes a resistor R connected in series. 16 and grounding capacitor C 14 .

[0028] The beneficial effects of the above-mentioned further scheme are: broadband amplification is achieved. Under the Cascode distributed circuit architecture, the input signal is coupled to the microstrip transmission line TL_in via the input capacitor Cin, and then passes through each Cascode amplification unit in a traveling wave manner. Each cell amplifies the signal, and the amplified signals are superimposed in phase along the TL_out transmission line. By rationally designing the characteristic impedance and length of the microstrip transmission line, as well as the spacing of the Cascode amplification units and the circuit component parameters, the phase consistency of signals of different frequencies on the transmission line is ensured, achieving efficient power combining over a wide bandwidth. This enables the amplifier to have a flat gain response over a wide frequency range, thus achieving broadband amplification.

[0029] Furthermore, the self-biased voltage divider network includes resistors R8, R9, and R... 10 Resistance R 11 Resistance R 12 Resistance R 13 and resistance R 14 ;

[0030] One end of resistor R8 is grounded, and the other end is connected to one end of resistor R9 and resistor R 10 one end and resistor R 11 One end is connected, the resistor R 11 The other end is connected to resistor R respectively 12 One end, resistor R 13 one end and resistor R 14 One end is connected;

[0031] The other end of resistor R9 is connected to the gate of the intermediate layer transistor in the first gate-source feedback stacked amplification network. 10 The other end is connected to the gate of the intermediate layer transistor in the second gate-source feedback stacked amplification network, and the resistor R 12 The other end is connected to the gate of the top-level transistor in the first gate-source feedback stacked amplification network, and the resistor R 13 The other end is connected to the gate of the top-level transistor in the second gate-source feedback stacked amplification network, and the resistor R 14 The other end is matched with the microstrip line TL in the output matching network. 26 connect.

[0032] Furthermore, the first gate-source feedback stacked amplification network and the second gate-source feedback stacked amplification network are active amplification networks, while the input matching network, output matching network, and self-biased voltage divider network are passive networks. Attached Figure Description

[0033] Figure 1The diagram shown is a block diagram of a broadband amplifier circuit with adjustable gain and die protection provided by the present invention.

[0034] Figure 2 The diagram shown is a schematic representation of a distributed broadband amplifier circuit based on a Cascode structure provided in an embodiment of the present invention. Detailed Implementation

[0035] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0036] This invention provides a broadband amplifier circuit with adjustable gain and die protection, such as... Figure 1 As shown, the amplifier includes an input matching network, a first gate-source feedback stacked amplification network, a second gate-source feedback stacked amplification network, a self-biased voltage divider network, and an output matching network. The input terminal of the input matching network is the input terminal of the entire power amplifier, its first output terminal is connected to the input terminal of the first gate-source feedback stacked amplification network, and its second output terminal is connected to the input terminal of the second gate-source feedback stacked amplification network. The output terminal of the output matching network is the output terminal of the entire power amplifier, its first input terminal is connected to the output terminal of the first gate-source feedback stacked amplification network, and its second input terminal is connected to the output terminal of the second gate-source feedback stacked amplification network. The self-biased voltage divider network is connected to the first gate-source feedback stacked amplification network, the second gate-source feedback stacked amplification network, and the output matching network, respectively.

[0037] Among them, the first gate-source feedback stacked amplification network and the second gate-source feedback stacked amplification network are active amplification networks, while the input matching network, the output matching network and the self-biased voltage divider network are passive networks.

[0038] like Figure 2 As shown, the input matching network includes a DC blocking capacitor C1, microstrip line TL1, microstrip line TL3, a first RC suppression circuit, and microstrip line TL7 connected in series. One end of the DC blocking capacitor C1 is the input terminal of the input matching network. An open-circuit microstrip line TL2 is also connected to the connection node of microstrip lines TL1 and TL3. The connection node of the first RC suppression circuit and microstrip line TL7 is also connected to one end of microstrip line TL4. The other end of microstrip line TL4 is connected to one end of resistor R3 and the second RC suppression circuit, respectively. The other end of resistor R3 is connected to the low-voltage bias power supply V. g1Connections; the other end of microstrip line TL7 is connected to one end of microstrip line TL6 and one end of microstrip line TL5 respectively. The other end of microstrip line TL6 is the first output terminal of the input matching network, and the other end of microstrip line TL5 is the second output terminal of the input matching network; the first RC suppression circuit includes a resistor R1 and a capacitor C2 connected in parallel, and the second RC suppression circuit includes a resistor R2 and a grounded capacitor C3 connected in series.

[0039] In this embodiment of the invention, the first gate-source feedback stacked amplification network and the second gate-source feedback stacked amplification network have the same structure.

[0040] The first gate-source feedback stacked amplification network includes a top-layer transistor M3, an intermediate-layer transistor M2, and a bottom-layer transistor M1, all stacked in a source-drain configuration. The source of the bottom-layer transistor M1 is grounded, and its gate serves as the input terminal of the first gate-source feedback stacked amplification network. The gate of the intermediate-layer transistor M2 is connected to both a self-biased voltage divider network and a first gate compensation circuit. A capacitor C4 and a microstrip line TL are connected in series between the gate and source of the intermediate-layer transistor M2. 10 The gate of the top-level transistor M3 is connected to both the self-biased voltage divider network and the second gate compensation circuit. A capacitor C5 and a microstrip line TL are connected in series between its gate and source. 13 Its drain is the output terminal of the first gate-source feedback stacked amplification network; a first L-type matching stub is connected between the drain of the bottom transistor M1 and the source of the middle layer transistor M2, and a second L-type matching stub is connected between the drain of the middle layer transistor M2 and the source of the top layer transistor M3.

[0041] The second gate-source feedback stacked amplification network includes a top-layer transistor M6, an intermediate-layer transistor M5, and a bottom-layer transistor M4, all stacked in a source-drain configuration. The source of the bottom-layer transistor M4 is grounded, and its gate serves as the input to the second gate-source feedback stacked amplification network. The gate of the intermediate-layer transistor M5 is connected to both a self-biased voltage divider network and a third gate compensation circuit, and a capacitor C is connected in series between its gate and source. 10 and microstrip lines TL 16 The gate of the top-level transistor M6 is connected to both the self-biased voltage divider network and the fourth gate compensation circuit, and a capacitor C is connected in series between its gate and source. 11 and microstrip lines TL 19 Its drain is the output terminal of the second gate-source feedback stacked amplification network; a third L-type matching stub is connected between the drain of the bottom transistor M4 and the source of the middle transistor M5, and a fourth L-type matching stub is connected between the drain of the middle transistor M5 and the source of the top transistor M6.

[0042] The first gate compensation circuit includes a gate stabilizing resistor R4 and a compensation grounding capacitor C6 connected in series; the second gate compensation circuit includes a gate stabilizing resistor R5 and a compensation grounding capacitor C7 connected in series; the third gate compensation circuit includes a gate stabilizing resistor R6 and a compensation grounding capacitor C8 connected in series; and the fourth gate compensation circuit includes a gate stabilizing resistor R7 and a compensation grounding capacitor C9 connected in series.

[0043] The first L-type matching stub includes a microstrip line TL9 connected in series between the drain of the bottom-layer transistor M1 and the source of the intermediate-layer transistor M2, and an open-circuit microstrip line TL8 connected in parallel between the drain of the bottom-layer transistor M1 and the microstrip line TL9. The second L-type matching stub includes a microstrip line TL8 connected in series between the drain of the intermediate-layer transistor M2 and the source of the top-layer transistor M3. 12 And the drain of the intermediate layer transistor M2 and the microstrip line TL connected in parallel. 12 Open-circuit microstrip line TL 11 The third L-type matching stub includes a microstrip line TL connected in series between the drain of the bottom transistor M4 and the source of the middle transistor M5. 15 And the drain and microstrip line TL connected in parallel to the bottom transistor M4 15 Open-circuit microstrip line TL 14 The fourth L-type matching stub includes a microstrip line TL connected in series between the drain of the intermediate layer transistor M5 and the source of the top layer transistor M6. 18 And the drain of the intermediate layer transistor M5 and the microstrip line TL connected in parallel. 18 Open-circuit microstrip line TL 17 .

[0044] In this embodiment of the invention, a structure of a two-way parallel gate-source feedback stacked amplification network is provided. The specific number of parallel gate-source feedback stacked amplification networks can be increased according to actual needs. The number of intermediate layer transistors in each parallel gate-source feedback stacked amplification network can also be increased according to actual needs.

[0045] The output matching network includes DC blocking capacitors C connected in series. 13 Microstrip line TL 32 Microstrip line TL 29 and microstrip lines TL 26 DC blocking capacitor C 13 One end is the output of the output matching network; microstrip line TL 32 and microstrip lines TL 29 The connection node is also connected to an open-circuit microstrip line TL. 30 and open-circuit microstrip line TL 31 microstrip line TL 29 and microstrip lines TL 26 The connection node is also connected to an open-circuit microstrip line TL. 27and open-circuit microstrip line TL 28 microstrip line TL 26 The other end is connected to the microstrip line TL. 22 One end, microstrip line TL 23 One end and the self-biased voltage divider network connection; microstrip line TL 22 The other end is connected to the microstrip line TL 20 One end is connected to the microstrip line TL 20 The other end is the first input of the output matching network, the microstrip line TL. 22 and microstrip lines TL 20 The connection node is also connected to the microstrip line TL 21 One end is connected to the microstrip line TL 21 The other end is connected to the third RC suppression circuit and the first high-voltage bias power supply V, respectively. d1 Connection; microstrip line TL 23 The other end is connected to the microstrip line TL 24 One end is connected to the microstrip line TL 24 The other end is the second input of the output matching network, the microstrip line TL 23 and microstrip lines TL 24 The connection node is also connected to the microstrip line TL 25 One end is connected to the microstrip line TL 25 The other end is connected to the fourth RC suppression circuit and the second high-voltage bias power supply V, respectively. d2 Connection; the third RC suppression circuit includes a series resistor R 15 and grounding capacitor C 12 The fourth RC suppression circuit includes a series resistor R 16 and grounding capacitor C 14 .

[0046] The self-biased voltage divider network includes resistors R8, R9, and R... 10 Resistance R 11 Resistance R 12 Resistance R 13 and resistance R 14 One end of resistor R8 is grounded, and the other end is connected to one end of resistor R9 and resistor R... 10 one end and resistor R 11 One end is connected to resistor R 11 The other end is connected to resistor R respectively 12 One end, resistor R 13 one end and resistor R 14 One end of resistor R9 is connected to the gate of transistor M2 in the intermediate layer of the first gate-source feedback stacked amplification network; the other end of resistor R9 is connected to the gate of transistor M2 in the intermediate layer of the first gate-source feedback stacked amplification network. 10 The other end is connected to the gate of the intermediate layer transistor M5 in the second gate-source feedback stacked amplification network, with resistor R12 The other end is connected to the gate of the top-level transistor M3 in the first gate-source feedback stacked amplification network, with resistor R 13 The other end is connected to the gate of the top-level transistor M6 in the second gate-source feedback stacked amplification network, with resistor R 14 The other end is matched with the microstrip line TL in the output matching network. 26 connect.

[0047] (a) Implementation Example

[0048] A Cascode distributed broadband amplifier circuit was designed based on GaAs technology. Utilizing the excellent high-frequency performance and high electron mobility of GaAs material, the amplifying dies T1 and T2, as well as the regulating transistor TB, were fabricated in the Cascode amplification unit. Multiple Cascode amplification units (CELL1 - CELL7) were cascaded via microstrip transmission lines to construct a distributed amplifier circuit. The microstrip transmission lines (TL_in series, TL_out series) at the input and output terminals were laid out and parameterized according to design requirements to achieve efficient signal transmission and synthesis, thus meeting the broadband amplification requirements.

[0049] (ii) Cascode Amplification Unit Settings

[0050] In each Cascode amplifier unit, T1 uses a common-source connection with a fixed gate voltage VG1 of -0.55V for initial amplification of the input RF signal. T2 uses a common-gate connection with its gate connected to the voltage adjustment node VG2. By adjusting the VG2 voltage within the range of -1.0V to +3V, the operating state of T2 is changed, thereby adjusting the gain of the Cascode amplifier unit. Simultaneously, the dimensions and parameters of T1 and T2 are rationally designed to optimize the performance of the Cascode structure and improve the amplifier's reverse isolation and high-frequency characteristics.

[0051] (III) Adjustment tube and bias network

[0052] The regulating transistor TB is set with a suitable gate voltage through a voltage divider network composed of RB1 and RB2, enabling it to operate in the linear region. During actual debugging, the resistance values ​​of RB1 and RB2 are precisely adjusted according to the overall power consumption and stability requirements of the circuit. This ensures that TB can stably output the VDD bias voltage based on the current demands of each amplification unit in the Cascode distributed circuit due to gain adjustment or load changes, providing a reliable power supply for each stage of the Cascode amplification unit.

[0053] (iv) Implementation of gain adjustment

[0054] The VG2 voltage is precisely adjusted within the range of -1.0V to +3V using an external control circuit. A high-precision voltage source and control chip are used to gradually change the VG2 voltage value according to a preset gain adjustment strategy. For example, when an amplifier gain needs to be increased, the VG2 voltage is slowly increased, and the amplitude and gain changes of the output signal of each Cascode amplification unit and the entire amplifier are monitored in real time until the target gain value is reached; conversely, the VG2 voltage is decreased to reduce the gain. Simultaneously, the signal transmission and superposition on the microstrip transmission line are observed to ensure signal integrity and stability during gain adjustment.

[0055] (V) Core protection is achieved

[0056] During circuit testing and operation, various abnormal voltage conditions were simulated, such as artificially applying excessively high gate negative bias voltage to the die of a Cascode amplifier unit. Using oscilloscopes and other testing instruments, the gate-drain / gate-source voltage waveforms of T1 and T2 in each Cascode amplifier unit were monitored in real time. When an overvoltage condition occurred, clamping diodes D1, D2, and D3 were clearly observed to quickly conduct, clamping the voltage within a safe threshold. This verified the effectiveness of the die protection mechanism in the Cascode distributed circuit, ensuring the safe operation of each die stage under complex conditions.

[0057] (vi) Implementation of broadband amplification

[0058] Using professional RF simulation software (such as ADS), the GaAs-based Cascode distributed broadband amplifier circuit was modeled and simulated. Parameters such as the length, width, and characteristic impedance of the microstrip transmission line, as well as the spacing of the Cascode amplification units and circuit component parameters, were optimized to ensure that the amplifier exhibits a flat gain response, good input-output matching characteristics, and low signal loss within the target frequency bandwidth (such as the X-band). Through repeated simulations and optimizations, the circuit parameters were adjusted to ultimately achieve broadband amplification performance that meets the requirements of practical applications, enabling the amplifier to stably and efficiently amplify signals over a wide frequency range.

[0059] The following is combined with Figure 2 The specific working principle and process of this invention are described below:

[0060] The broadband amplifier circuit of this invention is based on a Cascode distributed structure, with each functional module working together to achieve high efficiency. The following will integrate gain adjustment, die protection, bias stabilization, and broadband amplification processes to coherently explain its complete working principle and process.

[0061] The input signal is coupled to the microstrip transmission line TL_in via the input capacitor Cin and transmitted in a traveling wave manner. During this process, an external control signal can adjust the voltage node VG2, which, when varying from -1.0V to +3V, directly controls the gate potential of the common-gate transistor T2 in the Cascode amplifier unit. When the VG2 voltage increases, T2 conducts more strongly, the channel resistance decreases, and the transconductance of the Cascode unit increases, thus enhancing signal amplification; conversely, the gain decreases. The amplified signals from each unit are superimposed in phase on TL_out, achieving flexible gain adjustment.

[0062] The bias network formed by the regulating transistor TB and RB1 and RB2 provides VDD bias voltage for circuit stability. The voltage divider between RB1 and RB2 sets the gate voltage of TB so that it operates in the linear region. When the current demand changes due to gain adjustment or load changes, TB automatically adjusts its conduction state to maintain VDD stability and ensure the stability of the operating point of the Cascode amplifier unit.

[0063] During operation, if abnormal voltages such as negative bias occur at the gate of the Cascode cell die, clamping diodes D1, D2, and D3 will quickly conduct, clamping the gate-drain / gate-source voltages of T1 and T2 to a safe value, preventing die overvoltage breakdown and ensuring the safety of each stage of the die.

[0064] Meanwhile, the excellent high-frequency characteristics and reverse isolation of the Cascode structure reduce signal distortion interference. The rationally designed TL_out transmission line and the spacing between each unit ensure that the signals of different frequencies are in phase, realizing the in-phase superposition of amplified signals over a wide frequency range. Finally, the amplified broadband signal is output through the output capacitor Cout, which meets the needs of fields such as radio frequency communication and radar detection.

[0065] This broadband amplifier circuit is based on a Cascode structure design, containing multiple cascaded Cascode amplification units (CELL1 - CELL7). Each cell consists of a pair of common-source, common-gate connected amplification dies (T1 and T2), forming a Cascode amplification structure. The circuit includes a D-mode adjustment transistor TB, whose gate and drain are connected to RB1 and RB2, respectively; it also features clamping diodes D1, D2, and D3, which work in conjunction with RB1 and RB2. Furthermore, microstrip transmission lines (TL_in series and TL_out series) are provided at the input and output terminals, along with input / output matching network components such as input capacitor Cin, output capacitor Cout, and matching resistor Rg1, as well as power supply decoupling components such as a high-frequency choke LDD, decoupling resistor RDD, and decoupling capacitor CDD.

[0066] Specific embodiments have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

[0067] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A broadband amplifier circuit with adjustable gain and die protection function, characterized in that, include: At least one amplification unit CELL based on a Cascode structure, the amplification unit includes a bottom transistor T1 connected to a common source and a top transistor T2 connected to a common gate. The gate of the top transistor T2 is connected to a gain adjustment node VG2, which is used to change its conduction state by receiving an adjustment voltage in the range of -1.0V to +3.0V, thereby realizing continuous adjustment of the circuit gain. The circuit includes multiple amplification units CELL1-CELL7, which are cascaded through an input microstrip transmission line TL_in and an output microstrip transmission line TL_out to form a distributed amplifier architecture. In each amplification unit, the gate of the bottom transistor T1 is coupled to the input microstrip transmission line TL_in through an input capacitor Cin, its drain is connected to the source of the top transistor T2, and the drain of the top transistor T2 is connected to the output microstrip transmission line TL_out. The bias stabilization circuit includes an adjustment transistor TB, a first bias resistor RB1, and a second bias resistor RB2. The first bias resistor RB1 is connected between the power supply VDD and the clamping circuit, and the second bias resistor RB2 is connected between the clamping circuit and the gate of the adjustment transistor TB. The drain of the adjustment transistor TB is used to provide a stable power supply bias voltage VDD for the amplification unit. The adjustment transistor TB is a depletion-mode D-mode transistor. The clamping circuit includes a first clamping diode D1, a second clamping diode D2, and a third clamping diode D3. The clamping diodes D1 / D2 / D3 are connected in series. Their series structure is connected between the connection point of the first bias resistor RB1 and the second bias resistor RB2 in the bias stabilization circuit and the gain adjustment node VG2, and is used to conduct when an abnormal voltage occurs to protect the transistor die. An input microstrip transmission line TL_in and an output microstrip transmission line TL_out are provided. The input microstrip transmission line TL_in is used to couple the input signal to the input terminal of the amplification unit, and the output microstrip transmission line TL_out is used to synthesize the signal amplified by the at least one amplification unit and output it. The characteristic impedance, length, and spacing between the amplification units of the input microstrip transmission line TL_in and the output microstrip transmission line TL_out are configured such that signals of different frequencies are superimposed in phase on the output microstrip transmission line TL_out to obtain a flat gain response over a wide bandwidth.

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