Digital oscillation ring, digital phase-locked loop and large-scale digital integrated circuit
By combining cascaded basic transmission units and digital phase-locked loops within a single loop, high flexibility and high precision of multi-frequency clock output are achieved, solving the problems of high resource consumption and poor design reusability in existing technologies, and adapting to the needs of different process nodes and application scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- YUXIAN MICROELECTRONICS (CHENGDU) CO LTD
- Filing Date
- 2026-02-28
- Publication Date
- 2026-06-02
AI Technical Summary
Existing technologies for implementing multi-frequency clock output suffer from problems such as high hardware resource consumption, poor design reusability, and insufficient flexibility, making it difficult to adapt to the needs of different process nodes and application scenarios.
A closed-loop oscillation structure consisting of N cascaded basic transmission units is adopted. The total loop delay is dynamically adjusted by digital configuration signals to achieve adjustable frequency output at multiple frequency points. Combined with the frequency and phase detection modules of the digital phase-locked loop, accurate frequency and phase calibration is performed.
It significantly saves chip area and physical resources, has high flexibility and modularity, and can achieve multi-frequency coverage within a single loop to adapt to the frequency requirements of different application scenarios.
Smart Images
Figure CN122137390A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of clock signal generation, in particular to a digital oscillation ring, a digital phase-locked loop and a large-scale digital integrated circuit. BACKGROUND
[0002] With the integrated circuit technology entering the nanometer level and the rapid development of high-speed computing technology, high-precision clock generation circuits have become the core components of modern SoC (System on Chip) design. In complex scenarios such as communication, data processing and multimedia applications, chips often need to output clock signals of multiple target frequencies according to different operating modes. Therefore, an oscillator circuit with multiple frequency points, adjustable, high precision and high stability has become a key module of frequency synthesizers such as ADPLL (All-Digital Phase-Locked Loop).
[0003] At present, the existing technical solutions for realizing multi-frequency point clock output mainly fall into two categories.
[0004] The first category is to use multiple independent oscillation loops in parallel. That is, for each target frequency, a fixed slow loop oscillation circuit is constructed on the hardware, and a multi-way selector (MUX) is used to switch between different loops according to requirements. Although this scheme can ensure the stability of the frequency output, it has the disadvantage of consuming a large amount of hardware resources. When the system needs to support a large number of frequency points (such as tens of frequency points), a large number of physical loops and complex routing selection networks need to be arranged, greatly increasing the area cost and power consumption of the chip.
[0005] The second category is a conventional digital control oscillation chain. Although this type of scheme attempts to introduce control logic into the chain, the existing structure often lacks good modular design and scalability. When the frequency coverage range or frequency resolution needs to be adjusted, the internal topology of the entire oscillator often needs to be redesigned, resulting in poor design reusability and difficulty in flexible adaptation to different process nodes and application scenario requirements.
[0006] Therefore, it is necessary to design a new clock signal generation scheme. SUMMARY
[0007] The purpose of the present application is to provide a digital oscillation ring, a digital phase-locked loop and a large-scale digital integrated circuit that can realize reliable coverage of multiple frequency points in a single loop, which can significantly save physical resource area and have high flexibility and modularization characteristics.
[0008] In order to achieve the above purpose, the present application provides a digital oscillation ring supporting multiple frequency points, which comprises a logic gate and N basic transmission units cascaded in sequence, N being an integer greater than 1. Each of the basic transmission units includes a unit input terminal, a unit output terminal, and a selection switch. The selection switch includes a first input terminal and a second input terminal. The unit input terminal is directly connected to the first input terminal to form a direct link. The unit input terminal is also connected to the second input terminal through a plurality of time delay units connected in series to form a delayed link. The selection switch is used to selectively connect one of the first input terminal and the second input terminal to the unit output terminal according to a configuration signal. The logic gate has a logic enable terminal, a logic feedback terminal, and a logic output terminal; the logic enable terminal is used to receive an enable signal, the logic feedback terminal is connected to the unit output terminal of the last basic transmission unit, and the logic output terminal is connected to the unit input terminal of the first basic transmission unit, so as to form a closed-loop oscillation circuit.
[0009] Preferably, the logic gate is a NAND gate, the two input terminals of the NAND gate are respectively used as the logic enable terminal and the logic feedback terminal, and the output terminal of the NAND gate is used as the logic output terminal.
[0010] Preferably, the delay unit is a transmission inverter.
[0011] Preferably, the output of each transmission inverter in the delay link is connected to a corresponding branch unit, the branch unit including one or more load inverters, the branch unit being used to increase the signal transmission delay of the delay link.
[0012] Preferably, when adjusting the output frequency of the digital oscillating loop, the enable signal received by the logic enable terminal is set to the off state; during the interval when the oscillating loop is off, the configuration signals of some or all of the selection switches in the basic transmission unit are reassigned.
[0013] Preferably, the interval is greater than or equal to 360 ps.
[0014] The present invention also provides a multi-frequency digital phase-locked loop, comprising: The digital oscillating ring described above is used to output an oscillation clock of a corresponding frequency according to the received configuration signal; A frequency discrimination module is connected to the digital oscillation ring. The frequency discrimination module is used to detect the frequency of the oscillation clock and trigger the update of the configuration signal according to the detection result to adjust the frequency of the oscillation clock so that the frequency of the oscillation clock meets the target frequency condition. A phase detection module, which is connected to the frequency detection module, is used to perform phase calibration based on the phase error between the oscillation clock and the reference clock after the frequency of the oscillation clock meets the target frequency condition, so as to output the locked target clock.
[0015] Preferably, the frequency discrimination module counts the frequency of the oscillation clock using an internal counter and compares the frequency value obtained by the count with a preset target frequency range; if the frequency value is within the target frequency range, it is determined that the target frequency condition is met, and the frequency discrimination pass flag and the current frequency signal are output to the phase discrimination module.
[0016] Preferably, it also includes a fine-tuning module and a frequency division module; The fine-tuning module is connected to the phase detection module and is used to receive the oscillating clock that has passed the frequency detection, and to adjust the signal path of the oscillating clock according to the phase error control signal output by the phase detection module, so as to output the fine-tuned clock signal. The frequency division module is connected to the fine-tuning module and the phase detection module respectively, and is used to receive the fine-tuned clock signal and perform frequency reduction processing to generate a feedback clock signal that matches the reference clock frequency, and input the feedback clock signal to the phase detection module; The phase detection module dynamically updates the phase error control signal by comparing the phase difference between the rising edge of the reference clock and the rising edge of the feedback clock signal to form a closed-loop control until the target clock is locked at the output.
[0017] The present invention also provides a large-scale digital integrated circuit, which includes a circuit body and a digital oscillation ring as described above disposed on the circuit body.
[0018] Compared to existing technologies, the digital oscillation ring provided by the above-mentioned technical solution achieves highly reconfigurable and precisely adjustable frequency output by adopting a closed-loop oscillation structure composed of N cascaded basic transmission units. Compared to traditional parallel multi-loop solutions, this solution only requires digital configuration of each level of unit within a single physical loop to cover a very wide frequency range, significantly reducing chip area and physical resource consumption. Secondly, the decoupling design of the through link and delay link in each basic transmission unit allows the system to flexibly control the total delay by increasing or decreasing the number of delayers, thus providing extremely high frequency adjustment flexibility and resolution. In addition, the fully digital circuit topology gives it excellent process adaptability and modularity, which not only simplifies circuit design and simulation complexity but also ensures the reliability and consistency of multi-frequency output in different application scenarios. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the principle structure of the digital oscillation ring in an embodiment of the present invention.
[0020] Figure 2 This is a schematic diagram of the principle structure of any one of the basic transmission units in the digital oscillation ring in an embodiment of the present invention.
[0021] Figure 3 This is a schematic diagram of the principle structure of the digital phase-locked loop in an embodiment of the present invention. Detailed Implementation
[0022] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.
[0023] This embodiment discloses a digital oscillator loop (DCO) that supports multiple frequency points, such as... Figure 1 and Figure 2 Its system mainly consists of logic gates Ge and N basic transmission units tag cascaded in sequence, where N is an integer greater than 1.
[0024] Each basic transmission unit (tag) includes a unit input terminal (t_in), a unit output terminal (t_out), and a selection switch (mux). The selection switch (mux) includes a first input terminal (m_in1), a second input terminal (m_in2), and an output terminal.
[0025] Within each basic transmission unit tag, the unit input terminal t_in and the first input terminal m_in1 are directly connected by a wire to form a straight-through link with low physical delay.
[0026] Meanwhile, the unit input terminal t_in is also connected to the second input terminal m_in2 through several time delay units Q1 connected in series to form a high physical delay delay link.
[0027] Select the output of the switch mux as an OR connection to the unit output t_out.
[0028] The logic gate Ge has a logic enable terminal G1, a logic feedback terminal G2, and a logic output terminal G3. In the overall topology, the logic output terminal G3 is connected to the unit input terminal t_in of the first (i.e., the first) basic transmission unit tag1. The unit output terminals t_out of each basic transmission unit tag are sequentially connected to the unit input terminals t_in of the next level basic transmission unit tag. The unit output terminal t_out of the last (i.e., the Nth) basic transmission unit tagN is connected to the logic feedback terminal G2, thus forming a physically connected closed-loop oscillating circuit.
[0029] The working principle and signal logic of the aforementioned digital oscillator loop (DCO) are as follows: The logic enable terminal G1 receives an external enable signal (ro_en). When the enable signal is at a valid level, the closed-loop circuit starts oscillating. The total delay of the oscillation loop determines the output frequency of the digital oscillator loop (DCO). The total delay is equal to the delay of the logic gate Ge plus the sum of the delays of the N basic transmission units (tags). For each basic transmission unit (tag), the selection switch mux is used to selectively connect its first input terminal m_in1 or its second input terminal m_in2 to the unit output terminal t_out based on the received configuration signal (sel). If the configuration signal indicates that the first input terminal m_in1 is connected, the signal follows a direct path, resulting in a smaller unit delay; if the configuration signal indicates that the second input terminal m_in2 is connected, the signal follows a delayed path including the delay unit Q1, resulting in a larger unit delay.
[0030] This embodiment, by selecting the combination of the switch mux and different delay links, only requires a basic oscillation loop supplemented by multiple basic transmission units tag. The total delay of the loop can be dynamically adjusted by digital configuration signals to achieve adjustable frequency output at multiple frequency points, which greatly saves the chip physical resources occupied by using a large number of independent slow loops and selectors.
[0031] Furthermore, the logic gate Ge is specifically a NAND gate. The two input pins of this NAND gate are configured as the logic enable terminal G1 and the logic feedback terminal G2, respectively, and its output pin serves as the logic output terminal G3.
[0032] The logic enable terminal G1 receives the enable signal. When ro_en=0 (low level), regardless of the input value of the logic feedback terminal G2, the NAND gate output is always high (1), the oscillation circuit is blocked, and oscillation stops; when ro_en=1 (high level), the NAND gate is equivalent to an inverter, which inverts the clock signal input to the logic feedback terminal G2 and outputs it to the first basic transmission unit tag1. This structure not only provides enable control function, but its own inversion characteristic also satisfies the inversion condition required for loop oscillation.
[0033] In addition, the delay unit Q1 in the delay link is specifically a transmission inverter Q1.
[0034] In chip integrated circuit design, several transmission inverters Q1 connected in series can provide a stable and predictable gate delay. In a basic transmission unit tag, several inverters and a selection switch mux are combined as a module component. The sum of the delays of all the series-connected transmission inverters Q1 determines the delay difference step size generated by the basic transmission unit tag when switching between a straight-through link and a delayed link.
[0035] In another embodiment, in the delay link, the output of each transmission inverter Q1 is physically connected to a corresponding branch unit D0. The branch unit D0 includes one or more load inverters Q2 connected in parallel.
[0036] The output of load inverter Q2 is either floating or connected to a fixed level, acting as a parasitic capacitance (MOS capacitor) in this circuit. When the signal is transmitted through the link of transmission inverter Q1, the addition of branch unit D0 increases the equivalent load capacitance along the signal transmission path, thereby increasing the RC charging and discharging time constant. For example, without branch unit D0, the delay of a single-stage inverter is 10 ps. By connecting two load inverters Q2 in parallel, the delay of this stage can be precisely stretched to 12 ps, thus achieving fine-grained control of the output frequency step size.
[0037] The frequency adjustment execution process for the aforementioned DCO is as follows: S11: When it is necessary to adjust the output frequency of the digital oscillator loop (DCO), the controller sends a control command to the logic enable terminal G1, setting the received enable signal from high level to low level (off state), and the oscillator loop stops working.
[0038] S12: During the interval when the oscillation circuit is closed, the controller reassigns the configuration signal of the selection switch mux in some or all of the basic transmission units tag according to the target frequency (for example, changing the configuration signal of some units from 0 to 1).
[0039] S13: After the assignment is completed, the enable signal will be reset to the on state (high level), and the oscillation circuit will start oscillating at the new frequency.
[0040] It should be noted that if the configuration signal of the selector switch mux is directly modified during the continuous oscillation (dynamic) of the loop, it is very easy to generate glitches at the edge of the clock signal, causing metastability or even runaway in the subsequent circuit. This embodiment avoids the risk of glitches generated by dynamic switching by switching the frequency point in a quasi-static scenario (i.e., during the interval between enabling and disabling).
[0041] Specifically, the interval for shutting down the oscillation circuit is configured to be greater than or equal to 360 ps.
[0042] In summary, let's now take a specific example to illustrate the detailed dynamic working process of the DCO in the above embodiments: Suppose a chip integrates a DCO containing N=10 basic transmission units (tags), with an inherent NAND gate delay of 50 ps. For each basic transmission unit (tag), the delay of the pass-through link is fixed at 10 ps, and the delay of the delay link (internal series connection of four transmission inverters Q1 and branch capacitors) is 50 ps. The selector switch mux selects the pass-through link when sel=0 and the delay link when sel=1.
[0043] Initial state: The system requires a high output frequency. The controller assigns all configuration signals [sel_9 : sel_0] of the 10 units to 0000000000.
[0044] Total one-way delay of the loop = NAND gate delay (50ps) + 10 * pass-through delay (10ps) = 150ps.
[0045] At this point, the oscillation period of the DCO is 2 * 150ps = 300ps, and the corresponding output frequency is 1 / 300ps ≈ 3.33GHz. Setting ro_en to 1 causes the loop to oscillate at 3.33GHz.
[0046] Due to a change in application scenario, the chip needs to be frequency-reduced to lower power consumption. The target frequency is adjusted to approximately 1.61GHz (the target oscillation period needs to reach approximately 620ps, and the corresponding target unidirectional delay needs to reach 310ps). The adjustment process is as follows: A: At time T0, the system pulls ro_en from high level to 0, cutting off the oscillation circuit and stopping the loop oscillation.
[0047] B: At time T0 + 50ps, the controller sends a new configuration signal, changing [sel_9 : sel_0] to 0000001111 (that is, retaining the direct links of 6 units and enabling the delayed links of 4 units).
[0048] At this point, the new expected one-way delay is calculated as follows: One-way delay = NAND gate delay (50ps) + (6 gates × pass-through delay 10ps) + (4 gates × delay link 50ps) = 50ps + 60ps + 200ps = 310ps.
[0049] C: The system is forced to wait until T0 + 400ps. Since the set interval (400ps) is greater than the safety margin required for setup and hold (limited to 360ps), the internal voltages of all selector switches mux have been absolutely stable to the new signal path by this time.
[0050] D: At time T0 + 400ps, the system pulls ro_en back high to 1. The loop begins to oscillate seamlessly and without glitches with a unidirectional delay of 310ps. At this time, the new oscillation period is 2 × 310ps = 620ps, accurately outputting a stable new frequency of 1 / 620ps ≈ 1.61GHz.
[0051] In another embodiment of the present invention, a multi-frequency digital phase-locked loop (ADPLL) is disclosed, which can be integrated into a digital chip as an independent component.
[0052] like Figure 3 The digital phase-locked loop includes the digital oscillation ring (DCO) disclosed in the above embodiments, as well as a frequency discrimination module (FD) and a phase discrimination module (PD).
[0053] The input terminal of the frequency discrimination module FD is connected to the output terminal of the digital oscillator ring DCO; the phase discrimination module PD is connected to the output terminal of the frequency discrimination module FD.
[0054] The working principle and data flow transmission of this ADPLL are as follows: First, the digital oscillator loop (DCO) starts according to the initial software configuration signal and outputs the initial oscillation clock (dco_clk).
[0055] Subsequently, the frequency discrimination module FD performs coarse adjustment detection on dco_clk, identifying the frequency difference between it and the reference clock (ref_clk). If the frequency does not meet the target frequency condition, the frequency discrimination module FD returns an error message or outputs a control signal (sel_en) to trigger the digital oscillator loop (DCO) to update the configuration signal, causing the tuning point to move forward or backward; if the condition is met, the signal is passed to the next stage.
[0056] Finally, the phase detection module (PD) intervenes after confirming that the coarse frequency adjustment meets the standard, and detects the phase difference between the oscillation clock and the external reference clock in real time. It generates a phase error control signal for fine phase calibration until the target clock (pll_clk) is fully locked.
[0057] This embodiment combines the multi-frequency flexibility of the digital oscillator loop (DCO) with the closed-loop control capabilities of the frequency discrimination module (FD) and the phase discrimination module (PD), thus eliminating the dependence of traditional analog phase-locked loops on high-process-sensitive components such as capacitors and resistors, and achieving stable output of the target frequency entirely with digital logic.
[0058] On the other hand, the frequency discrimination module FD integrates a high-frequency counter, comparator, and register.
[0059] Based on this, the execution logic of the frequency discrimination module FD is as follows: S21: The frequency discrimination module FD receives the oscillation clock output by the digital oscillation ring DCO, and uses an internal counter to count the rising edge of the oscillation clock within a fixed reference time window (such as one external reference clock cycle) to obtain the count value corresponding to the current frequency.
[0060] S22: The acquired count value is sent to the comparator and compared with the preset target frequency range (upper boundary value and lower boundary value) in the register.
[0061] S23: If the count value is not within the range, trigger the digital oscillator loop (DCO) to switch gears; if the count value is within the target frequency range, then the target frequency condition is met.
[0062] S24: After determining that the conditions are met, the frequency discrimination module FD pulls up the frequency discrimination pass flag signal (pd_en, dco_clk_stable) and outputs the frequency signal that has passed the frequency discrimination (fd_dco_clk) and the current target frequency code (fd_rate_code) to the phase discrimination module PD.
[0063] On the other hand, in addition to the digital oscillator ring (DCO), frequency discriminator module (FD), and phase discriminator module (PD), the ADPLL also includes a fine-tuning module (DDC) and a frequency divider module (DIV).
[0064] The output of the phase detector module PD is connected to the fine-tuning module DDC; the output of the fine-tuning module DDC is connected to the input of the frequency divider module DIV and the phase detector module PD respectively; the output of the frequency divider module DIV is connected to the phase detector module PD for reverse feedback.
[0065] The working principle of ADPLL in this embodiment is as follows: The oscillation clock (fd_dco_clk) that passes the initial screening by the frequency discrimination module FD is used as the reference input. The phase discrimination module PD first performs coarse calibration by capturing the rising edge, and selects the signal with the smallest phase difference from the reference clock as the input to the fine adjustment module DDC.
[0066] The fine-tuning module DDC adjusts the phase of the clock signal (pd_dco_clk) at the picosecond level by increasing or decreasing the overall delay through the internal digital delay chain (DDC chain) based on the phase error control signal (ddc_mux_sel) output by the phase detector module PD, and outputs the finely tuned clock signal (ddc_clk_out) to the phase detector module PD and the frequency divider module DIV.
[0067] The frequency divider module DIV receives the finely tuned high-frequency clock signal, performs frequency reduction processing according to the preset division ratio, generates a feedback clock signal (div_clk) that is consistent with the external reference clock frequency, and sends it to the phase detector module PD.
[0068] The phase detection module (PD) compares the phase difference between the rising edge of the external reference clock and the rising edge of the feedback clock signal. If a slight error still exists, the phase error control signal is dynamically updated to form a closed-loop adjustment; if the phase comparison is consistent (phase detection passes), the lockout indicator signal (pll_lock) is pulled high, and the final pll_clk is output.
[0069] The following example illustrates the specific working process of the ADPLL.
[0070] Assume an externally input, highly stable reference clock of 25MHz. The system requires the ADPLL output to lock onto a target clock of 1200MHz. Set the division ratio N of the frequency divider module DIV to 1200 / 25 = 48. The allowable range for the count value per reference cycle corresponding to the target frequency is set to [47, 49].
[0071] Phase 1 (Frequency discrimination module FD triggers digital oscillator loop DCO for coarse frequency adjustment): The software issues the initial configuration, the digital oscillator (DCO) starts oscillating, and the initial actual output frequency dco_clk = 1050MHz.
[0072] The frequency discrimination module FD's internal counter counts the rising edge of dco_clk within one 25MHz cycle (40ns) and obtains a count value of 42. 42 is not within the acceptable range of [47, 49].
[0073] If the FD determines that the frequency is too slow, it outputs the sel_en signal to guide the digital oscillator loop (DCO) to reduce the number of inverter stages in the delay link.
[0074] After several dynamic updates and interval restarts, the output frequency of the digital oscillator loop (DCO) increased to approximately 1200MHz (this is an approximation due to discrete digital control). At this point, the frequency discriminator module FD counted a value of 48, falling within the target range. The frequency discriminator module FD pulled up the frequency discrimination pass flag (pd_en) and released the clock signal (fd_dco_clk) that had now met the coarse adjustment criteria, handing it over to the subsequent modules.
[0075] The second stage (phase detection module PD controls DDC to perform phase fine-tuning and locking): The signal indicating that the coarse adjustment has met the target (fd_dco_clk) enters the fine adjustment module DDC.
[0076] In the initial state, the fine-tuning module DDC does not add any extra delay, and the signal passes directly through the fine-tuning module DDC and is output to the frequency divider module DIV.
[0077] The frequency divider module DIV performs a frequency reduction operation by dividing by 48, and outputs a feedback clock signal (div_clk) of about 25MHz to the phase detector module PD.
[0078] The phase detector module (PD) simultaneously receives a 25MHz external reference clock and a feedback clock (div_clk). The edge detection logic of the phase detector module (PD) found that although the two frequencies are roughly the same, the rising edge of the feedback clock is about 80ps ahead of the rising edge of the reference clock (there is a phase lead error).
[0079] The phase detection module (PD) immediately outputs a phase error control signal (ddc_mux_sel) to the fine-tuning module (DDC), instructing the fine-tuning module (DDC) to enable its internal micro digital delay chain.
[0080] The fine-tuning module DDC, following instructions, added an 80ps physical delay to the signal transmission path.
[0081] After delay compensation, the rising edge of the feedback clock signal (div_clk) output by the frequency divider module DIV is precisely pushed back, and finally coincides with the rising edge of the external 25MHz reference clock on the time axis (the phase difference tends to 0).
[0082] The phase detection module (PD) confirms that the phase comparison is consistent, determines that the closed loop is locked, and then pulls the lock indicator signal (pll_lock) high. At this time, the output signal (ddc_clk_out) after phase fine-tuning by the fine-tuning module (DDC) is output as the final lock clock (pll_clk) to the chip system for use.
[0083] In another embodiment of the present invention, a large-scale digital integrated circuit is also disclosed, which includes a circuit body with specific logic functions (e.g., CPU, DSP communication baseband module or SoC bus controller) and a digital oscillating ring (DCO) as disclosed in the above embodiment disposed on the circuit body.
[0084] In this integrated circuit, the Digital Oscillator (DCO) is constructed entirely using standard digital logic units (AND gates, inverters, and selectors), without relying on analog macrocells specific to a particular process node. Therefore, it possesses strong versatility and adaptability, and can be highly modularized. It is compatible with the clock allocation requirements of various processor architectures (such as ARM, x86, or RISC-V), and in addition to its application in ADPLL scenarios, it can also function as a standalone multi-frequency clock generator, flexibly providing clock sources for different asynchronous clock domains or Dynamic Voltage Frequency Scaling (DVFS) modules within the chip.
[0085] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.
Claims
1. A digital oscillation ring supporting multiple frequency points, characterized in that, It includes logic gates and N basic transmission units cascaded in sequence, where N is an integer greater than 1; Each of the basic transmission units includes a unit input terminal, a unit output terminal, and a selection switch. The selection switch includes a first input terminal and a second input terminal. The unit input terminal is directly connected to the first input terminal to form a direct link. The unit input terminal is also connected to the second input terminal through a plurality of time delay units connected in series to form a delayed link. The selection switch is used to selectively connect one of the first input terminal and the second input terminal to the unit output terminal according to a configuration signal. The logic gate has a logic enable terminal, a logic feedback terminal, and a logic output terminal; the logic enable terminal is used to receive an enable signal, the logic feedback terminal is connected to the unit output terminal of the last basic transmission unit, and the logic output terminal is connected to the unit input terminal of the first basic transmission unit, so as to form a closed-loop oscillation circuit.
2. The digital oscillating ring according to claim 1, characterized in that, The logic gate is a NAND gate, with its two input terminals serving as the logic enable terminal and the logic feedback terminal, respectively, and its output terminal serving as the logic output terminal.
3. The digital oscillating ring according to claim 1, characterized in that, The delay unit is a transmission inverter.
4. The digital oscillating ring according to claim 3, characterized in that, Each transmission inverter in the delay link has its output connected to a corresponding branch unit. The branch unit includes one or more load inverters and is used to increase the signal transmission delay of the delay link.
5. The digital oscillating ring according to claim 1, characterized in that, When adjusting the output frequency of the digital oscillation loop, the enable signal received by the logic enable terminal is set to the off state; during the interval when the oscillation loop is off, the configuration signals of some or all of the selection switches in the basic transmission unit are reassigned.
6. The digital oscillating ring according to claim 5, characterized in that, The interval time is greater than or equal to 360ps.
7. A multi-frequency digital phase-locked loop, characterized in that, include: The digital oscillating ring as described in any one of claims 1 to 6 is used to output an oscillation clock of a corresponding frequency according to the received configuration signal; A frequency discrimination module is connected to the digital oscillation ring. The frequency discrimination module is used to detect the frequency of the oscillation clock and trigger the update of the configuration signal according to the detection result to adjust the frequency of the oscillation clock so that the frequency of the oscillation clock meets the target frequency condition. A phase detection module, which is connected to the frequency detection module, is used to perform phase calibration based on the phase error between the oscillation clock and the reference clock after the frequency of the oscillation clock meets the target frequency condition, so as to output the locked target clock.
8. The digital phase-locked loop according to claim 7, characterized in that, The frequency discrimination module counts the frequency of the oscillation clock using an internal counter and compares the frequency value obtained by the count with a preset target frequency range. If the frequency value is within the target frequency range, it is determined that the target frequency condition is met, and the module outputs a frequency discrimination pass flag and the current frequency signal to the phase discrimination module.
9. The digital phase-locked loop according to claim 7, characterized in that, It also includes a fine-tuning module and a frequency division module; The fine-tuning module is connected to the phase detection module and is used to receive the oscillating clock that has passed the frequency detection, and to adjust the signal path of the oscillating clock according to the phase error control signal output by the phase detection module, so as to output the fine-tuned clock signal. The frequency division module is connected to the fine-tuning module and the phase detection module respectively, and is used to receive the fine-tuned clock signal and perform frequency reduction processing to generate a feedback clock signal that matches the reference clock frequency, and input the feedback clock signal to the phase detection module; The phase detection module dynamically updates the phase error control signal by comparing the phase difference between the rising edge of the reference clock and the rising edge of the feedback clock signal to form a closed-loop control until the target clock is locked at the output.
10. A large-scale digital integrated circuit, characterized in that, It includes a circuit body and a digital oscillating ring as described in any one of claims 1 to 6 disposed on the circuit body.