Semiconductor structure and method of manufacturing the same, storage system

Abstract

This disclosure provides a semiconductor structure and its fabrication method, as well as a memory system, relating to the field of semiconductor chip technology, and aims to solve the problem that some storage electrode layers in a capacitor structure cannot store charge. The semiconductor structure includes a semiconductor layer and a capacitor structure. The capacitor structure includes a first electrode structure, a second electrode structure, and a dielectric layer. The first electrode structure includes a first electrode layer and a second electrode layer. The first electrode layer is located on a first side of the semiconductor layer along a first direction, and the second electrode layer is located on a second side of the semiconductor layer along the first direction, with both the first and second electrode layers in contact with the semiconductor layer. The second electrode structure is disposed around the semiconductor layer and includes a first portion and a second portion. The first portion is located on the first side, and the second portion is located on the second side. The first electrode layer is disposed around the first portion, and the second electrode layer is disposed around the second portion. With the above arrangement, all first electrode layers can store charge.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, its fabrication method, and a storage system. Background Technology

[0002] With the continuous evolution of Dynamic Random Access Memory (DRAM), the storage density of planar DRAM has gradually approached the limits of process technology. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor structure, a method for fabricating the same, and a memory system.

[0004] The embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, a semiconductor structure is provided. The semiconductor structure includes a semiconductor layer and a capacitor structure; the capacitor structure includes a first electrode structure, a second electrode structure, and a dielectric layer. The first electrode structure includes a first electrode layer and a second electrode layer, the first electrode layer being located on a first side of the semiconductor layer along a first direction, and the second electrode layer being located on a second side of the semiconductor layer along the first direction, and both the first electrode layer and the second electrode layer are in contact with the semiconductor layer, the first direction intersecting the semiconductor layer; the second electrode structure is disposed around the semiconductor layer, and the second electrode structure includes a first portion and a second portion, the first portion being located on the first side, the second portion being located on the second side, the first electrode layer being disposed around the first portion, and the second electrode layer being disposed around the second portion; the dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer being located between the first electrode layer and the first portion, and the second dielectric layer being located between the second electrode layer and the second portion.

[0006] In some embodiments, the second electrode structure overlaps with the semiconductor layer in the first direction and the second direction, and the second electrode structure does not overlap with the semiconductor layer in the third direction; the second direction intersects with the third direction, and the first direction intersects in the plane containing the second direction and the third direction.

[0007] In some embodiments, the first electrode layer and the first portion overlap upwards in the first direction and the third party, and the first electrode layer and the first portion do not overlap in the second direction; the second electrode layer and the second portion overlap upwards in the first direction and the third party, and the second electrode layer and the second portion do not overlap in the second direction.

[0008] In some embodiments, the dielectric layer is disposed around the semiconductor layer, and the dielectric layer is also disposed around the second electrode structure.

[0009] In some embodiments, the semiconductor structure includes an isolation structure that penetrates the semiconductor layer along the first direction; the semiconductor layer in the same layer includes a first sub-layer and a second sub-layer arranged along the second direction, and the isolation structure is located between the first sub-layer and the second sub-layer.

[0010] In some embodiments, the isolation structure includes an isolation pillar and the dielectric layer; the isolation pillar includes a first sub-pillar, a second sub-pillar, and a third sub-pillar arranged sequentially along the third direction.

[0011] In some embodiments, the semiconductor structure further includes a gate layer stacked with the semiconductor layer, the gate layer including a first gate layer and a second gate layer, the first gate layer being located on the first side and the second gate layer being located on the second side; on the plane where the gate layer is located, the second sub-pillar is spaced apart from the first sub-pillar and the third sub-pillar respectively, and the gate layer is disposed around the second sub-pillar.

[0012] In some embodiments, on the plane where the gate layer is located, the area of ​​the second sub-pillar is smaller than the area of ​​the first sub-pillar, and the area of ​​the second sub-pillar is smaller than the area of ​​the third sub-pillar.

[0013] In some embodiments, on the plane where the semiconductor layer is located, the second sub-pillar is connected between the first sub-pillar and the third sub-pillar.

[0014] In some embodiments, the semiconductor structure further includes a plurality of bit lines that penetrate the semiconductor layer along the first direction, the bit lines are connected to the semiconductor layer, and the third sub-pillar is located between two adjacent bit lines.

[0015] In some embodiments, the semiconductor structure includes a plurality of semiconductor layers and a plurality of capacitor structures stacked along the first direction, wherein the second electrode structures of the plurality of capacitor structures together constitute a common electrode layer; the semiconductor structure further includes a conductive structure that penetrates the plurality of semiconductor layers along the first direction, and the conductive structure is in contact with the common electrode layer.

[0016] In some embodiments, a portion of the conductive structure is also located between two adjacent semiconductor layers along the first direction.

[0017] On the other hand, a method for fabricating a semiconductor structure is also provided, comprising: forming a semiconductor layer; forming a capacitor structure, the capacitor structure comprising a first electrode structure, a second electrode structure, and a dielectric layer, wherein the first electrode structure comprises a first electrode layer and a second electrode layer, the first electrode layer is located on a first side of the semiconductor layer along a first direction, the second electrode layer is located on a second side of the semiconductor layer along the first direction, and both the first electrode layer and the second electrode layer are in contact with the semiconductor layer, the first direction intersecting the semiconductor layer; the second electrode structure is disposed around the semiconductor layer, the second electrode structure comprising a first portion and a second portion, the first portion being located on the first side, the second portion being located on the second side, the first electrode layer being disposed around the first portion, and the second electrode layer being disposed around the second portion; the dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer being located between the first electrode layer and the first portion, and the second dielectric layer being located between the second electrode layer and the second portion.

[0018] In some embodiments, forming a semiconductor layer includes: forming a stacked structure, the stacked structure including the semiconductor layer and a first sacrificial layer alternately stacked along a first direction; after forming the semiconductor layer and before forming the capacitor structure, the method further includes: forming an isolation pillar, the isolation pillar penetrating the stacked structure along the first direction, the semiconductor layer in the same layer including a first sub-layer and a second sub-layer arranged along a second direction, the isolation pillar being located between the first sub-layer and the second sub-layer, the second direction being parallel to the semiconductor layer; forming a gate layer, the gate layer being stacked with the semiconductor layer, the gate layer including a first gate layer and a second gate layer, the first gate layer being located on a first side, and the second gate layer being located on a second side; and forming a bit line, the bit line penetrating the stacked structure along the first direction, and the bit line being connected to the semiconductor layer.

[0019] In some embodiments, forming an isolation pillar includes: forming a first structural aperture that penetrates the stacked structure along a first direction; removing the first sacrificial layer through the first structural aperture; forming a dielectric layer including a first dielectric layer, a second dielectric layer, and a third dielectric layer, wherein the first dielectric layer surrounds the semiconductor layer, the second dielectric layer surrounds the first dielectric layer, and the third dielectric layer surrounds the second dielectric layer; removing a portion of the dielectric layer covering the aperture wall of the first structural aperture to expose the semiconductor layer; removing a portion of the semiconductor layer; and filling the first structural aperture with an insulating material to form a portion of the isolation pillar.

[0020] In some embodiments, forming the gate layer includes: forming a second structural aperture that penetrates the stacked structure along the first direction; removing a portion of the dielectric layer covering the sidewall of the second structural aperture; removing a portion of the second dielectric layer through the second structural aperture to form a filling space; filling the filling space with a first conductive material to form the gate layer; and filling the second structural aperture with an insulating material to form a portion of the isolation pillar.

[0021] In some embodiments, forming a bit line includes: forming a third structural hole that penetrates the stacked structure along a first direction; removing a portion of the dielectric layer covering the sidewall of the third structural hole; filling the third structural hole with a second conductive material to form the bit line; and filling the third structural hole with a third conductive material to form a contact, the contact being stacked with the bit line along the first direction.

[0022] In some embodiments, after forming the contact and before forming the capacitor structure, the method further includes: forming a fourth dielectric layer, the fourth dielectric layer being stacked with the stack structure along the first direction, and the fourth dielectric layer being located on the side of the contact away from the bit line.

[0023] In some embodiments, forming the capacitor structure includes: forming a fourth structural aperture that penetrates the stacked structure along a first direction; removing a portion of the first dielectric layer and a portion of the second dielectric layer through the fourth structural aperture; forming an electrode layer that surrounds the semiconductor layer and the third dielectric layer; removing a portion of the electrode layer covering the sidewall of the fourth structural aperture to form a first electrode structure, wherein the electrode layer on the first side constitutes the first electrode layer and the electrode layer on the second side constitutes the second electrode layer; forming a dielectric layer that surrounds the semiconductor layer and the third dielectric layer; forming a second electrode structure that surrounds the dielectric layer and covers the sidewall of the fourth structural aperture; and filling the fourth structural aperture with a fourth conductive material to form a conductive structure.

[0024] In some embodiments, after forming the electrode layer and before removing a portion of the electrode layer covering the sidewall of the fourth structural aperture, the method further includes: forming a second sacrificial layer, the second sacrificial layer being disposed around the electrode layer; removing a portion of the second sacrificial layer covering the sidewall of the fourth structural aperture; and after removing the portion of the electrode layer covering the sidewall of the fourth structural aperture and before forming the dielectric layer, the method further includes: removing the second sacrificial layer.

[0025] In some embodiments, the first structural hole, the second structural hole, the third structural hole, and the fourth structural hole are formed in the same process step.

[0026] In another aspect, a storage system is also provided, comprising: a semiconductor structure as described above and a controller, the controller being coupled to the semiconductor structure to control the semiconductor structure to store data. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0028] Figure 1 A block diagram of an electronic device according to some embodiments;

[0029] Figure 2 A block diagram of a memory according to some embodiments;

[0030] Figure 3 This is a circuit diagram of a semiconductor structure according to some embodiments;

[0031] Figure 4 This is a schematic diagram of a semiconductor structure according to some embodiments;

[0032] Figure 5 This is a partial structural schematic diagram of a semiconductor structure according to some embodiments;

[0033] Figure 6 This is a schematic diagram of another semiconductor structure according to some embodiments;

[0034] Figure 7 for Figure 6 A magnified view of box A in the image;

[0035] Figure 8 This is a schematic diagram of the structure of a semiconductor structure in the plane containing the semiconductor layer according to some embodiments;

[0036] Figure 9 This is a schematic diagram of the structure of a semiconductor structure in the plane containing the gate layer according to some embodiments;

[0037] Figure 10This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0038] Figure 11 This is a schematic diagram of the structure after the stacked structure is formed according to some embodiments;

[0039] Figure 12 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0040] Figures 13 to 73 This is a schematic diagram of the fabrication process of a semiconductor structure according to some embodiments.

[0041] Reference numerals: 1000, Semiconductor structure; X, First direction; Y, Second direction; Z, Third direction; 100, Semiconductor layer; 101, First side; 102, Second side; 110, First sub-layer; 120, Second sub-layer; 200, Capacitor structure; 210, First electrode structure; 211, First electrode layer; 212, Second electrode layer; 220, Second electrode structure; 221, First part; 222, Second part; 223, Common electrode layer; 230, Dielectric layer; 231, First dielectric layer; 232, Second dielectric layer; 240, Conductive structure; 250, Third electrode structure; 260, Fourth electrode structure; 300, Isolation structure; 310, Isolation pillar; 311, First sub-pillar; 312, Second sub-pillar; 313, Third sub-pillar; 4 00, Gate layer; 410, First gate layer; 420, Second gate layer; BL, Bit line; 500, Stacked structure; 510, First sacrificial layer; 501, First structural via; 502, Second structural via; 503, Third structural via; 504, Fourth structural via; 520, Isolation layer; 531, First sacrificial pillar; 532, Second sacrificial pillar; 533, Third sacrificial pillar; 534, Fourth sacrificial pillar; 540, Dielectric layer; 541, First dielectric layer; 542, Second dielectric layer; 5421, Fill space; 543, Third dielectric layer; 544, Fourth dielectric layer; 550, Contact; 560, Electrode layer; 570, Second sacrificial layer; 5041, Gap; 591, First conductive material; 592, Second conductive material; 593, Third conductive material. Detailed Implementation

[0042] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0043] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0044] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0045] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0046] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0047] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0048] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0049] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0050] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0051] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0052] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0053] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0054] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0055] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0056] Figure 1 This is a block diagram of an electronic device according to some embodiments. Some embodiments of this disclosure provide an electronic device 9000. The electronic device 9000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0057] like Figure 1 As shown, the electronic device 9000 may include a storage system 910 and a motherboard 920. The storage system 910 can be integrated into various types of storage devices, such as memory cards. These memory cards include any of the following: PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital memory cards (SD cards), and universal flash storage (UFS). In other words, the storage system 910 can be applied to and packaged into different types of electronic products.

[0058] The motherboard 920 may include a processor of the electronic device 9000, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The motherboard 920 may be configured to send data to or receive data from memory.

[0059] In some embodiments, the storage system 910 may have one or more memories 911 and a controller 912. For example, the controller 912 may be configured to operate in a low duty cycle environment, such as with an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment with an SSD or eMMC, which is used as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. Or, in some examples, the controller 912 is coupled to the memory 911 and the motherboard 920 and is configured to control data in the memory 911 while also being able to communicate with external devices (e.g., a host computer).

[0060] The number of memories 911 in the storage system 910 can be one or more. Figure 1The diagram illustrates three memories 911 as an example. The controller 912 manages the data stored in each memory 911 and communicates with the motherboard 920. The controller 912 can be configured to control the operation of each memory 911, such as read, write, and refresh operations. The controller 912 can also be configured to manage various functions related to the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the controller 912 is also configured to determine the maximum memory capacity usable by the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. The controller 912 can also perform any other suitable functions. The controller 912 can communicate with external devices (e.g., the motherboard 920) according to a specific communication protocol. For example, the controller 912 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0061] Figure 2 This is a block diagram of a memory according to some embodiments. This disclosure provides a memory 911 according to some embodiments. For example... Figure 2 As shown, memory 911 includes a memory cell array 913 and peripheral circuitry 914 for controlling the memory cell array 913. Peripheral circuitry 914 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 913. For example, peripheral circuitry 914 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0062] For example, the peripheral circuit 914 can use complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0063] The memory cell array 913 and the peripheral circuitry 914 can be arranged side-by-side in the same plane, for example, on the same wafer; that is, the memory cell array 913 and the peripheral circuitry 914 can be located in the same semiconductor structure. Alternatively, the memory cell array 913 and the peripheral circuitry 914 can be formed on different wafers and bonded together face-to-face. Figure 2 As shown, when the memory cell array 913 and the peripheral circuitry 914 are formed on different wafers and bonded together face-to-face, the memory 911 may include a first semiconductor structure 901 and a second semiconductor structure 902, as well as a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902. The first semiconductor structure 901 may include the memory cell array 913, and the second semiconductor structure 902 may include the peripheral circuitry 914.

[0064] The memory cell array 913 may be an array of memory cells that use vertical transistors as switching and selection devices. In some embodiments, the memory cell array 913 may be a dynamic random access memory (DRAM) cell array. For ease of description, DRAM cell array may be used to describe an example of the memory cell array 913 in this disclosure. However, it should be understood that the memory cell array 913 is not limited to DRAM cell arrays, and may include any other suitable type of memory cell array 913 that can use vertical transistors as switching and selection devices, such as PCM cell arrays, static random-access memory (SRAM) cell arrays, FRAM cell arrays, resistive memory cell arrays, magnetic memory cell arrays, spin transfer torque (STT) memory cell arrays, etc.

[0065] When the memory cell array 913 is a DRAM cell array, the memory cells therein are DRAM cells. A DRAM cell includes a capacitor and one or more transistors. The capacitor stores data as positive or negative charge, and the one or more transistors (also called transfer transistors) control (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a transistor and a capacitor (1T1C) cell. According to some embodiments, the DRAM cell can be refreshed by peripheral circuitry 914 to retain data.

[0066] As DRAM technology continues to evolve, the storage density of DRAM cells on a plane has gradually approached the limits of process technology. To further improve the storage density of DRAM cells, this disclosure provides a memory with 3D stacked DRAM cells in some embodiments. For example... Figure 3 As shown, the memory cell array 913 in this embodiment includes multiple memory cells arranged in a second direction Y and a third direction Z, and the multiple memory cells can also be stacked along the first direction X.

[0067] In this embodiment, the second direction Y and the third direction Z intersect, and the first direction X intersects the plane containing the second direction Y and the third direction Z. For ease of understanding, this embodiment assumes that the second direction Y and the third direction Z are perpendicular, and the first direction X is perpendicular to the plane containing the second direction Y and the third direction Z.

[0068] Continue to refer to Figure 3 and Figure 4 A memory cell includes a transistor T and a capacitor C. The transistor T can be formed by a channel structure formed by a semiconductor layer and a gate layer adjacent to the channel structure. A gate dielectric layer is also disposed between the semiconductor layer and the corresponding gate layer.

[0069] Transistor T has a source and a drain. The drain of transistor T is connected to the bit line BL, which can be parallel to the first direction X. The source of transistor T is connected to one plate of capacitor C, and the other plate of capacitor C can be connected to a reference voltage, which can be ground or another voltage. The capacitor C can represent logical 1 and 0 by the amount of charge stored in it, or the high or low voltage difference across capacitor C. The gate layer of transistor T is connected to the word line WL. The word line WL can be parallel to the second direction Y. With the above settings, the memory can control the transistor T to be turned on or off by applying a voltage to the word line WL. When transistor T is turned on, the bit line BL performs a read or write operation on capacitor C.

[0070] This disclosure provides a semiconductor structure in some embodiments. This semiconductor structure can be part of the memory 911 in some of the above embodiments; for example, the semiconductor structure can be a first semiconductor structure 901. Alternatively, if the semiconductor structure is used as memory 911, it may further include peripheral circuitry 914, which is not a limitation of this disclosure.

[0071] Please refer to Figure 4 and Figure 5 This disclosure provides a semiconductor structure 1000, which includes a semiconductor layer 100 and a capacitor structure 200.

[0072] Semiconductor layer 100 may include a semiconductor material. The semiconductor material may be, for example, single-crystal silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. Semiconductor layer 100 may be partially or completely doped. Exemplarily, semiconductor layer 100 may include doped regions doped with a p-type dopant. Semiconductor layer 100 may also include undoped regions.

[0073] like Figure 4 and Figure 5 As shown, the capacitor structure 200 includes: a first electrode structure 210, a second electrode structure 220, and a dielectric layer 230.

[0074] The first electrode structure 210 includes a first electrode layer 211 and a second electrode layer 212. The first electrode layer 211 is located on a first side 101 of the semiconductor layer 100 along the first direction X, and the second electrode layer 212 is located on a second side 102 of the semiconductor layer 100 along the first direction X. That is, the first electrode layer 211 and the second electrode layer 212 are located on opposite sides of the semiconductor layer 100 along the first direction X. Furthermore, both the first electrode layer 211 and the second electrode layer 212 are in contact with the semiconductor layer 100.

[0075] The first direction X intersects with the semiconductor layer 100; for example, the first direction X can be perpendicular to the semiconductor layer 100. In some later embodiments, a second direction Y and a third direction Z also appear, intersecting each other, with the first direction X intersecting in the plane containing the second direction Y and the third direction Z. For ease of understanding, some embodiments of this disclosure place the semiconductor structure 1000 in an XYZ coordinate system, with the semiconductor layer 100 parallel to the plane containing the second direction Y and the third direction Z, and the first direction X perpendicular to the semiconductor layer 100 (the first direction X is perpendicular to the plane containing the second direction Y and the third direction Z). The second direction Y can be perpendicular to the third direction Z. This disclosure uses the semiconductor structure 1000 situated in the aforementioned XYZ coordinate system as an example to explain and illustrate the semiconductor structure 1000 provided in some embodiments.

[0076] like Figure 4 and Figure 5 As shown, the second electrode structure 220 is disposed around the semiconductor layer 100. It should be noted that the second electrode structure 220 may be disposed around a portion of the semiconductor layer 100. The second electrode structure 220 does not need to surround the entire semiconductor layer 100. For example, the second electrode structure 220 may surround the portion of the semiconductor layer 100 used for contact connection with the capacitor structure 200. The second electrode structure 220 includes a first portion 221 and a second portion 222, where the first portion 221 is located on a first side 101 of the semiconductor layer 100, and the second portion 222 is located on a second side 102 of the semiconductor layer 100. Exemplarily, the second electrode structure 220 may also include a structure for connecting the first portion 221 and the second portion 222 to provide voltage to both portions 221 and 222.

[0077] A first electrode layer 211 is disposed around the first portion 221, and a second electrode layer 212 is disposed around the second portion 222. (See reference) Figure 4 and Figure 5 In the XZ plane, the first electrode layer 211 can be a ring structure, and the first electrode layer 211 can be disposed around the first portion 221. A portion of the outer surface of the first electrode layer 211 is in contact with the surface of the first side 101 of the semiconductor layer 100. (Reference) Figure 4 and Figure 5 In the XZ plane, the second electrode layer 212 can be a ring structure, and the second electrode layer 212 can be arranged around the second part 222. Part of the outer surface of the second electrode layer 212 is in contact with the surface of the second side 102 of the semiconductor layer 100.

[0078] It should be noted that, in this embodiment, when defining the first part 221 and the second part 222, it can be understood that the first electrode structure 210 surrounded by the first electrode layer 211 is the first part 221, and the first electrode structure 210 surrounded by the second electrode layer 212 is the second part 222.

[0079] In this embodiment, as Figure 4 and Figure 5 As shown, dielectric layer 230 includes a first dielectric layer 231 and a second dielectric layer 232. The first dielectric layer 231 is located between the first electrode layer 211 and the first portion 221, and the second dielectric layer 232 is located between the second electrode layer 212 and the second portion 222. In the XZ plane, as... Figure 4 and Figure 5As shown, the first dielectric layer 231 can be arranged around the first portion 221, and the second dielectric layer 232 can be arranged around the second portion 222. The first portion 221, the first dielectric layer 231, the first electrode layer 211, the second portion 222, the second dielectric layer 232, and the second electrode layer 212 together constitute a capacitor structure 200 connected to the semiconductor layer 100.

[0080] Exemplarily, the semiconductor layer may include a semiconductor material, such as single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The semiconductor layer may have source and drain electrodes, the materials of which may include semiconductor materials doped with P-type or N-type dopants. P-type dopants include boron or gallium. N-type dopants include phosphorus or arsenic.

[0081] For example, the material of the first electrode structure 210 can be a single-layer structure formed by one of the following materials: W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, and WSi, or a stacked structure formed by two or more of the above materials. In this embodiment, the constituent material of the first electrode structure 210 may include titanium nitride. Titanium nitride material has a high melting point, high hardness, high-temperature chemical stability, and excellent electrical conductivity. Using titanium nitride material to prepare the first electrode layer 211 and the second electrode layer 212 is beneficial to improving the conductivity of the first electrode layer 211 and the second electrode layer 212, and also beneficial to improving the stability of the capacitor structure 200.

[0082] For example, the material of the dielectric layer 230 may include a high-k (K greater than 2.8) dielectric material to increase the capacitance value per unit area of ​​the capacitor. In specific embodiments, the dielectric layer 230 may be a single-layer structure formed by one of the following materials: HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO, or a stacked structure formed by two or more of the above materials.

[0083] For example, the material of the second electrode structure 220 can be a single-layer structure formed by one of the following materials: W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, and WSi, or a stacked structure formed by two or more of the above materials.

[0084] With the above configuration, the semiconductor layer 100 has partial capacitor structures 200 on both sides along the first direction X. Furthermore, the first electrode layer 211 can be arranged around the first portion 221, and the second electrode layer 212 can be arranged around the second portion 222. Therefore, all of the first electrode layer 211 and all of the second electrode layer 212 can store charge. Thus, the capacitor structure 200 in this embodiment fully utilizes the first electrode structure 210 to store charge. The absence of wasted portions in the first electrode structure 210 increases the facing area between the first electrode structure 210 and the second electrode structure 220, which is beneficial for the capacitor structure 200 to store more charge, thereby increasing the capacitance value. In addition, when the capacitor structure 200 in this embodiment and some other embodiments maintain the same capacitance value, the capacitor structure 200 in this embodiment fully utilizes the first electrode structure 210 to store charge. Therefore, the capacitor structure 200 in this embodiment can reduce its size in the second direction Y and the third direction Z, which is beneficial for reducing the size of the semiconductor structure 1000 and increasing the storage density of the semiconductor structure 1000.

[0085] In some embodiments, such as Figure 4 and Figure 5 As shown, the second electrode structure 220 and the semiconductor layer 100 do not overlap in the third direction Z. Figure 6 and Figure 7 As shown, the second electrode structure 220 overlaps with the semiconductor layer 100 in the first direction X and the second direction Y.

[0086] The second electrode structure 220 overlaps with the semiconductor layer 100 in the first direction X and the second direction Y. It can be understood that the orthographic projection of the second electrode structure 220 in the first direction X and the orthographic projection of the semiconductor layer 100 in the first direction X have overlapping parts, and the orthographic projection of the second electrode structure 220 in the second direction Y and the orthographic projection of the semiconductor layer 100 in the second direction Y have overlapping parts.

[0087] The second electrode structure 220 and the semiconductor layer 100 do not overlap in the third direction Z. This can be understood as the second electrode structure 220's orthogonal projection in the third direction Z and the semiconductor layer 100's orthogonal projection in the third direction Z having no overlapping parts.

[0088] In this embodiment, as Figure 4 , Figure 5 , Figure 6 and Figure 7As shown, the semiconductor layer 100 may include two surfaces disposed opposite each other along a first direction X, two surfaces disposed opposite each other along a second direction Y, and two surfaces disposed opposite each other along a third direction Z. Exemplarily, the second electrode structure 220 may surround the two surfaces of the semiconductor layer 100 disposed opposite each other along the first direction X and the two surfaces disposed opposite each other along the second direction Y. In this case, the second electrode structure 220 overlaps with the semiconductor layer 100 in the first direction X and the second direction Y, but does not overlap with the semiconductor layer 100 in the third direction Z.

[0089] In this embodiment, the second electrode structure 220 may include a first portion 221 and a second portion 222, with the first portion 221 located on the first side 101 and the second portion 222 located on the second side 102. With this arrangement, the second electrode structure 220 can be disposed around the semiconductor layer 100 in the XY plane, with the first portion 221 and the second portion 222 connected to facilitate the application of voltage to both the first portion 221 and the second portion 222 together.

[0090] Furthermore, the second electrode structure 220, which is not surrounded by the first electrode structure 210, such as the second electrode structure 220 located on both sides of the semiconductor layer 100 along the second direction Y, can be connected to the peripheral circuit, thereby transmitting electrical signals with the peripheral circuit.

[0091] For example, when the semiconductor structure 1000 includes multiple capacitor structures 200, the second electrode structure 220 surrounds the semiconductor layer 100 through the above-mentioned arrangement. Then, the multiple second electrode structures 220 can be led out to the peripheral circuit from the same side in the second direction Y, which helps to simplify the connection path between the second electrode structure 220 and the peripheral circuit, thereby simplifying the semiconductor structure 1000.

[0092] In addition, in this embodiment, a dielectric layer 230 may be disposed between the second electrode structure 220 and the semiconductor layer 100, that is, the dielectric layer 230 is also located between the second electrode structure 220 and the semiconductor layer 100 to isolate the second electrode structure 220 and the semiconductor layer 100.

[0093] In some embodiments, such as Figure 4 and Figure 5 As shown, the first electrode layer 211 and the first portion 221 overlap in the first direction X and the third direction Z, as... Figure 6 and Figure 7 As shown, the first electrode layer 211 and the first portion 221 do not overlap in the second direction Y.

[0094] The first electrode layer 211 and the first part 221 overlap in the first direction X and the third direction Z. It can be understood that the orthographic projection of the first electrode layer 211 in the first direction X and the orthographic projection of the first part 221 in the first direction X have overlapping parts, and the orthographic projection of the first electrode layer 211 in the third direction Z and the orthographic projection of the first part 221 in the third direction Z have overlapping parts.

[0095] The first electrode layer 211 and the first part 221 do not overlap in the second direction Y. This can be understood as the first electrode layer 211 having no overlapping portion with the first part 221 having no overlapping portion with the first part 221 having no overlapping portion in the second direction Y.

[0096] And, as Figure 4 and Figure 5 As shown, the second electrode layer 212 and the second portion 222 overlap in the first direction X and the third direction Z, as... Figure 6 and Figure 7 As shown, the second electrode layer 212 and the second portion 222 do not overlap in the second direction Y.

[0097] The second electrode layer 212 and the second part 222 overlap in the first direction X and the third direction Z. It can be understood that the orthographic projection of the second electrode layer 212 in the first direction X and the orthographic projection of the second part 222 in the first direction X have overlapping parts, and the orthographic projection of the second electrode layer 212 in the third direction Z and the orthographic projection of the second part 222 in the third direction Z have overlapping parts.

[0098] The second electrode layer 212 and the second part 222 do not overlap in the second direction Y. This can be understood as the second electrode layer 212 having no overlapping portion with the second part 222 having no overlapping portion in the second direction Y.

[0099] In this embodiment, as Figure 4 , Figure 5 , Figure 6 and Figure 7As shown, the first electrode layer 211 surrounds the first portion 221 in the same direction as the second electrode layer 212 surrounds the second portion 222, but the direction of the first electrode layer 211 surrounding the first portion 221 is different from the direction of the second electrode structure 220 surrounding the semiconductor layer 100. The first electrode layer 211 is arranged around the first portion 221 in the XZ plane, the second electrode layer 212 is arranged around the second portion 222 in the XZ plane, and the second electrode structure 220 is arranged around the semiconductor layer 100 in the XY plane. Furthermore, the first electrode layer 211 and the second electrode layer 212 are in contact with the two surfaces of the semiconductor layer 100 along the first direction X, respectively. This arrangement facilitates the arrangement of the second electrode structure 220 around the semiconductor layer 100. Simultaneously, the first electrode layer 211 is arranged around the first portion 221, and the second electrode layer 212 is arranged around the second portion 222.

[0100] Through the above configuration, the capacitor structure 200 in this embodiment fully utilizes the first electrode structure 210, increasing the facing area between the first electrode structure 210 and the second electrode structure 220. This facilitates the capacitor structure 200 in storing more charge, thereby increasing the capacitance value. Furthermore, when the capacitor structure 200 in this embodiment maintains the same capacitance value as those in other embodiments, and the capacitor structure 200 in this embodiment fully utilizes the first electrode structure 210, the size of the capacitor structure 200 in the second direction Y and the third direction Z can be reduced. This, in turn, helps to reduce the size of the semiconductor structure 1000 and increase its storage density.

[0101] In some embodiments, such as Figure 4 , Figure 5 , Figure 6 and Figure 7 As shown, in the XY plane, the dielectric layer 230 is disposed around the semiconductor layer 100. In both the XY and YZ planes, the dielectric layer 230 is also disposed around the second electrode structure 220.

[0102] With the above configuration, the dielectric layer 230 can isolate the semiconductor layer 100 and the second electrode structure 220, prevent the semiconductor layer 100 from being electrically connected to the second electrode structure 220, enable the semiconductor structure 1000 to work normally, and improve the storage stability of the semiconductor structure 1000.

[0103] In some embodiments, such as Figure 8As shown, the semiconductor layer 100 in the same layer may include multiple sublayers. For example, the semiconductor layer 100 in the same layer may include a first sublayer 110, a second sublayer 120, ... an Nth sublayer, etc., arranged along the second direction Y. This disclosure does not limit the number of sublayers included in the semiconductor layer 100 in the same layer.

[0104] The semiconductor structure 1000 also includes an isolation structure 300 that extends through the semiconductor layer 100 along a first direction X, and is also located between adjacent sub-layers along a second direction Y. The isolation structure 300 is used to isolate adjacent sub-layers along the second direction Y.

[0105] Taking a semiconductor layer 100 comprising a first sub-layer 110 and a second sub-layer 120 arranged along the second direction Y as an example, an isolation structure 300 is located between the first sub-layer 110 and the second sub-layer 120. The isolation structure 300 is used to isolate the first sub-layer 110 and the second sub-layer 120 arranged along the second direction Y. Here, it can also be understood that the isolation structure 300 divides the semiconductor layer 100 into the first sub-layer 110 and the second sub-layer 120.

[0106] In this embodiment, the first sub-layer 110 and the second sub-layer 120 can be disposed on the same layer. Disposal on the same layer means that multiple patterns are on the same pattern layer. A pattern layer refers to a film layer formed through a single patterning process. A patterning process refers to a process capable of forming at least one pattern with a certain shape. For example, a thin film is formed on a substrate using any of various film deposition processes such as deposition, coating, or sputtering, and then the thin film is patterned to form a film layer containing at least one pattern, which is called a pattern layer. The patterning steps include: coating photoresist, exposure, development, etching, and photoresist stripping. In this embodiment, the positional relationship of multiple patterns belonging to the same pattern layer is referred to as disposal on the same layer.

[0107] In this embodiment, multiple semiconductor sublayers can be arranged along the second direction Y to form multiple transistor structures. Through this arrangement, the semiconductor structure 1000 forms multiple memory (1T1C) cells in the second direction Y, which helps increase the memory capacity of the semiconductor structure 1000. Furthermore, the isolation structure 300 helps isolate the first sublayer 110 and the second sublayer 120, ensuring the normal operation of the semiconductor structure 1000 and thus improving the memory stability of the semiconductor structure 1000.

[0108] In other embodiments, such as Figure 8As shown, the isolation structure 300 may include isolation pillars 310 and a dielectric layer 230. The isolation pillars 310 may include a first sub-pillar 311, a second sub-pillar 312, and a third sub-pillar 313 arranged sequentially along a third direction Z. Exemplarily, the first sub-pillar 311 may penetrate a portion of the capacitor structure 200 along a first direction X, thereby allowing the first sub-pillar 311 to contact the dielectric layer 230. The dielectric layer 230, the first sub-pillar 311, the second sub-pillar 312, and the third sub-pillar 313 together serve to isolate the first sub-layer 110 and the second sub-layer 120.

[0109] The material of the insulating post 310 may include an insulating material. The insulating material may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable insulating materials.

[0110] It should be noted that the first sub-column 311, the second sub-column 312, and the third sub-column 313 can all be irregular columnar structures. For example, the maximum dimension of the first sub-column 311 in the third direction Z can be greater than its maximum dimension in the second direction Y; the maximum dimension of the second sub-column 312 in the third direction Z can be greater than its maximum dimension in the second direction Y; and the maximum dimension of the third sub-column 313 in the third direction Z can be greater than its maximum dimension in the second direction Y. For example, in the YZ plane, the first sub-column 311, the second sub-column 312, and the third sub-column 313 can all include curved edges. With the above configuration, the isolation column 310 can extend along the third direction Z to isolate the first sub-layer 110 and the second sub-layer 120 arranged along the second direction Y.

[0111] Furthermore, the maximum width of the second sub-pillar 312 in the second direction Y is less than the maximum width of the first sub-pillar 311 in the second direction Y, and the maximum width of the second sub-pillar 312 in the second direction Y is less than the maximum width of the third sub-pillar 313 in the second direction Y, so that the semiconductor layer 100 obtains a larger area.

[0112] In this embodiment, the dielectric layer 230 and the isolation pillar 310 in the capacitor structure 200 are used to jointly isolate the first sub-layer 110 and the second sub-layer 120, making full use of the existing structure in the semiconductor structure 1000, which helps to save the materials required to prepare the isolation structure 300 and save the preparation cost of the semiconductor structure 1000.

[0113] Furthermore, while isolating the first sublayer 110 and the second sublayer 120, the isolation structure 300 also isolates the capacitor structure 200 corresponding to the first sublayer 110 and the capacitor structure 200 corresponding to the second sublayer 120. This can be understood as the isolation structure 300 dividing the capacitor structure 200 into two parts: one part connected to the first sublayer 110 and the other part connected to the second sublayer 120, thus forming two memory cells (1T1C). This configuration helps to increase the storage capacity of the semiconductor structure 1000, ensures its normal operation, and improves its storage stability.

[0114] In some embodiments, such as Figure 4 , Figure 5 and Figure 9 As shown, the semiconductor structure 1000 also includes a gate layer 400 stacked with the semiconductor layer 100. The gate layer 400 may include a first gate layer 410 and a second gate layer 420. The first gate layer 410 is located on the first side 101 of the semiconductor layer 100, and the second gate layer 420 is located on the second side 102 of the semiconductor layer 100.

[0115] The constituent materials of the gate layer 400 may include conductive materials, including but not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicides, or other suitable conductive materials. In some examples, the gate layer 400 includes a metal layer, such as a tungsten layer. In some examples, the gate layer 400 includes a doped polysilicon layer. Polysilicon can be doped to a desired doping concentration using suitable dopant to become a conductive material that can be used as the material for the gate layer 400.

[0116] On the plane containing the gate layer 400 (either the first gate layer 410 or the second gate layer 420), the second sub-pillar 312 is disposed at intervals from the first sub-pillar 311 and the third sub-pillar 313, respectively, and the gate layer 400 is disposed around the second sub-pillar 312. For example, the gate layer 400 may be disposed around the second sub-pillar 312, in which case the gate layer 400 may be located between the first sub-pillar 311 and the second sub-pillar 312, or between the second sub-pillar 312 and the third sub-pillar 313.

[0117] With the above configuration, the isolation pillar 310 does not restrict the first gate layer 410 from extending along the second direction Y. The first gate layer 410 can extend along the second direction Y to form a word line WL (see reference). Figure 3 and Figure 4Similarly, the second gate layer 420 can also extend along the second direction Y. The transistor T can be composed of a semiconductor layer 100 and a gate layer 400 adjacent to the semiconductor layer 100. The semiconductor structure 1000 can apply a voltage to the semiconductor layer 100 through the gate layer 400, thereby controlling the transistor T to be turned on or off.

[0118] It should be noted that in this embodiment, when the semiconductor layer 100 of the same layer has multiple semiconductor sub-layers arranged along the second direction Y, the gate layer 400 can extend along the second direction Y, and then one gate layer 400 can apply a voltage to the semiconductor sub-layers located in the same row along the second direction Y.

[0119] In some embodiments, the gate layer 400 may only include the first gate layer 410, without the second gate layer 420, in which case the gate layer 400 and its adjacent semiconductor layer 100 can form a single-gate transistor. In this embodiment, the gate layer 400 includes both the first gate layer 410 and the second gate layer 420, thus forming a dual-gate transistor. Compared to a single-gate transistor, when the voltage of the first gate layer 410 is reduced, the voltage of the second gate layer 420 can be transferred to the semiconductor layer 100 through the common-gate effect, thereby reducing the impact of stress effects and improving the transistor's operational reliability and stability. Furthermore, due to the presence of the second gate layer 420, when the electrical signal changes, the dual-gate transistor can respond and change its conduction state more quickly, improving the transistor's switching speed. Additionally, the second gate layer 420 can also be used to adjust the voltage of the first gate layer 410, expanding the operating voltage range of the dual-gate transistor and thus adapting to more application scenarios.

[0120] In some embodiments, such as Figure 9 As shown, the shapes of the first sub-pillar 311, the second sub-pillar 312, and the third sub-pillar 313 on the same cross-section (YZ plane) can be different. For example, on the plane where the gate layer 400 is located, the area of ​​the second sub-pillar 312 can be smaller than the area of ​​the first sub-pillar 311, and the area of ​​the second sub-pillar 312 can also be smaller than the area of ​​the third sub-pillar 313. The areas of the first sub-pillar 311 and the third sub-pillar 313 can be the same or different.

[0121] With the above configuration, on the plane where the gate layer 400 is located, among the first sub-pillar 311, the second sub-pillar 312, and the third sub-pillar 313, the area of ​​the second sub-pillar 312 is the smallest. This is beneficial for the gate layer 400 to pass through the gap between the first sub-pillar 311 and the second sub-pillar 312, and also beneficial for the gate layer 400 to pass through the gap between the second sub-pillar 312 and the third sub-pillar 313. This facilitates the extension of the gate layer 400 along the second direction Y, so that the semiconductor structure 1000 can apply a voltage to the semiconductor layer 100 through the gate layer 400.

[0122] In some embodiments, such as Figure 8 As shown, on the plane where the semiconductor layer 100 is located, the second sub-pillar 312 is connected between the first sub-pillar 311 and the third sub-pillar 313. That is, on the plane where the semiconductor layer 100 is located, the second sub-pillar 312 is in contact with the first sub-pillar 311, and the second sub-pillar 312 is in contact with the third sub-pillar 313.

[0123] With the above configuration, the dielectric layer 230, the first sub-pillar 311, the second sub-pillar 312, and the third sub-pillar 313 can jointly isolate the first sub-layer 110 and the second sub-layer 120 arranged along the second direction Y, so that the semiconductor structure 1000 can selectively control the first sub-layer 110 and the second sub-layer 120, avoid mutual interference between the first sub-layer 110 and the second sub-layer 120, and improve the working stability of the semiconductor structure 1000.

[0124] In some embodiments, such as Figure 5 , Figure 8 and Figure 9 As shown, the semiconductor structure 1000 also includes multiple bit lines BL, which penetrate the semiconductor layer 100 along a first direction X and are connected to the semiconductor layer 100. For example, the bit line BL can be connected to the drain of the semiconductor layer 100. Multiple bit lines BL can be arranged along a second direction Y. When the semiconductor layer 100 in the same layer includes multiple semiconductor sublayers, one bit line BL can connect to one semiconductor sublayer. The third sub-pillar 313 in the isolation pillar 310 is also located between two adjacent bit lines BL along the second direction Y. Figure 8 As shown, on the plane where semiconductor layer 100 is located, the third sub-pillar 313 can contact both bit lines BL adjacent to each other along the second direction Y. Figure 9 As shown, on the plane where the gate layer 400 is located, the third sub-pillar 313 can be spaced apart from the two adjacent bit lines BL.

[0125] With the above configuration, when the transistor is turned on, the bit line BL can perform read or write operations on the capacitor structure 200. Furthermore, the third sub-pillar 313 can isolate two adjacent bit lines BL along the second direction Y, preventing mutual interference and improving the operational stability of the semiconductor structure 1000.

[0126] In some embodiments, such as Figure 8As shown, semiconductor layer 100 can be arranged in a centrally symmetrical manner with bit line BL as the symmetry point. Here, "central symmetry" means that the multiple semiconductor layers 100 can include absolute central symmetry and approximate central symmetry. Approximate central symmetry can be understood as the overall structure of the multiple semiconductor layers 100 exhibiting a symmetrical trend, while local variations may exist within the multiple semiconductor layers 100. Similarly, as... Figure 9 As shown, the multiple gate layers 400 can be arranged in a centrally symmetrical manner with the bit line BL as the symmetry point. The multiple capacitor structures 200 can also be arranged in a centrally symmetrical manner with the bit line BL as the symmetry point, which will not be described in detail in this disclosure.

[0127] In some embodiments, reference Figure 6 and Figure 7 The semiconductor structure 1000 includes a plurality of semiconductor layers 100 and a plurality of capacitor structures 200 stacked along a first direction X. The second electrode structures 220 of the plurality of capacitor structures 200 together constitute a common electrode layer 223. For example, adjacent second electrode structures 220 can be connected to form the common electrode layer 223. Here, it can be understood that the second electrode structures 220 of the plurality of capacitor structures 200 can be integrally disposed.

[0128] The semiconductor structure 1000 also includes a conductive structure 240, which penetrates the plurality of semiconductor layers 100 along a first direction X. The conductive structure 240 is in contact with a common electrode layer 223, so the semiconductor structure 1000 can apply a voltage to the common electrode layer 223 through the conductive structure 240. On the YZ plane, the common electrode layer 223 can be disposed around the conductive structure 240.

[0129] The conductive structure 240 is used to apply a voltage to the common electrode layer 223, and the constituent materials of the conductive structure 240 may include conductive materials. Conductive materials include, but are not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides, or other suitable conductive materials.

[0130] With the above configuration, the semiconductor structure 1000 can apply voltage to the second electrode structure 220 of the multiple capacitor structures 200 through the conductive structure 240, which helps to simplify the power supply circuit of the semiconductor structure 1000.

[0131] In this embodiment, multiple semiconductor layers 100 can be stacked along the first direction X, and correspondingly, multiple capacitor structures 200 can be stacked along the first direction X. Each semiconductor layer 100 can correspond one-to-one with a capacitor structure 200. Each semiconductor layer 100 may further include multiple semiconductor sublayers arranged along the second direction Y. Correspondingly, each capacitor structure 200 can be separated into multiple capacitors C by an isolation structure 300. The multiple semiconductor sublayers and their adjacent gate layers 400 can form multiple transistors T. A transistor T and a capacitor C can constitute a memory cell, and multiple memory cells can be arranged along the first direction X and the second direction Y.

[0132] And, as Figure 6 , Figure 7 , Figure 8 and Figure 9 As shown, multiple memory cells can be arranged along a third direction Z. For example, in this embodiment, multiple memory cells can be spaced apart along a third direction Z. Alternatively, multiple memory cells in this embodiment can be arranged symmetrically along the XY plane. Through the above arrangements, multiple memory cells in this embodiment can be arranged along the first direction X, the second direction Y, and the third direction Z to form a 3D stacked memory cell array, which is beneficial to improving the storage capacity of the semiconductor structure 1000.

[0133] In this embodiment, a bit line BL can be located between two adjacent memory cells along the third direction Z, and a bit line BL can be connected to the semiconductor layers 100 of both adjacent memory cells along the third direction Z. With this configuration, a bit line BL can transmit electrical signals to memory cells located in the same column along the first direction X, and the bit line BL can also transmit electrical signals to memory cells adjacent along the third direction Z (memory cells connected to the bit line BL). This reduces the number of bit lines BL, increases the storage density of the semiconductor structure 1000, and reduces the fabrication cost of the semiconductor structure 1000.

[0134] In some embodiments, as shown in the figure, a portion of the conductive structure 240 is also located between two adjacent semiconductor layers 100 along the first direction X. Since the second electrode structure 220 is disposed around the semiconductor layer 100, the portion of the conductive structure 240 extends between two adjacent semiconductor layers 100 along the first direction X, which facilitates sufficient contact between the conductive structure 240 and the second electrode structure 220, thereby improving the electrical signal transmission speed and transmission stability between the conductive structure 240 and the second electrode structure 220.

[0135] In this embodiment, the second electrode structure 220 is connected to the conductive structure 240, and the first electrode structure 210 is connected to the semiconductor layer 100. As mentioned above, the gate layer 400 of transistor T is connected to the word line, the drain of the semiconductor layer 100 of transistor T is connected to the bit line BL, and the source of the semiconductor layer 100 of transistor T is connected to the capacitor structure 200. The voltage signal on the word line can control the transistor T to turn on or off, thereby reading the data information stored in the capacitor structure 200 through the bit line BL, or writing the data information into the capacitor structure 200 for storage through the bit line BL.

[0136] This disclosure also provides a method for fabricating a semiconductor structure 1000 in some embodiments, which is described below in conjunction with... Figures 10 to 73 The method for preparing the semiconductor structure 1000 in some of the above embodiments will be explained.

[0137] like Figure 10 As shown, the method for fabricating the semiconductor structure 1000 includes: S1 to S2.

[0138] S1, Forming a semiconductor layer.

[0139] like Figure 11 As shown, in this step, a thin film deposition process can be used to form a semiconductor layer 100 and a first sacrificial layer 510 alternately stacked along the first direction X to form a stacked structure 500. The thin film deposition process includes any one of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD).

[0140] For example, the semiconductor layer 100 can be formed using a semiconductor material. Semiconductor materials include, for example, monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0141] In this step, a portion of the semiconductor layer 100 may be doped to form the source and drain. The materials for the source and drain may include semiconductor materials doped with P-type or N-type dopants. P-type dopants include boron or gallium. N-type dopants include phosphorus or arsenic.

[0142] For example, germanium-silicon can be used to form the first sacrificial layer 510, or other materials with different etching rates than the semiconductor layer 100 can be used to selectively remove the first sacrificial layer 510 in subsequent steps. The thickness of the first sacrificial layer 510 in the first direction X can be greater than the thickness of the semiconductor layer 100 in the first direction X.

[0143] like Figure 12 As shown, after forming the semiconductor layer 100 and before forming the capacitor structure 200, the method further includes steps S11 to S13.

[0144] S11. An isolation pillar is formed, which penetrates the stacked structure along a first direction. The semiconductor layer in the same layer includes a first sub-layer and a second sub-layer arranged along a second direction. The isolation pillar is located between the first sub-layer and the second sub-layer, and the second direction is parallel to the semiconductor layer.

[0145] In this step, such as Figure 13 As shown, the first structural hole 501, the second structural hole 502, the third structural hole 503, and the fourth structural hole 504 can be formed in the same process step. The first structural hole 501, the second structural hole 502, the third structural hole 503, and the fourth structural hole 504 all penetrate the stacked structure 500 along a first direction X. The first structural hole 501, the second structural hole 502, the third structural hole 503, and the fourth structural hole 504 can be formed by any suitable manufacturing process. For example, a patterned photoresist layer can be formed over the stacked structure 500. Here, the patterned photoresist layer can be formed, for example, sequentially using a coating process, an exposure process, and a development process. The patterned photoresist layer can expose the portions of the stacked structure 500 used to form the first structural hole 501, the second structural hole 502, the third structural hole 503, and the fourth structural hole 504. An appropriate etching process can be performed to remove portions of the stacked structure 500 used to form the first structural hole 501, the second structural hole 502, the third structural hole 503, and the fourth structural hole 504. For example, the etching process may include a dry etching process.

[0146] In this step, by forming the first structural hole 501, the second structural hole 502, the third structural hole 503 and the fourth structural hole 504 in the same process step, the drilling process step is combined, which helps to reduce the number of process steps and reduce the cost of preparing the semiconductor structure 1000.

[0147] like Figure 13 and Figure 14As shown, after forming the first structural via 501, the second structural via 502, the third structural via 503, and the fourth structural via 504, an isolation layer 520 can be formed within the first structural via 501, the second structural via 502, the third structural via 503, and the fourth structural via 504 using an ALD deposition process. The isolation layer 520 covers the sidewalls of the first structural via 501, the second structural via 502, the third structural via 503, and the fourth structural via 504. The material of the isolation layer 520 can be, for example, silicon oxide. Then, a sacrificial material, such as carbon, can be deposited within the first structural via 501, the second structural via 502, the third structural via 503, and the fourth structural via 504 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, thereby forming a first sacrificial pillar 531, a second sacrificial pillar 532, a third sacrificial pillar 533, and a fourth sacrificial pillar 534, respectively, within the first structural via 501, the second structural via 502, the third structural via 503, and the fourth structural via 504.

[0148] refer to Figure 13 , Figure 14 and Figure 15 After the first sacrificial pillar 531, the second sacrificial pillar 532, the third sacrificial pillar 533 and the fourth sacrificial pillar 534 are formed, an isolation layer 520 can be formed on the stacked structure 500 by a deposition process to allow for selective removal of the sacrificial pillars in subsequent steps, such as removing the first sacrificial pillar 531 alone.

[0149] refer to Figure 15 , Figure 16 and Figure 17 After forming an isolation layer 520 on the stacked structure 500, the isolation layer 520 covering the first sacrificial pillar 531 can be removed by a dry etching process after forming a patterned photoresist layer on the stacked structure 500, thereby exposing the first sacrificial pillar 531. The first sacrificial pillar 531 and the isolation layer 520 located within the first structural aperture 501 can be removed to open the first structural aperture 501. Exemplarily, when the material of the first sacrificial pillar 531 includes carbon, the process of removing all the first sacrificial pillars 531 within the first structural aperture 501 can include ashing. Exemplarily, a dry etching process can also be used to remove the first sacrificial pillar 531. In some other examples, other processes that can remove sacrificial materials, such as wet etching, can also be used to remove the first sacrificial pillar 531, without specific limitation. In this step, a wet etching process can be used to remove the isolation layer 520 located within the first structural aperture 501.

[0150] refer to Figure 17 and Figure 18 After opening the first structural hole 501, for example, a wet etching process can be used to inject etching solution into the first structural hole 501 to remove the first sacrificial layer 510.

[0151] refer to Figure 18 , Figure 19 , Figure 20 , Figure 21 and Figure 22 After removing the first sacrificial layer 510, a first dielectric layer 541, a second dielectric layer 542, and a third dielectric layer 543 can be sequentially formed at the location of the original first sacrificial layer 510 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a dielectric layer 540. The first dielectric layer 541, the second dielectric layer 542, and the third dielectric layer 543 can be arranged sequentially in a direction away from the semiconductor layer 100. Specifically, the first dielectric layer 541 is disposed around the semiconductor layer 100, the second dielectric layer 542 is disposed around the first dielectric layer 541, and the third dielectric layer 543 is disposed around the second dielectric layer 542.

[0152] For example, the materials of the first dielectric layer 541, the second dielectric layer 542, and the third dielectric layer 543 may all include insulating materials. The insulating material may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or may be other suitable insulating materials.

[0153] It should be noted that in some subsequent steps, a portion of the second dielectric layer 542 needs to be replaced with the gate layer 400. Therefore, the material of the second dielectric layer 542 needs to be different from the material of the first dielectric layer 541, and also different from the material of the third dielectric layer 543. Thus, in some subsequent steps, a portion of the second dielectric layer 542 can be selectively removed. For example, the material of the first dielectric layer 541 may include silicon oxide, the material of the second dielectric layer 542 may include silicon nitride, and the material of the third dielectric layer 543 may include silicon oxide.

[0154] refer to Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 and Figure 27 After the dielectric layer 540 is formed, a wet etching process can be used to remove a portion of the dielectric layer 540 covering the hole wall of the first structural hole 501, for example, by sequentially removing the third dielectric layer 543, the second dielectric layer 542 and the first dielectric layer 541, thereby exposing the semiconductor layer 100 in the first structural hole 501.

[0155] It should be noted that the reference Figure 24 , Figure 25 , Figure 26 and Figure 27In the above steps, if the material of the third dielectric layer 543 is the same as that of the first dielectric layer 541, then when a portion of the first dielectric layer 541 is removed using a wet etching process, a portion of the third dielectric layer 543 will also be removed. Therefore, on the YZ plane, a portion of the second dielectric layer 542 will protrude from the first dielectric layer 541 and the third dielectric layer 543. To improve the morphological regularity of the semiconductor structure 1000, refer to... Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 and Figure 29 After removing a portion of the first dielectric layer 541 and before removing a portion of the semiconductor layer 100 through the first structural hole 501, the second dielectric layer 542 protruding from the first dielectric layer 541 and the third dielectric layer 543 can be removed through the first structural hole 501 to maintain the regularity of the semiconductor structure 1000 morphology. By removing the portion of the second dielectric layer 542 protruding from the first dielectric layer 541 and the third dielectric layer 543 through the above steps, it is beneficial to maintain the sidewalls of the first structural hole 501 to be approximately flush, prevent uneven sidewalls, and improve the situation where material in recessed areas is difficult to remove.

[0156] refer to Figure 29 and Figure 30 Through the first structural aperture 501, a portion of the semiconductor layer 100 can be removed using a wet etching process. By removing a portion of the semiconductor layer 100, the same semiconductor layer 100 is divided into multiple semiconductor sub-layers. For example, a portion of the semiconductor layer 100 is removed to expose a portion of the isolation layer 520 located within the second structural aperture 502 and the isolation layer 520 located within the third structural aperture 503. Through the above steps, the semiconductor layer 100 can be divided into multiple spaced-apart semiconductor sub-layers, such as a first sub-layer 110 and a second sub-layer 120 arranged along the second direction Y. The first structural aperture 501, the second structural aperture 502, and the third structural aperture 503 are located between the first sub-layer 110 and the second sub-layer 120.

[0157] refer to Figure 29 , Figure 30 and Figure 31 After removing part of the semiconductor layer 100, an insulating material can be filled into the first structural hole 501 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a partial isolation pillar 310.

[0158] S12. A gate layer is formed, which is stacked with a semiconductor layer. The gate layer includes a first gate layer and a second gate layer, with the first gate layer located on a first side and the second gate layer located on a second side.

[0159] like Figure 32 , Figure 33and Figure 34 As shown, in this step, the second structural hole 502 can be opened by removing the second sacrificial column 532 and the isolation layer 520 located in the second structural hole 502.

[0160] For example, when the material of the second sacrificial pillar 532 includes carbon, the process of removing all the second sacrificial pillars 532 located within the second structural hole 502 may include ashing. After removing the second sacrificial pillars 532, a wet etching process may be used to remove the isolation layer 520 located within the second structural hole 502.

[0161] refer to Figure 34 , Figure 35 and Figure 36 After opening the second structural hole 502, remove part of the dielectric layer 540 covering the sidewall of the second structural hole 502 to expose the second dielectric layer 542.

[0162] refer to Figure 36 and Figure 37 A portion of the second dielectric layer 542 is removed through the second structural hole 502 to form a filling space 5421. For example, a wet etching process can be used to remove the second dielectric layer 542. In this step, since the material of the second dielectric layer 542 is different from that of the first dielectric layer 541, and the material of the second dielectric layer 542 is different from that of the third dielectric layer 543, the etching amount of the first dielectric layer 541 and the third dielectric layer 543 is small or negligible when the second dielectric layer 542 is processed by the wet etching process. This is beneficial to protecting the structural morphology of the first dielectric layer 541 and the third dielectric layer 543 from being damaged.

[0163] Furthermore, in this step, there can be multiple second structural holes 502. After the etching solution is introduced into some of the second structural holes 502, the removal of the second dielectric layer 542 by the etching solution allows the multiple second structural holes 502 to communicate with each other. Therefore, the etching solution can quickly flow out from other second structural holes 502, which helps to reduce the amount of material or other impurities (such as substances obtained from the reaction between the etching solution and the second dielectric layer 542) remaining in the filling space 5421. Through the above process steps, the integrity of the gate layer 400 morphology is improved, thereby optimizing the electrical performance of the gate layer 400.

[0164] refer to Figure 37 , Figure 38 , Figure 39 , Figure 40 and Figure 41After forming the filling space 5421, a first conductive material 591 can be filled into the filling space 5421 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a gate layer 400. The gate layer 400 located on the first side 101 of the semiconductor layer 100 is the first gate layer 410, and the gate layer located on the second side 102 of the semiconductor layer 100 is the second gate layer 420. The first dielectric layer 541 located between the semiconductor layer 100 and the first gate layer 410 constitutes a gate dielectric layer, and the first dielectric layer 541 located between the semiconductor layer 100 and the second gate layer 420 also constitutes a gate dielectric layer.

[0165] For example, the first conductive material 591 includes, but is not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, or other suitable conductive materials.

[0166] In the step of filling the filling space 5421 with the first conductive material 591, the second structural hole 502 is also filled with the first conductive material 591. In order to isolate the multiple gate layers 400 stacked along the first direction X from each other, after filling with the first conductive material 591, an etching process can be used to remove the first conductive material 591 located in the second structural hole 502 until the dielectric layer 540 is exposed.

[0167] After removing the first conductive material 591 located in the second structural hole 502 to expose the dielectric layer 540, an insulating material can be filled in the second structural hole 502 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a partial isolation pillar 310.

[0168] S13. A bit line is formed, which penetrates the stacked structure along a first direction and is connected to the semiconductor layer.

[0169] like Figure 42 , Figure 43 and Figure 44 As shown, in this step, the third structural hole 503 can be opened by removing the third sacrificial column 533 and the isolation layer 520 located in the third structural hole 503.

[0170] refer to Figure 44 and Figure 45 The dielectric layer 540 covering the sidewall of the third structural hole 503 can be removed by wet etching through the third structural hole 503 to expose the semiconductor layer 100.

[0171] refer to Figure 45 , Figure 46 and Figure 47After the semiconductor layer 100 is exposed in the third structural hole 503, a second conductive material 592 can be filled in the third structural hole 503 by one or more thin film deposition processes including but not limited to PVD, CVD, and ALD to form a bit line BL, which can then be connected to the semiconductor layer 100.

[0172] For example, the second conductive material 592 includes, but is not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicides, or may be other suitable conductive materials. The second conductive material 592 may be the same as or different from the first conductive material 591 used in forming the gate layer 400. For example, the material of the gate layer 400 may include tungsten, and the material of the bit line BL may include polysilicon.

[0173] refer to Figure 46 , Figure 47 and Figure 48 After forming the bit line BL, a portion of the bit line BL can be etched back, and a third conductive material 593 can be filled into the third structural hole 503 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a contact 550. The contact 550 and the bit line BL are stacked along the first direction X. (Reference) Figure 47 , Figure 48 and Figure 49 In this step, when the third conductive material 593 is filled into the third structural hole 503, a portion of the third conductive material 593 will be located outside the third structural hole 503. Therefore, after filling the third conductive material 593 into the third structural hole 503, the surface of the dielectric layer 540 can be planarized by chemical mechanical polishing (CMP), for example, making the upper surface of the contact 550 flush with the upper surface of the stacked structure 500. After planarizing the surface of the stacked structure 500, a mask layer 280 can be formed on the stacked structure 500, exposing the filling pillars 270 within the second channel hole 202.

[0174] The third conductive material 593 includes, but is not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides, or may be other suitable conductive materials.

[0175] The volume of bit line BL is larger than that of contact 550. Therefore, the amount of material required to fabricate bit line BL is greater than that required to fabricate contact 550. Thus, in this embodiment, the material of contact 550 can be different from the material of bit line BL to save on the fabrication cost of semiconductor structure 1000.

[0176] refer to Figure 49and Figure 50 After the contact 550 is formed, a fourth dielectric layer 544 can be formed on the stacked structure 500 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. The fourth dielectric layer 544 is stacked with the stacked structure 500 along the first direction X, and the fourth dielectric layer 544 is located on the side of the contact 550 away from the bit line BL. The material of the fourth dielectric layer 544 may include an insulating material.

[0177] S2. A capacitor structure is formed, comprising a first electrode structure, a second electrode structure, and a dielectric layer. The first electrode structure comprises a first electrode layer and a second electrode layer. The first electrode layer is located on a first side of the semiconductor layer along a first direction, and the second electrode layer is located on a second side of the semiconductor layer along the first direction. Both the first electrode layer and the second electrode layer are in contact with the semiconductor layer, and the first direction intersects with the semiconductor layer. The second electrode structure is disposed around the semiconductor layer and comprises a first portion and a second portion. The first portion is located on a first side, and the second portion is located on a second side. The first electrode layer is disposed around the first portion, and the second electrode layer is disposed around the second portion. The dielectric layer comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is located between the first electrode layer and the first portion, and the second dielectric layer is located between the second electrode layer and the second portion.

[0178] like Figure 51 , Figure 52 and Figure 53 As shown, in this step, the fourth structural hole 504 can be opened by removing the fourth sacrificial pillar 534 and the isolation layer 520 located in the fourth structural hole 504.

[0179] For example, when the material of the fourth sacrificial pillar 534 includes carbon, the process for removing all the fourth sacrificial pillars 534 located within the fourth structural aperture 504 may include ashing. After removing the fourth sacrificial pillars 534, a wet etching process may be used to remove the isolation layer 520 located within the fourth structural aperture 504.

[0180] In some embodiments, the isolation layer 520 and the third dielectric layer 543 may be made of the same material. For example, both the isolation layer 520 and the third dielectric layer 543 may be made of silicon oxide. Therefore, in the step of removing the isolation layer 520 located in the fourth structural hole 504 using a wet etching process, a portion of the third dielectric layer 543 exposed in the fourth structural hole 504 may also be removed, thereby exposing the second dielectric layer 542 in the fourth structural hole 504.

[0181] refer to Figure 53 , Figure 54 and Figure 55After removing the isolation layer 520 located in the fourth structural hole 504, a wet etching process can be used to remove part of the second dielectric layer 542 exposed in the fourth structural hole 504 to expose the first dielectric layer 541.

[0182] refer to Figure 55 , Figure 56 and Figure 57 After removing a portion of the second dielectric layer 542, a wet etching process can be used to remove a portion of the first dielectric layer 541 exposed in the fourth structural hole 504 to expose the semiconductor layer 100. In this step, after removing a portion of the second dielectric layer 542 and a portion of the first dielectric layer 541, a gap 5041 is formed between the semiconductor layer 100 and the third dielectric layer 543, and this gap 5041 communicates with the fourth structural hole 504.

[0183] refer to Figure 56 and Figure 57 After exposing the semiconductor layer 100, a portion of the semiconductor layer 100 can be doped through the fourth structural hole 504. For example, a P-type dopant can be used to dope a portion of the semiconductor layer 100, thereby forming a source electrode that connects to the capacitor structure 200 formed in subsequent steps. The P-type dopant includes boron or gallium.

[0184] refer to Figure 57 , Figure 58 and Figure 59 After doping a portion of the semiconductor layer 100, an electrode layer 560 can be formed on the surface of the semiconductor layer 100 using an ALD process, for example, through the fourth structural hole 504 and the gap 5041. This process is a layered growth, forming an electrode layer not only on the surface of the semiconductor layer 100 but also on the surface of the dielectric layer 540. It should be noted that the electrode layer 560 is a layered structure located on the surfaces of the fourth structural hole 504 and the gap 5041, and it does not fill the entire space of the fourth structural hole 504 and the gap 5041. The fourth structural hole 504 and the gap 5041 still exist after the electrode layer 560 is formed. The electrode layer 560 formed through the above steps is disposed around the semiconductor layer 100 and also around the third dielectric layer 543.

[0185] For example, the material of the electrode layer 560 may include one or more of the following materials: W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, and WSi.

[0186] refer to Figure 59 , Figure 60 and Figure 61After forming the electrode layer 560, a second sacrificial layer 570 can be formed on the surface of the electrode layer 560 using a thin-film deposition process. The second sacrificial layer 570 covers the surface of the electrode layer 560, fills the gaps 5041, and surrounds the electrode layer 560. Here, the material of the second sacrificial layer 570 is different from the material of the first dielectric layer 541, and the material of the second sacrificial layer 570 is different from the material of the third dielectric layer 543. For example, the material of the second sacrificial layer 570 may include silicon nitride.

[0187] refer to Figure 61 , Figure 62 and Figure 63 After the second sacrificial layer 570 is formed, a wet etching process can be used to remove part of the second sacrificial layer 570 covering the sidewall of the fourth structural hole 504 to expose the electrode layer 560.

[0188] After the electrode layer 560 is exposed within the fourth structural hole 504, a wet etching process can be used to remove a portion of the electrode layer 560 covering the sidewalls of the fourth structural hole 504 until the semiconductor layer 100 is exposed, forming the first electrode structure 210. The above steps involve removing the electrode layer 560 covering both sides of the semiconductor layer 100 along the second direction Y through the fourth structural hole 504, retaining a portion of the electrode layer 560 located on the surface of the gap 5041. The retained electrode layer 560 constitutes the first electrode structure 210. The electrode layer 560 located on the first side 101 constitutes the first electrode layer 211, and the electrode layer located on the second side 102 constitutes the second electrode layer 212. Both the first electrode layer 211 and the second electrode layer 212 are annular structures.

[0189] refer to Figure 64 , Figure 65 , Figure 66 and Figure 67 After the first electrode structure 210 is formed, the second sacrificial layer 570 can be removed by wet etching through the fourth structural hole 504.

[0190] refer to Figure 67 , Figure 68 and Figure 69 After removing the second sacrificial layer 570, a dielectric layer 230 can be formed on the surface of the semiconductor layer 100, the surface of the first electrode structure 210, and the surface of the dielectric layer 540 through the fourth structural hole 504 using the ALD process. The dielectric layer 230 is disposed around the first electrode structure 210, around the semiconductor layer 100, and around the third dielectric layer 543.

[0191] For example, the dielectric layer 230 may be made of a high-k (K greater than 2.8) dielectric material to increase the capacitance per unit area. In specific embodiments, the dielectric layer 230 may include one or more of the following materials: HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO.

[0192] In this step, the dielectric layer 230 covers the sidewall of the fourth structural hole 504, and the dielectric layer 230 can contact the isolation pillar 310. The dielectric layer 230 and the isolation pillar 310 can together form the isolation structure 300. The isolation structure 300 is located between the first sub-layer 110 and the second sub-layer 120 arranged along the second direction Y.

[0193] refer to Figure 69 , Figure 70 and Figure 71 After the dielectric layer 230 is formed, electrode material can be deposited through the fourth structural hole 504 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a second electrode structure 220. The second electrode structure 220 covers the surface of the dielectric layer 230, is disposed around the dielectric layer 230, and covers the sidewall of the fourth structural hole 504.

[0194] It should be noted that in the preceding steps, the first electrode structure 210 and dielectric layer 230 formed by the ALD process are both thin-film structures. Therefore, the first electrode layer 211 can enclose a gap, the second electrode layer 212 can also enclose a gap, and the dielectric layer 230 can also enclose a gap. In this step, the second electrode structure 220 can extend into the gap enclosed by the dielectric layer 230, that is, the second electrode structure 220 can extend into the gap enclosed by the first electrode layer 211 and the gap enclosed by the second electrode layer 212. The second electrode structure 220 extending into the gap enclosed by the first electrode layer 211 is the first part 221, and the second electrode structure 220 extending into the gap enclosed by the second electrode layer 212 is the second part 222. Thus, the first electrode layer 211 is arranged around the first part 221, and the second electrode layer 212 is arranged around the second part 222.

[0195] refer to Figure 71 , Figure 72 and Figure 73 After forming the second electrode structure 220, a fourth conductive material can be filled into the fourth structural hole 504 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a conductive structure 240. The conductive structure 240 is in contact with the second electrode structure 220.

[0196] For example, the fourth conductive material includes, but is not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, or other suitable conductive materials.

[0197] The capacitor structure 200 formed through the above steps arranges the first electrode structure 210 around the second electrode structure 220, making full use of the first electrode structure 210 and increasing the facing area between the first electrode structure 210 and the second electrode structure 220. This is beneficial for the capacitor structure 200 to store more charge, thereby increasing the capacitance value of the capacitor structure 200. Furthermore, when the capacitor structure 200 in this embodiment maintains the same capacitance value as the capacitor structures 200 in some other embodiments, and the capacitor structure 200 in this embodiment fully utilizes the first electrode structure 210, the size of the capacitor structure 200 in the second direction Y and the third direction Z can be reduced, which is beneficial for reducing the size of the semiconductor structure 1000 and increasing the storage density of the semiconductor structure 1000.

[0198] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, Includes semiconductor layers and capacitor structures; The capacitor structure includes: The first electrode structure includes a first electrode layer and a second electrode layer. The first electrode layer is located on a first side of the semiconductor layer along a first direction, and the second electrode layer is located on a second side of the semiconductor layer along the first direction. Both the first electrode layer and the second electrode layer are in contact with the semiconductor layer, and the first direction intersects with the semiconductor layer. A second electrode structure is disposed around the semiconductor layer. The second electrode structure includes a first part and a second part, the first part being located on the first side and the second part being located on the second side. The first electrode layer is disposed around the first part and the second electrode layer is disposed around the second part. The dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is located between the first electrode layer and the first portion, and the second dielectric layer is located between the second electrode layer and the second portion.

2. The semiconductor structure according to claim 1, characterized in that, The second electrode structure overlaps with the semiconductor layer in the first direction and the second direction, but does not overlap with the semiconductor layer in the third direction; the second direction intersects with the third direction, and the first direction intersects in the plane containing the second direction and the third direction.

3. The semiconductor structure according to claim 2, characterized in that, The first electrode layer and the first portion overlap in the first direction and the third direction, but do not overlap in the second direction; The second electrode layer and the second portion overlap in the first direction and the third direction, but do not overlap in the second direction.

4. The semiconductor structure according to claim 1, characterized in that, The dielectric layer is disposed around the semiconductor layer, and the dielectric layer is also disposed around the second electrode structure.

5. The semiconductor structure according to any one of claims 2-4, characterized in that, The semiconductor structure includes an isolation structure that penetrates the semiconductor layer along the first direction; The semiconductor layer in the same layer includes a first sublayer and a second sublayer arranged along the second direction, and the isolation structure is located between the first sublayer and the second sublayer.

6. The semiconductor structure according to claim 5, characterized in that, The isolation structure includes isolation pillars and the dielectric layer; The isolation column includes a first sub-column, a second sub-column, and a third sub-column arranged sequentially along the third direction.

7. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure further includes a gate layer stacked with the semiconductor layer. The gate layer includes a first gate layer and a second gate layer, with the first gate layer located on the first side and the second gate layer located on the second side. On the plane where the gate layer is located, the second sub-pillar is spaced apart from the first sub-pillar and the third sub-pillar, and the gate layer is arranged around the second sub-pillar.

8. The semiconductor structure according to claim 7, characterized in that, On the plane where the gate layer is located, the area of ​​the second sub-pillar is smaller than the area of ​​the first sub-pillar, and the area of ​​the second sub-pillar is smaller than the area of ​​the third sub-pillar.

9. The semiconductor structure according to claim 6, characterized in that, On the plane where the semiconductor layer is located, the second sub-pillar is connected between the first sub-pillar and the third sub-pillar.

10. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure further includes a plurality of bit lines that penetrate the semiconductor layer along the first direction and are connected to the semiconductor layer. The third sub-pillar is also located between two adjacent bit lines.

11. The semiconductor structure according to any one of claims 1-5, characterized in that, The semiconductor structure includes a plurality of semiconductor layers and a plurality of capacitor structures stacked along the first direction, wherein the second electrode structures of the plurality of capacitor structures together constitute a common electrode layer. The semiconductor structure further includes a conductive structure that extends through the plurality of semiconductor layers along the first direction, and the conductive structure is in contact with the common electrode layer.

12. The semiconductor structure according to claim 11, characterized in that, The conductive structure is also located between two adjacent semiconductor layers along the first direction.

13. A method for fabricating a semiconductor structure, characterized in that, include: Forming a semiconductor layer; A capacitor structure is formed, the capacitor structure including a first electrode structure, a second electrode structure and a dielectric layer. The first electrode structure includes a first electrode layer and a second electrode layer. The first electrode layer is located on a first side of the semiconductor layer along a first direction, and the second electrode layer is located on a second side of the semiconductor layer along the first direction. Both the first electrode layer and the second electrode layer are in contact with the semiconductor layer. The first direction intersects with the semiconductor layer. The second electrode structure is disposed around the semiconductor layer. The second electrode structure includes a first part and a second part. The first part is located on the first side, and the second part is located on the second side. The first electrode layer is disposed around the first part, and the second electrode layer is disposed around the second part. The dielectric layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located between the first electrode layer and the first part, and the second dielectric layer is located between the second electrode layer and the second part.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The formation of the semiconductor layer includes: A stacked structure is formed, the stacked structure comprising the semiconductor layer and the first sacrificial layer alternately stacked along a first direction; After forming the semiconductor layer and before forming the capacitor structure, the method further includes: An isolation pillar is formed, which penetrates the stacked structure along the first direction. The semiconductor layer in the same layer includes a first sub-layer and a second sub-layer arranged along a second direction. The isolation pillar is located between the first sub-layer and the second sub-layer, and the second direction is parallel to the semiconductor layer. A gate layer is formed, wherein the gate layer is stacked with the semiconductor layer, and the gate layer includes a first gate layer and a second gate layer, wherein the first gate layer is located on the first side and the second gate layer is located on the second side; A bit line is formed, which penetrates the stacked structure along the first direction and is connected to the semiconductor layer.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, The formation of the isolation column includes: A first structural hole is formed, and the first structural hole penetrates the stacked structure along the first direction; The first sacrificial layer is removed through the first structural hole; A dielectric layer is formed, the dielectric layer including a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the first dielectric layer is disposed around the semiconductor layer, the second dielectric layer is disposed around the first dielectric layer, and the third dielectric layer is disposed around the second dielectric layer; Remove a portion of the dielectric layer covering the hole wall of the first structural hole to expose the semiconductor layer; Remove part of the semiconductor layer; Insulating material is filled into the first structural hole to form a portion of the isolation pillar.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, The formation of the gate layer includes: A second structural hole is formed, which penetrates the stacked structure along the first direction; Remove a portion of the dielectric layer covering the sidewall of the second structural hole; A portion of the second dielectric layer is removed through the second structural pore to form a filling space; The filling space is filled with a first conductive material to form the gate layer; Insulating material is filled into the second structural hole to form a portion of the isolation pillar.

17. The method for preparing a semiconductor structure according to claim 15, characterized in that, The formation of bit lines includes: A third structural hole is formed, which penetrates the stacked structure along the first direction; Remove a portion of the dielectric layer covering the sidewall of the third structural hole; The third structural hole is filled with a second conductive material to form the bit line; A third conductive material is filled into the third structural hole to form a contact, and the contact and the bit line are stacked together along the first direction.

18. The method for preparing a semiconductor structure according to claim 17, characterized in that, After forming the contact and before forming the capacitor structure, the method further includes: A fourth dielectric layer is formed, which is stacked with the stacked structure along the first direction, and the fourth dielectric layer is located on the side of the contact away from the bit line.

19. The method for fabricating a semiconductor structure according to claim 17 or 18, characterized in that, The formation of the capacitor structure includes: A fourth structural hole is formed, which penetrates the stacked structure along the first direction; Part of the first dielectric layer and part of the second dielectric layer are removed through the fourth structural hole; An electrode layer is formed, the electrode layer being disposed around the semiconductor layer and the electrode layer being disposed around the third dielectric layer; A portion of the electrode layer covering the sidewall of the fourth structural hole is removed to form the first electrode structure, wherein the electrode layer located on the first side constitutes the first electrode layer, and the electrode layer located on the second side constitutes the second electrode layer. The dielectric layer is formed, the dielectric layer is disposed around the semiconductor layer, and the dielectric layer is disposed around the third dielectric layer; A second electrode structure is formed, the second electrode structure is disposed around the dielectric layer, and the second electrode structure covers the sidewall of the fourth structural hole; A fourth conductive material is filled into the fourth structural hole to form a conductive structure.

20. The method for preparing a semiconductor structure according to claim 19, characterized in that, After the formation of the electrode layer, and before the removal of the portion of the electrode layer covering the sidewall of the fourth structural hole, the method further includes: A second sacrificial layer is formed, which is disposed around the electrode layer; Remove a portion of the second sacrificial layer covering the sidewall of the fourth structural hole; After removing a portion of the electrode layer covering the sidewall of the fourth structural hole, and before forming the dielectric layer, the method further includes: Remove the second sacrificial layer.

21. The method for preparing a semiconductor structure according to claim 19, characterized in that, The first structural hole, the second structural hole, the third structural hole, and the fourth structural hole are formed in the same process step.

22. A storage system, characterized in that, include: The semiconductor structure according to any one of claims 1-12; A controller coupled to the semiconductor structure to control the semiconductor structure to store data.

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