Memory for artificial intelligence
By employing complementary transistor structures and interleaved pulse signal control in the memory, the challenge of configuring high-cell-density neural networks was solved, improving computing power and overcoming the memory wall and power consumption wall, thus achieving efficient neural network computing.
CN122138398APending Publication Date: 2026-06-02BAIDAI (SHANGHAI) DATA TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BAIDAI (SHANGHAI) DATA TECH CO LTD
- Filing Date
- 2026-01-29
- Publication Date
- 2026-06-02
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Figure CN122138398A_ABST
Abstract
This invention relates to a memory for artificial intelligence applications. Multiple trenches are formed on a semiconductor substrate, and two storage transistors housed in each trench are considered a set of complementary transistors. A string of complementary transistors is configured to be connected in parallel. The drain of each storage transistor in the string is coupled to the bit line of the string, and the source of each storage transistor in the string is coupled to the source line of the string. Input data from a neural network to the string is input as pulse signals to the gates of the respective storage transistors in the string. The control method for the first and second complementary transistors receiving the pulse signals is staggered; that is, during a single input cycle, if the gate of the first transistor is high-level, the gate of the second transistor does not have a high-level pulse, or vice versa.
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