Memory devices and methods of manufacturing memory devices

Abstract

The present application relates to memory devices and methods of manufacturing memory devices. A memory device includes a contact and a plurality of support structures disposed about the contact, wherein each of the support structures is formed with a plurality of overlapping holes. The support structures include an insulating layer disposed within the overlapping holes. The support structures are formed by expanding a plurality of first openings and overlapping them.

Description

Technical Field

[0001] This disclosure generally relates to memory devices and methods for manufacturing memory devices. Background Technology

[0002] Memory devices include non-volatile memory devices that retain stored data even without power. Based on the arrangement of their memory cells, non-volatile memory devices are classified as two-dimensional or three-dimensional structures. Memory cells of a two-dimensional non-volatile memory device can be arranged in a single layer on a substrate. Memory cells of a three-dimensional non-volatile memory device can be stacked in a direction perpendicular to the substrate. Because the integration density of three-dimensional non-volatile memory devices is greater than that of two-dimensional non-volatile memory devices, electronic devices incorporating three-dimensional non-volatile memory devices have recently become increasingly popular. Summary of the Invention

[0003] According to one embodiment, a memory device may include: a contact; and a plurality of support structures disposed around the contact, wherein each of the plurality of support structures is formed in a plurality of overlapping holes.

[0004] According to one embodiment, a method of manufacturing a memory device may include the steps of: forming a stacked structure including a plurality of interlayer insulating layers and a plurality of sacrificial layers alternately stacked in a first direction; forming a contact opening extending from a first sacrificial layer among the plurality of sacrificial layers along the first direction; forming a plurality of first openings extending through the stacked structure and surrounding the contact opening; expanding the plurality of first openings to form a plurality of overlapping holes; and forming a support structure by providing insulating layers within the plurality of overlapping holes.

[0005] According to one embodiment, a memory device includes contacts and a plurality of support structures disposed around the contacts. Each of the support structures may include a plurality of continuous members. The distance between the centers of adjacent continuous members may be less than the width of one of the adjacent continuous members. Attached Figure Description

[0006] Figure 1 This is a diagram illustrating a memory device according to an embodiment of the present disclosure;

[0007] Figure 2 This is a diagram illustrating a memory block of a memory device according to an embodiment of the present disclosure;

[0008] Figure 3A and Figure 3B This is a diagram illustrating a memory device including a support structure according to an embodiment of the present disclosure;

[0009] Figures 4A to 4Z This is a view showing a memory device including a support structure formed by a method of manufacturing a memory device including a support structure according to an embodiment of the present disclosure.

[0010] Figure 5A and Figure 5B This is a diagram illustrating a memory device including a support structure and support columns according to an embodiment of the present disclosure;

[0011] Figures 6A to 6N This is a view showing a memory device including a support structure and support pillars formed by a method of manufacturing a memory device including a support structure and support pillars according to an embodiment of the present disclosure.

[0012] Figures 7A to 7F This is a diagram illustrating various support structures according to embodiments of the present disclosure;

[0013] Figure 8 This is a diagram illustrating a memory card system including a memory device according to an embodiment of the present disclosure; and

[0014] Figure 9 This is a diagram illustrating a solid-state drive (SSD) system including a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0015] Embodiments of this disclosure will be described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0016] The use of terms such as “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “on top,” “upper,” “side,” “upper,” “lower,” “higher,” “column,” “row,” and “level,” as well as other terms that suggest relative spatial relationships or orientations, is for the purpose of description or reference to the accompanying drawings only and is not intended to be limiting in any other way. When one element is identified as being “on” or “above” another element, these elements may be in direct contact with each other, or an intermediate element may be placed between these elements.

[0017] Cross-shading throughout the figures indicates corresponding or similar areas between figures, rather than indicating material associated with those areas.

[0018] When one element is marked as “connected” to another element, the elements can be directly connected or connected through at least one intermediate element between them. When two elements are marked as “directly connected”, one element is directly connected to the other element without any intermediate element between them.

[0019] As the integration density of non-volatile memory devices, including three-dimensional structures, increases, support structures that prevent bending of vertically stacked material layers are advantageous. This disclosure describes a memory device with improved support structure performance, a simplified manufacturing process for the support structure, and a method for manufacturing the memory device.

[0020] Figure 1 This is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0021] Reference Figure 1 The memory device 100 includes a memory cell array 110, peripheral circuitry 170, and control circuitry 180.

[0022] The memory cell array 110 includes memory blocks BLK1 to BLKi, where i is a positive integer. Each of the first memory block BLK1 to the i-th memory block BLKi includes a memory cell capable of storing data. Drain select line DSL, word line WL, source select line SSL, and source line SL are connected to each of the memory blocks BLK1 to BLKi, and the bit line BL is collectively connected to the memory blocks BLK1 to BLKi.

[0023] The memory blocks BLK1 to BLKi have a three-dimensional structure. Each memory block with a three-dimensional structure includes, for example, memory cells stacked vertically on a substrate.

[0024] Each memory cell stores one, two, three, four, five, or more bits of data, depending on the programming method. For example, storing one bit of data in one memory cell is called the Single-Level Cell (SLC) method, and storing two bits of data in one memory cell is called the Multi-Level Cell (MLC) method. Storing three bits of data in one memory cell is called the Three-Level Cell (TLC) method, and storing four bits of data in one memory cell is called the Quadruple-Level Cell (QLC) method.

[0025] Peripheral circuitry 170 is configured to perform programming operations that store data in memory cell array 110, read operations that output data stored in memory cell array 110, and erase operations that erase data stored in memory cell array 110. For example, peripheral circuitry 170 includes voltage generator 120, row decoder 130, page buffer group 140, column decoder 150, and input / output circuitry 160.

[0026] Voltage generator 120 generates various operating voltages Vop used during programming, reading, or erasing operations in response to operation code OPCD. For example, voltage generator 120 can be configured to generate programming voltage, turn-on voltage, turn-off voltage, negative voltage, pre-charge voltage, verification voltage, read voltage, pass voltage, or erase voltage in response to operation code OPCD. The operating voltage Vop generated by voltage generator 120 is applied to the drain select line DSL, word line WL, source select line SSL, and source line SL of the selected memory block via line decoder 130.

[0027] During programming operations, a programming voltage is applied to the selected word line (WL) and used to increase the threshold voltage of the memory cell connected to the selected word line. A turn-on voltage is applied to the drain select line (DSL) or the source select line (SSL) and used to turn on the drain select transistor and the source select transistor. A turn-off voltage is applied to the drain select line (DSL) or the source select line (SSL) and used to turn off the drain select transistor and the source select transistor. For example, the turn-off voltage can be set to 0V. A precharge voltage can be higher than 0V and can be applied to the bit line (BL) during read operations. During verification operations, a verification voltage is used to determine whether the threshold voltage of the selected memory cell has increased to a target level. The verification voltage can be set to various levels according to the target level and can be applied to the selected word line.

[0028] A read voltage is applied to the selected word line during a read operation of the selected memory cell. For example, the read voltage can be set to various levels depending on the programming method of the selected memory cell. An unselected word line is applied to the word line WL during a programming or read operation to turn on the memory cells connected to the unselected word line. An erase voltage is used during an erase operation to erase the memory cells included in the selected memory block and is applied to the source line SL.

[0029] The row decoder 130 is configured to transmit the operating voltage Vop to the drain select line DSL, word line WL, source select line SSL, and source line SL, which are connected to the memory blocks selected according to the row address RADD. For example, the row decoder 130 is connected to the voltage generator 120 via a global line and to memory blocks BLK1 to BLKi via the drain select line DSL, word line WL, source select line SSL, and source line SL.

[0030] Page buffer group 140 includes page buffers (not shown) respectively connected to memory blocks BLK1 to BLKi. The page buffers are connected to memory blocks BLK1 to BLKi via bit lines BL. During a read operation, the page buffer senses the current or voltage of bit line BL, which varies according to the threshold voltage of the selected memory cell, in response to the page buffer control signal PBSIG, and temporarily stores the sensed data.

[0031] The column decoder 150 is configured to facilitate data transfer between the page buffer group 140 and the input / output circuitry 160 in response to the column address CADD. For example, the column decoder 150 is coupled to the page buffer group 140 via column line CL and transmits an enable signal via column line CL. The page buffers included in the page buffer group 140 receive or output data via data line DL in response to the enable signal.

[0032] Input / output circuit 160 is configured to receive or output commands (CMD), addresses (ADD), or data via input / output line I / O. For example, input / output circuit 160 transmits commands (CMD) and addresses (ADD) received from an external controller via input / output line I / O to control circuit 180, and transmits data received from an external controller via input / output line I / O to page buffer group 140. Input / output circuit 160 outputs data transmitted from page buffer group 140 to the external controller via input / output line I / O.

[0033] Control circuit 180 responds to command CMD and address ADD by outputting at least one of operation code OPCD, row address RADD, page buffer control signal PBSIG, and column address CADD. For example, when command CMD input to control circuit 180 corresponds to a programming operation, control circuit 180 controls peripheral circuit 170 to perform a programming operation on the memory block selected by address ADD. When command CMD input to control circuit 180 corresponds to a read operation, control circuit 180 controls peripheral circuit 170 to perform a read operation on the memory block selected by address ADD and outputs the read data. When command CMD input to control circuit 180 corresponds to an erase operation, control circuit 180 controls peripheral circuit 170 to perform an erase operation on the selected memory block.

[0034] Figure 2 This is a diagram showing a memory block of a memory device 100 according to an embodiment of the present disclosure.

[0035] Reference Figure 2 The memory device 100 includes memory blocks BLK1 to BLKi disposed on a peripheral circuit structure PC, which is disposed above the substrate SUB. The memory blocks BLK1 to BLKi overlap with the peripheral circuit structure PC at least once.

[0036] The substrate SUB can be a single-crystal semiconductor layer. For example, the substrate SUB can be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by selective epitaxial growth.

[0037] The peripheral circuit structure PC includes, for example, peripheral circuitry 170 comprising a row decoder 130, a column decoder 150, and a page buffer group 140, as well as control circuitry 180 controlling the operation of memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC may include NMOS transistors, PMOS transistors, resistors, and capacitors electrically connected to memory blocks BLK1 to BLKi. Figure 2 In the example, the peripheral circuit structure PC is positioned between the substrate SUB and the memory blocks BLK1 to BLKi.

[0038] Each of the memory blocks BLK1 to BLKi includes a source structure, bit lines, a string of cells electrically connected to the source structure and bit lines, a word line electrically connected to the string of cells, and a select line electrically connected to the string of cells. Each of the string of cells includes a memory cell and a select transistor connected in series via cell plugs. Each select line is the gate electrode of the corresponding select transistor, and each word line is the gate electrode of the corresponding memory cell.

[0039] In one embodiment, the substrate SUB, the peripheral circuit structure PC, and the memory blocks BLK1 to BLKi are relative to Figure 2 The order shown is stacked in reverse order. For example, the peripheral circuit structure PC is positioned above the memory blocks BLK1 to BLKi.

[0040] In one implementation, with Figure 2 Conversely, the peripheral circuit structure PC is disposed above some areas of the substrate SUB that may not overlap with the memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC and the memory blocks BLK1 to BLKi may be disposed in areas of the substrate SUB that do not overlap with each other.

[0041] Figure 3A and Figure 3B This is a diagram illustrating a memory device 100 including a support structure according to an embodiment of the present disclosure. Figure 3A This is a plan view showing the layout of a memory device 100 according to an embodiment of the present disclosure. Figure 3B It shows along Figure 3A The cross section intercepted by line A-A'.

[0042] Reference Figure 3A The memory device 100 has a cell region CR and a contact region CTR. The contact region CTR and the cell region CR are distributed along the X direction. The contact region CTR extends from the cell region CR along the X direction. Figure 3A The contact area CTR shown is different; the contact area CTR can extend from the element region CR along the Y direction, or it can extend along both the X and Y directions. The element region CR and the contact area CTR can be arranged in various ways.

[0043] Cell plugs (CPLs) are located within cell regions (CR). Cell plugs (CPLs) are arranged along the X and Y directions. Cell plugs (CPLs) are spaced apart from each other in the X and Y directions. Each cell plug (CPL) extends along the Z direction. Each cell plug (CPL) is electrically connected to a bitline (e.g., via a wiring structure) through a wiring configuration. Figure 1 Bit lines (BL) and source lines (e.g., Figure 1 The source line (SL).

[0044] Each of the cell plugs (CPL) includes a memory layer ML, a channel layer CH, and a gap fill layer GF. The memory layer ML may have a cylindrical shape. The memory layer ML surrounds the channel layer CH. Although not shown, the memory layer ML includes a barrier layer, a charge trapping layer, and a tunnel insulating layer. The channel layer CH is formed along the inner wall of the memory layer ML. The gap fill layer GF fills the channel layer CH. The gap fill layer GF may have a cylindrical shape surrounded by the channel layer CH.

[0045] The barrier layer and tunnel insulating layer included in the memory layer ML may include oxide layers such as silicon oxide layers, or oxynitride layers such as silicon oxide nitride layers, or combinations thereof. The charge trapping layer included in the memory layer ML may include nitride layers or variable resistance materials. The channel layer CH may include undoped silicon layers or doped silicon layers. The gap filling layer GF may include insulating layers such as oxide layers.

[0046] The contact element CT is located within the contact area CTR. Although Figure 3A A single contact element (CT) is shown, but multiple contacts are arranged within the contact area (CTR). The contact element (CT) extends along the Z-direction. The contact element (CT) comprises a conductive material. The contact element (CT) can be referred to as a contact plug.

[0047] The spacer SPA surrounds the side surface of the contact CT. The contact CT may fill the internal area of ​​the spacer SPA. The spacer SPA includes an insulating layer. For example, the spacer SPA may include an oxide layer.

[0048] The support structure SS is located within the contact area CTR. The support structure SS is disposed around the contact element CT. For example, the support structure SS may extend from the contact element CT along the X direction, Y direction, the direction opposite to the X direction, the direction opposite to the Y direction, or any direction in the XY plane. The support structures SS are spaced apart. The support structure SS may contact the spacer SPA. The support structure SS may partially overlap with the contact element CT in the Z direction. The support structure SS may include insulating material.

[0049] Each of the support structures SS has a shape formed using overlapping support holes SH formed during the manufacturing process. One of the support structures SS can be formed by two or more overlapping support holes SH. For example, in... Figure 3A In this structure, each of the support structures SS is formed using four overlapping support holes SH. Each of the support structures SS includes an insulating layer, such as an oxide layer, disposed or filled in the overlapping support holes SH.

[0050] In this disclosure, overlapping support holes SH (also referred to as overlapping holes or overlapping support holes) include, for example, contiguous holes, because the openings used to form the support holes extend from the center or middle of each opening by removing material adjacent to the opening until the extended openings are adjacent and form a single continuous aperture for each support structure SS. The term "support hole" does not imply that the support hole SH provides physical support, but is so named because the process of forming the support structure SS utilizes the support hole SH. Alternatively, overlapping support holes SH include a common area between adjacent or contiguous support holes SH in the XY plane. Figure 3A In the example, the centers of all four overlapping support holes SH form the vertices of a parallelogram, but this disclosure is not limited to this example. For example, the support structure SS can be formed by two, three, five or more overlapping support holes SH, as shown in, for example, reference... Figures 7A to 7F As described above. For example, the support structure SS may include four overlapping support holes SH, but in some embodiments, two of the four support holes SH do not overlap, as shown in reference [reference needed]. Figure 7E and Figure 7F For example, the support structure SS can have a shape in which the centers of the overlapping support holes SH are arranged in a line or arc, rather than forming vertices of shapes such as quadrilaterals, parallelograms, rectangles, triangles, pentagons, hexagons or other shapes.

[0051] Reference Figure 3BThe memory device 100 includes a stacked structure STK. The stacked structure STK includes a conductive layer CD and an interlayer insulating layer IIL. The conductive layer CD and the interlayer insulating layer IIL are stacked alternately in the Z direction. The stacked structure STK includes an upper insulating layer UIL. The conductive layer CD may include at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polysilicon (poly-Si). The conductive layer CD corresponds to, for example, a gate line, such as... Figure 1 The drain select line DSL, word line WL, and source select line SSL are shown. The interlayer insulating layer IIL may include an oxide layer such as a silicon oxide layer. The upper insulating layer UIL may include the same material as the interlayer insulating layer IIL.

[0052] Cell plugs (CPLs) extend through the cell regions (CRs) of the stacked structure (STK). Each cell plug (CPL) may include a memory layer (ML), a channel layer (CH), and a gap fill layer (GF). Memory cells or select transistors are formed at the intersection of the cell plug (CPL) and the conductive layer (CD). The cell plug (CPL) can serve as the channel region for a cell string.

[0053] The support structure SS extends through the contact area CTR of the laminated structure STK. The support structure SS extends along the Z-direction. The support structure SS includes overlapping support holes SH. Because... Figure 3B Corresponding to along Figure 3A The cross-section is taken from line A-A', so four support holes SH are used to form the support structure SS. Because the four support holes SH used to form each support structure SS overlap, there are no sidewalls of the stacked structure STK between the support holes. Figure 3B Unlike other structures, the sidewalls of the stacked STK can exist between two of the support holes SH included in each of the support structures SS. For example, when the distance between two support holes SH is large enough that the support holes SH do not overlap along line A-A', the sidewalls of the stacked STK remain between the support holes SH, such as... Figure 7E The support structure SS is shown in the figure. In one embodiment, although there are sidewalls at the bottom of the support holes SH, there are no sidewalls at the top of the support holes SH. The support structure SS is formed in overlapping support holes SH. The support structure includes multiple continuous members. For example, the continuous members can be considered to be formed in each overlapping hole, and the resulting structure forms a single support structure. The continuous members can be formed simultaneously using an insulating layer. The distance between the centers or middles of adjacent continuous members is less than the width of one of the adjacent continuous members, so the continuous members can be considered to be overlapping.

[0054] The contact CT extends along the Z-direction in the contact region CTR of the laminated structure STK. The contact CT extends along the Z-direction from the first conductive layer CD1, which is included in the conductive layer CD of the laminated structure STK. The lower surface of the contact CT contacts the area of ​​the upper surface of the first conductive layer CD1. The contact CT is electrically connected to the first conductive layer CD1. Although as... Figure 3A As shown, the first conductive layer CD1 is connected to the contact CT through the electrical path between the supporting structures SS, but... Figure 3B The cross-section shown does not show the extension of the first conductive layer CD1 between the cell region CR and the contact CT in the contact region CTR.

[0055] The side surfaces of the contact element CT include alternating concave and convex surfaces, such as square serrations. The contact element CT includes protrusions extending between the contact and the conductive layer CD. The protrusions of the contact element CT may be located at a height corresponding to the height of the conductive layer CD.

[0056] Spacer SPA surrounds the side surface of contact CT. Spacer SPA extends along the protrusions of contact CT. Spacer SPA may have alternating convex and concave structures corresponding to the shape of contact CT. Spacer SPA includes protrusions and recesses. Protrusions along the outer surface of spacer SPA may be located at a height corresponding to the height of conductive layer CD, and recesses along the outer surface of spacer SPA may be located at a height corresponding to the height of interlayer insulating layer ILL. Spacer SPA insulates contact CT from conductive layer CD other than the first conductive layer CD1. For example, spacer SPA insulates and separates contact CT from conductive layer CD located above the first conductive layer CD1 in laminated structure STK.

[0057] The supporting structure SS contacts the outer surface of the spacer SPA. (Refer to...) Figure 3A and Figure 3B The support structure SS contacts the outer surface of the spacer SPA, and the support structure SS extends from the contact CT in the X direction, extends from the contact CT in the Y direction, extends from the contact CT in a direction opposite to the X direction, and extends from the contact CT in a direction opposite to the Y direction. For example, the support structure SS contacts the outer surface of the spacer SPA and the lower surface of the spacer SPA.

[0058] The support structure SS contacts the lower surface of the contact CT. The lower surface of the contact CT contacts the first conductive layer CD1 and the support structure SS. The support structure SS overlaps with the contact CT in the Z direction.

[0059] The shape of the support hole SH closest to the contact element CT is determined by, or corresponds to, the shape of the contact element CT and the shape of the spacer SPA. (Refer to...) Figures 4A to 4Z Describe in detail the shape of the support structure SS and the support hole SH.

[0060] Figures 4A to 4Z This is a view showing a memory device including a support structure formed by a method of manufacturing a memory device 100 including a support structure SS according to an embodiment of the present disclosure. Figures 4A to 4Z This includes plan views taken from the Z direction of various steps during the method for manufacturing the memory device 100, and corresponding cross-sectional views taken through line A-A' of each plan view.

[0061] Reference Figure 4A and Figure 4B A preliminary stacked structure pSTK is formed, comprising alternating layers of sacrificial layer SF and interlayer insulating layer IIL. Upper insulating layer UIL is stacked over the interlayer insulating layer IIL and the sacrificial layer SF. The interlayer insulating layer IIL may comprise an insulating material. For example, the interlayer insulating layer IIL may comprise an oxide layer, such as a silicon oxide layer. The upper insulating layer UIL may comprise the same material as the interlayer insulating layer IIL. The sacrificial layer SF comprises a material that can be selectively removed. The sacrificial layer SF may comprise a material having an etch selectivity different from that of the interlayer insulating layer IIL. For example, the sacrificial layer SF may comprise a nitride layer.

[0062] A channel opening CHH and a first opening OP1 are formed extending through the initial stacked structure pSTK. The channel opening CHH extends through the unit region CR of the initial stacked structure pSTK. The first opening OP1 extends through the contact region CTR of the initial stacked structure pSTK. Each of the channel opening CHH and the first opening OP1 may have a circular shape. For example, the channel opening CHH and the first opening OP1 may have a circular or elliptical shape in the XY plane.

[0063] The channel opening CHH and the first opening OP1 can be formed simultaneously or during the same process. For example, the channel opening CHH and the first opening OP1 can be formed during a single etching process. The first opening OP1 can be formed simultaneously with the channel opening CHH using an etching process in which openings with high aspect ratios are etched simultaneously. By simultaneously etching openings with high aspect ratios, the cost and time used during the etching process can be reduced. An anisotropic dry etching process can be performed to form the channel opening CHH and the first opening OP1.

[0064] In one embodiment, the channel opening CHH and the first opening OP1 have equal areas in the same XY plane. In another embodiment, the channel opening CHH and the first opening OP1 have different areas in the same XY plane.

[0065] Reference Figure 4C and Figure 4D A first sacrificial pillar SFP1 is formed in the channel opening CHH and the first opening OP1. The first sacrificial pillar SFP1 may fill the channel opening CHH and the first opening OP1. The first sacrificial pillar SFP1 may include a carbon layer. For example, the first sacrificial pillar SFP1 may include a carbon layer, may include a carbon layer and polysilicon, or may include a carbon layer and a metal nitride such as TiN.

[0066] Reference Figure 4E and Figure 4F The first sacrificial pillar SFP1 in the channel opening CHH is removed. A cell plug CPL is formed in the channel opening CHH. The memory layer ML, the channel layer CH, and the gap fill layer GF are sequentially formed along the inner surface of the initial stacked structure pSTK, the inner surface being adjacent to the channel opening CHH.

[0067] Reference Figure 4G and Figure 4H A contact opening CTH is formed in the contact region CTR of the initial stacked structure pSTK. The first sacrificial layer SF1 within the sacrificial layer SF is exposed through the contact opening CTH. The contact opening CTH extends from the first sacrificial layer SF1 along the Z-direction. The upper surface of the first sacrificial layer SF1 is exposed through the contact opening CTH.

[0068] A process including alternating removal of the interlayer insulating layer IIL and the sacrificial layer SF can be performed to form the contact opening CTH. A process including sequential etching of the oxide layer and the nitride layer can be performed such that the contact opening CTH is formed at a specific depth, such as the depth corresponding to the first sacrificial layer SF1. Due to the multiple etching processes, at the same height in the Z direction, the planar area of ​​the contact opening CTH can be larger than the planar area of ​​the channel opening CHH or the first opening OP1.

[0069] The contact opening CTH is spaced apart from the first opening OP1. The first sacrificial pillar SFP1 in the first opening OP1 is not exposed through the contact opening CTH.

[0070] Reference Figure 4I and Figure 4JA portion of the sacrificial layer SF is etched through the contact opening CTH. A recess RC is formed by etching the portion of the side of the sacrificial layer SF exposed through the contact opening CTH. To prevent defects caused by the connection of the conductive layer CD arranged along the Z direction, the sacrificial layer SF exposed through the contact opening CTH includes a recess along the X direction. Figure 4J Compared to the example shown, the upper surface of the first sacrificial layer SF1 can be further etched.

[0071] Reference Figure 4K and Figure 4L A liner LL is formed along the inner surface of the initial laminated structure pSTK, which is adjacent to the contact opening CTH. The liner LL extends along the side surface of the initial laminated structure pSTK adjacent to the contact opening CTH and the upper surface of the first sacrificial layer SF1 adjacent to the contact opening CTH. The liner LL is formed on the side of the initial laminated structure pSTK exposed through the contact opening CTH. The liner LL is conformally formed along the recess RC of the sacrificial layer SF and along the interlayer insulating layer IIL. The liner LL may comprise at least one material comprising TiN, SiCN, or polycrystalline silicon.

[0072] Reference Figure 4M and Figure 4N A second sacrificial pillar SFP2 is formed in the liner LL formed in the contact opening CTH. The second sacrificial pillar SFP2 fills the liner LL formed in the contact opening CTH. The second sacrificial pillar SFP2 is surrounded by the liner LL. The second sacrificial pillar SFP2 is separated from or insulated from the initial laminated structure pSTK by the liner LL. The second sacrificial pillar SFP2 may include at least one of a carbon layer or polysilicon.

[0073] Remove the first sacrificial post SFP1 formed in the first opening OP1. When the first sacrificial post SFP1 is removed, a first opening OP1' is formed at a position substantially the same as the first opening OP1. The first opening OP1' is located around the contact opening CTH.

[0074] Reference Figure 4O and Figure 4P Each of the first openings OP1' is expanded to form a support via SH. A portion of the interlayer insulating layer IIL and the sacrificial layer SF of the initial stacked structure pSTK is removed through the first opening OP1'. The side surfaces of the interlayer insulating layer IIL and the sacrificial layer SF exposed through the first opening OP1' are etched, thereby expanding the first opening OP1'. To increase the volume of the first opening OP1', either a wet etching process or a dry etching process can be performed.

[0075] As the first opening OP1' is expanded, the support holes SH overlap. For example, as the sidewalls of the interlayer insulating layer IIL and the sacrificial layer SF located between the first openings OP1' are gradually etched, the sidewalls between the support holes SH are removed. Each set of support holes SH overlaps and forms a single space. For example, a space is formed by expanding a set of four first openings OP1' extending in the X direction from the liner LL formed in the contact opening CTH. Figure 4O Four groups of support holes SH are shown, each group extending radially from the liner LL formed in the contact opening CTH and spaced 90 degrees apart. The planar shape of a group of overlapping support holes SH can be several overlapping circles or ellipses. The degree to which the first opening OP1' is expanded (e.g., time, etchant concentration, etc.) is controlled such that the support holes SH overlap each other. For example, the degree of expansion of the first opening OP1' is determined such that the first group of support holes SH extending from the liner LL formed in the contact opening CTH in the X direction overlaps, and the first group of support holes SH does not overlap with other groups of support holes SH (such as multiple groups of support holes SH extending from the liner LL formed in the contact opening CTH in the Y direction).

[0076] When the first opening OP1' is expanded, the liner LL can serve as an etch stop layer. The support hole SH does not extend beyond the liner LL into the second sacrificial pillar SFP2 formed in the contact opening CTHL. The side surfaces of the liner LL are exposed through the support hole SH. Figure 4L As shown, the liner LL is formed above the inner surface of the initial laminated structure pSTK adjacent to the contact opening CTH to separate the contact opening CTH from the support hole SH.

[0077] The first opening OP1' is expanded so that the support hole SH exposes the lower surface of the liner LL formed in the contact opening CTH. The support hole SH extends toward the bottom of the liner LL formed in the contact opening CTH. The support hole SH may overlap with a portion of the liner LL formed in the contact opening CTH in the Z direction. The distance between the support hole SH1, which extends from the liner LL in the contact opening CTH in the X direction and contacts the liner LL, and the support hole SH2, which extends from the liner LL in the contact opening CTH in the Y direction and contacts the liner LL, is less than the diameter of the contact opening CTH in the X direction. In order to improve the support structure to be provided in the support hole SH (such as...) Figure 3A and Figure 3B The support structure SS provides support, with the support hole SH extending below the bottom of the liner LL formed in the contact opening CTH. Therefore, a region of the lower surface of the liner LL is exposed through the support hole SH.

[0078] Reference Figure 4Q and Figure 4RA support structure SS is formed in each set of overlapping support holes SH. The support structure SS may include an insulating layer disposed in or filled in the overlapping support holes SH. Each of the support structures SS can be formed by depositing an oxide material in the overlapping support holes SH using a thermal atomic layer deposition (ALD) method.

[0079] Reference Figure 4S and Figure 4T The second sacrificial pillar SFP2 and the liner LL are removed to form a new contact opening at the same location as the contact opening CTH. A spacer layer SPL is formed along the inner surface of the initial laminated structure pSTK, adjacent to the new contact opening CTH. The spacer layer SPL extends along the side surface of the initial laminated structure pSTK adjacent to the new contact opening and the upper surface of the first sacrificial layer SF1 adjacent to the new contact opening. The spacer layer SPL may include an insulating material. For example, the spacer layer SPL may include an oxide layer. A third sacrificial pillar SFP3 is formed in the new contact opening. The third sacrificial pillar SFP3 is separated from the initial laminated structure pSTK by the spacer layer SPL. The third sacrificial pillar SFP3 may include a carbon layer.

[0080] Reference Figure 4U and Figure 4V The sacrificial layer SF of the initial stacked structure pSTK is removed. The sacrificial layer SF can be etched by extending through a slit (not shown) through the initial stacked structure pSTK. As the sacrificial layer SF is removed, empty spaces are formed between adjacent interlayer insulating layers IIL. According to this disclosure, since the support structures SS support the interlayer insulating layers IIL at intervals, the bending of the interlayer insulating layers IIL can be reduced. For example, as the planar area of ​​the contact opening CTH increases, the risk of bending of the interlayer insulating layer IIL located below the contact opening CTH increases. According to an embodiment of this disclosure, because the support structure SS extends below the contact opening CTH, the support effect of the support structure SS can be improved.

[0081] A conductive layer CD is formed in the space created by removing the sacrificial layer SF. The conductive layer CD can fill the space between adjacent interlayer insulating layers IIL. The sacrificial layer SF is replaced with the conductive layer CD. For example, the first sacrificial layer SF1 is replaced with the first conductive layer CD1.

[0082] Reference Figure 4W and Figure 4XThe third sacrificial pillar SFP3, formed in the new contact opening, is removed to form contact opening CTH'. The lower surface of spacer layer SPL is removed to form spacer SPA. Spacer SPA extends along the inner surface of the laminated structure STK adjacent to contact opening CTH'. Because the lower surface of spacer layer SPL is removed, the upper surface of first conductive layer CD1 is exposed through contact opening CTH'. The surface of support structure SS can be exposed through contact opening CTH'.

[0083] Reference Figure 4Y and Figure 4Z A contact CT is formed in the contact opening CTH'. For example, the contact CT can be formed by filling the contact opening CTH' with a conductive material. The contact CT is electrically connected to the first conductive layer CD1.

[0084] Figure 5A and Figure 5B This is a diagram illustrating a memory device 100 including a support structure SS and a support column SP according to an embodiment of the present disclosure. Figure 5A This is a plan view showing the layout of a memory device 100 according to an embodiment of the present disclosure. Figure 5B It shows along Figure 5A The cross section intercepted by line B-B'.

[0085] Figure 5A and Figure 5B Various structures and configurations are similar to Figure 3A and Figure 3B The structure and configuration described and shown in the text.

[0086] Reference Figure 5A and Figure 5B The memory device 100 includes cell plugs (CPLs). The cell plugs (CPLs) are disposed within cell regions (CRs). Each cell plug (CPL) extends through the cell regions (CRs) of the stacked structure (STK). Each cell plug (CPL) includes a memory layer (ML), a channel layer (CH), and a gap fill layer (GF).

[0087] The memory device 100 includes a contact CT and a spacer SPA disposed in a contact region CTR. The contact CT is in contact with a first conductive layer CD1 of the conductive layers CD of the stacked structure STK. The contact CT is electrically connected to the first conductive layer CD1. The spacer SPA insulates the contact CT from the conductive layers CD other than the first conductive layer CD1.

[0088] The memory device 100 includes a support structure SS disposed around a contact member CT. The support structure SS extends through the contact region CTR of the stacked structure STK. The support structure SS contacts the outer surface of the spacer SPA. The support structure SS contacts the lower surface of the contact member CT.

[0089] In one embodiment, three support structures SS are disposed around the contact CT. Each support structure SS includes two or more overlapping support holes SH. Each support structure SS includes an insulating layer disposed in or filled in the overlapping support holes SH. The support structures SS are not limited to... Figure 5A and Figure 5B And related text.

[0090] Compared to examples where four or more support structures SS are arranged around the contact element CT, the distance between the support structures SS is greater in examples with three support structures SS. For example, the three support structures SS are spaced 120 degrees apart, while the four support structures are spaced 90 degrees apart. When the three support structures SS are arranged around the contact element CT, the support columns SP can be placed between adjacent support structures SS. For example, as... Figure 5A As shown, three support columns SP can be set between three support structures SS.

[0091] Support post SP is arranged in the contact area CTR. Support post SP extends along the Z direction within the stacked structure STK. Support post SP extends through the contact area CTR of the stacked structure STK. Support post SP is spaced apart from contact element CT, spacer SPA, and support structure SS. Support post SP and element plug CPL can have equal areas in the same XY plane.

[0092] exist Figure 5A and Figure 5B In the example, the support post SP has a structure similar to the cell plug CPL. The support post SP includes a dummy memory layer DML, a dummy channel layer DCH, and a dummy gap fill layer DGF. The dummy memory layer DML can have a cylindrical shape. The dummy memory layer DML surrounds the dummy channel layer DCH. Although not shown, the dummy memory layer DML includes a dummy barrier layer, a dummy charge trapping layer, and a dummy tunnel insulation layer. The dummy channel layer DCH is formed along the inner wall of the dummy memory layer DML. The dummy gap fill layer DGF fills the dummy channel layer DCH. The dummy gap fill layer DGF can have a cylindrical shape surrounded by the dummy channel layer DCH.

[0093] The dummy barrier layer, dummy charge trapping layer, and dummy tunnel insulating layer included in the dummy memory layer (DML) may each comprise the same material as the barrier layer, charge trapping layer, and tunnel insulating layer included in the memory layer (ML). The dummy channel layer (DCH) may comprise the same material as the channel layer (CH). The dummy gap fill layer (DGF) may comprise the same material as the gap fill layer.

[0094] Figures 6A to 6NThis is a view showing a memory device including a support structure and a support column formed by a method of manufacturing a memory device 100 including a support structure SS and a support column SP according to an embodiment of the present disclosure. Figures 6A to 6N This includes plan views taken from the Z direction of various steps during the method for manufacturing the memory device 100 and corresponding cross-sectional views taken through line B-B' of each plan view.

[0095] Figures 6A to 6N Various structures and configurations are similar to Figures 4A to 4Z The structure and configuration described and shown in the text.

[0096] Reference Figure 6A and Figure 6B This forms a preliminary laminated structure pSTK consisting of alternating layers of sacrificial SF and interlayer insulation IIL. An upper insulation layer UIL is then laminated on top of the interlayer insulation IIL and the sacrificial SF.

[0097] A channel opening CHH, a first opening OP1, and a second opening OP2 are formed extending through the initial stacked structure pSTK. The channel opening CHH extends through the unit region CR of the initial stacked structure pSTK. The first opening OP1 and the second opening OP2 extend through the contact region CTR of the initial stacked structure pSTK. The channel opening CHH, the first opening OP1, and the second opening OP2 can have a circular shape. For example, the channel opening CHH, the first opening OP1, and the second opening OP2 can have a circular or elliptical shape in the XY plane.

[0098] The channel opening CHH, the first opening OP1, and the second opening OP2 can be formed simultaneously or during the same process. For example, the channel opening CHH, the first opening OP1, and the second opening OP2 can be formed during a single etching process. Using an etching process that simultaneously etches openings with high aspect ratios, the first opening OP1 and the second opening OP2 are formed simultaneously with the channel opening CHH. By simultaneously etching openings with high aspect ratios, the cost and time required for the etching process can be reduced. An anisotropic dry etching process can be performed to form the channel opening CHH, the first opening OP1, and the second opening OP2.

[0099] In one embodiment, the channel opening CHH, the first opening OP1, and the second opening OP2 may have equal planar areas. In another embodiment, the channel opening CHH, the first opening OP1, and the second opening OP2 may have different areas in the same XY plane.

[0100] The distance between the second openings OP2 is greater than the distance between the channel openings CHH. The distance between the second openings OP2 is greater than the distance between the adjacent first openings OP1.

[0101] Reference Figure 6C and Figure 6D A first sacrificial pillar SFP1 is formed in the channel opening CHH, the first opening OP1, and the second opening OP2. The first sacrificial pillar SFP1 may fill the channel opening CHH, the first opening OP1, and the second opening OP2. The first sacrificial pillar SFP1 may include a carbon layer. For example, the first sacrificial pillar SFP1 may include a carbon layer and polysilicon, or it may include a carbon layer and a metal nitride such as TiN.

[0102] Reference Figure 6E and Figure 6F Remove the first sacrificial pillar SFP1 from the channel opening CHH. Remove the first sacrificial pillar SFP1 from the second opening OP2. The process of removing the first sacrificial pillar SFP1 from the channel opening CHH and the second opening OP2 can be performed simultaneously. For example, an isotropic wet etching process can be used to etch the first sacrificial pillar SFP1.

[0103] The unit plug CPL and the support post SP can be formed in the channel opening CHH and the second opening OP2, respectively. When the unit plug CPL is formed in the channel opening CHH, the support post SP can be formed simultaneously in the second opening OP2.

[0104] For example, a memory layer ML is formed along the inner surface of the initial stacked structure pSTK adjacent to the channel opening CHH. A dummy memory layer DML is formed along the inner surface of the initial stacked structure pSTK adjacent to the second opening OP2. The dummy memory layer DML may include the same material as the memory layer ML. The dummy memory layer DML and the memory layer ML can be formed simultaneously. For example, after the initial barrier layer, the initial charge trapping layer, and the initial tunnel insulating layer are formed above the initial stacked structure pSTK, a portion of the initial barrier layer, a portion of the initial charge trapping layer, and a portion of the initial tunnel insulating layer on the initial stacked structure pSTK are removed. The remaining initial barrier layer, the remaining initial charge trapping layer, and the remaining initial tunnel insulating layer formed in the channel opening CHH form the memory layer ML. The initial barrier layer, the initial charge trapping layer, and the initial tunnel insulating layer retained in the second opening OP2 form the dummy memory layer DML.

[0105] A channel layer CH is formed in the channel opening CHH. A dummy channel layer DCH is formed in the second opening OP2. The channel layer CH is formed on the inner surface of the memory layer ML, and the dummy channel layer DCH is formed on the inner surface of the dummy memory layer DML. The dummy channel layer DCH may include the same material as the channel layer CH, such as silicon. The dummy channel layer DCH may be formed simultaneously with the formation of the channel layer CH. For example, after forming polysilicon above the initial stacked structure pSTK on which the first opening OP1 and the second opening OP2 are formed, a portion of the polysilicon above the initial stacked structure pSTK may be removed. The polysilicon retained in the channel opening CHH forms the channel layer CH, and the polysilicon retained in the second opening OP2 forms the dummy channel layer DCH.

[0106] A gap fill layer GF is formed within the channel layer, and a dummy gap fill layer DGF is formed within the dummy channel layer DCH. The gap fill layer GF is surrounded by the channel layer CH. The dummy gap fill layer DGF is surrounded by the dummy channel layer DCH. The memory layer ML, the channel layer CH, and the gap fill layer GF form a cell plug CPL. The dummy memory layer DML, the dummy channel layer DCH, and the dummy gap fill layer DGF form a support pillar SP.

[0107] about Figures 6A to 6N The various processes described are similar to those described about Figures 4A to 4Z The described process.

[0108] Reference Figure 6G and Figure 6H A contact opening CTH is formed in the contact region CTR of the initial laminated structure pSTK. The first sacrificial layer SF1 in the sacrificial layer SF is exposed through the contact opening CTH. In the same XY plane, the area of ​​the contact opening CTH is greater than each of the areas of the channel opening CHH, the first opening OP1, and the second opening OP2. The contact opening CTH is spaced apart from the first opening OP1 and the support post SP.

[0109] Reference Figure 6I and Figure 6J The sacrificial layer SF is etched through the contact opening CTH. A liner LL is formed along the inner surface of the initial stacked structure pSTK adjacent to the contact opening CTH. A second sacrificial pillar SFP2 is formed in the liner LL formed in the contact opening CTH. The first sacrificial pillar SFP1 formed in the first opening OP1 is removed. When the first sacrificial pillar SFP1 is removed, the first opening OP1' is formed at a position substantially the same as the first opening OP1.

[0110] Reference Figure 6K and Figure 6LEach first opening OP1' is expanded to form a support via SH. A portion of the interlayer insulating layer IIL and sacrificial layer SF of the initial stacked structure pSTK is removed through the first opening OP1'. Because the first opening OP1' is expanded, the support vias SH overlap. When the first opening OP1' is expanded, the liner LL can be used as an etch stop layer. The first opening OP1' is expanded such that the support via SH exposes the lower surface of the liner LL. The support via SH extends toward the bottom of the liner LL formed in the contact opening CTH.

[0111] Reference Figure 6M and Figure 6N A support structure SS is formed in each set of overlapping support holes SH. The second sacrificial post SFP2 and the liner LL are removed to form a new contact opening, and a spacer layer is formed in the new contact opening, for example, Figure 4S The spacer layer SPL. A third sacrificial pillar is formed in the new contact opening, such as... Figure 4S The third sacrificial pillar, SFP3.

[0112] The sacrificial layer SF of the initial laminated structure pSTK is removed. With the removal of the sacrificial layer SF, empty spaces are formed between adjacent interlayer insulation layers IIL. According to this disclosure, since the support structure SS and support columns SP are arranged at intervals to support the interlayer insulation layers IIL, the bending of the interlayer insulation layers IIL can be reduced.

[0113] The conductive layer CD is formed in the space created by removing the sacrificial layer SF. For example, the first sacrificial layer SF1 is replaced with the first conductive layer CD1.

[0114] The third sacrificial pillar SFP3 is removed from the new contact opening to form contact opening CTH', and the lower surface of spacer layer SPL is removed. Contact CT, surrounded by spacer SPA, is formed in contact opening CTH'. Contact CT is electrically connected to the first conductive layer CD1.

[0115] Figures 7A to 7F This is a diagram illustrating various support structures SS according to embodiments of the present disclosure.

[0116] Figure 7A and Figure 7C It shows things like Figure 3A The diagram shows various support structures SS when four support structures SS are arranged around the contact CT. Figure 7B and Figure 7D It shows things like Figure 5A The diagram shows various support structures SS when the three support structures SS are arranged around the contact CT. Figure 7E Various support structures SS in which the four support holes SH used to form the support structure SS overlap in different ways are shown. Figure 7FAn embodiment in which the four support holes SH used to form the support structure SS are arranged in an adjacent overlapping manner is shown.

[0117] Reference Figure 7A and Figure 7B Each of the support structures SS is formed using two overlapping support holes SH on a line extending radially from the contact element CT. The two support holes SH forming each support structure SS overlap radially or in a direction extending from the center of the contact element CT. For example, the two overlapping support holes SH form a single space. The support holes SH can be formed by expanding the first opening (e.g., Figure 4A and Figure 6A The first opening OP1 in the structure is used to form the structure. Part of the stacked structure STK may not remain between the two support holes SH.

[0118] Support holes SH are arranged in a direction away from the contact element CT. Two overlapping support holes SH are arranged in a line. For example, two support holes SH extending from the contact element CT in the X direction are arranged in the X direction. Two support holes SH extending from the contact element CT in the Y direction are arranged in the Y direction.

[0119] Reference Figure 7C and Figure 7D Each of the support structures SS is formed using three overlapping support holes SH. The three support holes SH forming each support structure SS overlap each other. For example, there can be a common area between two of the three support holes SH. There can be a common area between all three support holes SH.

[0120] exist Figure 7C and Figure 7D In the example, the centers of the support holes SH form the vertices of a triangle. The centers of the three overlapping support holes SH can be arranged such that one support hole SH is adjacent to the contact CT and the other two support holes SH are disposed away from the contact CT, such that one vertex is closer to the contact CT than the other two vertices disposed further away from the contact CT, forming a triangle shape. In one embodiment, the centers of the three overlapping support holes SH can be arranged such that two support holes SH are adjacent to the contact CT and the third support hole SH is disposed away from the contact CT, such that two vertices are closer to the contact CT and one vertex is further away from the contact CT, forming a triangle shape.

[0121] Figure 7C and Figure 7D The descriptions herein are illustrative and this disclosure is not limited to these examples. In one example, two of the three support holes SH used to form each support structure SS overlap, while in another example, two of the three support holes SH do not overlap. Each support structure SS may be formed using three overlapping support holes SH arranged in a row or column.

[0122] Figure 7E The diagram shows various overlap amounts between the support holes SH used to form the support structure SS when the four support holes SH overlap.

[0123] exist Figure 7E In the implementation of the method, such as Figure 3A and Figure 5A As shown, a support structure SS is formed using four overlapping support holes SH. In this example, a common area may exist between any two adjacent support holes SH. In this example, a common area exists between any three support holes SH. In this example, a common area exists between all four support holes SH.

[0124] exist Figure 7E In this implementation, a support structure SS' is formed using four partially overlapping support holes SH. For example, there is a common area between any two adjacent support holes SH. There is a common area between some, but not all, combinations of the three support holes SH, and in this example, there is no common area between all four support holes.

[0125] exist Figure 7E In this implementation, a support structure SS is formed using four partially overlapping support holes SH. For example, although any two adjacent support holes SH overlap, two opposing support holes SH do not overlap. In this example, there is no common area between any combination of three support holes SH. In this example, there is no common area between all four support holes SH, and a portion of the stacked structure STK can be retained between the four support holes SH.

[0126] Figure 7F Another arrangement is shown, utilizing four overlapping support holes SH to form the support structure SS. (Refer to...) Figure 7F The support holes SH are arranged around the contact element CT. The support holes SH are arranged in an arc shape adjacent to the contact element CT, and only adjacent or adjacent support holes SH overlap. Any number or arrangement of overlapping support holes SH can be used to form the support structure SS.

[0127] Figure 8 This is a diagram illustrating a memory card system 3000 including a memory device according to an embodiment of the present disclosure.

[0128] Reference Figure 8 The memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0129] Controller 3100 is coupled to memory device 3200. Controller 3100 is configured to access memory device 3200. For example, controller 3100 is configured to control programming operations, read operations, erase operations, and background operations of memory device 3200. Controller 3100 is configured to provide an interface between memory device 3200 and a host. Controller 3100 may be configured to drive firmware controlling memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0130] Controller 3100 communicates with external devices via connector 3300. Controller 3100 communicates with external devices (e.g., a host) according to a specific communication protocol. For example, controller 3100 can be configured to communicate with external devices via at least one of the following communication protocols: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 3300 can be configured according to at least one of these communication protocols.

[0131] Memory device 3200 includes, for example, with Figure 1 , Figure 3A , Figure 5A The memory device 100 shown is configured in the same manner and utilizes the reference. Figures 4A to 4Z or Figures 6A to 6N The described method is a method for manufacturing a memory device that forms multiple memory cells.

[0132] The controller 3100 and memory device 3200 are integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and memory device 3200 can be integrated into a single semiconductor device to form a memory card, such as a personal computer (PC) card in the form of a PCMCIA card, a compact flash memory (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro or eMMC), a secure digital card (SD) card (SD, miniSD, microSD or SDHC), and a universal flash memory (UFS).

[0133] Figure 9This is a diagram illustrating a solid-state drive (SSD) system 4000 including a memory device according to an embodiment of the present disclosure.

[0134] Reference Figure 9 The SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 through a signal connector 4001 and receives power through a power connector 4002. The SSD 4200 includes a controller 4210, multiple memory devices 4221 to 422n, an auxiliary power supply 4230, and a cache memory 4240.

[0135] The controller 4210 controls a plurality of memory devices 4221 to 422n in response to signals received from the host 4100. For example, the signals may be based on the interface between the host 4100 and the SSD 4200. For example, the signals may be configured or constructed according to at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe interface.

[0136] Each of the plurality of memory devices 4221 to 422n includes a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n is connected to... Figure 1 , Figure 3A , Figure 5A The memory device 100 shown is configured in the same manner and utilizes the reference. Figures 4A to 4Z or Figures 6A to 6N The described method is used to manufacture a memory device. Multiple memory devices 4221 to 422n communicate with a controller 4210 via channels CH1 to CHn.

[0137] Auxiliary power supply 4230 is connected to host 4100 via power connector 4002. Auxiliary power supply 4230 receives power from host 4100 and uses that power to charge the SSD. When the power supply from host 4100 is unstable, auxiliary power supply 4230 provides power to SSD 4200. For example, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be located on the motherboard and can provide auxiliary power to SSD 4200.

[0138] Buffer memory 4240 is a buffer memory for SSD 4200. For example, buffer memory 4240 stores data received from host 4100 or data received from multiple memory devices 4221 to 422n, or it may store metadata (e.g., a mapping table) of memory devices 4221 to 422n. Buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0139] According to embodiments of the present disclosure, the support effect of the support structure of the memory device can be enhanced, and the manufacturing process can be simplified by improving the manufacturing process and structure of the support structure.

[0140] The concepts have been disclosed in conjunction with examples and embodiments. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions are possible without departing from the scope and technical concepts of this disclosure. The embodiments disclosed in this specification should be considered from an illustrative rather than a restrictive perspective. Therefore, the scope of this disclosure is not limited to these descriptions. All variations within the meaning of the claims and their equivalents are included within its scope.

[0141] Cross-references to related applications

[0142] This application claims priority to Korean Patent Application No. 10-2024-0176522, filed with the Korean Intellectual Property Office on December 2, 2024, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: Contact elements; as well as Multiple support structures are disposed around the contact element; Each of the plurality of support structures is formed in a plurality of overlapping holes.

2. The memory device according to claim 1, wherein, Each of the plurality of support structures includes an insulating layer disposed in the overlapping holes.

3. The memory device according to claim 1, wherein, Each of the plurality of support structures is formed using two overlapping holes, and The two overlapping holes extend in a direction away from the contact element.

4. The memory device according to claim 1, wherein, Each of the plurality of support structures is formed using three overlapping holes, and The centers of the three overlapping holes form the vertices of a triangle.

5. The memory device according to claim 1, wherein, Each of the plurality of support structures is formed using four overlapping holes, and at least two of the four overlapping holes include a common area. The centers of the four overlapping holes are arranged to form the vertices of a quadrilateral.

6. The memory device according to claim 1, wherein, Each of the plurality of support structures is formed using four overlapping holes, and at least two of the four overlapping holes include a common area. The four overlapping holes are arranged to surround the contact element.

7. The memory device of claim 1, further comprising a stacked structure including a plurality of interlayer insulating layers and a plurality of conductive layers alternately stacked along a first direction. in, The contact extends from the first conductive layer of the plurality of conductive layers along the first direction, and The plurality of support structures extend through the stacked structure along the first direction.

8. The memory device according to claim 7, wherein, The first conductive layer is in contact with the lower surface of the contact element.

9. The memory device of claim 7, further comprising a spacer surrounding a side surface of the contact. in, The spacer separates the contact from the conductive layers other than the first conductive layer among the plurality of conductive layers.

10. The memory device according to claim 9, wherein, The plurality of support structures are in contact with the outer surface of the spacer and the lower surface of the contact member.

11. The memory device according to claim 1, wherein, Four or more support structures are arranged around the contact element.

12. The memory device according to claim 1, wherein, Three support structures are disposed around the contact, and the memory device further includes a plurality of support pillars, each of which is disposed between adjacent support structures of the plurality of support structures.

13. The memory device of claim 12, further comprising: A stacked structure comprising a plurality of interlayer insulating layers and a plurality of conductive layers alternately stacked along a first direction; as well as Multiple unit plugs extending through the stacked structure along the first direction. The plurality of support columns include a dummy material layer corresponding to the material layer included in the unit plug.

14. The memory device according to claim 13, wherein, Each of the unit plugs includes a memory layer, a channel layer, and a gap-filling layer, and Each of the support columns includes a dummy memory layer corresponding to the memory layer, a dummy channel layer corresponding to the channel layer, and a dummy gap filling layer corresponding to the gap filling layer.

15. The memory device according to claim 12, wherein, Each of the plurality of support columns is spaced apart from the contact element and the plurality of support structures.

16. A method of manufacturing a memory device, the method comprising the steps of: A laminated structure is formed, the laminated structure comprising a plurality of interlayer insulating layers and a plurality of sacrificial layers alternately stacked in a first direction; A contact opening is formed extending from the first sacrificial layer among the plurality of sacrificial layers along the first direction; Forming a plurality of first openings extending through the stacked structure and surrounding the contact opening; Expand the plurality of first openings to form a plurality of overlapping holes; as well as The support structure is formed by providing an insulating layer within the plurality of overlapping holes.

17. The method of claim 16, further comprising forming a plurality of channel openings extending through the stacked structure while forming the plurality of first openings.

18. The method of claim 17, further comprising the step of: A first sacrificial pillar is formed within each of the plurality of first openings; as well as A unit plug is formed in each of the plurality of channel openings.

19. The method of claim 17, further comprising forming a plurality of second openings extending through the stacked structure while forming the plurality of first openings.

20. The method of claim 19, further comprising the step of: A first sacrificial column is formed in each of the plurality of first openings; A unit plug is formed in each of the plurality of channel openings; as well as A support column is formed in each of the plurality of second openings.

21. The method according to claim 16, wherein, The contact opening is formed to be spaced apart from the plurality of first openings.

22. The method of claim 16, further comprising the step of: Etch the side surface of each of the plurality of sacrificial layers exposed through the contact opening to form a recess; A liner is formed extending along the inner surface of the laminated structure adjacent to the contact opening; as well as A second sacrificial column is formed within the contact opening.

23. The method according to claim 22, wherein, When the plurality of first openings are expanded, the liner serves as an etch stop layer.

24. The method according to claim 22, wherein, The side and bottom surfaces of the liner are exposed through the overlapping holes.

25. The method according to claim 22, further comprising the following steps: Remove the second sacrificial column and the liner to form a new contact opening; A spacer is formed on the inner surface of the stacked structure adjacent to the new contact opening; as well as A contact element is formed in the new contact opening.

26. The method of claim 25, wherein, The steps of forming the spacer include the following: Forming a spacer layer extending along the inner surface of the laminated structure adjacent to the new contact opening; and The lower surface of the spacer layer is removed to form the spacer.

27. The method of claim 26, further comprising the following steps: A third sacrificial pillar is formed within the spacer layer; The plurality of sacrificial layers of the stacked structure are replaced with a plurality of conductive layers; as well as Remove the third sacrificial column.

28. A memory device, the memory device comprising: Contact elements; as well as A plurality of support structures are disposed around the contact member, wherein each of the support structures includes a plurality of continuous members, wherein the distance between the centers of adjacent continuous members is less than the width of one of the adjacent continuous members.

29. The memory device according to claim 28, wherein, The continuous component includes an insulating layer.

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