Ferroelectric thin-film capacitors and their fabrication methods, ferroelectric memory and electronic devices

Abstract

This application provides a ferroelectric thin-film capacitor and its fabrication method, a ferroelectric memory, and an electronic device. Each ferroelectric thin-film capacitor in the ferroelectric memory includes two electrode layers and a ferroelectric layer, with the ferroelectric layer located between the two electrode layers. The ferroelectric layer comprises hafnium dioxide material and includes at least one first doped region, in which a first doping element is doped. The atomic radius of the first doping element is smaller than the atomic radius of the hafnium element in the ferroelectric layer. The ferroelectric memory of this application can achieve higher crystallization quality under low-temperature rapid thermal crystallization conditions, thereby reducing operating voltage and power consumption, and improving storage reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a ferroelectric thin-film capacitor, a method for preparing a ferroelectric thin-film capacitor, a ferroelectric memory, and an electronic device. Background Technology

[0002] Non-volatile memory technologies face challenges in miniaturization and incompatibility with logic processes as they evolve towards smaller process nodes. Ferroelectric random access memory (FeRAM), however, utilizes the unique non-volatile electrical properties of ferroelectric materials for data storage. Its non-volatile data storage and high access speed offer new opportunities to overcome size limitations. Ferroelectric memory typically uses a ferroelectric thin-film capacitor between two electrode layers to store data, forming a "sandwich" structure of "electrode layer-ferroelectric layer-electrode layer". In this structure, the ferroelectric phase in the ferroelectric layer is generated by the significant difference in thermal expansion coefficients between the electrode layer and the ferroelectric thin-film capacitor, providing lattice stress during annealing to produce the ferroelectric phase.

[0003] The stress provided solely by the interface between the electrode layer and the ferroelectric thin-film capacitor is extremely limited, thus requiring a higher rapid thermal annealing (RTA) temperature to induce a higher content of the ferroelectric phase. However, integrated circuit processes demand a lower thermal budget for thin-film fabrication. Therefore, under lower thermal budget crystallization conditions, how to improve the ferroelectric crystallization level, reduce the operating voltage, increase the ferroelectric storage window, and enhance the high-temperature retention and cycling durability of ferroelectric memory devices are pressing problems that need to be solved in existing ferroelectric memory systems. Summary of the Invention

[0004] This application provides a ferroelectric thin-film capacitor, a method for fabricating a ferroelectric thin-film capacitor, a ferroelectric memory, and an electronic device. The ferroelectric memory of this application achieves higher ferroelectric polarization with a lower thermal budget by specifically optimizing the internal material and structure of the ferroelectric thin-film capacitor. This means it can achieve higher crystallization quality under low-temperature rapid thermal processing crystallization conditions, thereby reducing operating voltage and power consumption, and improving storage reliability. Specifically, this application includes the following technical solutions:

[0005] In a first aspect, this application provides a ferroelectric memory, which includes a plurality of memory cells. Each memory cell includes at least one transistor and at least one ferroelectric thin-film capacitor. The at least one transistor is used to control the storage or release of charge in the at least one ferroelectric thin-film capacitor. Each ferroelectric thin-film capacitor includes two electrode layers and a ferroelectric layer. The ferroelectric layer is located between the two electrode layers. The ferroelectric layer includes hafnium dioxide material and at least one first doped region. The at least one first doped region is doped with a first doping element, wherein the atomic radius of the first doping element is smaller than the atomic radius of the hafnium element in the ferroelectric layer.

[0006] The ferroelectric thin-film capacitor in this application's ferroelectric memory introduces a first dopant element into the first doping region. Since the atomic radius of the first dopant element is smaller than that of hafnium in the ferroelectric layer, the first dopant element, after forming a diffusion bond with oxygen, can further induce lattice distortion within the ferroelectric layer, thereby generating tensile stress within the ferroelectric layer. That is, by doping the ferroelectric layer with a first dopant element whose atomic radius is smaller than that of hafnium in the hafnium dioxide material of the ferroelectric layer, the ferroelectric phase formation energy can be reduced, thus achieving higher ferroelectric polarization under lower thermal budget conditions. Simultaneously, by doping the ferroelectric layer with a first dopant element, oxygen can be provided to the hafnium dioxide material in the ferroelectric layer, thereby reducing the oxygen vacancy content and further improving the crystallization quality of the ferroelectric phase. Furthermore, the first doping region can be understood as the region in the hafnium dioxide material of the ferroelectric layer doped with the first dopant element, and the planar structural shape of the first doping region is the same as the planar structural shape of the ferroelectric layer.

[0007] This application's ferroelectric memory achieves the effect of multi-doping by introducing a first doping element into the ferroelectric thin film capacitor. This enables precise control of the internal stress and charged defects of oxygen vacancies in the ferroelectric thin film capacitor, thereby reducing the thermal budget for ferroelectric thin film crystallization and achieving higher crystallization quality under low-temperature rapid thermal treatment crystallization conditions. Consequently, it can reduce operating voltage and power consumption, and improve storage reliability.

[0008] In one implementation, along the direction of the stacking of the two electrode layers, the distance between at least one first doped region and any electrode layer is greater than or equal to 0.3 nm.

[0009] In this implementation, in the direction of the two electrode layers being stacked, by setting the distance between the first doped region and any electrode layer to be greater than or equal to 0.3 nm, the doped region of the first doped element is located near the middle of the ferroelectric layer, thereby further improving the crystallization level inside the ferroelectric layer.

[0010] In one implementation, the atomic radius R1 of the first dopant element satisfies the condition: R1≥0.1R2, where R2 is the atomic radius of hafnium.

[0011] In this implementation, by limiting the atomic radius R1 of the first dopant element to be smaller than the atomic radius R2 of the hafnium element, and the atomic radius R1 of the first dopant element to be greater than or equal to 10% of the atomic radius R2 of the hafnium element, the bonding effect between the first dopant element and the oxygen element in the hafnium dioxide material is improved and the crystalline stress is generated, while the bonding effect between the first dopant element and the oxygen element is also guaranteed, thereby further improving the crystallization quality of the ferroelectric layer under the low-temperature rapid thermal treatment crystallization conditions.

[0012] In one implementation, the first doping element includes at least one of niobium, tantalum, or molybdenum.

[0013] In this implementation, by setting the first doping element to include at least one of niobium (Nb), tantalum (Ta), or molybdenum (Mo), the first doping element in the first doping region of the ferroelectric layer can occupy lattice sites, interstitial spaces, and defects in the hafnium dioxide base, further inducing lattice distortion and generating glacial stress within the ferroelectric layer. Simultaneously, variable-valence elements such as niobium, tantalum, or molybdenum can also provide oxygen to the ferroelectric layer of the hafnium dioxide-based material, further reducing oxygen vacancy content and increasing the proportion of the ferroelectric phase.

[0014] In one implementation, along the direction of the stacking of the two electrode layers, the width of each first doped region in at least one first doped region is greater than or equal to 0.1 nm and less than or equal to 2 nm.

[0015] In this implementation, by setting the width of the first doped region to be greater than or equal to 0.1 nm and less than or equal to 2 nm, the bonding range between the first doped element and the oxygen element in the hafnium dioxide material in the ferroelectric layer can be guaranteed. This ensures that the first doped element generates sufficient glacial stress in the ferroelectric layer, which can further enhance the ferroelectric polarization inside the ferroelectric layer with a lower thermal budget.

[0016] In one implementation, the number of first doped regions is one, and along the stacking direction of the two electrode layers, the first doped region is located on either side of the centerline of the ferroelectric layer.

[0017] In this implementation, by doping a first doping element on either side of the center line of the ferroelectric layer along the stacking direction of the two electrode layers, i.e., the first doping region is arranged on one side of the ferroelectric layer, the data read / write capability of the ferroelectric memory can be adjusted to be more biased towards 0 or more biased towards 1.

[0018] In one implementation, at least one first doped region includes two first doped regions, wherein, along the stacking direction of the two electrode layers, both first doped regions are located on the same side of the centerline of the ferroelectric layer.

[0019] In one implementation, at least one first doped region includes two first doped regions, wherein the two first doped regions are symmetrically arranged about the centerline of the ferroelectric layer along the stacking direction of the two electrode layers.

[0020] In this implementation, along the direction of the stacking of the two electrode layers, by doping the two sides of the ferroelectric layer with first doping elements respectively, and the two first doping regions formed by the first doping elements on both sides of the center line of the ferroelectric layer are symmetrically arranged, so that the data storage capabilities of the ferroelectric memory are close.

[0021] In one implementation, the two first doped regions are located on the same side of the centerline of the ferroelectric layer, the distance between the two first doped regions is greater than or equal to 0.5 nm and less than or equal to 5 nm, the two first doped regions are symmetrically arranged about the centerline of the ferroelectric layer, and the distance between the two first doped regions is greater than or equal to 3 nm and less than or equal to 20 nm.

[0022] In this implementation, along the stacking direction of the two electrode layers, when the two first doped regions are located on the same side of the center line of the ferroelectric layer, the distance between the two first doped regions is limited to be greater than or equal to 0.5 nm and less than or equal to 5 nm. Alternatively, when the two first doped regions are symmetrically arranged about the center line of the ferroelectric layer, the distance between the two first doped regions is limited to be greater than or equal to 3 nm and less than or equal to 20 nm. This enables fine adjustment of the data read / write capability of the ferroelectric memory, allowing the data read / write capability of the ferroelectric memory to be adjusted according to different usage requirements or application scenarios, thereby increasing the applicability and application scenarios of the ferroelectric memory.

[0023] In one implementation, the ferroelectric layer includes at least two second doped regions, each doped with a second doping element, wherein the electronegativity of the second doping element is greater than that of hafnium. Along the stacking direction of the two electrode layers, the at least two second doped regions are spaced apart from each other, and at least one second doped region is provided between each electrode layer and the first doped region.

[0024] In this implementation, by doping the hafnium dioxide material in the ferroelectric layer with a second dopant element, and setting the electronegativity of the second dopant element to be greater than (higher than) that of the hafnium element in the hafnium dioxide material, the second dopant element pins the oxygen vacancies in the ferroelectric layer. This prevents the oxygen vacancies in the ferroelectric layer from diffusing towards the electrode layer and forming an interface dead layer, thus avoiding the adverse effects of fatigue, imprinting effect, and breakdown on the storage reliability of the ferroelectric memory. Simultaneously, by doping the second dopant element along the stacking direction of the two electrode layers, a second dopant element is provided on the side of each first doped region near the electrode layer. This pins the oxygen vacancies in the ferroelectric layer near the electrode layer, preventing the formation of interface dead layers on both sides of the ferroelectric layer. This further reduces the crystallization heat budget while improving the crystallization quality within the ferroelectric layer, thereby enhancing the reliability of the ferroelectric memory.

[0025] In one implementation, the second doping element includes at least one of scandium, titanium, vanadium, chromium, or manganese.

[0026] In this implementation, by setting the first doping element to include at least one of scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), or manganese (Mn), the second doping element in the second doped region of the ferroelectric layer can occupy the lattice sites, interstices, and defects of the hafnium dioxide base. This allows the ferroelectric layer to adsorb and pin oxygen vacancies during heat treatment, preventing oxygen vacancies in the ferroelectric layer from diffusing towards the two electrode layers and potentially causing an undesirable interface dead layer.

[0027] In one implementation, two second doped regions are symmetrically arranged about the centerline of the ferroelectric thin film capacitor along the stacking direction of the two electrode layers, and the distance between each second doped region and its adjacent electrode layer is greater than or equal to 0.3 nm and less than or equal to 4 nm.

[0028] In this implementation, by doping each side of the ferroelectric layer near the electrode layer with a second dopant element, the second dopant element adsorbs and pins oxygen vacancies on each side of the ferroelectric layer near the electrode layer, further reducing the charge defects of oxygen vacancies in the ferroelectric layer and thus further improving the reliability of the ferroelectric memory. Simultaneously, by setting the distance between the second doped region formed by the second dopant element and an adjacent electrode layer to be greater than or equal to 0.3 nm and less than or equal to 4 nm, the doping position and range of the second dopant element can be limited, thereby achieving fine control over the charge defects of oxygen vacancies in the ferroelectric layer, while ensuring that the second dopant element effectively dops and pins oxygen vacancies in the ferroelectric layer.

[0029] In one implementation, the distance between each second doped region and an adjacent first doped region is greater than or equal to 0.2 nm and less than or equal to 3 nm.

[0030] In one implementation, the ferroelectric thin-film capacitor further includes at least one interface layer, each interface layer being inserted between an electrode layer and a ferroelectric layer, wherein the material of the at least one interface layer includes at least one of titanium dioxide, niobium pentoxide, or tantalum pentoxide.

[0031] In this implementation, an interface layer is inserted between the ferroelectric layer and an adjacent electrode layer. The lattice constant of the interface layer is different from that of the ferroelectric layer, which can further generate interface stress near the electrode layer in the ferroelectric layer. The mismatch dislocations generated in the ferroelectric layer near the electrode layer can induce lattice symmetry breaking, which is conducive to the formation of the ferroelectric phase in the ferroelectric layer, improves the ferroelectric crystallization quality, reduces the crystallization preheating calculation, and improves the ferroelectric polarization and reliability.

[0032] In one implementation, the hafnium dioxide material with the ferroelectric layer is further doped with at least one of zirconium, lanthanum, silicon, cerium, gadolinium, yttrium, aluminum, or strontium, wherein the atomic radius of the first dopant element is smaller than the atomic radius of at least one of zirconium, lanthanum, silicon, cerium, gadolinium, yttrium, aluminum, or strontium in the hafnium dioxide material.

[0033] In this implementation, by setting the hafnium dioxide material of the ferroelectric layer to be doped with various elements, it is possible to achieve fine control of the ferroelectric layer material, so that the ferroelectric memory can meet different usage requirements or application scenarios, and expand the applicability and application scenarios of the ferroelectric memory.

[0034] Secondly, this application provides an electronic device, which includes a circuit board and a ferroelectric memory as provided in any of the above implementations, wherein the ferroelectric memory is disposed on the circuit board and electrically connected to the circuit board.

[0035] The electronic device of this application, by incorporating a ferroelectric memory, is capable of data transmission. Furthermore, because the electronic device of this application incorporates the ferroelectric memory of any of the above-described implementations, it possesses all the beneficial effects that the ferroelectric memory provided in any of the above-described implementations may have.

[0036] Thirdly, this application provides a ferroelectric thin-film capacitor, which includes two electrode layers and a ferroelectric layer. The ferroelectric layer is located between the two electrode layers. The ferroelectric layer includes a hafnium dioxide material and includes at least one first doped region. The at least one first doped region is doped with a first doping element, wherein the atomic radius of the first doping element is smaller than the atomic radius of the hafnium element in the ferroelectric layer.

[0037] This application's ferroelectric thin-film capacitor incorporates a second dopant element within the hafnium dioxide material of the ferroelectric layer. The second dopant element has a higher electronegativity than the hafnium element in the hafnium dioxide material, pinning oxygen vacancies in the ferroelectric layer. This prevents oxygen vacancies from diffusing towards the electrode layer and forming an interfacial dead layer, thus avoiding fatigue, imprinting effects, and breakdown that negatively impact the reliability of the ferroelectric memory. By doping the first and second dopant elements at different locations within the ferroelectric layer, a multi-doping effect is achieved, enabling precise control of internal stress and oxygen vacancy charging defects. This reduces the ferroelectric thin-film crystallization heat budget and achieves higher crystallization quality under low-temperature rapid thermal processing, thereby lowering operating voltage and power consumption and improving memory reliability.

[0038] In one implementation, the ferroelectric layer includes at least two second doped regions, each doped with a second doping element, wherein the electronegativity of the second doping element is greater than that of hafnium. Along the stacking direction of the two electrode layers, the at least two second doped regions are spaced apart from each other, and at least one second doped region is provided between each electrode layer and the first doped region.

[0039] In this implementation, the ferroelectric thin film capacitor is doped by introducing a first doping element into the first doping region. Since the atomic radius of the first doping element is smaller than that of the hafnium element in the ferroelectric layer, the first doping element can further induce lattice distortion inside the ferroelectric layer after forming a diffusion bond with the oxygen element, so as to generate tensile stress inside the ferroelectric layer.

[0040] Fourthly, this application provides a method for preparing a ferroelectric thin-film capacitor, comprising:

[0041] An electrode layer is prepared and a first ferroelectron layer is prepared on the surface of the electrode layer;

[0042] A first ferroelectric doped layer and a second ferroelectric layer are prepared by cycling on the surface of the first ferroelectric layer. The first ferroelectric doped layer and the second ferroelectric layer are cycled at least once. The first ferroelectric layer, the first ferroelectric doped layer and the second ferroelectric layer both include hafnium dioxide material. The hafnium dioxide material in the first ferroelectric doped layer is doped with a first doping element to form a first doped region. The atomic radius of the first doping element is smaller than the atomic radius of the hafnium element in the hafnium dioxide material.

[0043] Another electrode layer is prepared on the surface of the second ferroelectronic layer, which has the largest spacing from an electrode layer.

[0044] One implementation method is that the thin film deposition process includes any one of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0045] One implementation involves cyclically preparing a first ferroelectric doped layer and a second ferroelectric layer on the surface of the first ferroelectric layer, wherein the number of cycles for the first ferroelectric doped layer and the second ferroelectric layer is at least one, comprising:

[0046] A second ferroelectric doped layer and a third ferroelectric doped layer are sequentially prepared on the surface of the first ferroelectric layer. Both the second ferroelectric doped layer and the third ferroelectric doped layer include hafnium dioxide material. The hafnium dioxide material in the second ferroelectric doped layer is doped with a second doping element to form a second doped region. The electronegativity of the second doping element is greater than that of the hafnium element in the hafnium dioxide material.

[0047] A first ferroelectric doped layer and a second ferroelectric doped layer are prepared by cycling on the surface of the third ferroelectric layer, and the number of cycles for the first ferroelectric doped layer and the second ferroelectric doped layer is at least one.

[0048] A second ferroelectric doped layer is prepared on the surface of the second ferroelectronic layer with the largest distance from an electrode layer, and then another second ferroelectronic layer is prepared. Attached Figure Description

[0049] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0050] Figure 1 This is a structural block diagram of the electronic device provided in the embodiments of this application;

[0051] Figure 2 This is a structural block diagram of the ferroelectric memory provided in the embodiments of this application;

[0052] Figure 3 This is a structural block diagram of a storage cell in a ferroelectric memory provided in an embodiment of this application;

[0053] Figure 4 This is a circuit structure diagram of a storage cell in a ferroelectric memory provided in an embodiment of this application;

[0054] Figure 5 This is a schematic diagram of the ferroelectric thin-film capacitor of the ferroelectric memory provided in the embodiments of this application;

[0055] Figure 6 This is a schematic cross-sectional view of the ferroelectric thin-film capacitor provided in an embodiment of this application;

[0056] Figure 7 This is a schematic cross-sectional view of the ferroelectric thin-film capacitor provided in an embodiment of this application;

[0057] Figure 8 This is a schematic cross-sectional view of the ferroelectric thin-film capacitor provided in an embodiment of this application;

[0058] Figure 9 This is a schematic cross-sectional view of the ferroelectric thin-film capacitor provided in an embodiment of this application;

[0059] Figure 10 This is a schematic cross-sectional view of the ferroelectric thin-film capacitor provided in an embodiment of this application;

[0060] Figure 11 This is a schematic diagram of the workflow of the ferroelectric thin film capacitor fabrication method provided in the embodiments of this application;

[0061] Figure 12 This is a schematic diagram of the structure in the ferroelectric thin film capacitor fabrication method provided in the embodiments of this application;

[0062] Figure 13 This is a schematic diagram illustrating the workflow of preparing the first ferroelectric doped layer and the second ferroelectronic layer using the ferroelectric thin film capacitor preparation method provided in the embodiments of this application. Detailed Implementation

[0063] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are merely some, and not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection claimed in this application.

[0064] This application provides a ferroelectric memory comprising multiple memory cells, each memory cell including at least one transistor and at least one ferroelectric thin-film capacitor. The at least one transistor is used to control the storage or release of charge in the at least one ferroelectric thin-film capacitor. Each ferroelectric thin-film capacitor includes two electrode layers and a ferroelectric layer, with the ferroelectric layer located between the two electrode layers. The ferroelectric layer comprises hafnium dioxide material, in which a first doping element is doped. The first doping element forms at least one first doped region in the ferroelectric layer, wherein the atomic radius of the first doping element is smaller than the atomic radius of the hafnium element in the ferroelectric layer. Along the stacking direction of the two electrode layers, the distance between the at least one first doped region and any electrode layer is greater than or equal to 0.3 nm. This application's ferroelectric memory achieves higher ferroelectric polarization with a lower thermal budget by specifically optimizing the internal material and structure of the ferroelectric thin-film capacitor, i.e., achieving higher crystallization quality under low-temperature rapid thermal processing crystallization conditions, thereby reducing operating voltage and power consumption and improving storage reliability.

[0065] This application also provides an electronic device, which includes a circuit board and the ferroelectric memory provided in the above-described implementation. The ferroelectric memory is disposed on the circuit board and electrically connected to the circuit board. By incorporating the ferroelectric memory, the electronic device of this application can improve its operating performance and lifespan.

[0066] This application provides a ferroelectric thin-film capacitor, which includes two electrode layers and a ferroelectric layer located between the two electrode layers. The ferroelectric layer includes a hafnium dioxide material, in which a first doping element and a second doping element are doped. The first doping element forms two first doped regions in the ferroelectric layer, and the second doping element forms two second doped regions in the ferroelectric layer. The atomic radius of the first doping element is smaller than that of the hafnium element in the hafnium dioxide material, and the electronegativity of the second doping element is greater than that of the hafnium element in the hafnium dioxide material. Along the stacking direction of the two electrode layers, the two first doped regions and the two second doped regions are arranged alternately, with each second doped region located between an electrode layer and a first doped region. The distance between each second doped region and its adjacent electrode layer is greater than or equal to 0.3 nm.

[0067] This application provides a method for fabricating a ferroelectric thin-film capacitor, comprising: fabricating an electrode layer and fabricating a first ferroelectron layer on the surface of the electrode layer; cyclically fabricating a first ferroelectric doped layer and a second ferroelectron layer on the surface of the first ferroelectron layer, wherein the first ferroelectric doped layer and the second ferroelectron layer are cyclically fabricated at least once, wherein the first ferroelectron layer, the first ferroelectric doped layer, and the second ferroelectron layer all comprise hafnium dioxide material, the hafnium dioxide material in the first ferroelectric doped layer is doped with a first doping element to form a first doped region, the atomic radius of the first doping element being smaller than the atomic radius of the hafnium element in the hafnium dioxide material; and fabricating another electrode layer on the surface of the second ferroelectron layer, which has the largest distance from the first electrode layer. The ferroelectric thin-film capacitor fabricated by the method of this application can improve the working reliability and service life of the ferroelectric thin-film capacitor.

[0068] Please see Figure 1 , Figure 1 This is a structural block diagram of the electronic device 1000 provided in an embodiment of this application. Figure 1 In the illustrated embodiment, the electronic device 1000 includes a storage device 100, a processor 1001, an input device 1002, and an output device 1003.

[0069] Storage device 100 is used to store software programs and modules. Storage device 100 includes a program storage area and a data storage area. The program storage area can store and back up the operating system, applications required for at least one function, etc. For example, but not limited to, the program storage area may store programs for implementing sound playback functions, or it may store programs for implementing image playback functions, but is not limited to that storage area. The data storage area is used to store data created based on the use of electronic device 1000, such as audio data, image data, phonebook data, or other data.

[0070] For example, the storage device 100 further includes an external storage device 101 and an internal storage device 10, and data stored in the external storage device 101 and data stored in the internal storage device can be transferred between each other. The external storage device 101 can be, but is not limited to, any one of a hard disk, a USB flash drive, or a floppy disk. The internal storage device 10 can be, but is not limited to, any one of random access memory (RAM) or read-only memory (ROM). The random access memory can, for example, include ferroelectric memory, phase-change memory, or magnetic memory.

[0071] The processor 1001 is used to run or execute software programs and / or modules stored in the storage device 100, and to call data stored in the storage device 100 and to perform various functions and data processing of the electronic device 1000, thereby enabling the electronic device 1000 to achieve the desired function.

[0072] For example, processor 1001 may be, but is not limited to, at least one of an application processor (AP), a modem processor, and a graphics processing unit (GPU). The application processor is used to handle the operating system, user interface, and applications, while the modem processor is used to handle wireless communication.

[0073] For example, the different processors 1001 can be independent devices or integrated. For example, but not limited to, processor 1001 can integrate an application processor and a modem processor.

[0074] For example, the application processor can be, but is not limited to, a central processing unit (CPU). Figure 1 In the illustrated embodiment, the processor 1001 may be a central processing unit (CPU), which includes an arithmetic logic unit (ALU) 1001a and a controller 1001b. The ALU 1001a is used to acquire data stored in the internal memory 10 and to process the data stored in the internal memory 10. The ALU 1001a is also used to transfer the processed results to the internal memory 10. The controller 1001b is used to control the ALU 1001a to process the data, and the controller 1001b is also used to control the external memory 101 and the internal memory 10 to read or write data.

[0075] Input device 1002 is used to receive input numerical or character information and to generate key signal inputs related to user settings and function control of electronic device 1000. Input device 1002 may be, but is not limited to, a touchscreen or other input device 1002. By configuring input device 1002, it is possible to collect user touch operations on or near the touchscreen; for example, but not limited to, operations performed by the user using a finger, stylus, or other tool on or near the touchscreen. After acquiring the user's touch operations, input device 1002 can drive the corresponding connected device according to a pre-set program.

[0076] The output device 1003 is used to output the input of the input device 1002 and to output the signal corresponding to the data stored in the internal memory 10. For example, the output device 1003 may be, but is not limited to, being able to output signals such as audio signals, video signals, or image signals.

[0077] It should be noted that in this application Figure 1The embodiments shown are merely illustrative examples of one possible arrangement, data transmission method, and type of functional devices within the electronic device 1000, and do not limit the types, transmission methods, and arrangement of the functional devices within the electronic device 1000 provided in this application embodiment to this. In other embodiments of this application, the types of functional devices or components within the electronic device 1000, the data transmission directions between them, and their respective arrangement positions and methods can all be adjusted according to the actual design requirements and application scenarios of the electronic device, and this application embodiment does not specifically limit them in this regard.

[0078] The electronic device 1000 provided in this application embodiment may be, but is not limited to, different types of user equipment or terminal devices such as mobile phones, tablet computers, personal digital assistants (PDAs), televisions, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances, drones, radar, aerospace equipment, and vehicle-mounted equipment. The electronic device 1000 provided in this application embodiment embodiment may also be network equipment such as base stations.

[0079] In this specification, a mobile phone is used as an example of electronic device 1000 for illustrative purposes, and ferroelectric memory is used as an example of internal memory for illustrative purposes. Internal memory 10 is also illustrated as ferroelectric memory 10 in this application specification. Ferroelectric memory 10, as a type of memory within internal memory 10, utilizes the unique non-volatile electrical properties of ferroelectric materials for data storage. Its characteristics of non-volatile data storage and fast access speed provide new opportunities for overcoming size limitations.

[0080] For example, the electronic device 1000 also includes a circuit board, and the ferroelectric memory 10 may, but is not limited to, be disposed on the circuit board and is electrically connected to the circuit board.

[0081] Please refer to the following: Figures 2-4 , Figure 2 This is a structural block diagram of the ferroelectric memory 10 provided in the embodiments of this application. Figure 3 This is a structural block diagram of the storage cell 11 in the ferroelectric memory 10 provided in the embodiments of this application. Figure 4 This is a circuit diagram of the storage cell 11 in the ferroelectric memory 10 provided in an embodiment of this application. Figures 2-4 As shown, the ferroelectric memory 10 includes a substrate 12 and a plurality of memory cells 11, which are arranged in an array on the substrate 12.

[0082] Each memory cell 11 includes at least one transistor T and at least one ferroelectric thin-film capacitor 111. Figure 4 In the illustrated embodiment, each storage cell 11 includes a transistor T and a ferroelectric thin-film capacitor 111. At least one transistor T is used to control the storage or release of charge in the corresponding at least one ferroelectric thin-film capacitor 111. The presence of charge indicates the state of the storage cell 11, and may be, but is not limited to, a high voltage indicating logic "1" and a low voltage indicating logic "0".

[0083] Specifically, the source S of transistor T is electrically connected to the bit line BL, the drain D of transistor T is electrically connected to one electrode layer 1111 of ferroelectric thin-film capacitor 111, and the gate G of transistor T is electrically connected to the word line WL. The other electrode layer 1111 of ferroelectric thin-film capacitor 111 is electrically connected to the plate line PL.

[0084] like Figures 2-4 As shown, each ferroelectric thin-film capacitor 111 includes two electrode layers 1111 and one ferroelectric layer 1112, with the ferroelectric layer 1112 located between the two electrode layers 1111. Specifically, the ferroelectric layer 1112 comprises a ferroelectric material that has spontaneous polarization properties and a ferroelectric phase crystal.

[0085] For example, when the two electrode layers 1111 receive a voltage signal, an electric field is generated between the two electrode layers 1111 and applied to the ferroelectric layer 1112 between them. The central atoms of the ferroelectric phase crystal in the ferroelectric layer 1112 will move along the direction of the electric field and remain in a low-energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, and the ferroelectric domains form polarization charges under the action of the electric field.

[0086] When the electric fields generated by the two electrode layers 1111 are reversed, the central atoms of the ferroelectric phase crystal in the ferroelectric layer 1112 move along the direction of the electric field within the crystal and remain in another low-energy state. That is, the ferroelectric domains are oriented and flipped under the action of the reversed electric field. Furthermore, the polarization charge energy formed by the ferroelectric domains before and after the electric field reversal is different. This binary stable state (positive and negative polarization state) causes the ferroelectric thin film capacitor 111 to charge and discharge, which can then be identified by the external circuit to determine whether the storage cell 11 is in a "0" or "1" storage state, thereby realizing the reading or writing of data by the ferroelectric memory 10.

[0087] For example, the ferroelectric memory 10 also includes a decoder 12, a driver 13, a timing controller 14, a register 15, and an input / output interface 16. Specifically, in Figures 2-4In the illustrated embodiment, decoder 12 is used to decode the received address to determine the memory cell 11 that needs to be accessed among a plurality of memory cells 11. Driver 13 is used to generate a control signal based on the decoding result output by decoder 12. This control signal is transmitted through word line WL to the gate G of transistor T in memory cell 11 to control transistor T to be turned on or off, thereby enabling access to the specified memory cell 11.

[0088] The buffer 15 receives the data signal output from the storage unit 11 via the board line PL, and is used to buffer the data signal. For example, but not limited to, the buffer 15 can use a first-in first-out (FIFO) method for buffering. The timing controller 14 is used to control the timing of the buffer 15 and to control the driver 13 to drive at least one storage unit 11. The input / output interface 16 is used to transmit data signals, such as receiving or sending data signals.

[0089] For example, the decoder 12, driver 13, timing controller 14, buffer 15, input / output interface 16 and multiple storage units 11 in the ferroelectric memory 10 can be integrated into a single chip or into different chips. This application embodiment does not specifically limit this.

[0090] It should be noted that, in Figures 2-4 In the illustrated embodiments, the types, arrangements, and connection methods of the functional devices within the ferroelectric memory 10 are merely illustrative examples, and are not limited to these specific features. In other embodiments of this application, the types, arrangements, and connection methods of the functional devices within the ferroelectric memory 10 may be adjusted according to the actual design requirements and application scenarios of the ferroelectric memory 10, and are not specifically limited in this regard.

[0091] At the same time, it should be noted that, in Figure 4 In the illustrated embodiments, the 1T1C (1-transistor-1-capacitor) structure of the memory cell 11 is used as an example for illustrative purposes only, and the number of transistors T and ferroelectric film capacitors 111 in the memory cell 11 provided in this application embodiment is not limited to this. In other embodiments of this application, the number of transistors T and ferroelectric film capacitors 111 in each memory cell 11 can be adjusted according to the actual design requirements and application scenarios of the ferroelectric memory 10, and this application embodiment does not specifically limit this. The memory cell 11 can also be, but is not limited to, a 1T2C, 2T2C, or other types of structures.

[0092] Please see Figure 5 , Figure 5 This is a schematic diagram of the ferroelectric thin-film capacitor 111 of the ferroelectric memory 10 provided in an embodiment of this application. Figure 5 In the illustrated embodiment, the structure of the ferroelectric thin-film capacitor 111 can be... Figure 4 The planar type shown in the embodiment may also be, but is not limited to, being... Figure 5 The vertical fin type shown in (a) can also be, but is not limited to, the type shown in (a). Figure 5 The three-dimensional channel type shown in (b) can also be, but is not limited to, [the following]. Figure 5 The three-dimensional columnar shape shown in (c).

[0093] Ferroelectric memories typically consist of a ferroelectric thin-film capacitor placed between two electrode layers, storing data through this capacitor, thus forming a "sandwich" structure of "electrode layer-ferroelectric layer-electrode layer". In this structure, the ferroelectric phase in the ferroelectric layer is obtained by utilizing the significant difference in thermal expansion coefficients between the electrode layer and the ferroelectric thin-film capacitor, which provides lattice stress during annealing to generate the ferroelectric phase. Generally, the stress provided at the interface between the electrode layer and the ferroelectric thin-film capacitor is extremely limited, therefore requiring a high rapid thermal annealing temperature to induce a higher content of the ferroelectric phase.

[0094] However, due to the high temperature requirements of integrated circuit processes, thin film structures in ferroelectric memories need to be fabricated under lower thermal budget conditions. Therefore, how to improve the ferroelectric crystallization level, reduce the operating voltage, and simultaneously increase the ferroelectric storage window, as well as enhance the high-temperature retention and cycle durability of ferroelectric memory devices under lower thermal budget crystallization conditions, is an urgent problem to be solved for ferroelectric memories.

[0095] The ferroelectric memory 10 of this application achieves higher ferroelectric polarization with a lower thermal budget by specifically optimizing the internal material and structure of the ferroelectric thin film capacitor 111. That is, it can achieve higher crystallization quality under low temperature rapid thermal treatment crystallization conditions, thereby reducing operating voltage and power consumption and improving storage reliability.

[0096] The following description uses the ferroelectric thin-film capacitor 111 as a planar structure and, in conjunction with the accompanying drawings and specific embodiments, provides an exemplary description of the ferroelectric thin-film capacitor 111 in the ferroelectric memory 10.

[0097] Please see Figure 6 , Figure 6 This is a schematic cross-sectional view of the ferroelectric thin-film capacitor 111 provided in an embodiment of this application. Figure 6 In the illustrated embodiment, the two electrode layers 1111 are schematically represented as a first electrode layer 1111a and a second electrode layer 1111b, respectively. The first electrode layer 1111a is located between the ferroelectric layer 1112 and the substrate 12, and the second electrode layer 1111b is located on the side of the ferroelectric layer 1112 away from the substrate 12.

[0098] Specifically, the ferroelectric layer 1112 comprises hafnium dioxide material, and the hafnium dioxide material in the ferroelectric layer 1112 is doped with a first doping element Q, which forms at least one first doped region P1 in the ferroelectric layer 1112. The atomic radius R1 of the first doping element Q is smaller than the atomic radius R2 of the hafnium element H in the ferroelectric layer 1112.

[0099] For example, along the stacking direction of the two electrode layers 1111, the distance between at least one first doped region P1 and any electrode layer 1111 is greater than or equal to 0.3 nm.

[0100] For example, the hafnium dioxide material of the ferroelectric layer 1112 is also doped with at least one of zirconium, lanthanum, silicon, cerium, gadolinium, yttrium, aluminum, and strontium. It is understandable that by setting the hafnium dioxide material of the ferroelectric layer 1112 to be doped with multiple elements, fine control of the ferroelectric layer 1112 material can be achieved, enabling the ferroelectric memory 10 to meet different usage requirements or application scenarios, thus expanding the applicability and application scenarios of the ferroelectric memory 10.

[0101] For example, the atomic radius R1 of the first dopant element Q is smaller than the atomic radius of at least one of zirconium, lanthanum, silicon, cerium, gadolinium, yttrium, aluminum, and strontium in the hafnium dioxide material.

[0102] Understandably, the ferroelectric thin-film capacitor 111 introduces a first dopant element Q into the first doping region P1. Since the atomic radius of the first dopant element Q is smaller than that of the hafnium element H in the ferroelectric layer 1112, the first dopant element Q, after forming a diffusion bond with oxygen, can further induce lattice distortion inside the ferroelectric layer 1112, thereby generating tensile stress inside the ferroelectric layer 1112. That is, by doping the ferroelectric layer 1112 with the first dopant element Q and setting the atomic radius of the first dopant element Q to be smaller than that of the hafnium element H in the hafnium dioxide material of the ferroelectric layer 1112, it is possible to reduce the ferroelectric phase formation energy, thereby achieving higher ferroelectric polarization under lower thermal budget conditions.

[0103] Simultaneously, by doping the ferroelectric layer 1112 with the first dopant element Q, oxygen can be provided to the hafnium dioxide material in the ferroelectric layer 1112, thereby reducing the oxygen vacancy content and further improving the crystallization quality of the ferroelectric phase. Furthermore, the first doped region P1 can be understood as the region in the hafnium dioxide material of the ferroelectric layer 1112 doped with the first dopant element Q, and the planar structural shape of the first doped region P1 is the same as the planar structural shape of the ferroelectric layer 1112. In the direction of the stacking of the two electrode layers 1111, by setting the distance between the first doped region P1 and either electrode layer 1111 to be greater than or equal to 0.3 nm, the doped region of the first dopant element Q is located near the center of the ferroelectric layer 1112, further improving the crystallization level inside the ferroelectric layer 1112.

[0104] In other words, the ferroelectric memory 10 achieves the effect of multi-doping by introducing the first doping element Q into the ferroelectric thin film capacitor 111. This enables precise control of the internal stress and charged defects of oxygen vacancies in the ferroelectric thin film capacitor 111, thereby reducing the thermal budget for ferroelectric thin film crystallization and achieving higher crystallization quality under low-temperature rapid thermal treatment conditions. Consequently, it can reduce the operating voltage and power consumption, and improve storage reliability.

[0105] Because the electronic device 1000 of this application is equipped with the ferroelectric memory 10 in any of the above implementations, the electronic device 1000 of this application has all the possible beneficial effects of the ferroelectric memory 10 provided in any of the above implementations.

[0106] For example, the first doping element Q includes, but is not limited to, at least one of niobium, tantalum, and molybdenum. By setting the first doping element Q to, but not limited to, at least one of niobium (Nb), tantalum (Ta), and molybdenum (Mo), the first doping element Q in the first doped region P1 of the ferroelectric layer 1112 can occupy lattice sites, interstitial spaces, and defects in the hafnium dioxide base, further inducing lattice distortion and generating glacial stress within the ferroelectric layer 1112. Simultaneously, variable-valence elements such as niobium, tantalum, and molybdenum can also provide oxygen to the ferroelectric layer 1112 of the hafnium dioxide-based material, further reducing the oxygen vacancy content and increasing the proportion of the ferroelectric phase.

[0107] For example, along the stacking direction of the two electrode layers 1111, the width of each first doped region P1 in at least one first doped region P1 is greater than or equal to 0.1 nm and less than or equal to 2 nm. It can be understood that by setting the width of the first doped region P1 to be greater than or equal to 0.1 nm and less than or equal to 2 nm, the bonding range between the first doped element Q and the oxygen element in the hafnium dioxide material in the ferroelectric layer 1112 can be guaranteed, thereby ensuring that the first doped element Q generates sufficient glacial stress in the ferroelectric layer 1112, that is, the ferroelectric polarization inside the ferroelectric layer 1112 can be further improved with a lower thermal budget.

[0108] For example, along the stacking direction of the two electrode layers 1111, the width of the ferroelectric layer 1112 is greater than or equal to 4 nm and less than or equal to 20 nm.

[0109] For example, there is one first doped region P1, located on either side of the center line of the ferroelectric layer 1112 along the stacking direction of the two electrode layers 1111. Figure 6 In the embodiment shown, along the stacking direction of the two electrode layers 1111, a first doping element Q is doped on the side of the ferroelectric layer 1112 near the first electrode layer 1111a to form a first doped region P1 on the side of the ferroelectric layer 1112 near the first electrode layer 1111a.

[0110] The centerline of the ferroelectric layer 1112 can be understood as the geometric symmetry centerline of the ferroelectric layer 1112 along the stacking direction of the two electrode layers 1111. Alternatively, it can be understood as the midpoint between the distances between the two opposing surfaces of the ferroelectric layer 1112 along the stacking direction of the two electrode layers 1111.

[0111] Understandably, by doping the first doping element Q on either side of the center line of the ferroelectric layer 1112 along the stacking direction of the two electrode layers 1111, i.e., the first doping region P1 is arranged on one side of the ferroelectric layer 1112, the data read / write capability of the ferroelectric memory 10 can be adjusted to be more biased towards 0 or more biased towards 1.

[0112] For example, the atomic radius R1 of the first dopant element Q satisfies the condition: R1≥0.1R2, where R2 is the atomic radius R2 of the hafnium element H in the hafnium dioxide material.

[0113] By limiting the atomic radius R1 of the first dopant element Q to be smaller than the atomic radius R2 of the hafnium element H, and the atomic radius R1 of the first dopant element Q to be greater than or equal to 10% of the atomic radius R2 of the hafnium element H, the bonding effect between the first dopant element Q and the oxygen element in the hafnium dioxide material is enhanced and the resulting crystallization stress is generated. At the same time, the bonding effect between the first dopant element Q and the oxygen element can be guaranteed, thereby further improving the crystallization quality of the ferroelectric layer 1112 under low-temperature rapid heat treatment conditions.

[0114] It should be noted that, in Figure 6 In the illustrated embodiment, only one first doped region P1 in the ferroelectric layer 1112 is used as an example, and this first doped region P1 is located on the side of the ferroelectric layer 1112 near the first electrode layer 1111a, to exemplify the possible doping positions of the first doping element Q. However, this does not limit the doping positions of the first doping element Q in the ferroelectric thin film capacitor 111 provided in this embodiment to this. In other embodiments of this application, the doping positions of the first doping element Q can be adjusted according to actual design requirements and application scenarios.

[0115] Please see Figure 7 , Figure 7 This is a schematic cross-sectional view of the ferroelectric thin-film capacitor 111 provided in an embodiment of this application. Figure 7 As shown, the number of first doped regions P1 formed by doping the first doping element Q in the ferroelectric layer 1112 can be one, or it can be, but is not limited to, two or more.

[0116] For example, in Figure 7 In the embodiment shown in (a), there are two first doped regions P1, and both first doped regions P1 are located on the same side of the center line of the ferroelectric layer 1112 along the stacking direction of the two electrode layers 1111. Specifically, the two first doped regions P1 located on the same side of the center line of the ferroelectric layer 1112 are spaced apart.

[0117] For example, Figure 7 In the embodiment shown in (a), the two first doped regions P1 are located on the same side of the center line of the ferroelectric layer 1112, and the distance between the two first doped regions P1 is greater than or equal to 0.5 nm and less than or equal to 5 nm.

[0118] For example, in Figure 7 In the embodiment shown in (b), the two first doped regions P1 are symmetrically arranged about the center line of the ferroelectric layer 1112 along the stacking direction of the two electrode layers 1111.

[0119] Specifically, such as Figure 7 As shown in (b), two first doped regions P1 are distributed on both sides of the center line of the ferroelectric layer 1112. It can be understood that by doping the two electrode layers 1111 on both sides of the ferroelectric layer 1112 with first doping element Q, and by symmetrically arranging the two first doped regions P1 formed by the first doping element Q on both sides of the center line of the ferroelectric layer 1112, the data storage capabilities of the ferroelectric memory 10 for storing 0 and 1 are similar.

[0120] For example, in Figure 7In the embodiment shown in (b), the two first doped regions P1 are symmetrically arranged about the center line of the ferroelectric layer 1112, and the distance between the two first doped regions P1 is greater than or equal to 3 nm and less than or equal to 20 nm.

[0121] Understandably, along the stacking direction of the two electrode layers 1111, when the two first doped regions P1 are located on the same side of the center line of the ferroelectric layer 1112, the distance between the two first doped regions P1 is limited to be greater than or equal to 0.5 nm and less than or equal to 5 nm. Alternatively, when the two first doped regions P1 are symmetrically arranged about the center line of the ferroelectric layer 1112, the distance between the two first doped regions P1 is limited to be greater than or equal to 3 nm and less than or equal to 20 nm. This enables fine adjustment of the data read / write capability of the ferroelectric memory 10, thereby allowing the data read / write capability of the ferroelectric memory 10 to be adjusted according to different usage requirements or application scenarios, increasing the applicability and application scenarios of the ferroelectric memory 10.

[0122] Please see Figure 8 , Figure 8 This is a schematic cross-sectional view of the ferroelectric thin-film capacitor 111 provided in an embodiment of this application. Figure 8 As shown, the hafnium dioxide material in the ferroelectric layer 1112 is also doped with a second doping element, which forms a second doping region P2 in the ferroelectric layer 1112. The electronegativity of the second doping element is greater than that of the hafnium element H in the hafnium dioxide material.

[0123] The second doped region P2 can be understood as the region where the second doped element is located in the ferroelectric layer 1112. Furthermore, along the planar direction of the ferroelectric layer 1112, the planar shape and size of the second doped region P2 may, but are not limited to, being the same as the planar shape and size of the ferroelectric layer 1112.

[0124] For example, along the stacking direction of the two electrode layers 1111, the width of the second doped region P2 is greater than or equal to 0.1 nm and less than or equal to 2 nm.

[0125] For example, the second doping element includes, but is not limited to, at least one of scandium, titanium, vanadium, chromium, and manganese. By setting the first doping element Q to include, but is not limited to, at least one of scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), and manganese (Cr), the second doping element in the second doped region of the ferroelectric layer 1112 can occupy lattice sites, interstitials, and defects of the hafnium dioxide substrate. This allows the ferroelectric layer 1112 to adsorb and pin oxygen vacancies during heat treatment, preventing oxygen vacancies in the ferroelectric layer 1112 from diffusing towards the two electrode layers 1111 and potentially causing an undesirable interface dead layer.

[0126] For example, the number of second doped regions P2 is at least two. Along the stacking direction of the two electrode layers 1111, at least two second doped regions P2 are spaced apart from each other, and at least one second doped region P2 is provided between each electrode layer 1111 and the first doped region P1.

[0127] Specifically, in Figure 8 In the illustrated embodiment, along the stacking direction of the two electrode layers 1111, there is one first doped region P1, located on one side of the centerline of the ferroelectric layer 1112. Between the first doped region P1 and the first electrode layer 1111a, the hafnium dioxide material of the ferroelectric layer 1112 is doped with a second doping element, and the hafnium dioxide material doped with the second doping element together forms a second doped region P2 in the ferroelectric layer 1112. Between the first doped region P1 and the second electrode layer 1111b, the hafnium dioxide material of the ferroelectric layer 1112 is doped with a second doping element, and the hafnium dioxide material doped with the second doping element together forms another second doped region P2 in the ferroelectric layer 1112.

[0128] When the ferroelectric layer is in direct contact with the electrode layer, an interface dead layer will be formed at the interface, which will lead to adverse conditions such as ferroelectric fatigue caused by domain wall pinning or breakdown caused by oxygen vacancy connectivity.

[0129] The ferroelectric thin film capacitor 11 provided in this application embodiment does a second doping element in the hafnium dioxide material of the ferroelectric layer 1112, so that the oxygen vacancies near the electrode layer are pinned and the oxygen vacancies near the center line of the ferroelectric layer 112 are absorbed, thereby suppressing the migration of oxygen vacancies to the electrode layer 1111 under the action of the electric field, and effectively slowing down the reduction of the storage window during the ferroelectric switching process.

[0130] In other words, by doping the hafnium dioxide material of the ferroelectric layer 1112 with a second doping element, and setting the electronegativity of the second doping element to be greater than (higher than) the electronegativity of hafnium element H in the hafnium dioxide material, the second doping element pins the oxygen vacancies in the ferroelectric layer 1112, thereby preventing the oxygen vacancies in the ferroelectric layer 1112 from diffusing toward the electrode layer 1111 and forming an interface dead layer, and thus avoiding the adverse effects of fatigue, imprinting effect, breakdown and other phenomena on the storage reliability of the ferroelectric memory 10.

[0131] Meanwhile, along the stacking direction of the two electrode layers 1111, a second doping element is doped on the side of each first doped region P1 near the electrode layer 1111, that is, a second doped region P2 is set on the side of each first doped region P1 near the electrode layer 1111. This allows the second doping element to pin the oxygen vacancy on the side of the ferroelectric layer 1112 near the electrode layer 1111, thus avoiding the undesirable phenomenon of interface dead layers on both sides of the ferroelectric layer 1112. This further improves the crystallization quality inside the ferroelectric layer 1112 while reducing the crystallization heat budget, thereby improving the reliability of the ferroelectric memory 10.

[0132] The ferroelectric thin-film capacitor 11, by doping a first dopant element and a second dopant element into the ferroelectric layer 112 respectively, can significantly improve the ferroelectric crystallization level, resulting in a ferroelectric remnant polarization (2Pr) greater than or equal to 53 μC / cm², a coercive electric field Ec less than or equal to 1.1 MV / cm, and a ferroelectric crystallization thermal budget reduced by at least 75 °C. The ferroelectric thin-film capacitor 11, by introducing two variable-valence dopant elements, namely the first and second dopant elements, into the ferroelectric layer 112, can effectively pin oxygen vacancies, preventing oxygen vacancies from diffusing to the interface and forming an interface dead layer, maintaining a cycle durability full-cycle storage window 2Pr above 45 μC / cm². Simultaneously, the same-state (SS) window of the ferroelectric thin-film capacitor 11 remains without significant decay, effectively improving the operating performance and lifespan of the ferroelectric thin-film capacitor 11 provided in this application embodiment.

[0133] Please see Figure 9 , Figure 9 This is a schematic cross-sectional view of the ferroelectric thin-film capacitor 111 provided in an embodiment of this application. Figure 9 As shown, there are at least two second doped regions P2. Along the stacking direction of the two electrode layers 1111, the two second doped regions P2 are symmetrically arranged about the center line of the ferroelectric thin film capacitor 111.

[0134] Specifically, in Figure 9 In the illustrated embodiment, there are two first doped regions P1 and two second doped regions P2. Along the stacking direction of the two electrode layers 1111, there is one first doped region P1 and one second doped region P2 on each side of the center line of the ferroelectric layer 1112. That is, one first doped region P1 and one second doped region P2 are located between the center line of the first electrode layer 1111a and the ferroelectric layer 1112. The other first doped region P1 and the other second doped region P2 are located between the center line of the ferroelectric layer 1112 and the second electrode layer 1111b.

[0135] In this configuration, one first doped region P1 is further away from the first electrode layer 1111a than its adjacent second doped region P2. Alternatively, one second doped region P2 can be understood as being located between the first electrode layer 1111a and one first doped region P1. Similarly, another first doped region P1 is further away from the second electrode layer 1111b than its adjacent second doped region P2. This can also be understood as being located between the second electrode layer 1111b and another second doped region P2.

[0136] For example, the distance between the second doped region P2 and its adjacent electrode layer 1111 is greater than or equal to 0.3 nm and less than or equal to 4 nm.

[0137] Understandably, by doping each side of the ferroelectric layer 1112 near the electrode layer 1111 with a second doping element, the second doping element adsorbs and pins oxygen vacancies on each side of the ferroelectric layer 1112 near the electrode layer 1111, thereby further reducing the charged defects of oxygen vacancies in the ferroelectric layer 1112 and further improving the reliability of the ferroelectric memory 10.

[0138] Meanwhile, by setting the distance between the second doped region P2 formed by the second doped element and an adjacent electrode layer 1111 to be greater than or equal to 0.3 nm and less than or equal to 4 nm, the doping position and range of the second doped element can be limited, thereby achieving fine control of the charged defects of oxygen vacancies in the ferroelectric layer 1112, while ensuring that the second doped element is effectively doped and pins oxygen vacancies in the ferroelectric layer 1112.

[0139] In one implementation, the distance between the second doped region P2 and its adjacent first doped region P1 is greater than or equal to 0.2 nm and less than or equal to 3 nm.

[0140] Please see Figure 10 , Figure 10 This is a schematic cross-sectional view of the ferroelectric thin-film capacitor 111 provided in an embodiment of this application. Figure 10 As shown, the ferroelectric thin film capacitor 111 further includes at least one interface layer 1113, which is inserted between an electrode layer 1111 and a ferroelectric layer 1112. The material of the at least one interface layer 1113 includes at least one of titanium dioxide, niobium pentoxide, and tantalum pentoxide.

[0141] Understandably, by inserting an interface layer 1113 between the ferroelectric layer 1112 and an adjacent electrode layer 1111, the lattice constant of the interface layer 1113 is different from that of the ferroelectric layer 1112. This allows for the generation of interface stress in the vicinity of the ferroelectric layer 1112 near the electrode layer 1111. The mismatch dislocations generated in the ferroelectric layer 1112 near the electrode layer 1111 can induce lattice symmetry breaking, which is beneficial for the formation of the ferroelectric phase in the ferroelectric layer 1112, improving the ferroelectric crystallization quality, reducing crystallization preheating calculations, and enhancing the ferroelectric polarization and reliability performance.

[0142] For example, the materials of the first electrode layer 1111a and the second electrode layer 1111b may include, but are not limited to, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN).

[0143] For example, the thickness of at least one of the first electrode layer 1111a and the second electrode layer 1111b is between 3 nm and 260 nm.

[0144] This application also provides a method for preparing a ferroelectric thin-film capacitor 111, used to prepare the ferroelectric thin-film capacitor 111 in any of the above embodiments. Next, this application specification will describe the ferroelectric thin-film capacitor 111 provided by this application in conjunction with the accompanying drawings and specific embodiments.

[0145] Please refer to the following: Figure 11 and Figure 12 , Figure 11 This is a schematic diagram illustrating the workflow of the ferroelectric thin-film capacitor fabrication method provided in the embodiments of this application. Figure 12 This is a schematic diagram of the structure in the ferroelectric thin-film capacitor fabrication method provided in the embodiments of this application. Figure 11 In the illustrated embodiment, the method for fabricating a ferroelectric thin-film capacitor includes:

[0146] Step S100: Prepare an electrode layer 1111 and prepare a first ferroelectron layer 11121 on the surface of the electrode layer 1111;

[0147] like Figure 12 As shown in (a), the electrode layer 1111 can be prepared using a thin-film deposition process, but is not limited to this process, and a first ferroelectron layer 11121 can be prepared on the surface of the electrode layer 1111. The material and internal doping elements of the first ferroelectron layer 11121 can be the same as described above. Figures 6-10 The ferroelectric layer 1112 provided in the illustrated embodiment has the same material and doping elements.

[0148] For example, thin film deposition processes include any one of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0149] For example, before the first ferroelectron layer 11121 can be prepared on the surface of the electrode layer 1111 using a thin film deposition process, an interface layer 1113 can be prepared on the surface of the electrode layer 1111 first, and then the first ferroelectron layer 11121 can be prepared on the surface of the interface layer 1113 facing away from the electrode layer 1111. The specific structure is as follows. Figure 10 As shown.

[0150] Step S200: A first ferroelectric doped layer and a second ferroelectric doped layer 11122 are prepared by cycling on the surface of the first ferroelectric doped layer 11121. The first ferroelectric doped layer and the second ferroelectric doped layer 11122 are cycled at least once. The first ferroelectric doped layer 11121, the first ferroelectric doped layer and the second ferroelectric doped layer 11122 both include hafnium dioxide material. The hafnium dioxide material in the first ferroelectric doped layer is doped with a first doping element Q to form a first doped region P1. The atomic radius of the first doping element Q is smaller than the atomic radius of the hafnium element H in the hafnium dioxide material.

[0151] Specifically, but not limited to, a first ferroelectric doped layer can be first prepared on the surface of the first ferroelectric layer 11121 away from the electrode layer 1111 using a thin film deposition process, and then a second ferroelectric layer 11122 can be prepared on the surface of the first ferroelectric doped layer away from the first ferroelectric layer 11121 using a thin film deposition process. For the specific structure, please refer to [link / reference]. Figure 6 and Figure 7 The illustrated embodiment.

[0152] The cyclical preparation of the first ferroelectric doped layer and the second ferroelectronic layer 11122 can be understood as follows: during the preparation process, the preparation order of the first ferroelectric doped layer and the second ferroelectronic layer 11122 remains unchanged, but it is not limited to the thickness of the first ferroelectric doped layer and the second ferroelectric doped layer being the same or different in each cycle. That is, in the embodiments provided in this application, the thickness of the first ferroelectric doped layer and the second ferroelectric doped layer can be adjusted according to different design requirements during the cycle, and this application embodiment does not specifically limit this.

[0153] Please combine Figure 12 See also Figure 13 , Figure 13 This is a schematic diagram illustrating the workflow for fabricating the first ferroelectric doped layer and the second ferroelectronic layer 11122 using the ferroelectric thin-film capacitor fabrication method provided in this application embodiment. Figure 13 In the illustrated embodiment, step S200, "Creating a first ferroelectric doped layer and a second ferroelectric layer 11122 by cycling on the surface of the first ferroelectric doped layer 11121, wherein the number of cycles for the first ferroelectric doped layer and the second ferroelectric layer 11122 is at least one," includes:

[0154] Step S201: A second ferroelectric doped layer and a third ferroelectric doped layer 11123 are sequentially prepared on the surface of the first ferroelectric layer 11121. The second ferroelectric doped layer and the third ferroelectric doped layer 11123 both include hafnium dioxide material. The hafnium dioxide material in the second ferroelectric doped layer is doped with a second doping element to form a second doped region P2. The electronegativity of the second doping element is greater than that of the hafnium element H in the hafnium dioxide material.

[0155] Specifically, such as Figure 12 As shown in (b), in step S201, a thin film deposition process may be used, but is not limited to, to sequentially deposit a second ferroelectric doped layer and a third ferroelectric doped layer 11123 on the surface of the first ferroelectric layer 11121 facing away from the electrode layer 1111. The hafnium dioxide material in the second ferroelectric doped layer is doped with a second doping element to form a second doped region P2.

[0156] Step S202: Prepare a first ferroelectric doped layer and a second ferroelectric layer 11122 by cycling on the surface of the third ferroelectric layer 11123, wherein the first ferroelectric doped layer and the second ferroelectric layer 11122 are cycled at least once.

[0157] Specifically, such as Figure 12 As shown in (c), in step S202, after depositing a third ferroelectronic layer 11123, at least one set of first ferroelectric doped layer and second ferroelectronic layer 11122 is prepared on the surface of the third ferroelectronic layer 11123 facing away from the electrode layer 1111. That is, the number of cycles for the first ferroelectric doped layer and the second ferroelectronic layer 11122 is at least one. Figure 12 In the embodiment shown in (c), the number of cycles is two, and the thickness of the second ferroelectric layer 11122 is different in the two cycles. It can be understood that by depositing a third ferroelectric layer 11123 between the second ferroelectric doped layer and the first ferroelectric doped layer, a spacer effect is formed between the second ferroelectric doped layer and the first ferroelectric doped layer, thereby improving the working performance and effect of the first ferroelectric doped layer and the second ferroelectric doped layer respectively.

[0158] The materials and internal doping elements of the first ferroelectron layer 11121, the second ferroelectron layer 11122, and the third ferroelectron layer 11123 can be the same or different. In this specification, the ferroelectric layer 1112 is divided into the first ferroelectron layer 11121, the second ferroelectron layer 11122, and the third ferroelectron layer 11123 only for distinguishing and illustrating the ferroelectron layers at different locations within the ferroelectric layer 1112. This does not limit the materials and internal doping elements of the ferroelectron layers at different locations within the ferroelectric layer 1112 to be different, nor does it limit the materials and internal doping elements of two ferroelectron layers at different locations to be the same.

[0159] Meanwhile, along the plane direction perpendicular to one of the electrode layers 1111, this application does not limit the thickness of each of the first ferroelectron layer 11121, the second ferroelectron layer 11122, and the third ferroelectron layer 11123. In the accompanying drawings provided in the embodiments of this application, the thickness of each of the first ferroelectron layer 11121, the second ferroelectron layer 11122, and the third ferroelectron layer 11123 is only described exemplarily in one possible embodiment. In other embodiments of this application, the first ferroelectron layer 11121, the second ferroelectron layer 11122, and the third ferroelectron layer 11123 can also be adjusted according to actual design requirements.

[0160] Step S203: Prepare a second ferroelectric doped layer on the surface of the second ferroelectronic layer 11122 with the largest distance from an electrode layer 1111, and then prepare another second ferroelectronic layer 11122.

[0161] Specifically, such as Figure 12 As shown in (d), in step S203, after completing the cyclic preparation of the first ferroelectric doped layer and the second ferroelectronic layer 11122, a second ferroelectric doped layer and a second ferroelectronic layer 11122 are deposited on the outer surface of the second ferroelectronic layer 11122 with the largest distance from the electrode layer 1111. This can be done, but is not limited to, using a thin film deposition process.

[0162] Step S300: Prepare another electrode layer 1111 on the surface of the second ferroelectron layer 11122, which has the largest distance from an electrode layer 1111.

[0163] Specifically, such as Figure 12 As shown in (e), in step S300, another electrode layer 1111 is prepared on the surface of the second ferroelectron layer 11122, which has the largest distance from the first electrode layer 1111, along a plane direction perpendicular to the first electrode layer 1111.

[0164] For example, before fabricating another electrode layer 1111 on the surface of the second ferroelectron layer 11122 with the largest distance from one electrode layer 1111, an interface layer 1113 can be fabricated on the surface of the second ferroelectron layer 11122 facing away from one electrode layer 1111. Then, a first ferroelectron layer 11121 can be fabricated on the surface of the interface layer 1113 facing away from the second ferroelectron layer 11122. The specific structure is as follows: Figure 10 As shown.

[0165] Understandably, the ferroelectric thin film capacitor 111 prepared by the ferroelectric thin film capacitor preparation method of this application is doped by introducing a first doping element Q into the first doping region P1. Since the atomic radius of the first doping element Q is smaller than the atomic radius of the hafnium element H in the ferroelectric layer 1112, the first doping element Q can further induce lattice distortion inside the ferroelectric layer 1112 after forming a diffusion bond with the oxygen element, so as to generate tensile stress inside the ferroelectric layer 1112.

[0166] By doping a second doping element into the hafnium dioxide material of the ferroelectric layer 1112 to form a second doped region P2, and setting the electronegativity of the second doping element to be greater than (higher than) the electronegativity of hafnium element H in the hafnium dioxide material, the second doping element pins the oxygen vacancies in the ferroelectric layer 1112, thereby preventing the oxygen vacancies in the ferroelectric layer 1112 from diffusing toward the electrode layer 1111 and forming an interface dead layer, and thus avoiding the adverse effects of fatigue, imprinting effect, breakdown and other phenomena on the storage reliability of the ferroelectric memory 10.

[0167] In other words, the ferroelectric thin film capacitor 111 prepared by the ferroelectric thin film capacitor preparation method of this application can achieve the effect of multi-doping inside the ferroelectric layer 1112 by doping the first doping element Q and the second doping element at different positions inside the ferroelectric layer 1112, thereby achieving fine control of internal stress and oxygen vacancy charged defects in the ferroelectric thin film capacitor 111. This reduces the crystallization heat budget of the ferroelectric thin film and achieves higher crystallization quality under low temperature rapid heat treatment conditions, thereby reducing the operating voltage and power consumption and improving storage reliability.

[0168] Of course, the above-described embodiments can be applied individually or in combination. The above description is the preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A ferroelectric memory, characterized in that, The device includes multiple memory cells, each memory cell including at least one transistor and at least one ferroelectric thin-film capacitor. The at least one transistor is used to control the storage or release of charge in the at least one ferroelectric thin-film capacitor. Each ferroelectric thin-film capacitor includes two electrode layers and a ferroelectric layer located between the two electrode layers. The ferroelectric layer includes hafnium dioxide material and includes at least one first doped region. The at least one first doped region is doped with a first doping element, wherein the atomic radius of the first doping element is smaller than the atomic radius of the hafnium element in the ferroelectric layer.

2. The ferroelectric memory according to claim 1, characterized in that, Along the stacking direction of the two electrode layers, the distance between the at least one first doped region and either of the electrode layers is greater than or equal to 0.3 nm.

3. The ferroelectric memory according to claim 1 or 2, characterized in that, The atomic radius R1 of the first doped element satisfies the condition: R1≥0.1R2, where R2 is the atomic radius of the hafnium element.

4. The ferroelectric memory according to any one of claims 1-3, characterized in that, The first doping element includes at least one of niobium, tantalum, or molybdenum.

5. The ferroelectric memory according to any one of claims 1-4, characterized in that, Along the direction of the stacking of the two electrode layers, the width of each first doped region in the at least one first doped region is greater than or equal to 0.1 nm and less than or equal to 2 nm.

6. The ferroelectric memory according to any one of claims 1-5, characterized in that, The at least one first doped region includes two first doped regions, wherein, along the direction of stacking of the two electrode layers: Both first doped regions are located on the same side of the centerline of the ferroelectric layer; Alternatively, the two first doped regions are arranged symmetrically about the centerline of the ferroelectric layer.

7. The ferroelectric memory according to claim 6, characterized in that, The two first doped regions are both located on the same side of the centerline of the ferroelectric layer, and the distance between the two first doped regions is greater than or equal to 0.5 nm and less than or equal to 5 nm; or The two first doped regions are symmetrically arranged about the center line of the ferroelectric layer, and the distance between the two first doped regions is greater than or equal to 3 nm and less than or equal to 20 nm.

8. The ferroelectric memory according to any one of claims 1-7, characterized in that, The ferroelectric layer includes at least two second doped regions, each of which is doped with a second doping element, wherein: The electronegativity of the second dopant element is greater than that of the hafnium element; Along the direction of the stacking of the two electrode layers, the at least two second doped regions are spaced apart from each other, and at least one second doped region is provided between each electrode layer and the first doped region.

9. The ferroelectric memory according to claim 8, characterized in that, The second doping element includes at least one of scandium, titanium, vanadium, chromium, or manganese.

10. The ferroelectric memory according to claim 8 or 9, characterized in that, Along the stacking direction of the two electrode layers, the two second doped regions are symmetrically arranged about the center line of the ferroelectric thin film capacitor, and the distance between each second doped region and its adjacent electrode layer is greater than or equal to 0.3 nm and less than or equal to 4 nm.

11. The ferroelectric memory according to any one of claims 8-10, characterized in that, The distance between each second doped region and an adjacent first doped region is greater than or equal to 0.2 nm and less than or equal to 3 nm.

12. The ferroelectric memory according to any one of claims 1-11, characterized in that, The ferroelectric thin-film capacitor further includes at least one interface layer, which is inserted between one of the electrode layers and the ferroelectric layer. The material of the at least one interface layer includes at least one of titanium dioxide, niobium pentoxide, or tantalum pentoxide.

13. The ferroelectric memory according to any one of claims 1-12, characterized in that, The hafnium dioxide material is also doped with at least one of zirconium, lanthanum, silicon, cerium, gadolinium, yttrium, aluminum, or strontium. The atomic radius of the first dopant element is smaller than the atomic radius of at least one of zirconium, lanthanum, silicon, cerium, gadolinium, yttrium, aluminum, or strontium in the hafnium dioxide material.

14. An electronic device, characterized in that, The electronic device includes a circuit board and a ferroelectric memory as described in any one of claims 1-13, the ferroelectric memory being disposed on the circuit board and electrically connected to the circuit board.

15. A ferroelectric thin-film capacitor, characterized in that, The ferroelectric thin-film capacitor includes two electrode layers and a ferroelectric layer, with the ferroelectric layer located between the two electrode layers. The ferroelectric layer includes hafnium dioxide material and at least one first doped region, wherein the at least one first doped region is doped with a first doping element, wherein the atomic radius of the first doping element is smaller than the atomic radius of the hafnium element in the ferroelectric layer.

16. The ferroelectric thin-film capacitor according to claim 15, characterized in that, The ferroelectric layer includes at least two second doped regions, each of which is doped with a second doping element, wherein: The electronegativity of the second dopant element is greater than that of the hafnium element; Along the direction of the stacking of the two electrode layers, the at least two second doped regions are spaced apart from each other, and at least one second doped region is provided between each electrode layer and the first doped region.

17. A method for preparing a ferroelectric thin-film capacitor, characterized in that, include: An electrode layer is prepared and a first ferroelectron layer is prepared on the surface of the electrode layer; A first ferroelectric doped layer and a second ferroelectric layer are prepared by cycling on the surface of the first ferroelectric layer. The first ferroelectric doped layer and the second ferroelectric layer are cycled at least once. The first ferroelectric layer, the first ferroelectric doped layer and the second ferroelectric layer all include hafnium dioxide material. The hafnium dioxide material in the first ferroelectric doped layer is doped with a first doping element to form a first doped region. The atomic radius of the first doping element is smaller than the atomic radius of the hafnium element in the hafnium dioxide material. Another electrode layer is prepared on the surface of the second ferroelectronic layer, which has the largest spacing from the first electrode layer.

18. The method for preparing a ferroelectric thin-film capacitor according to claim 17, characterized in that, The step of cyclically preparing a first ferroelectric doped layer and a second ferroelectric layer on the surface of the first ferroelectric layer, wherein the first ferroelectric doped layer and the second ferroelectric layer are cycled at least once, includes: A second ferroelectric doped layer and a third ferroelectric doped layer are sequentially prepared on the surface of the first ferroelectric layer. The second ferroelectric doped layer and the third ferroelectric doped layer both include the hafnium dioxide material. The hafnium dioxide material in the second ferroelectric doped layer is doped with a second doping element to form a second doped region. The electronegativity of the second doping element is greater than that of the hafnium element in the hafnium dioxide material. The first ferroelectric doped layer and the second ferroelectric doped layer are prepared cyclically on the surface of the third ferroelectric layer, and the first ferroelectric doped layer and the second ferroelectric doped layer are prepared at least once; A second ferroelectric doped layer is prepared on the surface of the second ferroelectronic layer with the largest distance from the first electrode layer, and then another second ferroelectronic layer is prepared.

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