Semiconductor structure and method of fabrication

Abstract

This application relates to the field of semiconductor technology, specifically disclosing a semiconductor structure and fabrication method. The fabrication method uses five photomasks to form conductive connectors under RRAM cells, mark grooves, dielectric layers of MIM cell capacitors, top electrodes of RRAM cells and MIM cells, and top vias, thereby achieving integrated manufacturing of MIM and RRAM cells. While ensuring the functionality of existing devices, it effectively improves the functional density of the chip, making it suitable for high-density storage, analog / RF circuits, and in-memory computing chips. Compared to traditional discrete processes that use 8-10 photomasks, this application significantly reduces the number of photomasks through a shared photomask process, thereby reducing photomask costs and the cost of repetitive manufacturing processes.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the rapid development of technologies such as artificial intelligence and intelligent vehicles, the performance requirements for storage technology and analog circuits are becoming increasingly stringent, necessitating the integration of the entire "storage-computation-signal conditioning" chain. Resistive Random-Access Memory (RRAM) has become one of the mainstream memory types due to its non-volatile storage characteristics and nanosecond-level read / write speeds; while Metal-Insulator-Metal (MIM) capacitors provide high-precision analog functions (such as filtering and coupling), playing a crucial role in applications such as high dynamic range image sensing and power management. Integrating RRAM and MIM capacitors onto a single chip can be widely applied in in-memory computing chips, automotive-grade microcontroller units, display drivers, and other fields, meeting the high-performance requirements of systems.

[0003] In traditional processes, RRAM and MIM capacitors are typically manufactured discretely, requiring a total of 8-10 photomasks. This low photomask reuse rate leads to high manufacturing costs and complex processes, hindering their application in large-scale integration. Therefore, developing a process solution that can efficiently integrate RRAM and MIM capacitors is crucial for reducing manufacturing costs and improving chip performance. Summary of the Invention

[0004] To address the issues of high photomask quantity, low reusability, and high manufacturing cost resulting from the independent fabrication of RRAM and MIM capacitors in traditional discrete processes, this application provides a semiconductor structure and fabrication method.

[0005] In a first aspect, this application provides a method for preparing a semiconductor structure, comprising the following steps: A semiconductor substrate having a metal interconnect layer is provided, wherein the semiconductor substrate has at least a resistive switching region and a capacitive region; A diffusion-resistant layer is deposited, and a conductive connector plug connected to the metal interconnect layer is prepared in the resistive switching region; Marking grooves are etched on the anti-diffusion layer, and a first conductive material layer and a capacitor dielectric material layer are deposited sequentially. A capacitor dielectric layer is obtained in the capacitor region by using a capacitor-defined photomask and a primary photoresist, and etching the capacitor dielectric material layer using a photolithography process. Deposited resistive switching material layer; A capacitive photomask and a secondary photoresist are used, and a resistive switching material layer on the capacitive dielectric layer is removed by photolithography. The positive and negative values ​​of the secondary photoresist are opposite to those of the primary photoresist. Deposit a second conductive material layer; The second conductive material layer, the resistive switching material layer, and the first conductive material layer are sequentially etched using an electrode-defined photomask and photolithography to obtain RRAM cells in the resistive switching region and MIM cells in the capacitor region.

[0006] Further, the step of etching marking grooves on the anti-diffusion layer includes: A first hard mask layer is deposited on the anti-diffusion layer; The photomask is defined by a marking groove, and the anti-diffusion layer is etched in the contact area between the resistive switching region and the capacitive region using photolithography to obtain the marking groove.

[0007] Furthermore, in the process of removing the resistive switching material layer on the capacitor dielectric layer using photolithography by employing a capacitor-defined photomask and a second photoresist, the window of the photoresist pattern obtained by exposing and developing the second photoresist using the capacitor-defined photomask is the area where the capacitor dielectric layer is located. The window of the photoresist pattern is pulled back before etching the resistive switching material layer.

[0008] Further, the step of sequentially etching the second conductive material layer, the resistive switching material layer, and the first conductive material layer using an electrode-defined photomask and photolithography to obtain RRAM cells in the resistive switching region and MIM cells in the capacitive region includes: A second hard mask layer is deposited on the second conductive material layer; Photoresist is coated on the second hard mask layer, and an electrode photoresist pattern is obtained by exposure and development using an electrode definition photomask. The electrode photoresist pattern includes a first pattern for defining the shape of the RRAM cell and a second pattern for defining the shape of the top electrode of the MIM cell. Using the first and second patterns as barrier layers, the second hard mask layer and the second conductive material layer are etched and left on the resistive switching material layer, respectively obtaining the corresponding top electrodes in the resistive switching region and the capacitor region. Using the first and second patterns as barrier layers, the resistive switching material layer is etched onto the first conductive material layer using a selective etching process. Using the first pattern, the second pattern, and the capacitor dielectric layer as barrier layers, the first conductive material layer is etched using a selective etching process to obtain the corresponding bottom electrodes in the resistive switching region and the capacitor region, respectively.

[0009] Furthermore, the size of the second pattern is smaller than the size of the capacitor dielectric layer.

[0010] Furthermore, the capacitor dielectric layer and the resistive switching material layer have the same thickness.

[0011] Secondly, this application provides a semiconductor structure prepared using the above-described preparation method.

[0012] Thirdly, this application provides a method for preparing a semiconductor structure, comprising the following steps: A semiconductor substrate having a metal interconnect layer is provided, wherein the semiconductor substrate has at least a resistive switching region and a capacitive region; A diffusion-resistant layer is deposited, and a conductive connector plug connected to the metal interconnect layer is prepared in the resistive switching region; Marking grooves are etched on the anti-diffusion layer, and a first conductive material layer and a capacitor dielectric material layer are deposited sequentially. A capacitor dielectric layer is obtained in the capacitor region by using a capacitor-defined photomask and a primary photoresist, and etching the capacitor dielectric material layer using a photolithography process. Deposited resistive switching material layer; A capacitive photomask and a secondary photoresist are used, and a resistive switching material layer on the capacitive dielectric layer is removed by photolithography. The positive and negative values ​​of the secondary photoresist are opposite to those of the primary photoresist. Deposit a second conductive material layer; The second conductive material layer, the resistive switching material layer, and the first conductive material layer are sequentially etched using an electrode definition photomask and photolithography to obtain RRAM cells in the resistive switching region and MIM cells in the capacitor region. Deposited device protective layer; Through-holes connecting the RRAM cell and the MIM cell are etched on the device protective layer; The via is filled with conductive material to bring out the RRAM cell and MIM cell.

[0013] Furthermore, before depositing the device protective layer, an isolation layer is first deposited to cover the RRAM cell and the MIM cell.

[0014] Fourthly, this application provides a semiconductor structure prepared using the above-described preparation method.

[0015] This application includes the following beneficial technical effects: The semiconductor structure and fabrication method provided in this application ingeniously employ the combination of a capacitor-defined photomask and positive and negative photoresists to achieve fabrication of the resistive switching layer and the capacitor dielectric layer without mutual interference. This application not only realizes the integrated manufacturing of MIM capacitors and RRAM devices, but also effectively improves the functional density of the chip while ensuring the functionality of existing devices, meeting the development needs of chip miniaturization, thereby improving the product's cost-effectiveness and market competitiveness. It is applicable to chip fields such as high-density memory, analog / RF circuits, and in-memory computing chips, and has broad application prospects. The unexpected technical effects of this application include: compared with traditional discrete processes, this application reduces the number of photomasks from the traditional 8-10 to 4-5 through a shared photomask process, significantly reducing the number of photomasks, lowering photomask costs, and reducing the cost of repetitive manufacturing processes. Attached Figure Description

[0016] Figure 1 This is a flowchart of the method for fabricating the semiconductor structure in Embodiment 1 of this application; Figure 2 This is a schematic diagram of the semiconductor substrate of Embodiment 1 of this application; Figure 3 This is a schematic diagram of the deposition of an anti-diffusion layer on a semiconductor substrate according to Embodiment 1 of this application; Figure 4 This is a schematic diagram of the preparation of a conductive connector in the anti-diffusion layer according to Embodiment 1 of this application; Figure 5 This is a schematic diagram of the deposition of a first hard mask layer on the anti-diffusion layer in Embodiment 1 of this application; Figure 6 This is a schematic diagram of the marking groove formed in the anti-diffusion layer in Embodiment 1 of this application; Figure 7 This is a schematic diagram of the deposition of a first conductive material layer and a capacitor dielectric material layer on the anti-diffusion layer in Embodiment 1 of this application; Figure 8 This is a schematic diagram of Embodiment 1 of this application after the capacitively defined photomask and primary photoresist have been developed; Figure 9 This is a schematic diagram of the etching of the capacitor dielectric material layer in Embodiment 1 of this application; Figure 10 This is a schematic diagram of the resistive switching material layer deposited in Embodiment 1 of this application; Figure 11 This is a schematic diagram of Embodiment 1 of this application after the development of a capacitively defined photomask and a second photoresist; Figure 12 This is a schematic diagram of the pull-back process of the secondary photoresist in Embodiment 1 of this application; Figure 13 This is a schematic diagram of the etching of the resistive switching material layer in Embodiment 1 of this application; Figure 14This is a schematic diagram of the deposition of the second conductive material layer in Embodiment 1 of this application; Figure 15 This is a schematic diagram of the deposition of the second hard mask layer in Embodiment 1 of this application; Figure 16 This is a schematic diagram of the electrode-defined photomask and photoresist after development in Embodiment 1 of this application; Figure 17 This is a schematic diagram of etching the second conductive material layer in Embodiment 1 of this application; Figure 18 This is a schematic diagram of selective etching of the resistive switching material layer in Embodiment 1 of this application; Figure 19 This is a schematic diagram of selective etching of the first conductive material layer in Embodiment 1 of this application; Figure 20 This is a schematic diagram of the semiconductor structure prepared in Example 1 of this application; Figure 21 This is a flowchart of the method for fabricating the semiconductor structure in Embodiment 2 of this application; Figure 22 This is a schematic diagram of the deposition of an isolation layer, a device protection layer, a buffer layer, and an interlayer dielectric layer in Embodiment 2 of this application; Figure 23 This is a schematic diagram of the through hole formed in Embodiment 2 of this application; Figure 24 This is a top view of the through hole formed in Embodiment 2 of this application; Figure 25 This is a schematic diagram of the semiconductor structure prepared in Example 2 of this application.

[0017] Reference numerals: 10, Semiconductor substrate; 11, Metal interconnect layer; 20, Anti-diffusion layer; 21, Conductive connector; 22, First hard mask layer; 23, Marker groove; 30, First conductive material layer; 31, RRAM bottom electrode; 32, MIM bottom electrode; 40, Capacitor dielectric material layer; 41, Capacitor dielectric layer; 51, First photoresist pattern; 52, Second photoresist pattern; 53, First pattern; 54, Second pattern; 60, Resistive switching material layer; 61, Resistive switching layer; 70, Second conductive material layer; 71, Second hard mask layer; 72, RRAM top electrode; 73, MIM top electrode; 80, Isolation layer; 90, Device protection layer; 91, Buffer layer; 92, Interlayer dielectric layer; 93, Through-hole; 94, Conductive material. Detailed Implementation

[0018] The following is in conjunction with the appendix Figure 1-25 This application will be described in further detail.

[0019] Example 1 This embodiment discloses a method for fabricating a semiconductor structure. (Refer to...) Figure 1The method for fabricating a semiconductor structure includes the following steps: Step S1: Provide a semiconductor substrate 10 having a metal interconnect layer 11, wherein the semiconductor substrate 10 has at least a resistive switching region and a capacitor region; Step S2: Deposit the anti-diffusion layer 20, and fabricate a conductive connector 21 connected to the metal interconnect layer 11 in the resistive switching region; Step S3: Etch marking grooves 23 on the anti-diffusion layer 20, and sequentially deposit the first conductive material layer 30 and the capacitor dielectric material layer 40; Step S4: Using a capacitor-defined photomask and a primary photoresist, the capacitor dielectric material layer 40 is etched using a photolithography process to obtain the capacitor dielectric layer 41 in the capacitor region; Step S5: Deposit resistive switching material layer 60; Step S6: Using a capacitor to define a photomask and a secondary photoresist, the resistive switching material layer 60 on the capacitor dielectric layer 41 is removed using a photolithography process, wherein the positive and negative polarities of the secondary photoresist are opposite to those of the primary photoresist. Step S7: Deposit the second conductive material layer 70; Step S8: The second conductive material layer 70, the resistive switching material layer 60 and the first conductive material layer 30 are sequentially etched using an electrode definition photomask and photolithography process to obtain RRAM cells in the resistive switching region and MIM cells in the capacitor region.

[0020] Reference Figure 2 The semiconductor substrate 10 provided in step S1 is a wafer that has completed front-end processing (FEOL) and partial back-end processing (BEOL). Partial back-end processing refers to the completion of the fabrication of the metal interconnect layer 11. The metal interconnect layer 11 is located on the front side of the wafer, surrounded by an interlayer dielectric (ILD) layer. Below the metal interconnect layer 11 is a semiconductor structure containing transistors, both fabricated using existing technologies, which will not be elaborated further in this application. The metal interconnect layer 11 typically uses copper or aluminum as the conductive substrate to enable electrical signal connectivity between devices within the wafer.

[0021] Reference Figure 3 In step S2, an anti-diffusion layer 20 is deposited on the surface of the semiconductor substrate 10. The function of the anti-diffusion layer 20 is to prevent metal atoms in the underlying metal interconnect layer 11 from diffusing upwards into the MIM cells or RRAM cells during the high-temperature process, thereby preventing device performance degradation or failure. At the same time, the anti-diffusion layer 20 can also prevent impurities such as oxygen and moisture from penetrating, providing a flat, stable and highly adhesive interface for subsequent functional layers, and serving as an etch stop layer in the etching process to protect the underlying structure.

[0022] In terms of material selection, the anti-diffusion layer 20 typically uses high-density, chemically inert materials, including TiN (titanium nitride), TaN (tantalum nitride), Ti / TiN composite layers, SiN (silicon nitride), and SiCN (silicon carbonitride). In this embodiment, the anti-diffusion layer 20 is made of SiCN material with a thickness of 50nm-100nm, and can be prepared using processes such as physical vapor deposition or atomic layer deposition.

[0023] In step S2, a conductive connector 21 connected to the metal interconnect layer 11 is fabricated in the resistive switching region, specifically including the following steps: Photoresist is coated onto the surface of the anti-diffusion layer 20 to form a photoresist layer. The type of photoresist material is not limited; it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, the photoresist layer is patterned through photolithography processes such as exposure with a first photomask and development.

[0024] Using a patterned photoresist layer as a mask, the anti-diffusion layer 20 is etched until the metal interconnect layer 11 is exposed to form a filling trench. The etching method can be plasma dry etching, and the etching gas includes at least one of CF4 and CHF3, as well as inert gases such as argon. After etching, an ashing process is used to remove the photoresist layer.

[0025] A conductive material is deposited within the filling trench. This conductive material combines diffusion-blocking properties with good conductivity and can be materials such as TiN, TaN, or Ti / TiN composite layers. It effectively prevents metal atoms in the underlying metal interconnect layer 11 from diffusing upwards into the RRAM functional layer, while providing a stable interface with low contact resistance and maintaining structural reliability during subsequent high-temperature processes. In this embodiment, the conductive material is TaN, which can be prepared using processes such as physical vapor deposition or atomic layer deposition.

[0026] After the conductive material is deposited, it is planarized by chemical mechanical polishing to expose the anti-diffusion layer 20, thus obtaining the conductive connector 21. Figure 4 As shown.

[0027] In step S3, marking grooves 23 are etched on the anti-diffusion layer 20, specifically including the following steps: Step S3.1: Deposit a first hard mask layer 22 on the surface of the planarized anti-diffusion layer 20, such as... Figure 5 As shown. In this embodiment, a plasma-enhanced chemical vapor deposition process is used to deposit silicon dioxide as the first hard mask layer 22 using TEOS (tetraethyl orthosilicate) as a precursor.

[0028] Step S3.2: Coat the surface of the first hard mask layer 22 with photoresist to form a photoresist layer; define the photomask (second photomask) by marking grooves and perform photolithography processes such as exposure and development to pattern the photoresist layer.

[0029] Step S3.3: Using a patterned photoresist layer as a mask, a fluorine-based plasma dry etching process and gas systems such as CF4 / CHF3 / Ar, C4F8 / Ar / O2, or CF4 / CH2F2 / Ar are used to etch the first hard mask layer 22 and the anti-diffusion layer 20 in the contact area between the resistive switching region and the capacitor region, forming a marking groove 23; after etching, the first hard mask layer 22 is removed by wet etching, such as... Figure 6 As shown.

[0030] In this step, the main function of the first hard mask layer 22 is to accurately transfer the photoresist pattern to the anti-diffusion layer 20. Specifically, the pattern is first formed on the first hard mask layer 22 through photolithography, and then the patterned first hard mask layer 22 is used as a mask to etch the anti-diffusion layer 20. This avoids the photoresist from directly contacting the etching environment of the anti-diffusion layer 20. The high etching selectivity between the first hard mask layer 22 and the anti-diffusion layer 20 ensures that the groove morphology is controllable and the dimensions are accurate.

[0031] The marking groove 23 serves as both a photolithographic alignment mark and an isolation trench between the RRAM and MIM units. On one hand, the marking groove 23, through its significant differences in surface morphology, material reflectivity, and optical phase compared to the surrounding flat area, forms a high-contrast scattering or diffraction signal in the photolithography alignment system, thereby achieving precise optical alignment reference positioning and enabling high-precision overlay alignment of the RRAM and MIM units in integrated manufacturing. On the other hand, as a physical isolation structure, the marking groove 23, through its depth and width design (depth 35nm-75nm, width 0.2μm-2.0μm) combined with the insulating medium subsequently filled in the groove, effectively blocks leakage current paths and signal crosstalk between the RRAM and MIM units, improving the electrical isolation performance between devices. This application, by combining the alignment mark and isolation trench into one, simultaneously achieves improved photolithographic alignment accuracy and enhanced device isolation without additional photomasks and process steps, simplifying the process flow and reducing manufacturing costs.

[0032] In this embodiment, the RRAM unit and the MIM unit share the same marking groove 23 as alignment marks because: in traditional discrete processes, separate alignment marks are usually fabricated for the RRAM unit and the MIM unit. Taking the RRAM unit as an example and the MIM unit as an example, when the MIM unit is manufactured, the multilayer thin film already deposited by the RRAM unit will cover and fill the alignment marks of the RRAM unit, making its depth shallower and its outline blurred, making it difficult for the lithography machine to accurately identify, thereby reducing the overlay accuracy (OVL) and yield. Sharing the same marking groove 23 as alignment marks can not only improve the reduction in overlay accuracy caused by multilayer thin film stacking, but also save a photomask.

[0033] In step S3, the first conductive material layer 30 and the capacitor dielectric material layer 40 are deposited sequentially, specifically including the following steps: Step S3.4: Deposit the first conductive material layer 30 to cover the anti-diffusion layer 20 and the conductive connector 21. The first conductive material layer 30 can be made of materials such as TiN, TaN, or Ti / TiN composite layers, which have good conductivity, diffusion blocking ability, and thermal stability. In this embodiment, the first conductive material layer 30 is a TiN layer with a thickness of 30nm-100nm, and can be prepared by processes such as physical vapor deposition or atomic layer deposition.

[0034] Step S3.5: Deposit a capacitor dielectric material layer 40 on the first conductive material layer 30, such as... Figure 7 As shown. The capacitor dielectric material layer 40 can be made of a high dielectric constant material, such as SiN, HfO2 (hafnium oxide), Al2O3 (aluminum oxide), ZrO2 (zirconia), or a composite structure thereof, to increase the capacitance density per unit area while maintaining low leakage current. In this embodiment, the capacitor dielectric material layer 40 is a SiN layer with a thickness of 5nm-50nm, prepared using processes such as atomic layer deposition or plasma-enhanced chemical vapor deposition.

[0035] In step S4, a capacitor-defined photomask and a primary photoresist are used, and the capacitor dielectric material layer 40 is etched using photolithography to obtain the capacitor dielectric layer 41 in the capacitor region. Specifically, this includes the following steps: Step S4.1: A first photoresist is coated on the surface of the capacitor dielectric material layer 40 to form a first photoresist layer. In this embodiment, the first photoresist is a positive photoresist. Subsequently, photolithography processes such as exposure and development using a capacitor-defined photomask (third photomask) are performed to form a first photoresist pattern 51, such as... Figure 8 As shown. The first photoresist pattern 51 defines the region of the capacitor dielectric in the MIM unit. The positive photoresist coverage area corresponds to the capacitor dielectric region of the subsequent MIM unit, and the exposed area (where the photoresist is removed) corresponds to the region of the capacitor dielectric material layer 40 that needs to be etched away later.

[0036] Step S4.2: Using the first photoresist pattern 51 as a mask, dry etching is performed on the capacitor dielectric material layer 40 to expose the first conductive material layer 30. Subsequently, the first photoresist pattern 51 is removed by an ashing process, resulting in the capacitor dielectric layer 41 in the capacitor region, which serves as the capacitor dielectric layer for the MIM unit. Figure 9 As shown.

[0037] In step S5, a resistive switching material layer 60 is deposited, such as... Figure 10 As shown. Preferably, the capacitor dielectric material layer 40 and the resistive switching material layer 60 have the same thickness, which facilitates device planarization in subsequent steps.

[0038] The resistive switching material layer 60 is a key functional layer of the RRAM cell, and it is usually made of transition metal oxide materials, such as HfO2 (hafnium oxide) and TaO. x Tantalum oxide, TiO2, ZrO2, and Al2O3 are among the devices that work based on the formation and breakage of conductive filaments. In the initial high-resistivity state, the resistive switching material layer 60 is insulating. When a forward voltage is applied, oxygen vacancies migrate and aggregate under the influence of the electric field to form conductive filaments, and the device transitions to a low-resistivity state. When a reverse voltage is applied, the conductive filaments are oxidized or electromigrated and break, and the device returns to the high-resistivity state, thereby achieving non-volatile data storage.

[0039] This application uses a TaO2 / Ta2O5 composite layer (i.e., a double-layer tantalum oxide structure with different oxygen contents) as the resistive switching material layer 60. Its advantages are: by confining the formation of conductive filaments in the TaO2 layer with a high oxygen vacancy concentration, and using the Ta2O5 layer as an oxygen ion reserve layer, the controllability and cycle consistency of conductive filament growth are significantly improved; at the same time, the self-rectification effect formed at the double-layer interface can effectively suppress the creeping current in the cross array and reduce leakage current and crosstalk; in addition, this composite structure also has the characteristics of low operating voltage, excellent durability and high compatibility with back-end processes, and is especially suitable for applications with stringent reliability requirements such as high-density in-memory computing chips and automotive-grade microcontroller units.

[0040] After deposition, rapid thermal annealing (RTA) treatment (400℃-500℃, 30s-60s, N2 atmosphere) can be performed to stabilize oxygen vacancy distribution, improve interface quality and optimize the switching performance of resistive switching material layer 60.

[0041] Step S6: Using a capacitor-defined photomask (third photomask) and a second photoresist, the resistive switching material layer 60 on the capacitor dielectric layer 41 is removed using a photolithography process. The positive and negative polarities of the second photoresist are opposite to those of the first photoresist. Specifically, this includes the following steps: Step S6.1: A second photoresist is coated on the surface of the resistive switching material layer 60 to form a second photoresist layer. Since the first photoresist used in step 4.1 is a positive photoresist, the second photoresist used in step S6.1 is a negative photoresist. In another feasible embodiment, the positive and negative properties of the two can be interchanged, that is, the first photoresist used in step 4.1 is a negative photoresist, and the second photoresist used in step S6.1 is a positive photoresist.

[0042] Subsequently, through photolithography processes such as exposure and development using a capacitance-defined photomask (third photomask), a secondary photoresist pattern 52 is formed, such as... Figure 11 As shown.

[0043] Since steps S6.1 and S4.1 use the same photomask (capacitor definition photomask), and are combined with the corresponding positive and negative photoresist processes, the secondary photoresist pattern 52 window formed after exposure and development of the secondary photoresist in step S6.1 corresponds to the position of the capacitor dielectric layer 41 obtained in step S4.2, which facilitates the subsequent removal of the resistive switching material layer 60 on the capacitor dielectric layer 41.

[0044] Step S6.2: Perform a pull-back process on the secondary photoresist pattern 52 to enlarge the window until the window size is the same as the size of the resistive switching material layer 60 above the capacitor dielectric layer 41, such as... Figure 12 As shown.

[0045] The pull-back process is performed in an ashing machine or a reactive ion etching machine. The reactive oxygen free radicals generated by the oxygen plasma have strong oxidizing properties and can react with the photoresist to produce volatile gases such as CO2 and H2O. Under conditions of low bias power (50-150W) and relatively high cavity pressure (e.g., 200-500mTorr), gas molecule collisions are frequent, the directionality of the plasma is weakened, and the chemical reaction dominates, allowing reactive oxygen free radicals to attack the photoresist from all directions. Therefore, the sidewalls of the window and the top of the secondary photoresist pattern 52 are etched at nearly the same rate, resulting in uniform sidewall retreat and an increase in window size; the increase in window size can be controlled by adjusting the pull-back process time.

[0046] Step S6.3: Using the secondary photoresist pattern 52 after pullback as a mask, etch the resistive switching material layer 60 until the capacitor dielectric layer 41 is exposed. Then, remove the secondary photoresist pattern 52 through an ashing process, as follows: Figure 13 As shown.

[0047] The resistive switching material layer 60 can be etched using a chlorine-based plasma dry etching process, with Cl2 / Ar or BCl3 / Cl2 / Ar as the main etching gas. By optimizing the BCl3 ratio, its reducing properties can be used to effectively remove TaO. x Oxygen in the plasma promotes the formation of volatile TaCl5, while precisely controlling the RF bias (typically <150W) and chamber pressure (controlled within a low-to-medium pressure range of 5-15 mTorr) allows etching to proceed in a chemical-dominated, physical-bombardment-assisted manner. Utilizing the characteristic that SiN surfaces readily form a dense passivation layer in chlorine-based plasma (silicon nitride has a high etching threshold), a high etching selectivity ratio for TaO2 / Ta2O5 and SiN is achieved, ensuring that etching stops at the surface of capacitor dielectric layer 41 (SiN layer) and avoiding damage to capacitor dielectric layer 41. Endpoint detection techniques (such as optical emission spectroscopy monitoring changes in Ta or Cl characteristic spectral lines) are employed to promptly terminate etching.

[0048] Since step S6.2 pulls back the secondary photoresist pattern 52, enlarging the window, in step S6.3, the resistive switching material layer 60 located above the capacitor dielectric layer 41 can be completely removed.

[0049] After etching, O2 plasma ashing combined with wet cleaning is used to remove residual polymers and byproducts from the surface, providing a clean and undamaged interface for the subsequent deposition of the second conductive material layer 70.

[0050] In step S7, a second conductive material layer 70 is deposited to cover the resistive switching material layer 60 and the capacitor dielectric layer 41, such as... Figure 14 As shown. Both the second conductive material layer 70 and the first conductive material layer 30 are made of TiN material with a thickness of 30nm-100nm. TiN, as a symmetrical electrode, can provide a stable interface barrier and symmetrical switching characteristics, which helps to improve the cycle consistency and durability of RRAM devices; at the same time, in MIM cells, the same electrode material helps to form a symmetrical electrical response, improving the linearity of capacitance and temperature stability.

[0051] In step S8, the second conductive material layer 70, the resistive switching material layer 60, and the first conductive material layer 30 are sequentially etched using an electrode definition photomask and photolithography to obtain RRAM cells in the resistive switching region and MIM cells in the capacitive region. Specifically, this includes the following steps: Step S8.1: Deposit SiN on the second conductive material layer 70 as the second hard mask layer 71, as follows. Figure 15 As shown, the second hard mask layer 71 will serve as a pattern transfer medium in the subsequent etching process.

[0052] Step S8.2: Photoresist is coated on the second hard mask layer 71, and exposure and development are performed using an electrode definition photomask (fourth photomask) to obtain an electrode photoresist pattern. The electrode photoresist pattern includes a first pattern 53 for defining the shape of the RRAM cell and a second pattern 54 for defining the shape of the top electrode of the MIM cell, such as... Figure 16 As shown.

[0053] Using the first pattern 53 and the second pattern 54 as barrier layers, plasma dry etching is performed on the second hard mask layer 71 and the second conductive material layer 70 using a Cl2 / BCl3 / Ar mixed gas, stopping on the resistive switching material layer 60. This results in the RRAM top electrode 72 and the MIM top electrode 73 being obtained in the resistive switching region and the capacitor region, respectively. Figure 17 As shown.

[0054] In this step, the pattern is first transferred from the photoresist to the second hard mask layer 71 (SiN layer) using photolithography. Then, the patterned second hard mask layer 71 is used as a mask to etch the underlying second conductive material layer 70 (TiN layer). By utilizing the difference in etching selectivity between SiN and TiN in chlorine-based plasma, high-fidelity transfer of the top electrode pattern and control of sidewall morphology are achieved, while avoiding direct exposure of the photoresist to the TiN etching environment, which could lead to mask erosion or pattern distortion.

[0055] During the etching process, the mixed gas ratio is set as Cl2:BCl3:Ar=1:(0.3-0.5):(0.1-0.3), the chamber pressure is controlled at 5mTorr-15mTorr, the source power is 500W-1000W, and the bias power is 100W-250W.

[0056] The proportion of BCl3 directly affects the sidewall morphology and the removal capacity of the natural oxide layer: BCl3 effectively removes the residual natural oxide layer (TiO2) on the surface of the second conductive material layer 70 (TiN layer) through a reduction reaction. x To ensure a smooth etching start-up, the etching anisotropy is controlled through sidewall polymer deposition to obtain a steep sidewall profile. If the BCl3 ratio is too low, insufficient oxide layer removal may lead to etching delay or failure to start. If the BCl3 ratio is too high, its strong physical bombardment and chemical activity may erode the photoresist mask, causing the pattern size to become out of control. Therefore, the BCl3 ratio must be strictly controlled within the optimized range to achieve high etching selectivity, good sidewall morphology and mask compatibility while completing the pattern definition of the top electrode.

[0057] Etching is terminated in a timely manner using endpoint detection technology to ensure that the etching stops at the surface of the underlying resistive switching material layer 60 while the RRAM top electrode 72 and MIM top electrode 73 are being formed.

[0058] After etching, O2 plasma ashing (power 200W-400W, time 30s-90s) combined with wet cleaning is used to remove residual polymers and byproducts on the surface, providing a clean interface for subsequent processes.

[0059] Step S8.3: Using the first pattern 53 and the second pattern 54 as barrier layers, selective etching is employed to etch the resistive switching material layer 60 onto the first conductive material layer 30. This etching step results in an extremely low etching rate for the capacitor dielectric layer 41. Figure 18 As shown, specifically: A plasma dry etching process is adopted, using a Cl2 / HBr / (He or Ar) / O2 mixed gas as the etching gas. The volume ratio of halogen gas (Cl2 / HBr), inert gas (He or Ar) and oxygen is controlled at 1:(0.2-0.5):(0.01-0.05). The chamber pressure is controlled at 4mTorr-10mTorr, the source power is 400W-800W, and the bias power is 50W-150W, so as to balance the etching rate and selectivity.

[0060] By adding a trace amount of O2 to the etching gas, a dense and non-volatile SiO2 layer can be formed on the surface of the capacitor dielectric layer 41 (SiN layer). x N x The passivation layer effectively suppresses the physical and chemical etching of SiN, thereby achieving the passivation of TaO. x High selectivity etching is required. The O2 flow rate needs fine adjustment; if the O2 ratio is too low, SiN passivation will be insufficient, leading to a decrease in selectivity; if the O2 ratio is too high, it will significantly reduce the selectivity of TaO. x Etching rate and excessive polymer accumulation on sidewalls and surface affect pattern morphology and process stability.

[0061] Meanwhile, the ratio of Cl2 to HBr can be adjusted within the range of 1:1 to 1:2 to optimize etching uniformity and sidewall slope: a higher HBr ratio helps increase sidewall polymer deposition, improve etching anisotropy, and obtain a steeper sidewall profile, while regulating the balance of chlorine / bromine radicals in the plasma to improve etching uniformity on large-area wafers; Cl2 provides the main chemical reactivity to ensure the resistive switching material layer 60 (TaO) x Sufficient etching of the TaO layer. By synergistically controlling the gas ratio and oxygen addition, TaO can be achieved. x It achieves highly selective etching of SiN (selectivity ratio can reach over 10:1), while also taking into account etching rate, morphology control and mask compatibility.

[0062] Etching is terminated in a timely manner by using time detection technology, so that the resistive switching material layer 60 is etched while the capacitor dielectric layer 41 is preserved.

[0063] After etching, O2 plasma ashing (power 200W-400W, time 30s-90s) combined with wet cleaning is used to remove residual polymer and byproducts from the surface.

[0064] Step S8.4: Using the first pattern 53, the second pattern 54, and the capacitor dielectric layer 41 as a barrier layer, the first conductive material layer 30 is etched using a selective etching process to obtain the RRAM bottom electrode 31 and the MIM bottom electrode 32 in the resistive switching region and the capacitor region, respectively. Figure 19 As shown, specifically: A plasma dry etching process is adopted, using a mixed gas of HBr / Cl2 / O2 as the etching gas. The gas volume ratio is set to HBr:Cl2:O2=1:(0.4-0.6):(0.03-0.06). The cavity pressure is controlled at 5mTorr-15mTorr, the source power is 500W-1000W, and the bias power is 100W-250W to ensure good anisotropy and sidewall perpendicularity.

[0065] By adding a trace amount of O2 to the etching gas, the exposed capacitor dielectric layer 41 (SiN layer) surface is passivated, generating a dense and non-volatile SiO2. x N y This process significantly optimizes the etching selectivity for SiN by creating a new layer. While improving selectivity, this process sacrifices the etching rate of the first conductive material layer 30 (TiN layer) to some extent. However, by finely controlling the O2 ratio, a balance can be achieved between selectivity and throughput, taking into account both etching morphology control and process stability. The etching endpoint can be monitored in real-time using photoemission spectroscopy to track changes in the characteristic spectral lines of Ti or Cl, combined with etching time control to ensure etching uniformity.

[0066] After etching is completed, the first pattern 53 and the second pattern 54 are removed by ashing process, and the second hard mask layer 71 is removed by wet etching.

[0067] A semiconductor structure was prepared using the above method, such as... Figure 20 As shown, the semiconductor structure includes a semiconductor substrate 10 having a metal interconnect layer 11, an anti-diffusion layer 20 formed on the semiconductor substrate 10, and RRAM cells and MIM cells formed on the anti-diffusion layer 20.

[0068] The RRAM cell includes an RRAM bottom electrode 31, a resistive switching layer 61, and an RRAM top electrode 72 stacked sequentially from bottom to top. The RRAM bottom electrode 31 is connected to the metal interconnect layer 11 via a conductive connector 21. The MIM cell includes a MIM bottom electrode 32, a capacitor dielectric layer 41, and a MIM top electrode 73 stacked sequentially from bottom to top. The resistive switching layer 61 of the RRAM cell and the capacitor dielectric layer 41 of the MIM cell are made of different materials; the resistive switching layer 61 and the capacitor dielectric layer 41 have the same thickness and are on the same plane, which is beneficial for achieving device planarization.

[0069] like Figure 20As shown, in the MIM cell, the size of the MIM top electrode 73 is smaller than the size of the capacitor dielectric layer 41, while the size of the capacitor dielectric layer 41 is the same as the size of the MIM bottom electrode 32. This effectively suppresses edge electric field effects. If the top electrode and bottom electrode edges are aligned, the electric field lines bend and concentrate at the edges, generating uncontrollable edge capacitance and affecting the stability of the capacitance value. By controlling the top electrode size to be smaller than the bottom electrode size, the critical parallel plate area is moved away from the physical edge, resulting in a more uniform electric field distribution and making the capacitance value closer to the ideal parallel plate capacitor formula, thereby ensuring the high-precision performance of the MIM cell in analog circuits.

[0070] Example 2 This embodiment discloses a method for fabricating a semiconductor structure, referring to... Figure 21 Based on the preparation method provided in Example 1, the preparation method in Example 2 further includes the following steps: Step S9: Deposit device protective layer 90; Step S10: Etch vias 93 connecting the RRAM cells and MIM cells on the device protective layer 90; Step S11: Fill the through hole 93 with conductive material to bring out the RRAM cell and MIM cell.

[0071] In step S9, the deposition of the device protective layer 90 specifically includes the following steps: Step S9.1: Deposit isolation layer 80 to cover RRAM cells and MIM cells. Isolation layer 80 can be a SiN layer with a thickness of 20nm-80nm. Utilizing the dense and highly oxidation-resistant properties of SiN, the RRAM cells and MIM cells are completely sealed to prevent oxidation or damage to the resistive switching layer 61 and capacitor dielectric layer 41 caused by subsequent processes (such as high temperature and oxygen-containing plasma).

[0072] Step S9.2: Deposit a device protective layer 90 on the isolation layer 80. Specifically, the device protective layer 90 is a SiO2 layer, deposited using plasma-enhanced chemical vapor deposition (PECVD) with TEOS as a precursor. The relatively thick device protective layer 90 serves as the main insulating layer, protecting the underlying RRAM and MIM cells. After deposition, chemical mechanical polishing (CMP) can be used to planarize the device protective layer 90, providing mechanical support and a planarized substrate.

[0073] Step S9.3: Sequentially deposit a buffer layer 91 and an interlayer dielectric layer 92 on the device protective layer 90, such as... Figure 22As shown in the diagram, the buffer layer 91 is a SiN layer. Its density and high selectivity for fluorine-based etching help slow down the etching rate and control the endpoint during subsequent via etching, preventing over-etching damage to underlying devices. The buffer layer 91 also effectively blocks the diffusion of tungsten or copper atoms into the functional areas of the device. The interlayer dielectric layer 92 is a SiO2 layer, providing the main electrical isolation thickness and mechanical support. The overall film stress is controlled by adjusting the SiN to SiO2 thickness ratio and deposition process parameters, balancing the thermal and mechanical stresses of the multilayer structure to ensure the yield and reliability of subsequent metal interconnect processes.

[0074] In step S10, vias 93 connecting the RRAM cells and MIM cells are etched on the device protective layer 90, specifically including the following steps: A via-hole definition mask (fifth mask) is used to define via-hole 93 patterns on the interlayer dielectric layer 92 through photolithography. Subsequently, anisotropic etching is performed to etch the interlayer dielectric layer 92, buffer layer 91, device protection layer 90, and isolation layer 80 to form several vias 93 penetrating to the RRAM bottom electrode 31, MIM bottom electrode 32, RRAM top electrode 72, or MIM top electrode 73. Figure 23 and Figure 24 As shown. The etching process has a high selectivity, ensuring that the etching stops at the surface of the corresponding electrode (TiN layer).

[0075] In step S11, conductive material 94 (such as copper, tungsten, or other metal materials) is filled into the through hole 93. Figure 25 As shown, the RRAM and MIM cells are brought out to achieve electrical connection between the RRAM and MIM cells and the devices above.

[0076] The above method was used to prepare the following: Figure 25 The semiconductor structure shown is based on the semiconductor structure prepared in Example 1. The semiconductor structure prepared in Example 2 further includes an isolation layer 80, a device protection layer 90, a buffer layer 91, and an interlayer dielectric layer 92 formed on the RRAM cell and the MIM cell, as well as a plurality of through holes 93 that penetrate the above-mentioned layer structure and are connected to the RRAM bottom electrode 31, the MIM bottom electrode 32, the RRAM top electrode 72, or the MIM top electrode 73, and also includes a conductive material 94 filled in the through holes 93.

[0077] In summary, this application reduces the number of photomasks from 8-10 in traditional discrete processes to 4-5 by using a shared photomask process. Specifically, a first photomask is used to form the conductive connector 21 under the RRAM cell, a marking groove defining photomask (second photomask) is used to form the marking groove 23, a capacitor defining photomask (third photomask) is used in conjunction with a positive and negative adhesive process to form the MIM cell capacitor dielectric layer 41, an electrode defining photomask (fourth photomask) is used to form the RRAM top electrode 72 and the MIM top electrode 73, and a via defining photomask (fifth photomask) is used to form the top via 93. This achieves integrated manufacturing of the MIM cell and RRAM cell, effectively improving the chip's functional density while maintaining the functionality of existing devices; at the same time, the significantly reduced number of photomasks lowers photomask costs and the cost of repetitive manufacturing processes.

[0078] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that: Includes the following steps: A semiconductor substrate having a metal interconnect layer is provided, wherein the semiconductor substrate has at least a resistive switching region and a capacitive region; A diffusion-resistant layer is deposited, and a conductive connector plug connected to the metal interconnect layer is prepared in the resistive switching region; Marking grooves are etched on the anti-diffusion layer, and a first conductive material layer and a capacitor dielectric material layer are deposited sequentially. A capacitor dielectric layer is obtained in the capacitor region by using a capacitor-defined photomask and a primary photoresist, and etching the capacitor dielectric material layer using a photolithography process. Deposited resistive switching material layer; A capacitive photomask and a secondary photoresist are used, and a resistive switching material layer on the capacitive dielectric layer is removed by photolithography. The positive and negative values ​​of the secondary photoresist are opposite to those of the primary photoresist. Deposit a second conductive material layer; The second conductive material layer, the resistive switching material layer, and the first conductive material layer are sequentially etched using an electrode-defined photomask and photolithography to obtain RRAM cells in the resistive switching region and MIM cells in the capacitor region.

2. The method for preparing the semiconductor structure according to claim 1, characterized in that: The step of etching marking grooves on the anti-diffusion layer includes: A first hard mask layer is deposited on the anti-diffusion layer; A photomask is defined using a marking groove, and an anti-diffusion layer is etched in the contact area between the resistive switching region and the capacitive region using a photolithography process to obtain the marking groove.

3. The method for preparing the semiconductor structure according to claim 1, characterized in that: In the process of removing the resistive switching material layer on the capacitor dielectric layer using a capacitively defined photomask and a second photoresist, the window of the photoresist pattern obtained by exposing and developing the second photoresist using the capacitively defined photomask is the area where the capacitor dielectric layer is located. The window of the photoresist pattern is pulled back before the resistive switching material layer is etched.

4. The method for preparing the semiconductor structure according to claim 1, characterized in that: The step of sequentially etching the second conductive material layer, the resistive switching material layer, and the first conductive material layer using an electrode-defined photomask and photolithography to obtain RRAM cells in the resistive switching region and MIM cells in the capacitive region includes: A second hard mask layer is deposited on the second conductive material layer; Photoresist is coated on the second hard mask layer, and an electrode photoresist pattern is obtained by exposure and development using an electrode definition photomask. The electrode photoresist pattern includes a first pattern for defining the shape of the RRAM cell and a second pattern for defining the shape of the top electrode of the MIM cell. Using the first and second patterns as barrier layers, the second hard mask layer and the second conductive material layer are etched and left on the resistive switching material layer, respectively obtaining the corresponding top electrodes in the resistive switching region and the capacitor region. Using the first and second patterns as barrier layers, the resistive switching material layer is etched onto the first conductive material layer using a selective etching process. Using the first pattern, the second pattern, and the capacitor dielectric layer as barrier layers, the first conductive material layer is etched using a selective etching process to obtain the corresponding bottom electrodes in the resistive switching region and the capacitor region, respectively.

5. The method for preparing the semiconductor structure according to claim 4, characterized in that: The size of the second pattern is smaller than the size of the capacitor dielectric layer.

6. The method for preparing the semiconductor structure according to claim 4, characterized in that: The capacitor dielectric layer and the resistive switching material layer have the same thickness.

7. A semiconductor structure, characterized in that: It is prepared by the method of any one of claims 1-6.

8. A method for fabricating a semiconductor structure, characterized in that: Includes the following steps: A semiconductor substrate having a metal interconnect layer is provided, wherein the semiconductor substrate has at least a resistive switching region and a capacitive region; A diffusion-resistant layer is deposited, and a conductive connector plug connected to the metal interconnect layer is prepared in the resistive switching region; Marking grooves are etched on the anti-diffusion layer, and a first conductive material layer and a capacitor dielectric material layer are deposited sequentially. A capacitor dielectric layer is obtained in the capacitor region by using a capacitor-defined photomask and a primary photoresist, and etching the capacitor dielectric material layer using a photolithography process. Deposited resistive switching material layer; A capacitive photomask and a secondary photoresist are used, and a resistive switching material layer on the capacitive dielectric layer is removed by photolithography. The positive and negative values ​​of the secondary photoresist are opposite to those of the primary photoresist. Deposit a second conductive material layer; The second conductive material layer, the resistive switching material layer, and the first conductive material layer are sequentially etched using an electrode definition photomask and photolithography to obtain RRAM cells in the resistive switching region and MIM cells in the capacitor region. Deposited device protective layer; Through-holes connecting the RRAM cell and the MIM cell are etched on the device protective layer; The via is filled with conductive material to bring out the RRAM cell and MIM cell.

9. The method for preparing the semiconductor structure according to claim 8, characterized in that: Before depositing the protective layer for the device, an isolation layer is first deposited to cover the RRAM cells and MIM cells.

10. A semiconductor structure, characterized in that: It is prepared by the method of any one of claims 8-9.

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