A method to prevent silicon capacitor warping
By depositing a silicon nitride thin film as a stress compensation layer on the back side of a semiconductor substrate and using plasma-enhanced chemical vapor deposition to control the hydrogen atom density, the wafer warpage problem caused by the ONO structure was solved, thus improving the stability and reliability of silicon capacitors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI IND U TECH RES INST
- Filing Date
- 2025-01-09
- Publication Date
- 2026-06-02
AI Technical Summary
In semiconductor devices, ONO structures can cause wafer warping due to stress imbalance. Existing technologies cannot reliably solve this problem, and the warping may be recovered in subsequent processes.
A silicon nitride thin film is deposited on the back side of a semiconductor substrate as a stress compensation layer using plasma-enhanced chemical vapor deposition. The stress of the semiconductor substrate is matched by adjusting the hydrogen atom density of the silicon nitride thin film, thereby achieving overall stress balance.
This effectively avoids the stable solution to the silicon capacitor warpage problem, ensuring that the warpage will not recover in subsequent processes, thus improving the stability and reliability of the device.
Smart Images
Figure CN122138412A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, and in particular relates to a method for preventing silicon capacitor warping. Background Technology
[0002] ONO (oxide-nitride-oxide) structure plays an important role in the application of high-power and high-temperature electronic devices in the semiconductor industry. Due to its good dielectric properties, stability and reliability, ONO structure is widely used in devices such as MIS (metal-insulator-semiconductor) capacitors.
[0003] ONO structure generally refers to SiO2-Si3N4-SiO2 structure. Compared with traditional MOS devices based on a single SiO2 (silicon dioxide) layer, ONO structure MIS capacitors exhibit better stability and reliability at room temperature / high temperature. However, due to the stress imbalance problem often encountered in the specific process implementation of ONO structure, wafer warping is relatively large, making subsequent processes difficult.
[0004] Existing technologies generally address warpage by depositing SiO2 (silicon dioxide) on the back of the wafer or by removing part of the film layer. While this can alleviate warpage to some extent, the effect is limited. If the wafer is left to stand for a period of time or undergoes other complex processes (such as etching or annealing), the wafer warpage may return to its original value, and the warpage problem cannot be stably improved. Summary of the Invention
[0005] This application provides a method to avoid silicon capacitor warpage. A silicon nitride thin film is deposited on the back side of a semiconductor substrate as a stress compensation layer using plasma-enhanced chemical vapor deposition. The internal stress of the silicon nitride thin film interacts with the stress of the semiconductor substrate to achieve a balance of overall wafer stress. This method stably solves the warpage problem caused by the deposition of the ONO structure in silicon capacitors, ensuring that the warpage remains stable in subsequent processes and does not revert to its original value after other processes are completed.
[0006] Other objects and advantages of the present invention can be further understood from the technical features disclosed herein.
[0007] To achieve one or more of the above objectives or other objectives, the present invention provides a method for preventing silicon capacitor warping.
[0008] One method to prevent silicon capacitor warping includes:
[0009] A semiconductor substrate is provided, and a patterned layer is formed on the front side of the semiconductor substrate;
[0010] The semiconductor substrate is etched according to the pattern of the patterned layer;
[0011] Remove the patterned layer, and sequentially fabricate a bottom electrode layer, an ONO structure layer, and a top electrode layer on the etched semiconductor substrate;
[0012] A stress compensation layer made of silicon nitride is prepared on the back side of the semiconductor substrate. The internal stress of the stress compensation layer interacts with the stress of the semiconductor substrate to ensure that the warpage value of the semiconductor substrate is within a preset range.
[0013] A silicon nitride thin film is deposited on the back side of the semiconductor substrate as a stress compensation layer using plasma-enhanced chemical vapor deposition. The internal stress of the silicon nitride thin film is controlled by changing the hydrogen atom density of the silicon nitride thin film.
[0014] The higher the hydrogen atom density of the silicon nitride film, the lower the internal stress of the silicon nitride film;
[0015] The lower the hydrogen atom density of the silicon nitride film, the greater the internal stress of the silicon nitride film.
[0016] The hydrogen atom density of the silicon nitride film can be altered by adjusting the temperature, pressure, composition ratio, deposition rate, power, and gas flow rate of the deposition process.
[0017] The silicon nitride film covers the back side of the semiconductor substrate and is deposited multiple times to form a silicon nitride film with a thickness of 1 μm. The internal stress of the silicon nitride film interacts with the stress of the semiconductor substrate to achieve overall stress balance.
[0018] Under the influence of plasma, silane and ammonia react, with a deposition temperature of 800±5℃, a gas flow rate of 200±5SLM, and a pressure of 0.3 Torr.
[0019] The specific process of forming a patterned layer on the front side of the semiconductor substrate includes:
[0020] A silicon dioxide thin film is deposited on the front side of the semiconductor substrate using plasma-enhanced chemical vapor deposition (PECVD). The silicon dioxide thin film is then patterned to form the patterned layer. The semiconductor substrate is then etched according to the pattern of the patterned layer.
[0021] The semiconductor substrate is a silicon wafer.
[0022] The etching width of the semiconductor substrate is 2μm-3μm, and the depth is 30μm-50μm.
[0023] The specific process of sequentially fabricating the bottom electrode layer, the ONO structure layer, and the top electrode layer includes:
[0024] A polycrystalline silicon layer is deposited on an etched semiconductor substrate using a low-pressure chemical vapor deposition process to serve as the bottom electrode layer.
[0025] The bottom oxide layer, the middle nitride layer and the top oxide layer are deposited sequentially to form an ONO structure layer;
[0026] A polycrystalline silicon layer is deposited on the ONO structure layer using a low-pressure chemical vapor deposition process to form the top electrode layer.
[0027] The specific process of forming the ONO structural layer includes:
[0028] A silicon dioxide layer is formed as the bottom oxide layer using a dry thermal oxidation process;
[0029] The oxidized semiconductor substrate is placed in a low-pressure chemical vapor deposition furnace tube to deposit a silicon nitride layer as an intermediate nitride layer.
[0030] Tetraethoxysilane was used as a precursor, and a silicon dioxide layer was formed as the top oxide layer through a low-pressure chemical vapor deposition process.
[0031] Compared with the prior art, the beneficial effects of the present invention mainly include:
[0032] This application provides a method to avoid silicon capacitor warpage. A silicon nitride thin film is deposited on the back side of a semiconductor substrate as a stress compensation layer using plasma-enhanced chemical vapor deposition. The internal stress of the silicon nitride thin film interacts with the stress of the semiconductor substrate to achieve a balance of overall wafer stress. This method stably solves the warpage problem caused by the deposition of the ONO structure in silicon capacitors, ensuring that the warpage remains stable in subsequent processes and does not revert to its original value after other processes are completed.
[0033] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0034] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0035] Figure 1 This is a process flow diagram of a method for preventing silicon capacitor warping provided in an embodiment of this application.
[0036] Figure 2 Warp value data for this application Figure 1 .
[0037] Figure 3 Warp value data for this application Figure 2 .
[0038] Figure 4 Warp value data for this application Figure 3 .
[0039] Figure 5 Warp value data for this application Figure 4 .
[0040] Figure 6 Warp value data for this application Figure 5 . Detailed Implementation
[0041] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.
[0042] This application provides a method to avoid silicon capacitor warpage. A silicon nitride thin film is deposited on the back side of a semiconductor substrate as a stress compensation layer using plasma-enhanced chemical vapor deposition. The internal stress of the silicon nitride thin film interacts with the stress of the semiconductor substrate to achieve a balance of overall wafer stress. This method stably solves the warpage problem caused by the deposition of the ONO structure in silicon capacitors, ensuring that the warpage remains stable in subsequent processes and does not revert to its original value after other processes are completed.
[0043] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0044] Example
[0045] like Figure 1 As shown, a method for preventing silicon capacitor warping includes:
[0046] Step 1: Provide a semiconductor substrate 1, and deposit a silicon dioxide thin film on the front side of the semiconductor substrate 1 using a plasma-enhanced chemical vapor deposition process;
[0047] Step 2: Pattern the silicon dioxide film to form pattern layer 2;
[0048] Step 3: Etch the semiconductor substrate 1 according to the pattern of pattern layer 2;
[0049] Step 4: Remove the pattern layer 2 using wet etching or dry etching, and sequentially prepare the bottom electrode layer 3, the ONO structure layer 5 and the top electrode layer 4 on the etched semiconductor substrate 1.
[0050] Step 5: A silicon nitride thin film is deposited on the back side of the semiconductor substrate 1 as a stress compensation layer 6 using plasma-enhanced chemical vapor deposition. The internal stress of the stress compensation layer 6 interacts with the stress of the semiconductor substrate 1 to achieve overall stress balance.
[0051] The gases used to prepare silicon nitride thin films (Si3N4) are SiH4, NH3, and N2. The silicon nitride thin films contain hydrogen atoms, mainly in the form of Si-H and NH. The stress of the silicon nitride thin film (Si3N4) can be adjusted by changing the hydrogen atom content. Higher hydrogen atom density results in lower internal stress in the silicon nitride thin film; lower hydrogen atom density results in higher internal stress.
[0052] Therefore, the hydrogen atom density of the silicon nitride film can be changed by adjusting the temperature, pressure, composition ratio, deposition rate, power and gas flow rate of the deposition process, thereby controlling the internal stress of the silicon nitride film, better matching the stress of the semiconductor substrate 1, and improving the wafer warpage problem caused by the ONO structure; while the stress of silicon dioxide is very sensitive to water content, which will lead to its stress instability.
[0053] Compared to silicon dioxide films, silicon nitride films have higher hardness and better mechanical strength, and can more effectively resist deformation caused by interlayer stress differences.
[0054] PECVD (Plasma Enhanced Chemical Vapor Deposition) utilizes plasma to lower the temperature required for chemical reactions, thereby enabling the deposition of high-quality thin films at lower temperatures. This helps reduce additional stress caused by temperature changes and further reduces the possibility of warping.
[0055] PECVD (Plasma Enhanced Chemical Vapor Deposition) involves introducing reactive gases into a vacuum chamber and applying radio frequency (RF) or microwave power to generate plasma. High-energy particles in the plasma promote chemical reactions between gas molecules, thereby forming solid materials that are deposited on the substrate surface. Due to the presence of plasma, the reaction can be carried out at relatively low temperatures, which reduces the impact of thermal stress on the substrate material and helps to maintain the original properties of the substrate.
[0056] Under the action of plasma, silane and ammonia react, the deposition temperature is 800±5℃, the gas flow rate is 200±5SLM, the pressure is 0.3 Torr, and multiple depositions form a silicon nitride thin film with a thickness of 10k (1μm) covering the back side of the semiconductor substrate. The internal stress of the silicon nitride thin film interacts with the stress of the semiconductor substrate to maintain the overall stress balance of the wafer.
[0057] In a preferred embodiment of the present invention, the semiconductor substrate 1 is a silicon wafer. The semiconductor substrate 1 is subjected to deep silicon etching according to the pattern of the pattern layer 2, with an etching width of 2μm-3μm and a depth of 30μm-50μm.
[0058] In a preferred embodiment of the present invention, the deposition thickness of the silicon nitride thin film is affected by the depth and width of the deep silicon etching of the semiconductor substrate 1.
[0059] Since the internal stress of the silicon nitride thin film and the stress of the semiconductor substrate 1 cannot be directly measured, the number of times the silicon nitride thin film is deposited can be determined by measuring whether the warpage value of the semiconductor substrate is within a preset range.
[0060] Specifically, in Figure 2 If the warpage value is large (the machine requires a warpage radius > 50 μm for the wafer), a 10 angstrom thick silicon nitride film needs to be deposited first, and the warpage value measured. Figure 3 As shown, the warpage value at this point is Radius = 34m < 50m, which is still relatively large, making it unsuitable for machine operation. Further silicon nitride film deposition is required, and the number of deposition cycles must be increased. After two more 10 angstrom thick silicon nitride films, for a total of three 10 angstrom thick silicon nitride films deposited on the crystal back, the warpage was significantly improved, as shown below. Figure 4 As shown.
[0061] Specifically, when the warpage value is small, Figure 5 The figure shows the warpage value of the wafer before silicon nitride deposition. The warpage value was measured after depositing a 10 angstrom thick silicon nitride film. Figure 6 As shown, after depositing silicon nitride with a thickness of 10 angstroms once, the warpage value of the wafer (Radius = 80m > 50m) is sufficient for machine operation.
[0062] The specific process of sequentially fabricating the bottom electrode layer 3, the ONO structure layer 5, and the top electrode layer 4 on the etched semiconductor substrate includes:
[0063] A polycrystalline silicon layer is deposited on an etched semiconductor substrate using LPCVD (low-pressure chemical vapor deposition) as the bottom electrode layer.
[0064] A bottom oxide layer, an intermediate nitride layer, and a top oxide layer are deposited sequentially to form an ONO structure layer 5;
[0065] A polycrystalline silicon layer was deposited on the ONO structure layer 5 using a low-pressure chemical vapor deposition process to form the top electrode layer.
[0066] A layer of doped polysilicon (D-Poly) is grown on an etched semiconductor substrate using LPCVD (low-pressure chemical vapor deposition) as the bottom electrode layer P1. The temperature range is typically 550℃-650℃, and the low-pressure environment is usually between 10-1000 Pa. The doping concentration of the polysilicon is controlled by adjusting the flow rate of the doping gas. Phosphine is typically used for n-type doping, and borane is typically used for p-type doping. The thickness of the polysilicon film can be precisely controlled by controlling the deposition time and gas flow rate. The surface smoothness of the film can also be improved by optimizing the deposition conditions.
[0067] In capacitor applications, polycrystalline silicon, as the bottom electrode, can provide stable capacitance characteristics, which helps to improve the performance and reliability of capacitors; doped polycrystalline silicon can form a low contact resistance interface with metal electrodes, which helps to improve the overall electrical performance of the device.
[0068] In a preferred embodiment of the present invention, an ellipsometry or profilometer is used to measure the thickness of the polycrystalline silicon thin film; a four-probe method is used to measure the resistivity of the polycrystalline silicon to ensure that the doping concentration meets the requirements; and a scanning electron microscope (SEM) or atomic force microscope (AFM) is used to examine the surface morphology and crystal quality of the thin film.
[0069] The specific process of forming the ONO structural layer 5 in this embodiment includes:
[0070] Forming the bottom oxide layer: A silicon dioxide layer is formed as the bottom oxide layer through a dry thermal oxidation process. Specifically, the cleaned silicon wafer is placed in a high-temperature oxidation furnace. The oxidation furnace needs to maintain certain temperature and atmosphere conditions. The temperature inside the oxidation furnace is gradually increased to the required high temperature, such as about 1000℃, to promote the oxidation reaction. At high temperature, dry oxygen or water vapor is introduced into the oxidation furnace. The growth rate and thickness of the silicon dioxide layer are controlled by adjusting parameters such as temperature, pressure, and oxygen flow rate to meet different process requirements. When the required oxide layer thickness is reached, the oxygen supply is stopped and the furnace temperature is lowered until the silicon wafer can be safely removed.
[0071] Forming an intermediate nitride layer: The oxidized semiconductor substrate is placed in a low-pressure chemical vapor deposition furnace tube to deposit a silicon nitride layer as an intermediate nitride layer;
[0072] Forming the top oxide layer: Tetraethoxysilane (TEOS) is used as a precursor to form a silica layer as the top oxide layer through low-pressure chemical vapor deposition. Specifically, the flow rate of tetraethoxysilane (TEOS) is 100-200 sccm, and the flow rate of oxygen is 1000-2000 sccm. It is necessary to ensure that the reaction chamber temperature is uniform and stable to avoid uneven film caused by local overheating or cold spots. The TEOS and oxygen used must be of high purity to avoid impurities being incorporated into the film and affecting its performance. It is also necessary to maintain stable pressure in the reaction chamber to avoid changes in the deposition rate caused by pressure fluctuations.
[0073] In a preferred embodiment of the present invention, the thickness of the bottom oxide layer is 800-1000 angstroms, the thickness of the intermediate nitride layer is 2000-2400 angstroms, and the thickness of the top oxide layer is 800-1000 angstroms.
[0074] This application provides a method to avoid silicon capacitor warpage. A silicon nitride thin film is deposited on the back side of a semiconductor substrate as a stress compensation layer using plasma-enhanced chemical vapor deposition. The internal stress of the silicon nitride thin film interacts with the stress of the semiconductor substrate to achieve a balance of overall wafer stress. This method stably solves the warpage problem caused by the deposition of the ONO structure in silicon capacitors, ensuring that the warpage remains stable in subsequent processes and does not revert to its original value after other processes are completed.
[0075] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.
[0076] It should also be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
Claims
1. A method for preventing silicon capacitor warping, characterized in that, include: A semiconductor substrate is provided, and a patterned layer is formed on the front side of the semiconductor substrate; The semiconductor substrate is etched according to the pattern of the patterned layer; Remove the patterned layer, and sequentially fabricate a bottom electrode layer, an ONO structure layer, and a top electrode layer on the etched semiconductor substrate; A stress compensation layer made of silicon nitride is prepared on the back side of the semiconductor substrate. The internal stress of the stress compensation layer interacts with the stress of the semiconductor substrate to ensure that the warpage value of the semiconductor substrate is within a preset range.
2. The method for preventing silicon capacitor warping according to claim 1, characterized in that, A silicon nitride thin film is deposited on the back side of the semiconductor substrate as a stress compensation layer using plasma-enhanced chemical vapor deposition. The internal stress of the silicon nitride thin film is controlled by changing the hydrogen atom density of the silicon nitride thin film.
3. The method for preventing silicon capacitor warping according to claim 2, characterized in that, The higher the hydrogen atom density of the silicon nitride film, the lower the internal stress of the silicon nitride film; The lower the hydrogen atom density of the silicon nitride film, the greater the internal stress of the silicon nitride film.
4. The method for preventing silicon capacitor warping according to claim 2, characterized in that, The hydrogen atom density of the silicon nitride film can be altered by adjusting the temperature, pressure, composition ratio, deposition rate, power, and gas flow rate of the deposition process.
5. A method for preventing silicon capacitor warping according to claim 2, characterized in that, The silicon nitride film covers the back side of the semiconductor substrate and is deposited multiple times to form a silicon nitride film with a thickness of 1 μm. The internal stress of the silicon nitride film interacts with the stress of the semiconductor substrate to achieve overall stress balance.
6. A method for preventing silicon capacitor warping according to claim 2, characterized in that, Under the influence of plasma, silane and ammonia react, with a deposition temperature of 800±5℃, a gas flow rate of 200±5SLM, and a pressure of 0.3 Torr.
7. The method for preventing silicon capacitor warping according to claim 1, characterized in that, The specific process of forming a patterned layer on the front side of the semiconductor substrate includes: A silicon dioxide thin film is deposited on the front side of the semiconductor substrate using plasma-enhanced chemical vapor deposition (PECVD). The silicon dioxide thin film is then patterned to form the patterned layer. The semiconductor substrate is then etched according to the pattern of the patterned layer. The semiconductor substrate is a silicon wafer.
8. A method for preventing silicon capacitor warping according to claim 7, characterized in that, The etching width of the semiconductor substrate is 2μm-3μm, and the depth is 30μm-50μm.
9. A method for preventing silicon capacitor warping according to claim 1, characterized in that, The specific process of sequentially fabricating the bottom electrode layer, the ONO structure layer, and the top electrode layer includes: A polycrystalline silicon layer is deposited on an etched semiconductor substrate using a low-pressure chemical vapor deposition process to serve as the bottom electrode layer. The bottom oxide layer, the middle nitride layer and the top oxide layer are deposited sequentially to form an ONO structure layer; A polycrystalline silicon layer is deposited on the ONO structure layer using a low-pressure chemical vapor deposition process to form the top electrode layer.
10. A method for preventing silicon capacitor warping according to claim 9, characterized in that, The specific process of forming the ONO structural layer includes: A silicon dioxide layer is formed as the bottom oxide layer using a dry thermal oxidation process; The oxidized semiconductor substrate is placed in a low-pressure chemical vapor deposition furnace tube to deposit a silicon nitride layer as an intermediate nitride layer. Tetraethoxysilane was used as a precursor, and a silicon dioxide layer was formed as the top oxide layer through a low-pressure chemical vapor deposition process.